Manufacturing method of via hole in integrated circuit packaging assembly and packaging assembly

Abstract

The embodiment of the invention discloses a manufacturing method of a via hole in an integrated circuit packaging assembly and the packaging assembly, relates to the technical field of integrated circuits, and aims to reduce the process cost, reduce the attenuation of transmission signals and improve the quality of the transmission signals. The method comprises the following steps: forming a bearing layer on the surface of a circuit layer; forming a barrier layer on the surface of the substrate; forming a first blind hole which penetrates through the barrier layer and the substrate layer and goes deep into the circuit layer through etching; wherein a conductive structure in the circuit layer is exposed at the bottom of the first blind hole; the hole opening of the first blind hole is expanded; and filling the first blind hole with a conductive material to form a first via hole with an integrated conductive structure. The manufacturing method is suitable for manufacturing the via hole in the integrated circuit packaging assembly.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method for manufacturing a via in an integrated circuit packaging component, a packaging component, a packaging method, and an integrated circuit device. Background Art

[0002] When two or more different wafers or chips are interconnected, it is necessary to make vias on the wafers, and then prepare pads on each of the vias to achieve the connection between the two pads.

[0003] In the prior art, when forming through holes and pads, two photomasks and two copper etchings are usually performed to realize the entire interconnection structure. Due to the two photomasks and etchings, on the one hand, the cost of the process is high, and on the other hand, a contact layer is generated between the through hole filling material and the pad filling material, which increases the overall resistance. When the through hole is used to transmit signals, the signal attenuation is large, affecting the quality of the transmitted signal. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a method for manufacturing vias in an integrated circuit packaging component, a packaging component, a packaging method and an integrated circuit device, which are convenient for reducing process costs, reducing the attenuation of transmission signals, and improving the quality of transmission signals.

[0005] In a first aspect, a method for manufacturing a via in an integrated circuit package component, the integrated circuit package component includes a substrate and a circuit layer arranged on the substrate; the method includes: forming a carrier layer on the surface of the circuit layer; forming a barrier layer on the surface of the substrate; forming a first blind hole penetrating the barrier layer and the substrate layer and penetrating into the circuit layer by etching; wherein the conductive structure in the circuit layer is exposed to the bottom of the first blind hole; expanding the hole mouth of the first blind hole; filling the first blind hole with a conductive material to form a first via with an integrated conductive structure.

[0006] According to a specific implementation method of the embodiment of the present application, the expanding the opening of the first blind hole includes: filling the first blind hole with an etching protection material; etching the etching protection material filled in the first blind hole to a first depth along the direction from the opening of the first blind hole to the bottom of the hole and reserving an etching protection material of a second depth in the blind hole to expose the side wall at the opening of the first blind hole; the sum of the second depth and the first depth is equal to the depth of the blind hole; and etching the side wall at the opening of the first blind hole to expand the aperture at the opening of the first blind hole.

[0007] According to a specific implementation method of an embodiment of the present application, etching the side wall at the opening of the first blind hole to expand the aperture at the opening of the first blind hole includes: etching the side wall at the opening of the first blind hole to form an inverted cone-shaped expansion section with a large end opening and a small internal opening at the opening of the first blind hole.

[0008] According to a specific implementation method of the embodiment of the present application, the etching of the side wall at the opening of the first blind hole to form an inverted cone-shaped expansion section with a large end opening and a small internal opening at the opening of the first blind hole includes: etching the side wall at the opening of the first blind hole to form an inverted cone-shaped expansion section with a large end opening and a small internal opening at the opening of the first blind hole, and making the central axis of the inverted cone-shaped expansion section coincide with the central axis of the first blind hole, and the internal opening of the inverted cone-shaped expansion section is connected to the openings of the remaining hole sections of the first blind hole except the expansion section.

[0009] According to a specific implementation method of an embodiment of the present application, forming a barrier layer on the surface of the substrate includes: forming a first barrier layer on the surface of the substrate, and forming a second barrier layer on the surface of the first barrier layer; the material of the second barrier layer is different from the material of the first barrier layer; wherein the first depth is greater than the thickness of the second barrier layer and less than the sum of the thickness of the second barrier layer and the thickness of the first barrier layer.

[0010] In a second aspect, a method for manufacturing a via in an integrated circuit packaging component, the integrated circuit packaging component includes a substrate and a circuit layer arranged on the substrate; the method includes: forming a barrier layer on the surface of the circuit layer; forming a second blind hole penetrating the barrier layer and extending into the circuit layer by etching; wherein the conductive structure in the circuit layer is exposed to the bottom of the second blind hole; expanding the hole opening of the second blind hole; and filling the second blind hole with a conductive material to form a second via with an integrated conductive structure.

[0011] According to a specific implementation method of an embodiment of the present application, the expanding the opening of the second blind hole includes: filling the second blind hole with an etching protection material; etching the etching protection material filled in the second blind hole to a first depth along the direction from the opening of the second blind hole to the bottom of the hole and reserving an etching protection material of a second depth in the second blind hole to expose the side wall at the opening of the second blind hole; etching the side wall at the opening of the second blind hole to expand the aperture at the opening of the second blind hole.

[0012] According to a specific implementation of the embodiment of the present application, etching the sidewall of the second blind hole at the opening to enlarge the aperture of the second blind hole at the opening includes: The side wall at the opening of the second blind hole is etched to form an inverted tapered expansion section with a large end opening and a small inner opening at the opening of the second blind hole.

[0013] According to a specific implementation of the embodiment of the present application, the etching of the side wall at the opening of the second blind hole to form an inverted tapered expansion section with a large end opening and a small inner opening at the opening of the second blind hole includes: The side wall at the opening of the second blind hole is etched to form an inverted cone-shaped expansion section with a large end opening and a small internal opening at the opening of the second blind hole, and the central axis of the inverted cone-shaped expansion section coincides with the central axis of the second blind hole, and the internal opening of the inverted cone-shaped expansion section is connected to the opening of the remaining hole sections of the second blind hole except the expansion section.

[0014] According to a specific implementation of the embodiment of the present application, forming a barrier layer on the surface of the circuit layer includes: forming a first barrier layer on the surface of the circuit layer, and forming a second barrier layer on the surface of the first barrier layer; the material of the second barrier layer is different from the material of the first barrier layer; The first depth is greater than the thickness of the second barrier layer and less than the sum of the thickness of the second barrier layer and the thickness of the first barrier layer.

[0015] In a third aspect, an embodiment of the present application provides an integrated circuit packaging component, comprising a substrate and a circuit layer arranged on the substrate; a barrier layer is formed on the surface of the substrate, and a first blind hole is formed in the barrier layer, the substrate layer and the circuit layer; wherein the first blind hole penetrates the barrier layer and the substrate layer and penetrates into the circuit layer, and the conductive structure in the circuit layer is exposed to the bottom of the first blind hole; at the opening of the first blind hole, there is a hole expansion section formed by a hole expansion process; the first blind hole is filled with a conductive material to form a via hole capable of conducting electricity.

[0016] According to a specific implementation of the embodiment of the present application, the expansion section is in the shape of an inverted cone with a large upper opening and a small bottom opening.

[0017] According to a specific implementation method of the embodiment of the present application, the central axis of the inverted cone reaming section coincides with the central axis of the first blind hole, and the internal opening of the inverted cone reaming section is connected to the opening of the remaining hole section of the first blind hole except the reaming section.

[0018] According to a specific implementation of the embodiment of the present application, the conductive material filled in the expansion section and the conductive material filled in the remaining hole sections of the first blind hole except the expansion section are an integrated structure.

[0019] According to a specific implementation method of an embodiment of the present application, the barrier layer includes: a first barrier layer formed on the surface of the substrate, and a second barrier layer formed on the surface of the first barrier layer; the material of the second barrier layer is different from the material of the first barrier layer; wherein the depth of the expansion section is equal to the thickness of the second barrier layer.

[0020] In a fourth aspect, an integrated circuit packaging component is characterized in that it includes a substrate and a circuit layer arranged on the substrate; a barrier layer is formed on the surface of the circuit layer; a second blind hole is formed in the barrier layer and the circuit layer; wherein the second blind hole penetrates the barrier layer and penetrates into the circuit layer, and the conductive structure in the circuit layer is exposed to the bottom of the second blind hole; at the opening of the second blind hole, there is a hole expansion section formed by a hole expansion process; the second blind hole is filled with a conductive material to form a via hole capable of conducting electricity.

[0021] According to a specific implementation of the embodiment of the present application, the expansion section is in the shape of an inverted cone with a large end opening and a small inner opening.

[0022] According to a specific implementation method of the embodiment of the present application, the central axis of the inverted cone reaming section coincides with the central axis of the second blind hole, and the internal opening of the inverted cone reaming section is connected to the opening of the remaining hole section of the second blind hole except the reaming section.

[0023] According to a specific implementation of the embodiment of the present application, the conductive material filled in the expansion section and the conductive material filled in the remaining hole sections of the second blind hole except the expansion section are an integrated structure.

[0024] According to a specific implementation method of an embodiment of the present application, the blocking layer includes: a first blocking layer formed on the surface of the circuit layer, and a second blocking layer formed on the surface of the first blocking layer; the material of the second blocking layer is different from the material of the first blocking layer; wherein the depth of the expansion section is equal to the thickness of the second blocking layer.

[0025] In a fifth aspect, an embodiment of the present application provides a packaging method for an integrated circuit device, comprising respectively manufacturing a first integrated circuit packaging component and a second integrated circuit packaging component; wherein at least one via in the first integrated circuit packaging component is formed by the via manufacturing method described in any of the aforementioned embodiments, and at least one via in the second integrated circuit packaging component is formed by the via manufacturing method described in any of the aforementioned embodiments; The first integrated circuit package component is bonded to the second integrated circuit package component, and the first via hole in the first integrated circuit package component is made to correspond to and be electrically connected to the second via hole in the second integrated circuit package component.

[0026] In a sixth aspect, an embodiment of the present application provides an integrated circuit device, including: a first integrated circuit packaging component and a second integrated circuit packaging component; wherein the first integrated circuit packaging component and the second integrated circuit packaging component are respectively the integrated circuit packaging components described in any of the foregoing embodiments, or are respectively the integrated circuit packaging components described in any of the foregoing embodiments, or the first integrated circuit packaging component is the integrated circuit packaging component described in any of the foregoing embodiments, and the second integrated circuit packaging component is the integrated circuit packaging component described in any of the foregoing embodiments; The first via in the first integrated circuit package component is electrically connected to the second via in the second integrated circuit package component.

[0027] The present embodiment provides a method for manufacturing a via hole in an integrated circuit packaging component, a packaging component, a packaging method and a circuit device, wherein the integrated circuit packaging component includes a substrate and a circuit layer arranged on the substrate, a bearing layer is formed on the surface of the circuit layer, a barrier layer is formed on the surface of the substrate, and a first blind hole is formed by etching to penetrate the barrier layer and the substrate layer and penetrate into the circuit layer, wherein the conductive structure in the circuit layer is exposed to the bottom of the first blind hole, the hole opening of the first blind hole is expanded, and a conductive material is filled in the first blind hole to form a first via hole with an integrated conductive structure. In the present embodiment, only the photolithography process is performed when manufacturing the first blind hole, and only one photomask is used, which is conducive to saving process costs. The formation of the integrated conductive structure does not have a contact layer between the through-hole filling material and the pad filling material in the existing solution, which is conducive to reducing the overall resistance. When the via hole is used to transmit a signal, it is convenient to reduce the attenuation of the transmission signal and improve the quality of the transmission signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A schematic flow chart of a method for manufacturing a via hole in an integrated circuit package assembly provided in an embodiment of the present application; Figure 2A schematic flow chart of a method for manufacturing a via in an integrated circuit package assembly provided by another embodiment of the present application; Figure 3-Figure 9 A process for making vias in an integrated circuit package assembly provided in an embodiment of the present application; Figure 10-13 A process for making vias in an integrated circuit package assembly provided by another embodiment of the present application; Fig.14 A schematic diagram of an integrated circuit device provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0031] In order to enable those skilled in the art to better understand the technical concept, implementation plan and beneficial effects of the embodiments of the present application, specific embodiments are described in detail below.

[0032] The method for manufacturing a via hole in an integrated circuit package assembly provided in the present embodiment is convenient for reducing process costs and reducing attenuation of transmission signals and improving the quality of transmission signals when using the via hole to transmit signals.

[0033] Embodiment 1 Figure 1 A schematic diagram of a process for manufacturing a via hole in an integrated circuit package assembly according to an embodiment of the present application is shown in FIG. Figure 1 As shown, the integrated circuit package assembly manufacturing method in this embodiment, the integrated circuit package assembly includes a substrate and a circuit layer provided on the substrate, and the method includes: S11, forming a bearing layer on the surface of the circuit layer.

[0034] In this embodiment, the integrated circuit packaging component can be processed from a wafer or from a grain. In the case of processing from a wafer, the wafer must first complete the front-end and back-end processes to obtain an integrated circuit packaging component. At this time, the integrated circuit packaging component includes a substrate and a circuit layer arranged on the substrate.

[0035] Since subsequent processes need to be performed on the back side of the wafer and the front side of the wafer needs to be protected, a carrier layer is formed on the surface of the circuit layer. In one example, the carrier layer can be formed by bonding the processed wafer face down to a temporary silicon carrier.

[0036] S12, forming a barrier layer on the surface of the substrate.

[0037] After forming the carrier layer on the surface of the circuit layer, the wafer is thinned from the back of the wafer to a target thickness, which is determined by the product characteristics. For example, in one embodiment of the invention, the target thickness is 15-20 μm. After thinning, the wafer is deposited with material on the surface of the substrate to form a barrier layer, which can be developed more conveniently to provide basic conditions for etching.

[0038] S13. Forming a first blind hole penetrating the barrier layer and the substrate layer and extending into the circuit layer by etching; wherein the conductive structure in the circuit layer is exposed at the bottom of the first blind hole.

[0039] A photoresist is coated on the barrier layer, and through an exposure, development and etching process, etching is performed in the barrier layer in the direction of the metal layer to a certain depth, thereby forming a first blind hole that penetrates the barrier layer and the substrate layer and penetrates into the circuit layer. The circuit layer includes a plurality of conductive structures connected together, and the conductive structures in the circuit layer are exposed at the bottom of the first blind hole.

[0040] S14, expanding the opening of the first blind hole.

[0041] In order to increase the contact area of ​​the hybrid bonding and ensure sufficient connection during subsequent bonding, the opening of the first blind hole is enlarged. The first via hole is filled with an etching protection material, and the etching protection material in the first via hole is back-etched from the opening of the first blind hole to the bottom of the first via hole to a preset depth, so that the side wall of the first via hole corresponding to the preset depth is exposed, and the exposed side wall of the first blind hole is etched to increase the opening area of ​​the first blind hole after etching.

[0042] In this embodiment, the cross-sectional shape of the first blind hole may be any shape. In some examples, the cross-sectional shape may be circular, and in other examples, the cross-sectional shape may be rectangular or square.

[0043] S15. Filling the first blind hole with a conductive material to form a first via hole with an integrated conductive structure.

[0044] After increasing the opening area of ​​the first blind hole, the remaining etching protection material is cleaned off, and a conductive material is filled in the first blind hole to form a first via with an integrated conductive structure with a smooth contact surface. In some examples, when filling the first blind hole with the conductive material, copper material is filled in the first blind hole to form a metal wire, and the surface of the wafer is ground and polished to make it more flat for subsequent process steps.

[0045] After the expanded hole section of the first blind hole is filled with conductive material, it can be used as a pad, and the integrated circuit package components containing such a pad structure can be interconnected through the pad.

[0046] In this embodiment, a carrier layer is formed on the surface of the circuit layer, a barrier layer is formed on the surface of the substrate, and a first blind hole is formed by etching, which penetrates the barrier layer and the substrate layer and penetrates into the circuit layer. The opening of the first blind hole is further enlarged, and a conductive material is filled in the first blind hole after the enlargement, thereby forming a first via with an integrated conductive structure. In this embodiment, only the photolithography process is performed when making the first blind hole, and a photomask can be used, which is conducive to saving process costs. The formation of an integrated structure does not have a contact layer between the through-hole filling material and the pad filling material in the existing solution, which is conducive to reducing the overall resistance. When the via is used to transmit a signal, it is convenient to reduce the attenuation of the transmission signal and improve the quality of the transmission signal.

[0047] When the through hole is enlarged, the hole can be enlarged directly or filled with a protective material for enlargement. After the through hole is filled with the material, the hole wall of other hole sections can be not damaged while the hole is enlarged.

[0048] In some embodiments, the step of expanding the opening of the first blind hole (step S14) includes: S14a, filling the first blind hole with an etching protection material.

[0049] When expanding the opening of the first blind hole, the first blind hole is first filled with an etching protection material, in one example, the etching protection material is a photoresist, and then the etching protection material is completely filled along the direction from the opening of the first blind hole to the bottom of the hole, and the surface of the barrier layer is also covered with the etching protection material.

[0050] S14b, etching the etching protection material filled in the first blind hole to a first depth along the direction from the hole mouth to the bottom of the first blind hole and reserving the etching protection material of a second depth in the blind hole to expose the side wall at the hole mouth of the first blind hole; the sum of the second depth and the first depth is equal to the depth of the blind hole.

[0051] The first blind hole filled with the etching protection material is etched back to the first depth, the etching protection material on the through hole and the surface of the barrier layer within the first depth range is cleaned, and the etching protection material of the second depth is reserved in the blind hole, and the etching protection material of the second depth is used to protect the hole section of the first blind hole other than the first depth from being affected by subsequent processes, so as to expose the side wall at the first depth of the first blind hole. The sum of the second depth and the first depth is equal to the depth of the first blind hole.

[0052] S14c, etching the sidewall of the first blind hole at the opening to enlarge the aperture of the first blind hole at the opening.

[0053] The side wall at the first depth opening of the exposed first blind hole is etched so that the opening of the etched first blind hole is a conical surface with a preset angle, thereby enlarging the aperture at the opening of the first blind hole, wherein the larger the preset angle, the larger the aperture, and the aperture size is determined by the size of the mask used when etching to form the first blind hole.

[0054] In some embodiments, etching the side wall at the opening of the first blind hole to expand the aperture at the opening of the first blind hole includes: etching the side wall at the opening of the first blind hole to form an inverted cone-shaped expansion section with a large end opening and a small internal opening at the opening of the first blind hole.

[0055] In order to expand the opening area, in this embodiment, etching is performed downward at a preset angle from the horizontal direction of the side wall at the opening of the first blind hole to form an inverted cone-shaped expansion section with a large end opening and a small internal opening, wherein the end opening is the opening of the first blind hole after the aperture is enlarged, the internal opening is the cross-section of the through hole at the first depth, and the aperture of the end opening is larger than the aperture of the internal opening.

[0056] In some embodiments, the etching of the side wall at the opening of the first blind hole to form an inverted cone-shaped expansion section with a large end opening and a small inner opening at the opening of the first blind hole includes: etching the side wall at the opening of the first blind hole to form an inverted cone-shaped expansion section with a large end opening and a small inner opening at the opening of the first blind hole, and making the central axis of the inverted cone-shaped expansion section coincide with the central axis of the first blind hole, and the inner opening of the inverted cone-shaped expansion section is connected to the openings of the remaining hole sections of the first blind hole except the expansion section.

[0057] In order to expand the opening area of ​​the blind hole, the etching protection material of the second depth is reserved in the blind hole, and the side wall at the hole mouth of the first blind hole is etched to form an inverted cone expansion section, and the central axis of the cross section of the inverted cone expansion section coincides with the central axis of the cross section of the first blind hole. The internal opening of the inverted cone expansion section refers to the cross section of the through hole at the first depth mentioned above, and the remaining hole section of the first blind hole except the expansion section refers to the through hole opening below the first depth and filled with etching protection material. The two openings are naturally connected without size mutation.

[0058] In some embodiments, forming a barrier layer on the surface of the substrate includes: forming a first barrier layer on the surface of the substrate, and forming a second barrier layer on the surface of the first barrier layer; the material of the second barrier layer is different from the material of the first barrier layer; wherein the first depth is greater than the thickness of the second barrier layer and less than the sum of the thickness of the second barrier layer and the thickness of the first barrier layer.

[0059] Before forming the first blind hole in the integrated circuit packaging assembly, a carrier layer is formed on the surface of the circuit layer, and a material is deposited on the surface of the substrate to form a barrier layer.

[0060] The barrier layer may include a first barrier layer formed on the surface of the substrate and a second barrier layer formed on the surface of the first barrier layer, wherein the material of the first barrier layer is different from the material of the second barrier layer. The material of the first barrier layer may be silicon dioxide or other low dielectric constant materials; any material having a significant etching selectivity ratio with the first barrier layer may be used as the second barrier layer, and the material of the second barrier layer may be silicon nitride or titanium nitride.

[0061] The thickness of the barrier layer deposition material is related to the first depth mentioned in the above embodiment. The first depth is greater than the thickness of the second barrier layer deposition material and less than the sum of the thickness of the second barrier layer deposition material and the thickness of the first barrier layer deposition material.

[0062] In the above embodiments, in order to increase the contact area of ​​the hybrid bonding and form a via with an integrated structure, lateral etching is performed after forming the first blind hole instead of directly using a mask, thereby reducing the number of masks from two to one, thereby reducing costs and process implementation steps, which is beneficial to manufacturing and yield. The via with an integrated structure optimizes the impedance discontinuity point, which is beneficial to signal transmission.

[0063] Embodiment 2 Figure 2 A schematic diagram of a process for manufacturing a via hole in an integrated circuit package assembly according to another embodiment of the present application is shown in FIG. Figure 2 As shown, a method for manufacturing a via in an integrated circuit package assembly in this embodiment, wherein the integrated circuit package assembly includes a substrate and a circuit layer provided on the substrate, and the method includes: S21, forming a barrier layer on the surface of the circuit layer.

[0064] In this embodiment, the integrated circuit package assembly can be processed from a wafer or from a crystal grain. In the case of processing from a wafer, the wafer must first complete the front-end and back-end processes to obtain an integrated circuit package assembly. At this time, the integrated circuit package assembly includes a substrate and a circuit layer provided on the substrate. A barrier layer is formed on the surface of the circuit layer. In one example, a material can be deposited on the processed wafer surface to form a barrier layer. Development can be performed more conveniently on the barrier layer to provide basic conditions for etching.

[0065] S22. Form a second blind hole penetrating the barrier layer and extending into the circuit layer by etching; wherein the conductive structure in the circuit layer is exposed at the bottom of the second blind hole.

[0066] A photoresist is coated on the barrier layer, and through an exposure, development and etching process, etching is performed in the barrier layer in the direction of the metal layer to a certain depth, thereby forming a second blind hole that penetrates the barrier layer and the substrate layer and penetrates into the circuit layer. The circuit layer includes a plurality of conductive structures connected together, and the conductive structures in the circuit layer are exposed at the bottom of the second blind hole.

[0067] S23, expanding the opening of the second blind hole.

[0068] In order to increase the contact area of ​​the hybrid bonding and ensure sufficient connection during subsequent bonding, the opening of the second blind hole is enlarged. The etching protection material is filled in the first via hole, and the etching protection material in the second via hole is back-etched from the opening of the second blind hole to the bottom of the second via hole to a preset depth, so that the side wall of the second via hole corresponding to the preset depth is exposed, and the exposed side wall of the second blind hole is etched to increase the opening area of ​​the etched second blind hole.

[0069] In this embodiment, the cross-sectional shape of the second blind hole may be any shape. In some examples, the cross-sectional shape may be circular, and in other examples, the cross-sectional shape may be rectangular or square.

[0070] S24, filling the second blind hole with a conductive material to form a second via hole with an integrated conductive structure.

[0071] After increasing the opening area of ​​the second blind hole, the remaining etching protection material is cleaned off, and a conductive material is filled in the second blind hole to form a second via with a smooth contact surface and an integrated conductive structure. In some examples, when filling the second blind hole with the conductive material, copper material is filled in the second blind hole to form a metal wire, and the surface of the wafer is ground and polished to make it flatter for subsequent process steps.

[0072] In this embodiment, a barrier layer is formed on the surface of the circuit layer, and a second blind hole is formed by etching to penetrate the barrier layer and penetrate into the circuit layer. The opening of the second blind hole is further expanded, and a conductive material is filled in the expanded second blind hole to form a second via with an integrated conductive structure. Since the second via has an integrated conductive structure, the opening of the expanded hole section of the integrated conductive structure is naturally connected to the opening of the remaining hole section of the second blind hole except the expanded hole section. There is no contact layer between the through-hole filling material and the pad filling material in the existing solution, which is conducive to reducing the overall resistance and optimizing the impedance discontinuity point between the through-hole and the pad. When the second via with an integrated conductive structure is used to transmit signals, it is convenient to reduce the reflection of the transmitted signal and improve the quality of the transmitted signal.

[0073] In some embodiments, the step of expanding the opening of the second blind hole (S23) includes: S23a, filling the second blind hole with an etching protection material; When expanding the opening of the second blind hole, the second blind hole is first filled with an etching protection material, in one example, the etching protection material is a photoresist, and then the etching protection material is completely filled along the direction from the opening of the second blind hole to the bottom of the hole, and the surface of the barrier layer is also covered with the etching protection material.

[0074] S23b, etching the etching protection material filled in the second blind hole to a first depth along the direction from the hole opening to the hole bottom of the second blind hole and reserving the etching protection material of a second depth in the second blind hole to expose the side wall at the hole opening of the second blind hole; After the second blind hole is filled with the etching protection material, the etching is performed back to the first depth, the etching protection material on the surface of the through hole and the barrier layer within the first depth range is cleaned, and the etching protection material of the second depth is reserved in the blind hole. The etching protection material of the second depth is used to protect the hole section of the second blind hole other than the first depth from being affected by subsequent processes, so as to expose the side wall of the first depth hole mouth of the second blind hole. The sum of the first depth and the second depth is the depth of the second blind hole.

[0075] S24c, etching the side wall at the opening of the second blind hole to enlarge the aperture at the opening of the second blind hole.

[0076] The side wall at the first depth opening of the exposed second blind hole is etched so that the opening of the etched second blind hole is a conical surface with a preset angle, thereby enlarging the aperture at the opening of the second blind hole, wherein the larger the preset angle, the larger the aperture, and the aperture size is determined by the size of the mask used when etching the second blind hole.

[0077] In some embodiments, etching the side wall at the opening of the second blind hole to expand the aperture at the opening of the second blind hole includes: etching the side wall at the opening of the second blind hole to form an inverted cone-shaped expansion section with a large end opening and a small internal opening at the opening of the second blind hole.

[0078] In order to expand the opening area, in this embodiment, etching is performed downward at a preset angle from the horizontal direction of the side wall at the opening of the second blind hole to form an inverted cone-shaped expansion section with a large end opening and a small internal opening, wherein the end opening is the opening of the second blind hole after the aperture is enlarged, the internal opening is the cross-section of the through hole at the first depth, and the aperture of the end opening is larger than the aperture of the internal opening.

[0079] In some embodiments, the etching of the side wall at the opening of the second blind hole to form an inverted cone-shaped expansion section with a large end opening and a small inner opening at the opening of the second blind hole includes: etching the side wall at the opening of the second blind hole to form an inverted cone-shaped expansion section with a large end opening and a small inner opening at the opening of the second blind hole, and making the central axis of the inverted cone-shaped expansion section coincide with the central axis of the second blind hole, and the inner opening of the inverted cone-shaped expansion section is connected to the openings of the remaining hole sections of the second blind hole except the expansion section.

[0080] In order to expand the opening area of ​​the blind hole, the etching protection material of the second depth is reserved in the blind hole, and the side wall at the hole mouth of the second blind hole is etched to form an inverted cone expansion section, and the central axis of the cross section of the inverted cone expansion section coincides with the central axis of the cross section of the second blind hole. And the internal opening of the inverted cone expansion section is connected to the opening of the remaining hole section of the second blind hole except the expansion section, wherein the internal opening of the inverted cone expansion section refers to the cross section of the through hole at the first depth mentioned above, and the remaining hole section of the second blind hole except the expansion section refers to the opening of the through hole filled with etching protection material below the first depth, and the two openings are naturally connected without size mutation.

[0081] In some embodiments, forming a barrier layer on the surface of the circuit layer includes: forming a first barrier layer on the surface of the circuit layer, and forming a second barrier layer on the surface of the first barrier layer; the material of the second barrier layer is different from the material of the first barrier layer; wherein the first depth is greater than the thickness of the second barrier layer and less than the sum of the thickness of the second barrier layer and the thickness of the first barrier layer.

[0082] Before forming the second blind hole in the integrated circuit packaging component, a barrier layer is formed on the surface of the circuit layer. The barrier layer may include a first barrier layer formed on the surface of the circuit layer and a second barrier layer formed on the surface of the first barrier layer, and the material of the first barrier layer is different from the material of the second barrier layer. The material of the first barrier layer may be silicon dioxide or other low dielectric constant materials; any material with a significant etching selectivity ratio with the first barrier layer may be used as the second barrier layer, and the material of the second barrier layer may be silicon nitride or titanium nitride.

[0083] The thickness of the barrier layer deposition material is related to the first depth mentioned in the above embodiment. The first depth is greater than the thickness of the second barrier layer deposition material and less than the sum of the thickness of the second barrier layer deposition material and the thickness of the first barrier layer deposition material.

[0084] In the above embodiments, in order to increase the contact area of ​​the hybrid bonding and form a via with an integrated structure, lateral etching is performed after forming the second blind hole instead of directly using a mask, thereby reducing the number of masks from two to one, thereby reducing costs and process implementation steps, which is beneficial to manufacturing and yield. The via with an integrated structure optimizes the impedance discontinuity point, which is beneficial to signal transmission.

[0085] Embodiment 3 This embodiment provides an integrated circuit packaging component, such as Figure 3-9 As shown, it includes a substrate 11 and a circuit layer 12 arranged on the substrate 11; a barrier layer 13 is formed on the surface of the substrate 11; a first blind hole 14 is formed in the barrier layer 13 and the circuit layer 12; wherein the first blind hole 14 penetrates the barrier layer 13 and penetrates into the circuit layer 12, and the conductive structure 15 in the circuit layer 12 is exposed to the bottom of the first blind hole 14; at the opening of the first blind hole 14, there is an expansion section formed by an expansion process; the first blind hole 14 is filled with a conductive material to form a via 16 capable of conducting electricity.

[0086] In this embodiment, a carrier layer is formed on the surface of the circuit layer, a barrier layer is formed on the surface of the substrate, and a first blind hole is formed by etching, which penetrates the barrier layer and the substrate layer and penetrates into the circuit layer. The opening of the first blind hole is further enlarged, and a conductive material is filled in the first blind hole after the enlargement, thereby forming a conductive via. In this embodiment, only the photolithography process is performed when making the first blind hole, and a photomask can be used, which is conducive to saving process costs. The enlarged hole section formed by the hole enlargement process does not have a contact layer between the through-hole filling material and the pad filling material in the existing solution, which is conducive to reducing the overall resistance. When the via is used to transmit a signal, it is convenient to reduce the attenuation of the transmission signal and improve the quality of the transmission signal.

[0087] Common substrate materials include single crystal silicon, sapphire with high hardness and transparency, silicon carbide for specific applications, etc., which are used to manufacture integrated circuit devices. In one embodiment of the present invention, the substrate material is single crystal silicon, and the wafer is thinned from the back of the wafer to a target thickness, which is determined by the product characteristics. After thinning, the wafer deposits material on the surface of the substrate to form a barrier layer.

[0088] Since subsequent processes need to be performed on the back side of the wafer and the front side of the wafer needs to be protected, a carrier layer is formed on the surface of the circuit layer. In one example, the carrier layer can be formed by bonding the processed wafer face down to a temporary silicon carrier.

[0089] A photoresist is coated on the barrier layer, and through an exposure, development and etching process, etching is performed in the barrier layer in the direction of the metal layer to a certain depth, thereby forming a first blind hole that penetrates the barrier layer and the substrate layer and penetrates into the circuit layer. The circuit layer includes a plurality of conductive structures connected together, and the conductive structures in the circuit layer are exposed at the bottom of the first blind hole.

[0090] In order to increase the contact area of ​​the hybrid bonding and ensure sufficient connection during subsequent bonding, the opening of the first blind hole is enlarged. The first via hole is filled with an etching protection material, and the etching protection material in the first blind hole is back-etched from the opening of the first blind hole to the bottom of the first blind hole to a preset depth, so that the side wall of the first blind hole corresponding to the preset depth is exposed, and the exposed side wall of the first blind hole is etched to increase the opening area of ​​the first blind hole after etching.

[0091] In this embodiment, the cross-sectional shape of the first blind hole may be any shape. In some examples, the cross-sectional shape may be circular, and in other examples, the cross-sectional shape may be rectangular or square.

[0092] After increasing the opening area of ​​the first blind hole, the remaining etching protection material is cleaned off, and a conductive material is filled in the first blind hole to form a first via with an integrated conductive structure with a smooth contact surface. In some examples, when filling the first blind hole with the conductive material, copper material is filled in the first blind hole to form a metal wire, and the surface of the wafer is ground and polished to make it more flat for subsequent process steps.

[0093] In some embodiments, the expansion section is in the shape of an inverted cone with a large end opening and a small inner opening.

[0094] In order to expand the opening area, in this embodiment, etching is performed downward at a preset angle from the horizontal direction of the side wall at the opening of the first blind hole to form an inverted cone-shaped expansion section with a large end opening and a small internal opening, wherein the end opening is the opening of the first blind hole after the aperture is enlarged, the internal opening is the cross-section of the through hole at the first depth, and the aperture of the end opening is larger than the aperture of the internal opening.

[0095] In some embodiments, the central axis of the inverted cone-shaped expansion section coincides with the central axis of the first blind hole, and the inner opening of the inverted cone-shaped expansion section is connected to the opening of the remaining hole sections of the first blind hole except the expansion section.

[0096] In order to expand the opening area of ​​the blind hole, an etching protection material of the first depth is reserved in the blind hole, and the side wall at the opening of the first blind hole is etched to form an inverted cone expansion section, and the central axis of the cross section of the inverted cone expansion section coincides with the central axis of the cross section of the first blind hole. The internal opening of the inverted cone expansion section refers to the cross section of the through hole at the first depth mentioned above, and the remaining hole section of the first blind hole except the expansion section refers to the through hole opening below the first depth and filled with etching protection material. The two openings are naturally connected without size mutation.

[0097] In some embodiments, the conductive material filled in the hole expansion section and the conductive material filled in the remaining hole sections of the first blind hole except the hole expansion section are an integrated structure.

[0098] A conductive material is filled in the first blind hole to form a first via having an integrated conductive structure with a smooth contact surface. In some examples, when the conductive material is filled in the first blind hole, copper material is filled in the first blind hole to form a metal wire, and the surface of the wafer is ground and polished to make it flatter for subsequent process steps.

[0099] In some embodiments, the barrier layer includes: a first barrier layer formed on the surface of the circuit layer, and a second barrier layer formed on the surface of the first barrier layer; the material of the second barrier layer is different from that of the first barrier layer; Wherein, the depth of the expansion section is equal to the thickness of the second barrier layer.

[0100] Before forming the first blind hole in the integrated circuit packaging component, a barrier layer is formed on the surface of the circuit layer. The barrier layer may include a first barrier layer formed on the surface of the circuit layer and a second barrier layer formed on the surface of the first barrier layer, and the material of the first barrier layer is different from the material of the second barrier layer. The material of the first barrier layer may be silicon dioxide or other low dielectric constant materials; any material with a significant etching selectivity ratio with the first barrier layer may be used as the second barrier layer, and the material of the second barrier layer may be silicon nitride or titanium nitride. The depth of the expansion section is equal to the thickness of the second barrier layer.

[0101] Embodiment 4 This embodiment provides an integrated circuit packaging component, such as Figure 10-13As shown, it includes a substrate 21 and a circuit layer 22 arranged on the substrate 21; a barrier layer 23 is formed on the surface of the circuit layer 22; a second blind hole 24 is formed in the barrier layer 23 and the circuit layer 22; wherein the second blind hole 24 penetrates the barrier layer 23 and penetrates into the circuit layer 22, and the conductive structure 25 in the circuit layer 22 is exposed at the bottom of the second blind hole 24; at the opening of the second blind hole 24, there is a hole expansion section formed by a hole expansion process; the second blind hole 24 is filled with a conductive material to form a via 26 capable of conducting electricity.

[0102] In this embodiment, a barrier layer is formed on the surface of the circuit layer, and a second blind hole is formed by etching to penetrate the barrier layer and penetrate into the circuit layer, and then the opening of the second blind hole is further expanded, and a conductive material is filled in the expanded second blind hole to form a conductive via. In this embodiment, a photolithography process is only performed when making the second blind hole, and a photomask can be used, which is conducive to saving process costs. The expanded hole section formed by the expansion process does not have a contact layer between the through-hole filling material and the pad filling material in the existing solution, which is conducive to reducing the overall resistance. When the via is used to transmit a signal, it is convenient to reduce the attenuation of the transmission signal and improve the quality of the transmission signal.

[0103] The circuit layer is a conductive layer used for signal transmission and power distribution inside the integrated circuit packaging component. A barrier layer is formed on the surface of the circuit layer. In an example, material can be deposited on the processed wafer surface to form a barrier layer. Development can be carried out more conveniently on the barrier layer to provide basic conditions for etching.

[0104] A photoresist is coated on the barrier layer, and through an exposure, development and etching process, etching is performed in the barrier layer in the direction of the metal layer to a certain depth, thereby forming a first blind hole that penetrates the barrier layer and the substrate layer and penetrates into the circuit layer. The circuit layer includes a plurality of conductive structures connected together, and the conductive structures in the circuit layer are exposed at the bottom of the second blind hole.

[0105] In order to increase the contact area of ​​the hybrid bonding and ensure sufficient connection during subsequent bonding, the opening of the second blind hole is enlarged. The etching protection material is filled in the second via hole, and the etching protection material in the second blind hole is back-etched from the opening of the second blind hole to the bottom of the second blind hole to a preset depth, so that the side wall of the second blind hole corresponding to the preset depth is exposed, and the exposed side wall of the second blind hole is etched to increase the opening area of ​​the etched second blind hole.

[0106] In this embodiment, the cross-sectional shape of the second blind hole may be any shape. In some examples, the cross-sectional shape may be circular, and in other examples, the cross-sectional shape may be rectangular or square.

[0107] After increasing the opening area of ​​the second blind hole, the remaining etching protection material is cleaned off, and a conductive material is filled in the second blind hole to form a second via with a smooth contact surface and an integrated conductive structure. In some examples, when filling the second blind hole with the conductive material, copper material is filled in the second blind hole to form a metal wire, and the surface of the wafer is ground and polished to make it flatter for subsequent process steps.

[0108] In some embodiments, the expansion section is in the shape of an inverted cone with a large end opening and a small inner opening.

[0109] In order to expand the opening area, in this embodiment, etching is performed downward at a preset angle from the horizontal direction of the side wall at the opening of the second blind hole to form an inverted cone-shaped expansion section with a large end opening and a small internal opening, wherein the end opening is the opening of the second blind hole after the aperture is enlarged, the internal opening is the cross-section of the through hole at the first depth, and the aperture of the end opening is larger than the aperture of the internal opening.

[0110] In some embodiments, the central axis of the inverted cone-shaped expansion section coincides with the central axis of the second blind hole, and the inner opening of the inverted cone-shaped expansion section is connected to the opening of the remaining hole section of the second blind hole except the expansion section.

[0111] In order to expand the opening area of ​​the blind hole, an etching protection material of the second depth is reserved in the blind hole, and the side wall at the hole mouth of the second blind hole is etched to form an inverted cone expansion section, and the central axis of the cross section of the inverted cone expansion section coincides with the central axis of the cross section of the second blind hole. The internal opening of the inverted cone expansion section refers to the cross section of the through hole at the first depth mentioned above, and the remaining hole section of the second blind hole except the expansion section refers to the through hole opening below the first depth and filled with etching protection material. The two openings are naturally connected without size mutation.

[0112] In some embodiments, the conductive material filled in the hole expansion section and the conductive material filled in the remaining hole sections of the second blind hole except the hole expansion section are an integrated structure.

[0113] A conductive material is filled in the second blind hole to form a second via with an integrated conductive structure having a smooth contact surface. In some examples, when the conductive material is filled in the second blind hole, copper material is filled in the second blind hole to form a metal conductor. The surface of the wafer is ground and polished to make it flatter for subsequent process steps.

[0114] In some embodiments, the barrier layer includes: a first barrier layer formed on the surface of the circuit layer, and a second barrier layer formed on the surface of the first barrier layer; the material of the second barrier layer is different from that of the first barrier layer; Wherein, the depth of the expansion section is equal to the thickness of the second barrier layer.

[0115] Before forming the second blind hole in the integrated circuit package assembly, a barrier layer is formed on the surface of the circuit layer. The barrier layer may include a first barrier layer formed on the surface of the circuit layer and a second barrier layer formed on the surface of the first barrier layer, and the material of the first barrier layer is different from the material of the second barrier layer. The material of the first barrier layer may be silicon dioxide or other low dielectric constant materials; any material with a significant etching selectivity ratio with the first barrier layer may be used as the second barrier layer, and the material of the second barrier layer may be silicon nitride or titanium nitride. The depth of the expansion section is equal to the thickness of the second barrier layer.

[0116] The solution of the present application is described in detail below with a specific embodiment.

[0117] See also Figure 4-9 The method for manufacturing a via in an integrated circuit package assembly of this embodiment may include: S31, forming a bearing layer on the surface of the circuit layer, and forming a barrier layer on the surface of the substrate, the result is as follows Figure 4 shown.

[0118] See also Figure 4 The integrated circuit package assembly includes a substrate 11 and a circuit layer 12 disposed on the substrate 11. The circuit layer 12 includes a plurality of conductive structures 15 connected together. A carrier layer 10 is formed on the surface of the circuit layer 12. A barrier layer 13 is formed on the surface of the substrate 11. The barrier layer 13 includes a first barrier layer 13a and a second barrier layer 13b deposited sequentially on the surface of the substrate 11. The material of the first barrier layer 13a is silicon dioxide (SiO2), and the material of the second barrier layer 13b is silicon nitride (SIN).

[0119] The present embodiment is not limited to this. In other embodiments, a barrier layer may also be deposited on the surface of the metal layer. The via method is the same as that of the present embodiment, which will be described in detail below. The process of depositing a barrier layer on a substrate or other layers is a prior art and will not be repeated here.

[0120] S32, perform the first etching to form the first blind hole. The result is as follows Figure 4 shown.

[0121] Figure 4 The via morphology after forming the first blind hole is shown in FIG. 14 is formed by photolithography, etching, cleaning and other processes. The first blind hole penetrates the barrier layer and the substrate layer and penetrates into the circuit layer. The conductive structure 15 in the circuit layer is exposed at the bottom of the first blind hole.

[0122] S33, filling the first blind hole with etching protection material, and expanding the opening of the first blind hole. Figure 5-8 shown.

[0123] like Figure 5 As shown in FIG. 1 , an etching protection material, such as photoresist, is filled in the blind hole to fill the first blind hole. Figure 6 As shown, etching is performed from the hole mouth to the first depth, the etching protection material on the surface of the through hole and the barrier layer within the first depth range is cleaned, and the etching protection material is reserved in the hole section outside the first depth of the first blind hole to expose the side wall at the hole mouth of the first blind hole. Figure 7 As shown in FIG. 1 , the side wall of the first blind hole is etched to form an inverted cone-shaped expansion section with a large end opening and a small inner opening at the opening of the first blind hole, so that the central axis of the inverted cone-shaped expansion section coincides with the central axis of the second blind hole and is connected to the opening of the remaining hole sections of the first blind hole except the expansion section, as shown in FIG. Figure 8 As shown, the remaining etch protection material is cleaned away.

[0124] S34, filling the first blind hole with a conductive material to form a first via hole with an integrated conductive structure, such as Fig. 9 shown.

[0125] Fig. 9 After the hole expansion is completed, the first blind hole is filled with conductive material to form a final via morphology with an integrated conductive structure. Copper material is filled into the first blind hole to form a metal conductor, and the surface of the wafer is ground and polished to make it more flat.

[0126] Embodiment 5 The present embodiment provides a packaging method for an integrated circuit device, comprising separately manufacturing a first integrated circuit packaging component and a second integrated circuit packaging component; wherein, at least one via in the first integrated circuit packaging component is formed by the via manufacturing method described in the above-mentioned embodiment 1, and at least one via in the second integrated circuit packaging component is formed by the via manufacturing method described in the above-mentioned embodiment 2; the first integrated circuit packaging component is bonded to the second integrated circuit packaging component, and the first via in the first integrated circuit packaging component is made to correspond to and electrically connect with the second via in the second integrated circuit packaging component.

[0127] The packaging method of vias in the integrated circuit packaging component of the present embodiment includes making a first integrated circuit packaging component and a second integrated circuit packaging component respectively. In the present embodiment, the photolithography process is only performed when making the first blind hole of the first integrated circuit packaging component and the second blind hole of the second integrated circuit packaging component, and one photomask can be used each time, which is conducive to saving process costs. The first blind hole and the second blind hole are enlarged and filled with conductive materials to form a first via and a second via with an integrated conductive structure. The formation of the integrated structure does not have a contact layer between the through-hole filling material and the pad filling material in the existing solution, which is conducive to reducing the overall resistance. When the via is used to transmit a signal, it is convenient to reduce the attenuation of the transmission signal and improve the quality of the transmission signal.

[0128] Embodiment 6 like Fig.14 As shown, this embodiment provides an integrated circuit device, including a first integrated circuit packaging component 31 and a second integrated circuit packaging component 32; wherein, the first integrated circuit packaging component 31 and the second integrated circuit packaging component 32 are respectively the integrated circuit packaging components described in the above-mentioned embodiment three, or are respectively the integrated circuit packaging components described in the above-mentioned embodiment four, or the first integrated circuit packaging component is the integrated circuit packaging component described in the above-mentioned embodiment three, and the second integrated circuit packaging component is the integrated circuit packaging component described in the above-mentioned embodiment four; the first via in the first integrated circuit packaging component is electrically connected to the second via in the second integrated circuit packaging component.

[0129] The integrated circuit device of this embodiment includes a first integrated circuit package component and a second integrated circuit package component. In this embodiment, the photolithography process is only performed when making the first blind hole of the first integrated circuit package component and the second blind hole of the second integrated circuit package component, and one mask can be used each time, which is conducive to saving process costs. The first blind hole and the second blind hole are enlarged and filled with conductive materials to form a first via and a second via with an integrated conductive structure. The formation of the integrated structure does not have a contact layer between the through-hole filling material and the pad filling material in the existing solution, which is conducive to reducing the overall resistance. When the via is used to transmit a signal, it is convenient to reduce the attenuation of the transmission signal and improve the quality of the transmission signal.

[0130] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0131] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0132] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for making a via in an integrated circuit package component, characterized in that: The integrated circuit package assembly comprises a substrate and a circuit layer arranged on the substrate; the method comprises: forming a bearing layer on the surface of the circuit layer; forming a barrier layer on the surface of the substrate; By etching, a first blind hole is formed which penetrates the barrier layer and the substrate layer and penetrates into the circuit layer; wherein the conductive structure in the circuit layer is exposed at the bottom of the first blind hole; Expanding the opening of the first blind hole; A conductive material is filled in the first blind hole to form a first via hole with an integrated conductive structure.

2. The method for making a via hole according to claim 1, characterized in that: The step of expanding the opening of the first blind hole comprises: Filling the first blind hole with an etching protection material; Along the direction from the opening to the bottom of the first blind hole, the etching protection material filled in the first blind hole is etched to a first depth and the etching protection material of a second depth is reserved in the blind hole to expose the side wall at the opening of the first blind hole; the sum of the second depth and the first depth is equal to the depth of the blind hole; The sidewall of the first blind hole at the hole opening is etched to enlarge the hole diameter at the hole opening of the first blind hole.

3. The method for making a via hole according to claim 2, characterized in that: The etching of the sidewall of the first blind hole at the opening of the first blind hole to enlarge the aperture of the first blind hole at the opening of the first blind hole comprises: The side wall at the opening of the first blind hole is etched to form an inverted tapered expansion section with a large end opening and a small inner opening at the opening of the first blind hole.

4. The method for making a via hole according to claim 3, characterized in that: The step of etching the side wall of the first blind hole at the opening of the first blind hole to form an inverted tapered expansion section with a large end opening and a small inner opening at the opening of the first blind hole comprises: The side wall at the opening of the first blind hole is etched to form an inverted cone-shaped expansion section with a large end opening and a small internal opening at the opening of the first blind hole, and the central axis of the inverted cone-shaped expansion section coincides with the central axis of the first blind hole, and the internal opening of the inverted cone-shaped expansion section is connected to the opening of the remaining hole sections of the first blind hole except the expansion section.

5. The method for making a via hole according to claim 2, characterized in that: The forming of the barrier layer on the surface of the substrate comprises: forming a first barrier layer on the surface of the substrate, and forming a second barrier layer on the surface of the first barrier layer; the material of the second barrier layer is different from that of the first barrier layer; The first depth is greater than the thickness of the second barrier layer and less than the sum of the thickness of the second barrier layer and the thickness of the first barrier layer.

6. A method for making a via in an integrated circuit package assembly, characterized in that: The integrated circuit package assembly comprises a substrate and a circuit layer arranged on the substrate; the method comprises: forming a barrier layer on the surface of the circuit layer; By etching, a second blind hole is formed which penetrates the barrier layer and penetrates into the circuit layer; wherein the conductive structure in the circuit layer is exposed at the bottom of the second blind hole; Expanding the opening of the second blind hole; The second blind hole is filled with a conductive material to form a second via hole with an integrated conductive structure.

7. The method for making a via hole according to claim 6, characterized in that: The step of expanding the opening of the second blind hole comprises: Filling the second blind hole with an etching protection material; Along the direction from the opening to the bottom of the second blind hole, the etching protection material filled in the second blind hole is etched to a first depth and the etching protection material of a second depth is reserved in the second blind hole to expose the side wall at the opening of the second blind hole; The sidewall of the second blind hole at the opening is etched to enlarge the aperture of the second blind hole at the opening.

8. The method for making a via hole according to claim 7, characterized in that: The etching of the sidewall of the second blind hole at the opening of the second blind hole to enlarge the aperture of the second blind hole at the opening of the second blind hole comprises: The side wall at the opening of the second blind hole is etched to form an inverted tapered expansion section with a large end opening and a small inner opening at the opening of the second blind hole.

9. The method for making a via hole according to claim 8, characterized in that: The step of etching the side wall at the opening of the second blind hole to form an inverted tapered expansion section with a large end opening and a small inner opening at the opening of the second blind hole comprises: The side wall at the opening of the second blind hole is etched to form an inverted cone-shaped expansion section with a large end opening and a small internal opening at the opening of the second blind hole, and the central axis of the inverted cone-shaped expansion section coincides with the central axis of the second blind hole, and the internal opening of the inverted cone-shaped expansion section is connected to the opening of the remaining hole sections of the second blind hole except the expansion section.

10. The method for making a via hole according to claim 7, characterized in that: The forming of the barrier layer on the surface of the circuit layer comprises: forming a first barrier layer on the surface of the circuit layer, and forming a second barrier layer on the surface of the first barrier layer; the material of the second barrier layer is different from the material of the first barrier layer; The first depth is greater than the thickness of the second barrier layer and less than the sum of the thickness of the second barrier layer and the thickness of the first barrier layer.

11. An integrated circuit package assembly, characterized in that: comprising a substrate and a circuit layer disposed on the substrate; A barrier layer is formed on the surface of the substrate, A first blind hole is formed in the barrier layer, the substrate layer and the circuit layer; wherein the first blind hole penetrates the barrier layer and the substrate layer and penetrates into the circuit layer, and the conductive structure in the circuit layer is exposed at the bottom of the first blind hole; At the opening of the first blind hole, there is an expansion section formed by an expansion process; The first blind hole is filled with a conductive material to form a conductive via hole.

12. The integrated circuit package assembly according to claim 11, characterized in that: The expansion section is in the shape of an inverted cone with a large opening at the top and a small opening at the bottom.

13. The integrated circuit package assembly according to claim 12, wherein: The central axis of the inverted cone-shaped expansion section coincides with the central axis of the first blind hole, and the inner opening of the inverted cone-shaped expansion section is connected to the opening of the remaining hole section of the first blind hole except the expansion section.

14. The integrated circuit package assembly according to claim 11, characterized in that: The conductive material filled in the hole expansion section and the conductive material filled in the remaining hole sections of the first blind hole except the hole expansion section form an integrated structure.

15. The integrated circuit package assembly according to claim 11, characterized in that: The barrier layer comprises: a first barrier layer formed on the surface of the substrate, and a second barrier layer formed on the surface of the first barrier layer; the material of the second barrier layer is different from that of the first barrier layer; Wherein, the depth of the expansion section is equal to the thickness of the second barrier layer.

16. An integrated circuit package assembly, characterized in that: comprising a substrate and a circuit layer disposed on the substrate; A barrier layer is formed on the surface of the circuit layer; A second blind hole is formed in the barrier layer and the circuit layer; wherein the second blind hole penetrates the barrier layer and penetrates into the circuit layer, and the conductive structure in the circuit layer is exposed at the bottom of the second blind hole; At the opening of the second blind hole, there is an expansion section formed by an expansion process; The second blind hole is filled with a conductive material to form a conductive via hole.

17. The integrated circuit package assembly according to claim 16, wherein: The expansion section is in the shape of an inverted cone with a large end opening and a small inner opening.

18. The integrated circuit package assembly according to claim 17, wherein: The central axis of the inverted cone-shaped expansion section coincides with the central axis of the second blind hole, and the inner opening of the inverted cone-shaped expansion section is connected to the opening of the remaining hole section of the second blind hole except the expansion section.

19. The integrated circuit package assembly according to claim 16, wherein: The conductive material filled in the hole expansion section and the conductive material filled in the remaining hole sections of the second blind hole except the hole expansion section form an integrated structure.

20. The integrated circuit package assembly according to claim 16, wherein: The barrier layer comprises: a first barrier layer formed on the surface of the circuit layer, and a second barrier layer formed on the surface of the first barrier layer; the material of the second barrier layer is different from that of the first barrier layer; Wherein, the depth of the expansion section is equal to the thickness of the second barrier layer.

21. A method for packaging an integrated circuit device, characterized in that: include: A first integrated circuit package component and a second integrated circuit package component are manufactured respectively; wherein at least one via in the first integrated circuit package component is formed by the via manufacturing method according to any one of claims 1 to 5, and at least one via in the second integrated circuit package component is formed by the via manufacturing method according to any one of claims 6 to 10; The first integrated circuit package component is bonded to the second integrated circuit package component, and the first via hole in the first integrated circuit package component is made to correspond to and be electrically connected to the second via hole in the second integrated circuit package component.

22. An integrated circuit device, characterized in that: include: A first integrated circuit package component and a second integrated circuit package component; wherein the first integrated circuit package component and the second integrated circuit package component are respectively the integrated circuit package components described in claims 11 to 15, or respectively the integrated circuit package components described in claims 16 to 20, or the first integrated circuit package component is the integrated circuit package component described in claims 11 to 15, and the second integrated circuit package component is the integrated circuit package component described in claims 16 to 20; The first via in the first integrated circuit package component is electrically connected to the second via in the second integrated circuit package component.

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