Method for accumulating charges at pressure release points of thermal foaming ink-jet chip

Abstract

According to the method for accumulating the charges at the pressure release points of the thermal foaming ink-jet chip, some virtual grounding PADs are placed near to-be-processed PADs needing gold wire bonding, and a discharge path of a passivation layer and an INL aluminum layer to the ground is formed; as the distance between the PAD to be processed and the virtual PAD is close enough, and charges can move along the surface of the passivation layer, as the small virtual PAD continuously extracts the charges accumulated in the passivation layer, excessive charges accumulated on the surface of the INL needing to be bonded on the large PAD in the early stage are also extracted to the virtual PAD and then are released through a grounding circuit; the surface of the INL on the gold wire bonding large PAD is ensured not to accumulate too many charges, and when a chip is subjected to EKC deep groove cleaning, because the INL surface does not have excessive charges, the INL surface does not have chemical reaction with EKC cleaning liquid, so that the surface of an INL aluminum layer is not abnormally eroded.

Description

Technical Field

[0001] The invention relates to the technical field of chip manufacturing, in particular to a method for accumulating electric charges at pressure points released by a thermal bubble inkjet chip. Background Art

[0002] The principle of thermal inkjet printer is to heat the nozzle to generate bubbles in the ink, and then use the expansion force of the bubbles to spray the ink, and finally form an image on the printing medium. Figure 1 As shown in the figure, it is a chip manufactured by a double-layer stacking process, which includes two layers of ASIC (Application-Specific Integrated Circuit) and MEMS (Micro ElectroMechanical Systems) stacked up and down. The structure of ASIC in the chip is: METAL1 (M1) + VIA1 + METAL2 (M2), M1 and M2 are aluminum layers, through hole VIA1 is a tungsten-filled hole; INL is the aluminum layer of the MEMS part. Unlike other single-layer chip manufacturing, in the manufacturing process of thermal bubble inkjet chips, when the ASIC and MEMS stage process processing is almost completed, the chip inkjet channel will be deeply etched to carve through the chip reserved ink channel.

[0003] In the single-layer chip process flow, ordinary deep etching usually only produces a very small amount of charge accumulation on the surface of the passivation layer and the aluminum layer. This small amount of accumulated charge generally does not cause abnormal erosion of the aluminum layer on the PAD due to the subsequent EKC deep groove cleaning. However, the deep etching of the large flow channel of the inkjet channel of the thermal bubble inkjet chip directly penetrates the chip. This deep etching requires a long plasma etching reaction time. After a long period of plasma etching reaction, more charges accumulate in the passivation layer of the chip. After the large flow channel etching of the inkjet channel is completed, in order to ensure that the inkjet channel and the nozzle are not blocked by the polymer and metal residues remaining in the etched flow channel, EKC deep groove cleaning is required to remove the residual polymer and metal residues.

[0004] Due to the deep etching of the large flow channel of the inkjet channel, a large amount of charge is accumulated in the passivation layer of the chip. These accumulated charges will move along the passivation layer and eventually accumulate on the aluminum layer of the PAD passivation window. Figure 1As shown in the figure, on the P-sub (P-type substrate), the Si3N4 surface passivation layer is attached to the SiO2 insulating dielectric layer through a deposition process; after passivation windowing, the INL aluminum layer is deposited, and the yellow marked area in the figure is the metal aluminum layer in the PAD windowing area; in the deep etching process, a large amount of charge is accumulated in the passivation layer Si3N4 (marked as ⊕ in the figure), and a large amount of charge is also accumulated on the metal aluminum layer INL of the PAD. When EKC deep groove cleaning is performed, the excess charge accumulated in the aluminum layer on the surface of the PAD will react with the EKC cleaning solution, causing the aluminum layer on the surface of the PAD to be abnormally corroded. When the chip is gold wire bonded, the abnormally corroded INL aluminum layer will cause bonding failure, causing a serious decrease in chip reliability.

[0005] In the prior art, the method for dealing with the charge accumulated in the passivation layer of the chip during the etching process is to add a cleaning process to the process and use a well-proportioned chemical solution to remove the static charge in the chip. However, this method requires the addition of special cleaning equipment and the configuration of special cleaning solutions for different types of chips. This greatly increases the overall cost of chip manufacturing and is not suitable for all scenarios. Summary of the invention

[0006] In order to solve the problem in the prior art that the electric charge accumulated in the chip passivation layer during the etching process leads to the corrosion of the metal layer on the PAD surface during the EKC cleaning process, the present invention provides a method for releasing the accumulated electric charge at the pressure point of the thermal bubble inkjet chip, which can avoid the problem of the metal layer on the PAD surface being corroded during the EKC cleaning process, and the method has a low implementation cost and is suitable for more application scenarios.

[0007] The technical solution of the present invention is as follows: a method for accumulating electric charge at a pressure point of a thermal bubble inkjet chip, characterized in that it comprises the following steps: S1: confirm the PAD on the inkjet chip that needs to be gold wire bonded, recorded as: PAD to be processed; S2: Finding a location for setting a virtual PAD around each of the PADs to be processed; The straight-line distance between the virtual PAD setting position and the PAD to be processed is less than the preset effective discharge distance; S3: Opening a PAD passivation layer at the virtual PAD setting position to form a virtual PAD, and depositing an INL aluminum layer wiring on the window opening area; Grounding the virtual PAD to form a discharge path for accumulated charges; S4: When the aluminum layer on the surface of the PAD to be processed accumulates excessive charges, the uppermost layer of the virtual PAD extracts the charges accumulated in the nearby passivation layer and releases them through the accumulated charge discharge path.

[0008] It is further characterized by: The effective discharge distance is set to 300 microns; The size of the virtual PAD is less than or equal to 10 microns*10 microns; When the PAD to be processed is located at the edge of the chip, the virtual PAD is set on the SEALRING scribe line protection ring; The structure of the inkjet chip includes: a passivation layer, METAL2 and METAL1 arranged from top to bottom on a substrate, and METAL2 and METAL1 are connected via a tungsten-filled hole; After the passivation layer is opened, a tungsten-filled hole is opened between METAL1 and the substrate for connection; The substrate is a P-type substrate, and the virtual PAD is connected to the P-type substrate through a tungsten filling hole CONT and a PDIFF layer to achieve grounding; The ratio of the number of the to-be-processed PADs to the number of the virtual PADs is: N:1, where N≥1.

[0009] The present application provides a method for releasing the accumulated charge at the pressure point of the hot bubble inkjet chip, which places some virtual grounding PADs near the PAD to be processed that needs to be gold wire bonded, forming a discharge path for the passivation layer and the INL aluminum layer to the ground; because the distance between the PAD to be processed and the virtual PAD is close enough, since the charge will move along the surface of the passivation layer, as the small virtual PAD continuously extracts the charge accumulated in the passivation layer, the excess charge on the INL surface accumulated on the large PAD that needs to be bonded in the early stage is also extracted to the virtual PAD, and then released through the grounding circuit; it is ensured that the INL surface on the large PAD bonded with gold wires will not accumulate too much charge. When the chip is cleaned by EKC deep grooves, since there is no excess charge on the INL surface at this location, it will not react chemically with the EKC cleaning solution to cause abnormal erosion of the INL aluminum layer surface. This method can be completed based on existing equipment, without the need to add additional hardware equipment, and the process flow is relatively simple. It can solve the problem of erosion of the metal layer on the PAD surface during the EKC cleaning process at a relatively low cost, and is suitable for a wider range of scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a schematic diagram of the structure of the thermal bubble inkjet chip using the double-layer manufacturing process in this application; Figure 2 This is a schematic diagram of the layout structure of the thermal bubble inkjet chip of the double-layer manufacturing process in this application; Figure 3 Example 1 for the discharge path of accumulated charge; Figure 4 This is the layout example corresponding to Example 1 of the accumulated charge discharge path; Figure 5 Example 2 for discharge path of accumulated charge; Figure 6 This is an overall example of the layout corresponding to Example 2 of the accumulated charge discharge path; Figure 7 A local example of the layout corresponding to Example 2 for the accumulated charge discharge path. DETAILED DESCRIPTION

[0011] The board structure of the inkjet chip of this embodiment is as follows Figure 2 As shown, a SEALRING scribe groove protection ring is set around the periphery of each chip to surround the chip in the middle. The PADs on the chip that need to be bonded with gold wires include: UPAD on the upper side, DPAD on the bottom, LPAD on the left, and RPAD on the right. Figure 6 for Figure 2 Schematic diagram of the enlarged structure of the LPAD on the left, including: LPAD1~LPAD12. Figure 7 for Figure 6 A partial enlarged view of LPAD10~LPAD12 in the layout.

[0012] The present application includes a method for accumulating electric charges at a pressure point of a thermal bubble inkjet chip, which includes the following steps.

[0013] S1: Identify the PAD on the inkjet chip that needs to be gold wire bonded, and record it as: PAD to be processed.

[0014] S2: Find the location of setting a virtual PAD around each PAD to be processed; The straight-line distance between the virtual PAD setting position and the PAD to be processed is smaller than the preset effective discharge distance.

[0015] S3: Opening a PAD passivation layer at the virtual PAD setting position to form a virtual PAD, and wiring the INL aluminum layer in the window area; The virtual PAD is grounded to form a discharge path for the accumulated charges.

[0016] S4: When the aluminum layer on the surface of the PAD to be processed accumulates excessive charges, the uppermost layer of the virtual PAD extracts the charges accumulated in the nearby passivation layer and releases them.

[0017] In specific implementation, the effective discharge distance is adaptively set according to the material and circuit structure of the chip. In this embodiment, the effective discharge distance is set to 300 microns. A distance less than 300 microns can ensure that the charge can be effectively released by the discharge circuit formed by the virtual PAD. The size of the virtual PAD is less than or equal to 10 microns * 10 microns, ensuring that it does not occupy too much chip surface space and does not affect the existing functions of the chip.

[0018] The structure of the inkjet chip of this embodiment includes: a passivation layer (SIO2+SI3N4), METAL2 and METAL1 are arranged from top to bottom on the substrate, METAL2 and METAL1 are connected by a tungsten-filled through hole VIA1, and VIA1 and Figure 3 exist Figure 5 The holes marked in gray in the figure. When setting up the virtual PAD, a tungsten-filled hole (marked as CONT green hole in the figure) is opened between METAL1 and the substrate for connection. The substrate of the inkjet chip is a P-type substrate. The virtual PAD is connected to the P-type substrate through the metal-filled via CONT and the P-type injection active area (PDIFF layer) to achieve grounding.

[0019] To further ensure that not too much chip surface space is occupied, when the PAD to be processed is located at the edge of the chip, a virtual PAD is set on the SEALRING scribe groove protection ring. When the PAD to be processed is located in the center of the chip and is more than 300 microns away from the SEALRING, some virtual grounding PADs are placed near the PAD that needs to be bonded with gold wires to form a discharge path from the passivation layer and the INL aluminum layer to the ground. Figure 5~Figure 7 shown.

[0020] like Figure 3 and Figure 4 As shown, when the PAD to be processed is far away from the SEALRING position, a small dummy PAD is designed near the large PAD that needs to be bonded with gold wires, and the small dummy PAD needs to be connected to the ground through the CONT and PDIFF layers. The small dummy PAD placed near the large PAD for gold wire bonding is connected to the ground through the CONT and PDIFF layers, so the top layer of the small dummy PAD will extract the charges accumulated in the nearby passivation layer. Since the charges will move along the surface of the passivation layer, as the small dummy PAD continuously extracts the charges accumulated in the passivation layer, the excess charges accumulated on the INL surface on the large PAD that needs to be bonded are also extracted to the small dummy PAD. Since the small dummy PAD is connected to the ground through the CONT and PDIFF layers, the extracted excess accumulated charges will be released to the ground of the P-SUB. This ensures that the INL surface on the gold wire bonding large PAD will not accumulate too much charge. When the chip is cleaned by EKC deep groove, since there is no excessive charge on the INL surface, it will not react chemically with the EKC cleaning solution to cause abnormal corrosion of the INL aluminum layer surface. This ensures the reliability of gold wire bonding and improves the stability of the chip.

[0021] like Figure 4In the example of the layout, when the PAD to be processed is far away from the SEALRING position, the virtual ground PAD is set at a suitable position within 300 microns around the PAD to be processed. The right side of the figure is a small virtual ground PAD, and the left side is a large PAD that needs gold wire bonding. The small virtual ground PAD on the right will extract the excess accumulated charge on the passivation layer and the INL surface on the large PAD that needs to be bonded and release it to the ground. It ensures that the INL surface of the large PAD that needs to be bonded will not accumulate excessive charge, improving the reliability of bonding and the stability of the chip.

[0022] The structure of SEALRING in this embodiment includes: a passivation layer (SIO2+SI3N4), METAL2 and METAL1 arranged on the P-Sub from top to bottom, and METAL2 and METAL1 are connected through a tungsten-filled through hole VIA1.

[0023] like Figure 2 As shown, generally speaking, most of the PADs in the chip that need to be gold wire bonded are set in an area very close to the edge of the SEALRING, and the distance from the SEALRING is about 50 microns. Figure 6 In the figure, only the PAD part that needs to be bonded on the left side of the layout is shown, and the PAD part that needs to be bonded on the right side is highly similar to the left side. As shown in the figure, the outer SEALRING surrounds the entire chip and is relatively close to the PAD that needs to be bonded, so the SEALRING can provide a relatively uniform discharge path to the ground.

[0024] In this method, in order to reduce the occupancy rate of the central area of ​​the chip, the virtual ground PADs corresponding to the PADs to be processed adjacent to the SEALRING are set on the SEALRING scribe groove protection ring, so that each PAD to be processed can be set with a ground PAD in a 1:1 ratio. At the same time, the virtual ground PADs are evenly set on the SEALRING, which can improve the charge release effect.

[0025] like Figure 5 FIG. 2 is an embodiment of using a grounded SEALRING scribe line protection ring to form a discharge path from the passivation layer and the INL aluminum layer to the ground.

[0026] Because there are usually no openings in the passivation layer (SIO2+SI3N4) in the SEALRING area, in this method, passivation PAD openings and INL wiring are performed on the original SEALRING, so that the SEALRING has the ability to form a discharge path to the ground for the passivation layer and INL aluminum layer near the bonding PAD. Since the SEALRING scribe groove protection ring surrounds the entire chip and is relatively close to the PAD that needs to be bonded, the structure can provide a relatively uniform discharge path to the ground. Since the SEALRING continuously extracts the accumulated charges in the passivation layer, the excess charges accumulated on the INL surface on the large PAD that needs to be bonded are also extracted to the SEALRING. Since the SEALRING is originally connected to the ground, the extracted excess accumulated charges will be released to the ground of the P-SUB. This ensures that the INL surface on the gold wire bonding large PAD will not accumulate too much charge. When the chip is cleaned by EKC deep groove, since there is no excessive charge on the INL surface, it will not react chemically with the EKC cleaning solution to cause abnormal corrosion of the INL aluminum layer surface. This ensures the reliability of gold wire bonding and improves the stability of the chip.

[0027] In this method, the optimal ratio of the PAD to be processed to the virtual PAD is 1:1. However, when the available positions on the chip surface cannot support this ratio, or in order to improve the chip manufacturing time and reduce the number of virtual PADs, the ratio of the number of PADs to be processed to the virtual PAD can be set to: N:1, where N≥1. That is, multiple PADs to be processed share one virtual PAD, and as long as the distance between each does not exceed 300 microns, the charge release function can be achieved.

[0028] After using the technical solution of the present invention, most of the virtual ground PADs and accumulated charge release circuits are opened in the SEALRING area, which will not affect the chip structure, thereby ensuring the stability of the chip. The release circuit can be processed based on the hardware equipment in the existing chip process program without adding additional hardware equipment, and the method can be implemented at a lower cost.

Claims

1. A method for accumulating electric charge at a pressure point of a thermal bubble inkjet chip, characterized in that: It includes the following steps: S1: confirm the PAD on the inkjet chip that needs to be gold wire bonded, recorded as: PAD to be processed; S2: Finding a location for setting a virtual PAD around each of the PADs to be processed; The straight-line distance between the virtual PAD setting position and the PAD to be processed is less than the preset effective discharge distance; S3: Opening a PAD passivation layer at the virtual PAD setting position to form a virtual PAD, and depositing an INL aluminum layer wiring on the window opening area; Grounding the virtual PAD to form a discharge path for accumulated charges; S4: When the aluminum layer on the surface of the PAD to be processed accumulates excessive charges, the uppermost layer of the virtual PAD extracts the charges accumulated in the nearby passivation layer and releases them through the accumulated charge discharge path.

2. The method for accumulating electric charge at the pressure point of a thermal bubble inkjet chip according to claim 1, characterized in that: The effective discharge distance is set to 300 microns.

3. The method for accumulating electric charge at the pressure point of a thermal bubble inkjet chip according to claim 1, characterized in that: The size of the virtual PAD is less than or equal to 10 microns*10 microns.

4. The method for accumulating electric charge at the pressure point of a thermal bubble inkjet chip according to claim 1, characterized in that: When the PAD to be processed is located at the edge of the chip, the dummy PAD is set on the SEALRING scribe line protection ring.

5. The method for accumulating electric charge at the pressure point of a thermal bubble inkjet chip according to claim 1, characterized in that: The structure of the inkjet chip includes: a passivation layer, METAL2 and METAL1 arranged from top to bottom on a substrate, and METAL2 and METAL1 are connected via a tungsten-filled hole; After the passivation layer is opened, a tungsten-filled hole is opened between METAL1 and the substrate for connection.

6. The method for accumulating electric charge at the pressure point of a thermal bubble inkjet chip according to claim 5, characterized in that: The substrate is a P-type substrate, and the virtual PAD is connected to the P-type substrate through a tungsten filling hole CONT and a PDIFF layer to achieve grounding.

7. The method for accumulating electric charge at the pressure point of a thermal bubble inkjet chip according to claim 1, characterized in that: The ratio of the number of the to-be-processed PADs to the number of the virtual PADs is: N:1, where N≥1.

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