Novel high-precision overcurrent protection circuit

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a novel high-precision overcurrent protection circuit. The over-current detection circuit comprises a reference circuit, a temperature detection circuit and an over-current detection core circuit. The over-current detection circuit can output more accurate over-current signals under different temperature conditions. The circuit is characterized in that the structure sets different temperature gradients through the temperature detection module to automatically enable the resistor string to present different resistance values, and the current value flowing through the resistor string fits the deviation generated by the sampling current due to the temperature change, thereby improving the precision of the overcurrent threshold, protecting the chip from being damaged under the condition of large current, and improving the reliability of the chip. And the stability of the whole circuit is enhanced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a novel high-precision overcurrent protection circuit. Background Art

[0002] With the rapid development of integrated circuit technology, the application of power integrated modules such as drivers has become more and more extensive, and the requirements for high driving capabilities have become increasingly higher. In order to prevent the device from being subjected to excessively high current for a long time, resulting in heat that cannot be dissipated and causing device damage, the current detection circuit is required to increase the protection of the circuit, which not only improves the reliability of the chip but also increases the service life of the chip. In order to protect the module circuit from damage when the load current is large, the overcurrent protection circuit came into being. At present, there are many methods to achieve high precision of overcurrent protection circuit. One of the methods is to reduce the current by multiples through sampling devices, compare the nearly lossless current generated by the current detection circuit or the current copied by the current mirror with the current with the same temperature change generated by the on-resistance of the same type of tube as the power tube, and act on the overall structure through a comparator or inverter to control the operation of the overall circuit, which is called the current comparison method; the other method is to reduce the current by multiples through the sampling device, and the voltage generated by the voltage difference generated by the resistor connected to the drain end of the sampling tube is compared with the reference voltage of the reference circuit, and act on the overall structure through a comparator to control the operation of the overall circuit, which is called the voltage comparison method; the current of the first method is a relatively accurate copy, but the linearity of the on-resistance of the power tube is poor, and the area of ​​the power tube is relatively large; the current of the sampling tube will not be accurately copied in the second method, and circuits such as op amps and comparators are required, and the required area is also large; these two methods will have a large overcurrent threshold range at different temperatures, usually with an error range of about 3A. Therefore, under normal circumstances, designers will design a current threshold in the module circuit as a reference for whether the circuit current is overcurrent. However, under current process conditions, the characteristics of CMOS devices will deviate with the change of temperature, causing the designed current threshold to deviate under different temperature conditions. Therefore, in the module circuit design, designers will design the current threshold range to be very wide. However, a high-precision overcurrent protection circuit is a guarantee of system stability and reliability. It will not only affect the performance of power devices, but also have a greater impact on the performance of analog circuits. Traditional overcurrent circuits can only protect the normal operation of modules and chips under a wide current range. With the upgrading of technology, the process is moving towards 3nm and 1nm, the chip area that can be manufactured is gradually reduced, and the current that the chip can carry is also getting smaller and smaller. The importance of the accuracy of the protection threshold of the overcurrent protection circuit is becoming more and more important. Summary of the invention

[0003] In order to solve the problem that the overcurrent threshold accuracy of the existing overcurrent protection circuit is low at different temperatures, the present invention proposes a novel high-precision overcurrent protection circuit structure.

[0004] The technical solution of the present invention is:

[0005] A novel high-precision overcurrent protection circuit, characterized in that it includes a reference circuit, a temperature detection circuit and an overcurrent detection core circuit;

[0006] The reference circuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first triode, a second triode, a third triode, a fourth triode, a fifth triode, and a sixth triode; wherein one end of the first resistor is connected to a power supply, and the other end is connected to a gate of the first NMOS tube, a gate of the second NMOS tube, The drain of the third NMOS tube, the source of the first NMOS tube, the source of the second NMOS tube, and the source of the third NMOS tube are grounded; the source of the first PMOS tube is connected to the power supply, and its gate is connected to the drain of the first NMOS tube, the gate and drain of the second PMOS tube, the gate of the fifth PMOS tube, the gate of the seventh PMOS tube, and the gate of the ninth PMOS tube, and a third reference voltage is output; the drain of the first PMOS tube is connected to the source of the third PMOS tube; the gate of the third PMOS tube is connected to the gate and drain of the fourth PMOS tube and the drain of the second NMOS tube, and the drain of the third PMOS tube is connected to the drain and gate of the fourth NMOS tube, the gate of the fifth NMOS tube, and the gate of the third NMOS tube. The gate of the fourth NMOS tube is connected to the collector and base of the first transistor and the base of the second transistor; the emitter of the first transistor is grounded; the source of the second PMOS tube is connected to the power supply, and its drain is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the drain of the fifth NMOS tube, the gate of the sixth PMOS tube, the gate of the eighth PMOS tube, and the gate of the tenth PMOS tube, and a fourth reference voltage is output; the source of the fifth NMOS tube is connected to the collector of the second transistor, and the emitter of the second transistor is grounded after passing through the second resistor; the source of the fifth PMOS tube is connected to the power supply, and its drain is connected to the source of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the base and collector of the third transistor The emitter of the third triode is connected to the ground after passing through the third resistor; the source of the seventh PMOS tube is connected to the power supply, and the drain thereof is connected to the source of the eighth PMOS tube; the drain of the eighth PMOS tube is connected to the base and collector of the fourth triode, and the first reference voltage is output; the emitter of the fourth triode is connected to the base and collector of the fifth triode, the emitter of the fifth triode is connected to the base and collector of the sixth triode, and the emitter of the sixth triode is connected to the ground after passing through the fourth resistor; the source of the ninth PMOS tube is connected to the power supply, and the drain thereof is connected to the source of the tenth PMOS tube, the drain of the tenth PMOS tube is connected to the drain and gate of the sixth NMOS tube, and the second reference voltage is output, and the source of the sixth NMOS tube is grounded;

[0007] The temperature detection circuit includes an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube, a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, and a thirty-fifth PMOS tube. OS tube, the thirty-sixth PMOS tube, the thirty-seventh PMOS tube, the thirty-eighth PMOS tube, the thirty-ninth PMOS tube, the fortieth PMOS tube, the forty-first PMOS tube, the forty-second PMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth MOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth MOS tube, the seventeenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twentieth NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-third NMOS tube, the twenty-fourth NMOS tube, the twenty-fifth NMOS tube, the second a sixteenth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirtieth NMOS tube, a thirty-first NMOS tube, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a seventh triode, an eighth triode, a ninth triode, a tenth triode, and an eleventh triode; wherein the source of the eleventh PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the twelfth PMOS tube; the gate of the twelfth PMOS tube is connected to the fourth reference voltage, and the drain thereof is connected to the drain of the sixteenth PMOS tube, the drain of the twenty-second PMOS tube, the drain of the twenty-eighth PMOS tube, the drain of the thirty-fourth PMOS tube, and the fortieth PMOS tube The drain of the fifth transistor, one end of the fifth resistor, the base of the seventh transistor, the base of the eighth transistor, the base of the ninth transistor, the base of the thirteenth transistor, and the base of the eleventh transistor are connected to ground; the source of the thirteenth PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the fourteenth PMOS tube; the gate of the fourteenth PMOS tube is connected to the fourth reference voltage, and the drain thereof is connected to the gate of the seventh NMOS tube and the collector of the seventh transistor; the drain of the seventh NMOS tube is connected to the power supply, and the source thereof is connected to the source of the eighth NMOS tube and the drain of the ninth NMOS tube;The source of the fifteenth PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the sixteenth PMOS tube; the gate of the sixteenth PMOS tube is connected to one end of the sixth resistor and the drain of the eleventh NMOS tube, outputs the first temperature control signal, and the other end of the sixth resistor is connected to the power supply; the source of the seventeenth PMOS tube is connected to the power supply, the gate and the drain thereof are interconnected, and the drain thereof is connected to the drain of the eighth NMOS tube; the gate of the eighth NMOS tube is connected to the first reference voltage; the gate of the ninth NMOS tube is connected to the second reference voltage, and the source thereof is grounded; the source of the eighteenth PMOS tube is connected to the power supply, the gate thereof is connected to the drain of the seventeenth PMOS tube, and the drain of the eighteenth PMOS tube is connected to the drain of the tenth NMOS tube; the gate of the tenth NMOS tube The gate of the eleventh NMOS tube is connected to the drain of the eighteenth PMOS tube, and the source of the eleventh NMOS tube is grounded; the source of the nineteenth PMOS tube is connected to the power supply, the gate of the nineteenth PMOS tube is connected to the third reference voltage, and the drain of the nineteenth PMOS tube is connected to the source of the twentieth PMOS tube; the gate of the twentieth PMOS tube is connected to the fourth reference voltage, and the drain of the twelfth NMOS tube is connected to the gate and the collector of the eighth transistor; the drain of the twelfth NMOS tube is connected to the power supply, and the source of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube are connected to the power supply; the source of the twenty-first PMOS tube is connected to the power supply, the gate of the twenty-second PMOS tube is connected to the third reference voltage, and the drain of the twenty-second PMOS tube is connected to the source of the twenty-second PMOS tube; the gate of the twenty-second PMOS tube is connected to the seventh reference voltage, and the drain of the twelfth NMOS tube is connected to the power supply. The second temperature control signal is outputted by connecting one end of the seventh resistor to the drain of the sixteenth NMOS tube, and the other end of the seventh resistor is connected to the power supply; the source of the twenty-third PMOS tube is connected to the power supply, the gate and drain of the twenty-third PMOS tube are interconnected, and the drain of the twenty-third NMOS tube is connected to the drain of the thirteenth NMOS tube; the gate of the thirteenth NMOS tube is connected to the first reference voltage, and the source of the thirteenth NMOS tube is connected to the drain of the fourteenth NMOS tube; the gate of the fourteenth NMOS tube is connected to the second reference voltage, and the source of the thirteenth NMOS tube is grounded; the source of the twenty-fourth PMOS tube is connected to the power supply, the gate of the twenty-third PMOS tube is connected to the drain of the fifteenth NMOS tube, and the gate of the sixteenth NMOS tube; the gate of the fifteenth NMOS tube is connected to the second reference voltage, and the source of the thirteenth NMOS tube is grounded; The source of the S tube is grounded; the source of the twenty-fifth PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the twenty-sixth PMOS tube; the gate of the twenty-sixth PMOS tube is connected to the fourth reference voltage, and the drain thereof is connected to the gate of the seventeenth NMOS tube and the collector of the ninth transistor; the drain of the seventeenth NMOS tube is connected to the power supply, and the source thereof is connected to the source of the eighteenth NMOS tube and the drain of the nineteenth NMOS tube; the source of the twenty-seventh PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the twenty-eighth PMOS tube; the gate of the twenty-eighth PMOS tube is connected to one end of the eighth resistor and the drain of the twenty-first NMOS tube, and the third temperature control signal is outputted, and the other end of the eighth resistor is connected to the power supply;The source of the twenty-ninth PMOS tube is connected to the power supply, the gate and drain of the twenty-ninth PMOS tube are interconnected, and the drain of the twenty-ninth NMOS tube is connected to the drain of the twenty-first NMOS tube; the gate of the twenty-first NMOS tube is connected to the first reference voltage, the gate of the twenty-ninth NMOS tube is connected to the second reference voltage, and the source of the twenty-ninth NMOS tube is connected to ground; the source of the thirtieth PMOS tube is connected to the power supply, the gate of the thirtieth PMOS tube is connected to the drain of the twentieth NMOS tube and the gate of the twenty-first NMOS tube; the gate of the twentieth NMOS tube is connected to the second reference voltage, and the source of the twentieth NMOS tube is connected to ground; the source of the twenty-first NMMOS tube is connected to ground; the source of the thirty-first PMOS tube is connected to the power supply, the gate of the thirtieth PMOS tube is connected to the third reference voltage, and the drain of the thirtieth PMOS tube is connected to the drain of the twentieth NMOS tube and the gate of the twenty-first NMOS tube The gate of the thirty-second PMOS tube is connected to the fourth reference voltage, and its drain is connected to the gate of the twenty-second NMOS tube and the collector of the thirteenth tube; the drain of the twenty-second NMOS tube is connected to the power supply, and its source is connected to the source of the twenty-third NMOS tube and the drain of the twenty-fourth NMOS tube; the source of the thirty-third PMOS tube is connected to the power supply, its gate is connected to the third reference voltage, and its drain is connected to the source of the thirty-fourth PMOS tube; the gate of the thirty-fourth PMOS tube is connected to one end of the ninth resistor and the drain of the twenty-sixth NMOS tube, and outputs a fourth temperature control signal; the source of the thirty-fifth PMOS tube is connected to the power supply, its gate and drain are interconnected, and its drain is connected to the drain of the twenty-third NMOS tube; The gate of the NMOS tube is connected to the first reference voltage; the gate of the twenty-fourth NMOS tube is connected to the second reference voltage, and the source thereof is grounded; the source of the thirty-sixth PMOS tube is connected to the power supply, the gate thereof is connected to the drain of the thirty-fifth PMOS tube, and the drain of the thirty-sixth PMOS tube is connected to the drain of the twenty-fifth NMOS tube and the gate of the twenty-sixth NMOS tube; the gate of the twenty-fifth NMOS tube is connected to the second reference voltage, and the source thereof is grounded; the source of the twenty-sixth NMOS tube is grounded; the source of the thirty-seventh PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the thirty-eighth PMOS tube; the gate of the thirty-eighth PMOS tube is connected to the fourth reference voltage, and the drain thereof is connected to the gate of the twenty-seventh NMOS tube and the gate of the eleventh NMOS tube; The collector of the transistor; the drain of the twenty-seventh NMOS tube is connected to the power supply, and the source thereof is connected to the source of the twenty-eighth NMOS tube and the drain of the twenty-ninth NMOS tube; the source of the thirty-ninth PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the fortieth PMOS tube; the gate of the fortieth PMOS tube is connected to the fourth reference voltage, the gate thereof is connected to one end of the tenth resistor and the drain of the thirty-first NMOS tube, and a thermal shutdown signal is output; the other end of the tenth resistor is connected to the power supply; the source of the forty-first PMOS tube is connected to the power supply, the gate and the drain thereof are interconnected, and the drain thereof is connected to the drain of the twenty-eighth NMOS tube; the gate of the twenty-eighth NMOS tube is connected to the first reference voltage, and the source of the twenty-ninth NMOS tube is grounded;The source of the 42nd PMOS tube is connected to the power supply, and the gate thereof is connected to the drain of the 41st PMOS tube. The drain of the 42nd PMOS tube is connected to the drain of the 30th NMOS tube and the gate of the 31st NMOS tube. The source of the 30th NMOS tube and the source of the 31st NMOS tube are grounded.

[0008] The overcurrent detection core circuit includes a forty-third PMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a second capacitor, a second Zener diode, a first high-voltage NMOS tube, and a second high-voltage NMOS tube; wherein the gate electrodes of the first high-voltage NMOS tube and the second high-voltage NMOS tube are connected to each other. The electrodes are respectively connected to the gates of the high-side power tubes of the H-bridge, the sources of the first high-voltage NMOS tube and the second high-voltage NMOS tube are respectively connected to the two bridge arms of the H, the drains of the first high-voltage NMOS tube and the second high-voltage NMOS tube are connected to the gate of the forty-third PMOS tube and one end of the twelfth resistor, the other end of the twelfth resistor and the source of the forty-third PMOS tube are connected to the power supply; the drain of the forty-third PMOS tube is connected to one end of the second Zener diode, one end of the second capacitor, the gate of the thirty-second NMOS tube, and one end of the thirteenth resistor; the other end of the second Zener diode and the other end of the second capacitor are grounded; the drain of the thirty-second NMOS tube is connected to the input end of the first inverter and one end of the eleventh resistor, the source of the thirty-second NMOS tube is grounded, and the eleventh The other end of the resistor is connected to the power supply; the other end of the thirteenth resistor is connected to the ground after passing through the fourteenth resistor, the fifteenth resistor, the sixteenth resistor, and the seventeenth resistor in sequence; the output end of the first inverter is connected to an input end of the first NOR gate, an input end of the second NOR gate, an input end of the third NOR gate, and an input end of the fourth NOR gate; the other input end of the first NOR gate is connected to the first temperature control signal, and the output end is connected to the gate of the thirty-third NMOS tube after passing through the sixth inverter and the second inverter in sequence, the drain of the thirty-third NMOS tube is connected to the connection point of the thirteenth resistor and the fourteenth resistor, the source of the thirty-third NMOS tube is connected to the connection point of the fourteenth resistor and the fifteenth resistor, and the drain of the thirty-fourth NMOS tube; the other input end of the second NOR gate is connected to the second The output end of the third NOR gate is connected to the gate of the thirty-fourth NMOS tube through the seventh inverter and the third inverter in sequence, and the source of the thirty-fourth NMOS tube is connected to the connection point of the fifteenth resistor and the sixteenth resistor, and the drain of the thirty-fifth NMOS tube; the other input end of the third NOR gate is connected to the third temperature control signal, the output end of the third NOR gate is connected to the gate of the thirty-sixth NMOS tube through the eighth inverter and the fourth inverter in sequence, and the source of the thirty-sixth NMOS tube is connected to the connection point of the sixteenth resistor and the seventeenth resistor, and the drain of the thirty-seventh NMOS tube; the other input end of the fourth NOR gate is connected to the fourth temperature control signal, the output end of the third NMOS tube is connected to the gate of the thirty-seventh NMOS tube through the ninth inverter and the fifth inverter in sequence, and the source of the thirty-seventh NMOS tube is grounded.

[0009] The beneficial effect of the present invention is that it can output a more accurate overcurrent signal under different temperature conditions. It is characterized in that the structure automatically makes the resistor string present different resistance values ​​by setting different temperature gradients through the temperature detection module, and the current value flowing through the resistor string is used to fit the deviation of the sampling current caused by temperature changes, so as to improve the accuracy of the overcurrent threshold, protect the chip from damage under high current conditions, and enhance the stability of the overall circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a structural functional block diagram of a novel high-precision overcurrent protection circuit involved in the present invention;

[0011] Figure 2 A circuit diagram of a reference circuit structure of a novel high-precision overcurrent protection circuit structure involved in the present invention;

[0012] Figure 3 A circuit diagram of a temperature detection circuit of a novel high-precision overcurrent protection circuit structure according to the present invention;

[0013] Figure 4 It is the core circuit diagram of the overcurrent protection circuit of the present invention;

[0014] Figure 5 It is a simulation diagram of the output voltage of the overcurrent detection module of the present invention at all temperatures (-55°C, 25°C, 125°C, 150°C);

[0015] Figure 6 This is a simulation diagram of the output voltage of the overcurrent detection module of the present invention at a high temperature (150° C.);

[0016] Figure 7 This is a simulation diagram of the output voltage of the overcurrent detection module of the present invention at a low temperature (-55°C); DETAILED DESCRIPTION

[0017] The present invention is described in detail below with reference to the accompanying drawings.

[0018] The overall circuit structure of the present invention is as follows Figure 1As shown, it includes a reference circuit, a temperature detection circuit and an overcurrent detection core circuit. First, the PTAT current is generated through the reference circuit to provide a current bias for the temperature detection module, so that the output signal of the temperature detection module has different high and low level signals at different temperatures, which acts on the adjustment circuit of the overcurrent detection module, so that the overcurrent detection module can accurately generate overcurrent thresholds at different temperatures to protect the safety of the H-bridge power tube and the entire chip. At the same time, thermal protection is also added. When a large current flows through the power tube of the H-bridge circuit and exceeds the current threshold, the overcurrent detection module starts and turns off the power tube switch in the H-bridge circuit. The chip no longer works normally, and the power tube current drops rapidly. After a period of time, the chip will restart. The overcurrent detection module will re-detect the current of the power tube in the H-bridge. If the current drops and is lower than the current threshold, the output signal of the overcurrent detection circuit will flip, and the chip will work normally again. If a large current is generated again and is higher than the current threshold, the overcurrent detection module will start again and the chip will be shut down again. This process will continue to cycle until no large current is generated. However, when repeating this cycle, the power tube in the H-bridge circuit will generate a large amount of heat energy, causing the chip to be damaged due to excessive temperature. When the temperature rises to the set temperature threshold, the temperature detection module will start and shut down the power tube switch in the H-bridge circuit, and the chip will no longer work normally.

[0019] Figure 2 The circuit diagram of the reference circuit is shown in FIG. 1 . The resistor R1 and the CMOS tubes MN1 to MN3 form a startup circuit. Due to the existence of the degenerate point, the circuit will have two states, one is the normal working state, and the other is that various tubes are normally turned on, but no current flows. In order to avoid the second situation, a startup circuit is needed to make the bandgap core circuit work normally. After the entire circuit works, the startup circuit is turned off through feedback to avoid affecting the operation of the core circuit. In the path formed by the resistor R1 and the MN3 tube, the MN3 tube is initially in the off state, the resistor R1 is an equipotential body, the gate voltage of the MN1 and MN2 tubes is equivalent to the power supply voltage, the MN1 and MN2 tubes are turned on, so that the gate voltage of the MP1 to MP4 tubes is low level, the MP1 to MP4 tubes are turned on, and the gate voltage of the MN3 tube is changed from the original low level to the high level, the MN3 tube is changed from the off state to the on state, and then the gate voltage of the MN1 and MN2 tubes is changed from the high level to the low level, the MN1 and MN2 tubes are turned off, and the startup circuit does not work. The current mirror structure composed of MP1 to MP4 makes the current I1 of the path composed of MP1, MP3, MN4, and NPN Q1 equal to the current I2 of the path composed of MP1, MP3, MN4, NPN Q2, and resistor R2. Next, their V BEThe difference shows a positive temperature coefficient. The size ratio of Q1 and Q2 is 1:n, so the base-emitter voltage difference of the two tubes is:

[0020]

[0021] The current flowing through R2 is proportional to the temperature and its magnitude is:

[0022] I2=△V BE / R2 (4)

[0023] The current mirror structure composed of MP1~MP10 can obtain I1=I2=I3=I PTAT

[0024] Therefore, the output voltage V OUT =V BEQ3 +(V T lnn / R2)×R3(5)

[0025] The positive temperature coefficient V T ln n and negative temperature coefficient V BEQ3 By adding them proportionally, we can get the output voltage V with zero temperature coefficient OUT And positive temperature current I PTAT .

[0026] Figure 3 The figure shows the circuit diagram of the temperature detection module. The bias voltages VB1~VB4 are generated and provided by the reference module. Under the action of the VB1~VB4 voltages, the MP11~MP14 tubes and the MN8~MN10 tubes are turned on, and the MP11 and MP12 tubes introduce positive temperature current I from the reference circuit. PTAT , flows through resistor R5, generates a voltage with a positive temperature coefficient, and as the temperature rises, NPN transistor Q7 is turned on, and the gate voltage of MN7 changes from high level to low level, and MN7 is turned off. At this time, the current in MN8 is the same as the current in MP17. Since the width-to-length ratio of MN9 is greater than that of MN10, and MP17 and MP18 form a 1:1 current mirror, the current flowing through MP18 competes with the current flowing through MN10, causing the gate voltage of MN11 to rise to VCC, and MN11 is turned on, and the output signal V out_temp<0> From high level to low level, when the output voltage is low level, MP16 is in the on state, and the PTAT current flowing through resistor R5 becomes larger, which requires a larger temperature change to change the state of transistor Q7. Reasonable design of the width and length of MP15 can set different PTAT current sizes and different hysteresis voltages. Similarly, V out_temp<1> ~V out_temp<3> and V OUTWhen the temperature rises to different temperature thresholds, the output signal changes from high level to low level, V OUT It is a thermal shutdown signal. When the module temperature rises to the over-temperature threshold as a large current passes through the H-bridge circuit, V OUT The signal will change from high level to low level, forcibly shutting down the H-bridge circuit and protecting the module from thermal damage;

[0027] Figure 4The figure shows the circuit diagram of the overcurrent detection module. The resistor R11 is a pull-up resistor, so that the output voltage of the overcurrent detection module is initially at a low level. NLDM3~NLDM6 are power tubes in the H-bridge circuit, NLDM1 and NLDM2 are sampling tubes of the power tubes NLDM3 and NLDM4, and their width-to-length ratio is 1:1000. The resistor R12 is 130Ω, and the resistance value of the resistor R12 is small. The gate voltage and source voltage of the sampling tube and the high-side power tube of the H-bridge are completely equal (the gates of the sampling tubes NLDM1 and NLDM2 are connected to the gates of the high-side power tubes NLDM3 and NLDM4 of the H-bridge through the H_OUT_GATE1 port and the H_OUT_GATE2 port, and the sources of the sampling tubes NLDM1 and NLDM2 are connected to the sources of the high-side power tubes NLDM3 and NLDM4 of the H-bridge through the OUTPUT1 port and the OUTPUT2 port) (H_OUT_GATE1 and H_OUT_GATE2 are the gate signals of the high-side power tube and the sampling tube, OUTPUT1 and OUTPUT2 are the output ports of the H-bridge circuit, and the ports OUTPUT1 and OUTPUT2 are connected to the gate signals of the high-side power tube and the sampling tube. UT2 is connected to a load). In order to achieve non-destructive testing, the drain voltages of the sampling tube and the high-side power tube should be equal as much as possible. However, the structure of the overcurrent detection circuit cannot ensure that the drain voltages of the sampling tube and the high-side power tube are equal. The resistance value of resistor R12 should be reduced as much as possible to make the current replication ratio as close as possible to the set ratio of the width-to-length ratio of the sampling tube and the power tube. When a large current flows through the power tube of the H-bridge circuit and exceeds the set current threshold, the current flowing through the sampling tube is one thousandth of the current flowing through the power tube. Resistor R12 generates a voltage drop under the action of the sampling current, causing the MP43 tube to turn on. At this time, the path composed of the MP43 tube and the resistor string R13~R17 is turned on, generating a gate voltage that turns on the MN32 tube, so that the output voltage of the overcurrent detection module changes from a low level to a high level, turning off the H-bridge circuit power tube, and the chip is turned off. At this time, NLDM1~NLDM6 are in the off state, MP43 tube is turned off, capacitor C1 stores the charge of the gate voltage that turns on MN32 tube under the action of current, which needs to be released through resistors R13~R17. When the voltage drop on capacitor C1 is released to a value lower than the gate voltage of MN32 tube, MN32 tube is turned off, the output voltage of the overcurrent detection module changes from high level to low level, and the chip resumes normal operation. At the same time, under different temperature gradients, the on-resistance R ds_onThere are also different temperature resistance values ​​(positive temperature coefficient). At the same time, the threshold voltages of MP43 and MN32 are also different (negative temperature coefficient). <0> ~in_temp <3> Different high and low level signals are input into the input port to act on the gates of NM33~NM36 tubes. NM33~NM36 tubes are in different working states (on or off), so that the resistance string composed of R13~R17 shows different resistance values, and the current value flowing through the resistance string R13~R17 is also different to fit the current value of the power tube and the switch tube at different temperatures, which can contribute to accurate overcurrent thresholds under different temperature gradients.

Claims

1. A new type of high-precision overcurrent protection circuit, characterized in that: Including reference circuit, temperature detection circuit and over-current detection core circuit; The reference circuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first triode, a second triode, a third triode, a fourth triode, a fifth triode, and a sixth triode; wherein one end of the first resistor is connected to a power supply, and the other end is connected to a gate of the first NMOS tube, a gate of the second NMOS tube, The drain of the third NMOS tube, the source of the first NMOS tube, the source of the second NMOS tube, and the source of the third NMOS tube are grounded; the source of the first PMOS tube is connected to the power supply, and its gate is connected to the drain of the first NMOS tube, the gate and drain of the second PMOS tube, the gate of the fifth PMOS tube, the gate of the seventh PMOS tube, and the gate of the ninth PMOS tube, and a third reference voltage is output; the drain of the first PMOS tube is connected to the source of the third PMOS tube; the gate of the third PMOS tube is connected to the gate and drain of the fourth PMOS tube and the drain of the second NMOS tube, and the drain of the third PMOS tube is connected to the drain and gate of the fourth NMOS tube, the gate of the fifth NMOS tube, and the gate of the third NMOS tube. The gate of the fourth NMOS tube is connected to the collector and base of the first transistor and the base of the second transistor; the emitter of the first transistor is grounded; the source of the second PMOS tube is connected to the power supply, and its drain is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the drain of the fifth NMOS tube, the gate of the sixth PMOS tube, the gate of the eighth PMOS tube, and the gate of the tenth PMOS tube, and a fourth reference voltage is output; the source of the fifth NMOS tube is connected to the collector of the second transistor, and the emitter of the second transistor is grounded after passing through the second resistor; the source of the fifth PMOS tube is connected to the power supply, and its drain is connected to the source of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the base and collector of the third transistor The emitter of the third triode is connected to the ground after passing through the third resistor; the source of the seventh PMOS tube is connected to the power supply, and the drain thereof is connected to the source of the eighth PMOS tube; the drain of the eighth PMOS tube is connected to the base and collector of the fourth triode, and the first reference voltage is output; the emitter of the fourth triode is connected to the base and collector of the fifth triode, the emitter of the fifth triode is connected to the base and collector of the sixth triode, and the emitter of the sixth triode is connected to the ground after passing through the fourth resistor; the source of the ninth PMOS tube is connected to the power supply, and the drain thereof is connected to the source of the tenth PMOS tube, the drain of the tenth PMOS tube is connected to the drain and gate of the sixth NMOS tube, and the second reference voltage is output, and the source of the sixth NMOS tube is grounded; The temperature detection circuit includes an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube, a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, and a thirty-fifth PMOS tube. OS tube, the thirty-sixth PMOS tube, the thirty-seventh PMOS tube, the thirty-eighth PMOS tube, the thirty-ninth PMOS tube, the fortieth PMOS tube, the forty-first PMOS tube, the forty-second PMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth MOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth MOS tube, the seventeenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twentieth NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-third NMOS tube, the twenty-fourth NMOS tube, the twenty-fifth NMOS tube, the second a sixteenth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirtieth NMOS tube, a thirty-first NMOS tube, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a seventh triode, an eighth triode, a ninth triode, a tenth triode, and an eleventh triode; wherein the source of the eleventh PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the twelfth PMOS tube; the gate of the twelfth PMOS tube is connected to the fourth reference voltage, and the drain thereof is connected to the drain of the sixteenth PMOS tube, the drain of the twenty-second PMOS tube, the drain of the twenty-eighth PMOS tube, the drain of the thirty-fourth PMOS tube, and the fortieth PMOS tube The drain of the fifth transistor, one end of the fifth resistor, the base of the seventh transistor, the base of the eighth transistor, the base of the ninth transistor, the base of the thirteenth transistor, and the base of the eleventh transistor are connected to ground; the source of the thirteenth PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the fourteenth PMOS tube; the gate of the fourteenth PMOS tube is connected to the fourth reference voltage, and the drain thereof is connected to the gate of the seventh NMOS tube and the collector of the seventh transistor; the drain of the seventh NMOS tube is connected to the power supply, and the source thereof is connected to the source of the eighth NMOS tube and the drain of the ninth NMOS tube;The source of the fifteenth PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the sixteenth PMOS tube; the gate of the sixteenth PMOS tube is connected to one end of the sixth resistor and the drain of the eleventh NMOS tube, outputs the first temperature control signal, and the other end of the sixth resistor is connected to the power supply; the source of the seventeenth PMOS tube is connected to the power supply, the gate and the drain thereof are interconnected, and the drain thereof is connected to the drain of the eighth NMOS tube; the gate of the eighth NMOS tube is connected to the first reference voltage; the gate of the ninth NMOS tube is connected to the second reference voltage, and the source thereof is grounded; the source of the eighteenth PMOS tube is connected to the power supply, the gate thereof is connected to the drain of the seventeenth PMOS tube, and the drain of the eighteenth PMOS tube is connected to the drain of the tenth NMOS tube; the gate of the tenth NMOS tube The gate of the eleventh NMOS tube is connected to the drain of the eighteenth PMOS tube, and the source of the eleventh NMOS tube is grounded; the source of the nineteenth PMOS tube is connected to the power supply, the gate of the nineteenth PMOS tube is connected to the third reference voltage, and the drain of the nineteenth PMOS tube is connected to the source of the twentieth PMOS tube; the gate of the twentieth PMOS tube is connected to the fourth reference voltage, and the drain of the twelfth NMOS tube is connected to the gate and the collector of the eighth transistor; the drain of the twelfth NMOS tube is connected to the power supply, and the source of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube are connected to the power supply; the source of the twenty-first PMOS tube is connected to the power supply, the gate of the twenty-second PMOS tube is connected to the third reference voltage, and the drain of the twenty-second PMOS tube is connected to the source of the twenty-second PMOS tube; the gate of the twenty-second PMOS tube is connected to the seventh reference voltage, and the drain of the twelfth NMOS tube is connected to the power supply. The second temperature control signal is outputted by connecting one end of the seventh resistor to the drain of the sixteenth NMOS tube, and the other end of the seventh resistor is connected to the power supply; the source of the twenty-third PMOS tube is connected to the power supply, the gate and drain of the twenty-third PMOS tube are interconnected, and the drain of the twenty-third NMOS tube is connected to the drain of the thirteenth NMOS tube; the gate of the thirteenth NMOS tube is connected to the first reference voltage, and the source of the thirteenth NMOS tube is connected to the drain of the fourteenth NMOS tube; the gate of the fourteenth NMOS tube is connected to the second reference voltage, and the source of the thirteenth NMOS tube is grounded; the source of the twenty-fourth PMOS tube is connected to the power supply, the gate of the twenty-third PMOS tube is connected to the drain of the fifteenth NMOS tube, and the gate of the sixteenth NMOS tube; the gate of the fifteenth NMOS tube is connected to the second reference voltage, and the source of the thirteenth NMOS tube is grounded; The source of the S tube is grounded; the source of the twenty-fifth PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the twenty-sixth PMOS tube; the gate of the twenty-sixth PMOS tube is connected to the fourth reference voltage, and the drain thereof is connected to the gate of the seventeenth NMOS tube and the collector of the ninth transistor; the drain of the seventeenth NMOS tube is connected to the power supply, and the source thereof is connected to the source of the eighteenth NMOS tube and the drain of the nineteenth NMOS tube; the source of the twenty-seventh PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the twenty-eighth PMOS tube; the gate of the twenty-eighth PMOS tube is connected to one end of the eighth resistor and the drain of the twenty-first NMOS tube, and the third temperature control signal is outputted, and the other end of the eighth resistor is connected to the power supply;The source of the twenty-ninth PMOS tube is connected to the power supply, the gate and drain of the twenty-ninth PMOS tube are interconnected, and the drain of the twenty-ninth NMOS tube is connected to the drain of the twenty-first NMOS tube; the gate of the twenty-first NMOS tube is connected to the first reference voltage, the gate of the twenty-ninth NMOS tube is connected to the second reference voltage, and the source of the twenty-ninth NMOS tube is connected to ground; the source of the thirtieth PMOS tube is connected to the power supply, the gate of the thirtieth PMOS tube is connected to the drain of the twentieth NMOS tube and the gate of the twenty-first NMOS tube; the gate of the twentieth NMOS tube is connected to the second reference voltage, and the source of the twentieth NMOS tube is connected to ground; the source of the twenty-first NMMOS tube is connected to ground; the source of the thirty-first PMOS tube is connected to the power supply, the gate of the thirtieth PMOS tube is connected to the third reference voltage, and the drain of the thirtieth PMOS tube is connected to the drain of the twentieth NMOS tube and the gate of the twenty-first NMOS tube The gate of the thirty-second PMOS tube is connected to the fourth reference voltage, and its drain is connected to the gate of the twenty-second NMOS tube and the collector of the thirteenth tube; the drain of the twenty-second NMOS tube is connected to the power supply, and its source is connected to the source of the twenty-third NMOS tube and the drain of the twenty-fourth NMOS tube; the source of the thirty-third PMOS tube is connected to the power supply, its gate is connected to the third reference voltage, and its drain is connected to the source of the thirty-fourth PMOS tube; the gate of the thirty-fourth PMOS tube is connected to one end of the ninth resistor and the drain of the twenty-sixth NMOS tube, and outputs a fourth temperature control signal; the source of the thirty-fifth PMOS tube is connected to the power supply, its gate and drain are interconnected, and its drain is connected to the drain of the twenty-third NMOS tube; The gate of the NMOS tube is connected to the first reference voltage; the gate of the twenty-fourth NMOS tube is connected to the second reference voltage, and the source thereof is grounded; the source of the thirty-sixth PMOS tube is connected to the power supply, the gate thereof is connected to the drain of the thirty-fifth PMOS tube, and the drain of the thirty-sixth PMOS tube is connected to the drain of the twenty-fifth NMOS tube and the gate of the twenty-sixth NMOS tube; the gate of the twenty-fifth NMOS tube is connected to the second reference voltage, and the source thereof is grounded; the source of the twenty-sixth NMOS tube is grounded; the source of the thirty-seventh PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the thirty-eighth PMOS tube; the gate of the thirty-eighth PMOS tube is connected to the fourth reference voltage, and the drain thereof is connected to the gate of the twenty-seventh NMOS tube and the gate of the eleventh NMOS tube; The collector of the transistor; the drain of the twenty-seventh NMOS tube is connected to the power supply, and the source thereof is connected to the source of the twenty-eighth NMOS tube and the drain of the twenty-ninth NMOS tube; the source of the thirty-ninth PMOS tube is connected to the power supply, the gate thereof is connected to the third reference voltage, and the drain thereof is connected to the source of the fortieth PMOS tube; the gate of the fortieth PMOS tube is connected to the fourth reference voltage, the gate thereof is connected to one end of the tenth resistor and the drain of the thirty-first NMOS tube, and a thermal shutdown signal is output; the other end of the tenth resistor is connected to the power supply; the source of the forty-first PMOS tube is connected to the power supply, the gate and the drain thereof are interconnected, and the drain thereof is connected to the drain of the twenty-eighth NMOS tube; the gate of the twenty-eighth NMOS tube is connected to the first reference voltage, and the source of the twenty-ninth NMOS tube is grounded;The source of the 42nd PMOS tube is connected to the power supply, and the gate thereof is connected to the drain of the 41st PMOS tube. The drain of the 42nd PMOS tube is connected to the drain of the 30th NMOS tube and the gate of the 31st NMOS tube. The source of the 30th NMOS tube and the source of the 31st NMOS tube are grounded. The overcurrent detection core circuit includes a forty-third PMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a second capacitor, a second Zener diode, a first high-voltage NMOS tube, and a second high-voltage NMOS tube; wherein the gate electrodes of the first high-voltage NMOS tube and the second high-voltage NMOS tube are connected to each other. The electrodes are respectively connected to the gates of the high-side power tubes of the H-bridge, the sources of the first high-voltage NMOS tube and the second high-voltage NMOS tube are respectively connected to the two bridge arms of the H, the drains of the first high-voltage NMOS tube and the second high-voltage NMOS tube are connected to the gate of the forty-third PMOS tube and one end of the twelfth resistor, the other end of the twelfth resistor and the source of the forty-third PMOS tube are connected to the power supply; the drain of the forty-third PMOS tube is connected to one end of the second Zener diode, one end of the second capacitor, the gate of the thirty-second NMOS tube, and one end of the thirteenth resistor; the other end of the second Zener diode and the other end of the second capacitor are grounded; the drain of the thirty-second NMOS tube is connected to the input end of the first inverter and one end of the eleventh resistor, the source of the thirty-second NMOS tube is grounded, and the eleventh The other end of the resistor is connected to the power supply; the other end of the thirteenth resistor is connected to the ground after passing through the fourteenth resistor, the fifteenth resistor, the sixteenth resistor, and the seventeenth resistor in sequence; the output end of the first inverter is connected to an input end of the first NOR gate, an input end of the second NOR gate, an input end of the third NOR gate, and an input end of the fourth NOR gate; the other input end of the first NOR gate is connected to the first temperature control signal, and the output end is connected to the gate of the thirty-third NMOS tube after passing through the sixth inverter and the second inverter in sequence, the drain of the thirty-third NMOS tube is connected to the connection point of the thirteenth resistor and the fourteenth resistor, the source of the thirty-third NMOS tube is connected to the connection point of the fourteenth resistor and the fifteenth resistor, and the drain of the thirty-fourth NMOS tube; the other input end of the second NOR gate is connected to the second The output end of the third NOR gate is connected to the gate of the thirty-fourth NMOS tube through the seventh inverter and the third inverter in sequence, and the source of the thirty-fourth NMOS tube is connected to the connection point of the fifteenth resistor and the sixteenth resistor, and the drain of the thirty-fifth NMOS tube; the other input end of the third NOR gate is connected to the third temperature control signal, the output end of the third NOR gate is connected to the gate of the thirty-sixth NMOS tube through the eighth inverter and the fourth inverter in sequence, and the source of the thirty-sixth NMOS tube is connected to the connection point of the sixteenth resistor and the seventeenth resistor, and the drain of the thirty-seventh NMOS tube; the other input end of the fourth NOR gate is connected to the fourth temperature control signal, the output end of the third NMOS tube is connected to the gate of the thirty-seventh NMOS tube through the ninth inverter and the fifth inverter in sequence, and the source of the thirty-seventh NMOS tube is grounded.

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