Comparison circuit, resistance calibration system and memory

Abstract

The invention discloses a comparison circuit, a resistance value calibration system and a memory, the comparison circuit comprises a comparator and a compensation module, the compensation module is connected with the comparator, the comparator is connected with the compensation module, and the input offset voltage of the comparator can be corrected according to the polarity of the differential mode voltage accessed by the compensation module. Therefore, the adverse effect of the input offset voltage on the precision is reduced, and the precision of the comparator is improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a comparison circuit, a resistance calibration system and a memory. Background Art

[0002] The accuracy of the comparator is a key factor in the design, especially in applications that require precise voltage detection. The input offset voltage (offset) of the comparator is one of the main factors affecting its voltage judgment accuracy.

[0003] Among them, the input offset voltage is caused by factors such as process deviation, temperature change, and power supply noise. It will cause the comparator to misjudge when the input voltage is close to the threshold voltage, thereby affecting the accuracy of resistance calibration. Summary of the invention

[0004] The present application provides a comparison circuit, a resistance calibration system and a memory to alleviate the technical problem of low precision caused by input offset voltage.

[0005] In a first aspect, the present application provides a comparison circuit, which includes a comparator and a compensation module, wherein the compensation module is connected to the comparator, and the compensation module is used to correct the input offset voltage of the comparator according to the polarity of an input differential mode voltage.

[0006] In a second aspect, the present application provides a resistance calibration system, which includes the above-mentioned comparison circuit, pin, logic controller and pull-up drive module, the inverting input terminal of the comparator is connected to the reference voltage terminal; the pin is connected to the non-inverting input terminal of the comparator and one end of the reference resistor, and the other end of the reference resistor is connected to the ground terminal; the input terminal of the logic controller is connected to the output terminal of the comparator; the control terminal of the pull-up drive module is connected to the output terminal of the logic controller, the first end of the pull-up drive module is connected to the third power supply terminal, and the second end of the pull-up drive module is connected to the pin.

[0007] In a third aspect, the present application provides a memory, which includes the above-mentioned comparison circuit, or the memory includes the above-mentioned resistance calibration system.

[0008] The comparison circuit, resistance calibration system and memory provided in the present application are connected to the compensation module via a comparator, and the input offset voltage of the comparator can be corrected according to the polarity of the differential mode voltage connected to the compensation module, thereby reducing the adverse effect of the input offset voltage on the accuracy, which improves the accuracy of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0010] Figure 1 A circuit schematic diagram of a comparison circuit provided in an embodiment of the present application.

[0011] Figure 2 A schematic diagram of a flow chart of determining the potential of a variable voltage input terminal of a compensation module provided in an embodiment of the present application.

[0012] Figure 3 A schematic diagram for determining the differential mode voltage connected to the compensation module provided in an embodiment of the present application.

[0013] Figure 4 This is a functional block diagram of a resistance calibration system provided in an embodiment of the present application.

[0014] Figure 5 A circuit schematic diagram of the pull-up drive module provided in an embodiment of the present application.

[0015] Figure 6 A schematic diagram showing a comparison of the resistance values ​​of the pull-up driving module before and after correction provided in an embodiment of the present application.

[0016] Figure 7 A schematic diagram of the structure of a memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0018] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0019] With the advancement of storage technology, the performance of dynamic random access memory (DDR) continues to improve, which is mainly reflected in the input / output (I / O) speed of its pins. In order to meet the growing speed requirements while ensuring the reliability of data transmission, signal integrity becomes particularly important. In high-speed data transmission, signal reflection and crosstalk are two key factors affecting signal integrity. In order to reduce these effects, the impedance matching on the signal path must be improved, which puts higher requirements on the accuracy of the driving resistor.

[0020] Starting with DDR3 memory technology, a port called ZQ has been added to the memory chip design. This port is used to connect a high-precision 240-ohm pull-down resistor, which acts as a reference resistor for calibrating the RON (turn-on resistance) and ODT (output driver terminal) resistances inside the chip. These internal resistors are usually composed of MOSFETs (metal-oxide-semiconductor field-effect transistors) and polysilicon resistors, and their resistance values ​​may be affected by external environmental factors such as process, voltage, and temperature (collectively referred to as PVT).

[0021] Because PVT variations affect the value of resistors, these internal resistors need to be calibrated to ensure their accuracy when the memory chip is powered on and when environmental conditions change.

[0022] However, there may be some challenges when performing resistance calibration. In particular, when the voltages at the two input terminals of the comparator are very close, the comparator may generate an offset due to manufacturing process deviations. This offset will affect the accuracy of the comparator's judgment of the voltage, which in turn directly affects the accuracy of the resistance calibration.

[0023] This embodiment provides a comparison circuit 100. Figures 1 to 3 ,like Figure 1 As shown, the comparison circuit 100 includes a comparator 10 and a compensation module 20. The compensation module 20 is connected to the comparator 10 and is used to correct the input offset voltage of the comparator 10 according to the polarity of the connected differential mode voltage.

[0024] It can be understood that the comparison circuit provided in the present application, by connecting the compensation module 20 via the comparator 10, can correct the input offset voltage of the comparator 10 according to the polarity of the differential mode voltage connected to the compensation module 20, thereby reducing the adverse effect of the input offset voltage on the accuracy, which improves the accuracy of the comparator.

[0025] It should be noted that the polarity of the differential mode voltage connected to the compensation module 20 is different from the polarity of the input offset voltage of the comparator 10. For example, when the input offset voltage of the comparator 10 is a negative input offset voltage, the polarity of the differential mode voltage connected to the compensation module 20 is a positive polarity. When the input offset voltage of the comparator 10 is a positive input offset voltage, the polarity of the differential mode voltage connected to the compensation module 20 is a negative polarity.

[0026] In some embodiments, such as Figure 1As shown, the comparator 10 includes a current mirror unit 11, a first differential amplifier unit 12 and a first current source A1 which are connected in sequence between a first power supply terminal VDD and a second power supply terminal VSS; the compensation module 20 includes a first current input terminal, a second current input terminal, a variable voltage input terminal and a reference voltage input terminal, the first current input terminal is connected to the first output terminal of the current mirror unit 11 and the first input terminal of the first differential amplifier unit 12, the second current input terminal is connected to the second output terminal of the current mirror unit 11 and the second input terminal of the first differential amplifier unit 12; the voltage difference between the variable voltage input terminal and the reference voltage input terminal is the differential mode voltage connected to the compensation module 20.

[0027] It should be noted that the first current input terminal can be connected to the current Irp, the second current input terminal can be connected to the current Irn, the variable voltage input terminal is used to connect the variable voltage VRP, and the reference voltage input terminal is used to connect the reference voltage VRN. Among them, the current Irp is a part of the current Ip output by the current mirror unit 11, and the other part of the current Ip is input to the first differential amplifier unit 12. The current Irn is a part of the current In output by the current mirror unit 11, and the other part of the current In is input to the first differential amplifier unit 12.

[0028] The differential mode voltage connected to the compensation module 20 is the difference between the variable voltage VRP and the reference voltage VRN.

[0029] In some embodiments, such as Figure 1 As shown, the current mirror unit 11 includes a first transistor MP1 and a second transistor MP2, wherein a first electrode of the first transistor MP1 is connected to a first power supply terminal VDD, and a second electrode of the first transistor MP1 is connected to a control electrode of the first transistor MP1 and a first current input terminal; a first electrode of the second transistor MP2 is connected to a first electrode of the first transistor MP1, a control electrode of the second transistor MP2 is connected to a control electrode of the first transistor MP1, and a second electrode of the second transistor MP2 is connected to a second current input terminal.

[0030] It should be noted that the channel type of the first transistor MP1 can be the same as the channel type of the second transistor MP2, for example, both are P-channel transistors. The first electrode can be one of the source and the drain, the second electrode can be the other of the source and the drain, and the control electrode can be the gate.

[0031] When the current Ip flows through the first transistor MP1, since the control electrodes of the first transistor MP1 and the second transistor MP2 are connected, the second transistor MP2 is also turned on, and since the control signals of the two transistors are the same, the current Ip flowing through the first transistor MP1 can be copied into the current In flowing through the second transistor MP2 in a corresponding proportion.

[0032] In some embodiments, such as Figure 1 As shown, the first differential amplifier unit 12 includes a third transistor MN3 and a fourth transistor MN4, a first electrode of the third transistor MN3 is connected to the first current input terminal, a second electrode of the third transistor MN3 is connected to one end of the first current source A1, the other end of the first current source A1 is connected to the second power supply terminal VSS, and a control electrode of the third transistor MN3 serves as a positive input terminal of the comparator 10; a first electrode of the fourth transistor MN4 is connected to the second current input terminal, a second electrode of the fourth transistor MN4 is connected to the second electrode of the third transistor MN3, and a control electrode of the fourth transistor MN4 serves as an inverting input terminal of the comparator 10.

[0033] It should be noted that the channel type of the third transistor MN3 can be the same as the channel type of the fourth transistor MN4, for example, both are N-channel transistors. Since the sum of the current flowing through the first electrode of the third transistor MN3 and Irp is Ip, when Irp is adjusted by VRP, the current flowing through the first electrode of the third transistor MN3 can be changed, thereby achieving accuracy correction of the comparator.

[0034] In some embodiments, such as Figure 2 As shown, the compensation module 20 also includes a second differential amplifier unit 21 and a second current source A2. The second differential amplifier unit 21 is connected to the first current input terminal, the second current input terminal, the variable voltage input terminal and the reference voltage input terminal; the second current source A2 is connected between the second differential amplifier unit 21 and the second power supply terminal VSS.

[0035] It should be noted that the potential connected to the second power supply terminal VSS is lower than the potential connected to the first power supply terminal VDD. For example, the second power supply terminal VSS may also be the ground terminal GND in some embodiments.

[0036] In some embodiments, such as Figure 1 As shown, the second differential amplifier unit 21 includes a fifth transistor MN5 and a sixth transistor MN6, the first electrode of the fifth transistor MN5 is connected to the first current input terminal and the first electrode of the third transistor MN3, the control electrode of the fifth transistor MN5 is connected to the variable voltage input terminal, the second electrode of the fifth transistor MN5 is connected to one end of the second current source A2, and the other end of the second current source A2 is connected to the second power supply terminal VSS; the first electrode of the sixth transistor MN6 is connected to the first electrode and the second current input terminal of the fourth transistor MN4, the second electrode of the sixth transistor MN6 is connected to the second electrode of the fifth transistor MN5, and the control electrode of the sixth transistor MN6 is connected to the control electrode of the fourth transistor MN4 and the reference voltage input terminal.

[0037] It should be noted that the channel type of the fifth transistor MN5 can be the same as the channel type of the sixth transistor MN6, for example, both are N-channel transistors. The channel type of the sixth transistor MN6 is the same as the channel type of the third transistor MN3 and the channel type of the fourth transistor MN4; and the channel type of the sixth transistor MN6 is different from the channel type of the first transistor MP1 and the channel type of the second transistor MP2.

[0038] Figure 2 A schematic diagram of a flow chart of determining the potential of a variable voltage input terminal of a compensation module provided in an embodiment of the present application. Figure 3 A schematic diagram for determining the differential mode voltage connected to the compensation module provided in an embodiment of the present application. Figure 2 and Figure 3 The specific contents shown are as follows:

[0039] Idle state (IDLE): When the state machine starts to enter the idle state, the output correction is enabled, that is, after the offset correction instruction is issued, the compensation module enters the working state.

[0040] SCAN_0: Corresponding Figure 3 In Step 1, VRP is first scanned from low to high. If the output of the comparator, Comp_out, changes (flips) during this process, it can be considered that the offset correction is successful, and the differential mode voltage (code) of VRP-VRN at this time is locked.

[0041] SCAN_1: If the comparator output does not flip, the corresponding Figure 3 In Step 2, VRP starts to scan from high to low. After the output of the comparator flips, it can be considered that the offset correction is successful. The differential mode voltage (code) of VRP-VRN at this time is locked, and the state machine ends its work.

[0042] For example, Figure 3 As shown in the figure, the process of determining VRP and VRN is as follows:

[0043] After the offset correction instruction is issued, the two input terminals of the comparator, namely the control electrode of the third transistor MN3 and the control electrode of the fourth transistor MN4, are short-circuited, wherein the voltage connected to the control electrode of the third transistor MN3 is VIP, and the voltage connected to the control electrode of the fourth transistor MN4 is VIN.

[0044] If the comparator offset is negative, the output Comp_out is low. The compensation module is turned on, the VRN value is fixed and the Figure 3 Step 1 and Step 2 shown start scanning the VRP.

[0045] When VRP < VRN, the output, i.e., Comp_out, remains low. When VRP > VRN, the currents Irp > Irn flowing through the two input transistors in the compensation module. When the load current Ip > In flowing through the comparator, the output, i.e., Comp_out, jumps to high, and the negative offset is corrected. Similarly, when VRP < VRN, the positive offset of the comparator is corrected.

[0046] During the offset correction process, the VRP voltage is scanned twice. The first scan is from low to high, and the second scan is from high to low. During the scan, if the comparator flips, the scan stops and the correction ends.

[0047] During the correction process, the differential-mode voltage of VRP - VRN is determined. The VRP and VRN voltages obtained by offset calibration are respectively connected to the positive and negative input terminals of the compensation module. The comparator and the compensation module work synchronously to improve the accuracy of the comparator.

[0048] In some embodiments, as Figure 4 shown, this embodiment provides a resistance calibration system 1000. The resistance calibration system 1000 includes the above-mentioned comparison circuit 100, pin ZQ - Pin, logic controller 200, and pull-up driving module 300. The inverting input terminal of the comparator 10 is connected to the reference voltage terminal; pin ZQ - Pin is connected to the non-inverting input terminal of the comparator 10 and one end of the reference resistor RZQ. The other end of the reference resistor RZQ is connected to the ground terminal GND; the input terminal of the logic controller 200 is connected to the output terminal of the comparator 10; the control terminal of the pull-up driving module 300 is connected to the output terminal of the logic controller 200. The first end of the pull-up driving module 300 is connected to the third power supply terminal, and the second end of the pull-up driving module 300 is connected to pin ZQ - Pin.

[0049] It can be understood that since the resistance calibration system 1000 provided in this application includes the above-mentioned comparison circuit 100, it can also connect the compensation module 20 through the comparator 10. The input offset voltage of the comparator 10 can be corrected according to the polarity of the differential-mode voltage accessed by the compensation module 20, thereby reducing the adverse effect of the input offset voltage on the accuracy. This improves the accuracy of the comparator, and thus improves the calibration accuracy of the resistance value of the pull-up driving module 300.

[0050] It should be noted that the voltages accessed by the comparison circuit 100 include not only VIP and VRN, but also the aforementioned VIN and VRP. VIN can be equal to VRN.

[0051] In some embodiments, as Figure 4As shown, the resistance calibration system 1000 further includes a pull-down driving module 400, which is connected to the pull-up driving module 300 and outputs a voltage VIN, and the output end of the comparison circuit 100 is connected to the logic controller 200, which is connected to the pull-down driving module 400. In this way, the resistance calibration accuracy of the pull-down driving module 400 can also be improved.

[0052] like Figure 5 As shown, the pull-up driving module 300 includes a plurality of transistors and a plurality of resistors. Each transistor is connected in series with a resistor and connected between VDDQ and the pin ZQ-Pin. The reference resistor RZQ is connected between the pin ZQ-Pin and VSSQ. The resistance value of the reference resistor RZQ is 240 ohms. The control electrode of each transistor is connected to the output data (code) PUDRV<6:0> of the logic controller 200 to control the switching state of each transistor, thereby realizing the correction of the resistance value of the pull-up driving module 400.

[0053] The resistance of each resistor may be exemplarily R, 2R, 4R, 8R, 16R, 32R, and 64R. R here represents a unit resistance, which may be set as required.

[0054] Figure 6 A schematic diagram comparing the resistance values ​​of the pull-up driver module before and after correction provided in an embodiment of the present application. Taking VDDQ=1.2V as an example, Vos represents the case where the offset of the comparator (for example, the positive input offset voltage of the non-inverting input terminal of the comparator) changes from 1mV to 10mV. Rpu_cal 240 represents the resistance value obtained by calibrating the pull-up driver module 300, and the target resistance value of the pull-up driver module 300 is 240 ohms. delta is equal to the difference between Rpu_cal 240 and the target resistance value divided by the target resistance value.

[0055] It can be seen that before correction, as Vos increases, Rpu_cal 240 increases and delta increases, which means that the offset of the comparator will reduce the accuracy of the resistance value obtained by calibration.

[0056] After the correction, as Vos increases, Rpu_cal 240 remains unchanged, and delta decreases and remains unchanged, which means that the offset of the comparator is compensated, and the accuracy of the calibrated resistance value can be improved.

[0057] In some embodiments, such as Figure 7 As shown, this embodiment provides a memory 2000 , and the memory 2000 includes the above-mentioned comparison circuit 100 , or the memory 2000 includes the above-mentioned resistance calibration system 1000 .

[0058] It can be understood that since the memory 2000 provided in the present application includes the above-mentioned comparison circuit 100 or resistance calibration system 1000, it can also be connected to the compensation module 20 through the comparator 10, and the input offset voltage of the comparator 10 can be corrected according to the polarity of the differential mode voltage connected to the compensation module 20, thereby reducing the adverse effect of the input offset voltage on the accuracy, which improves the accuracy of the comparator.

[0059] The memory 2000 may be, but is not limited to, a dynamic random access memory (DDR), or may be other chips that require internal resistance calibration, such as a memory chip, a processor chip, a communication chip, or a sensor chip. This improves the impedance matching on the signal path, which helps reduce the impact of IO (input / output) reflection and crosstalk on signal integrity.

[0060] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0061] The comparison circuit 100, the resistance calibration system 1000 and the memory 2000 provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A comparison circuit (100), characterized in that: The comparison circuit (100) comprises: Comparator (10); A compensation module (20), the compensation module (20) being connected to the comparator (10), and the compensation module (20) being used to correct an input offset voltage of the comparator (10) according to the polarity of an input differential mode voltage.

2. The comparison circuit (100) according to claim 1, characterized in that: The polarity of the differential mode voltage connected to the compensation module (20) is different from the polarity of the input offset voltage of the comparator (10).

3. The comparison circuit (100) according to claim 1, characterized in that: The comparator (10) comprises a current mirror unit (11), a first differential amplifier unit (12) and a first current source (A1) which are sequentially connected between a first power supply terminal (VDD) and a second power supply terminal (VSS); The compensation module (20) comprises a first current input terminal, a second current input terminal, a variable voltage input terminal and a reference voltage input terminal, the first current input terminal being connected to the first output terminal of the current mirror unit (11) and the first input terminal of the first differential amplifier unit (12), and the second current input terminal being connected to the second output terminal of the current mirror unit (11) and the second input terminal of the first differential amplifier unit (12); The voltage difference between the variable voltage input terminal and the reference voltage input terminal is the differential mode voltage connected to the compensation module (20).

4. The comparison circuit (100) according to claim 3, characterized in that: The compensation module (20) further comprises: A second differential amplification unit (21), the second differential amplification unit (21) being connected to the first current input terminal, the second current input terminal, the variable voltage input terminal and the reference voltage input terminal; A second current source (A2), the second current source (A2) is connected between the second differential amplifier unit (21) and the second power supply terminal (VSS).

5. The comparison circuit (100) according to claim 4, characterized in that: The second differential amplification unit (21) comprises: a fifth transistor (MN5), wherein a first electrode of the fifth transistor (MN5) is connected to the first current input terminal, a control electrode of the fifth transistor (MN5) is connected to the variable voltage input terminal, a second electrode of the fifth transistor (MN5) is connected to one terminal of the second current source (A2), and the other terminal of the second current source (A2) is connected to the second power supply terminal (VSS); a sixth transistor (MN6), wherein a first electrode of the sixth transistor (MN6) is connected to the second current input terminal, a second electrode of the sixth transistor (MN6) is connected to the second electrode of the fifth transistor (MN5), and a control electrode of the sixth transistor (MN6) is connected to the control electrode of the fourth transistor (MN4) and the reference voltage input terminal.

6. The comparison circuit (100) according to any one of claims 3 to 5, characterized in that: The current mirror unit (11) comprises: A first transistor (MP1), wherein a first electrode of the first transistor (MP1) is connected to the first power supply terminal (VDD), and a second electrode of the first transistor (MP1) is connected to a control electrode of the first transistor (MP1) and a first output terminal of the current mirror unit (11); a second transistor (MP2), wherein a first electrode of the second transistor (MP2) is connected to a first electrode of the first transistor (MP1), a control electrode of the second transistor (MP2) is connected to a control electrode of the first transistor (MP1), and a second electrode of the second transistor (MP2) is connected to a second output terminal of the current mirror unit (11); The first differential amplification unit (12) comprises: a third transistor (MN3), wherein a first electrode of the third transistor (MN3) is connected to a first input terminal of the first differential amplifier unit (12), a second electrode of the third transistor (MN3) is connected to one terminal of the first current source (A1), the other terminal of the first current source (A1) is connected to the second power supply terminal (VSS), and a control electrode of the third transistor (MN3) serves as a non-inverting input terminal of the comparator (10); A fourth transistor (MN4), wherein a first electrode of the fourth transistor (MN4) is connected to the second input terminal of the first differential amplifier unit (12), a second electrode of the fourth transistor (MN4) is connected to the second electrode of the third transistor (MN3), and a control electrode of the fourth transistor (MN4) serves as an inverting input terminal of the comparator (10).

7. The comparison circuit (100) according to claim 6, characterized in that: The channel type of the sixth transistor (MN6) is the same as the channel type of the third transistor (MN3) and the channel type of the fourth transistor (MN4); and the channel type of the sixth transistor (MN6) is different from the channel type of the first transistor (MP1) and the channel type of the second transistor (MP2).

8. The comparison circuit (100) according to claim 7, characterized in that: The sixth transistor (MN6), the fifth transistor (MN5) and the third transistor (MN3) are all N-channel transistors; and the first transistor (MP1) and the second transistor (MP2) are all P-channel transistors.

9. A resistance calibration system (1000), characterized in that: The resistance calibration system (1000) comprises: The comparison circuit (100) according to any one of claims 1 to 8, wherein the inverting input terminal of the comparator (10) is connected to a reference voltage terminal; A pin (ZQ-Pin), the pin (ZQ-Pin) is connected to a non-inverting input terminal of the comparator (10) and one end of a reference resistor (RZQ), and the other end of the reference resistor (RZQ) is connected to a ground terminal (GND); A logic controller (200), wherein an input end of the logic controller (200) is connected to an output end of the comparator (10); A pull-up driving module (300), wherein a control end of the pull-up driving module (300) is connected to an output end of the logic controller (200), a first end of the pull-up driving module (300) is connected to a third power supply end, and a second end of the pull-up driving module (300) is connected to the pin (ZQ-Pin).

10. A memory (2000), characterized in that: The memory (2000) includes the comparison circuit (100) according to any one of claims 1 to 8, or the memory (2000) includes the resistance calibration system (1000) according to claim 9.

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