Formation method of semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a second semiconductor layer on a first semiconductor layer, and the first semiconductor layer and the second semiconductor layer have different energy band gaps; performing an etching process to form openings respectively exposing a first vertical side wall of the first semiconductor layer and a second vertical side wall of the second semiconductor layer; and forming an electrode structure in the opening to cover the first vertical sidewall and the second vertical sidewall.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor structure, and in particular to a method for forming a semiconductor structure of a high electron mobility transistor (HEMT). Background Art

[0002] GaN-based semiconductor materials have many excellent material properties, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterojunction structures.

[0003] On-resistance (R on ) is an important factor affecting the power consumption of semiconductor devices, and its resistance value is proportional to the power consumption of semiconductor devices. The on-resistance includes the channel resistance of the channel layer and the contact resistance (R C ). Since a high electron mobility transistor (HEMT) includes a two-dimensional electron gas (2DEG) with high electron mobility and high carrier density formed on a heterogeneous interface, a high electron mobility transistor (HEMT) device has a lower channel resistance. Therefore, the on-resistance of a high electron mobility transistor (HEMT) device mainly depends on the size of the contact resistance between the channel layer and the source or drain.

[0004] With the development of gallium nitride semiconductor materials, these semiconductor devices using gallium nitride semiconductor materials are applied to more severe working environments, such as higher frequency, higher temperature or higher voltage environments. Therefore, the process conditions of semiconductor devices with gallium nitride semiconductor materials also face many new challenges. For example, in the existing high electron mobility transistor (HEMT) manufacturing process, a portion of the thinner aluminum gallium nitride (Al-GaN) layer is retained in the etching process, and the metal material for the source or drain is deposited in the opening above the aluminum gallium nitride layer. In such an example, the metal is melted at high temperature to penetrate the aluminum gallium nitride layer, thereby turning on the high electron mobility transistor (HEMT). However, the high temperature process will cause the metal to flow and is not conducive to the subsequent process, and the retained thickness of the aluminum gallium nitride layer is difficult to control. In addition, if the retained thickness is too thick, the temperature and heating time for conduction will increase significantly.

[0005] In other examples of the existing manufacturing process of high electron mobility transistors (HEMTs), the etching process is performed until the AlGaN layer is penetrated, so there is no need to consider the control of the remaining thickness of the AlGaN layer. In such examples, the interface profile of the ohmic contact between the subsequently deposited metal material for the source or drain and the two-dimensional electron gas under the AlGaN layer becomes critical. In the currently known high electron mobility transistor (HEMT) structure, since the contact resistance between the source or drain and the two-dimensional electron gas is still large and difficult to control, the performance of the formed high electron mobility transistor (HEMT) structure still has room for improvement. Summary of the invention

[0006] A method for forming a semiconductor structure includes: forming a second semiconductor layer on a first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have different energy band gaps; performing an etching process to form openings that respectively expose a first vertical side wall of the first semiconductor layer and a second vertical side wall of the second semiconductor layer; and forming an electrode structure in the opening to cover the first vertical side wall and the second vertical side wall.

[0007] The method for forming a semiconductor structure of the present invention can form a high electron mobility transistor that meets electrical requirements and can improve the product yield of the high electron mobility transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the device can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0009] Figure 1 FIG. 4 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

[0010] Figure 2A FIG. 1 is a partial cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

[0011] Figure 2B According to some existing semiconductor structure manufacturing processes, a partial cross-sectional view of a semiconductor structure without good ohmic contact between an electrode structure and a two-dimensional electron gas is depicted.

[0012] Figure 3 FIG. 4 is a graph showing the relationship between the vertical profile length and the contact resistance of a semiconductor structure according to some embodiments of the present invention.

[0013] Figure Number:

[0014] 10,10':Semiconductor structure

[0015] 110: first semiconductor layer

[0016] 110S: first vertical side wall

[0017] 112: Two-dimensional electron gas

[0018] 112I: Interface

[0019] 120: Second semiconductor layer

[0020] 120S: Second vertical side wall

[0021] 130: passivation layer

[0022] 140: Electrode structure

[0023] 142: bottom electrode layer

[0024] 144: Intermetallic dielectric layer

[0025] 146: Top electrode layer

[0026] H1,H2: Height

[0027] O,O': Open

[0028] T,T': thickness

[0029] θ1,θ2: tilt angle DETAILED DESCRIPTION

[0030] The following disclosure provides many different embodiments or examples to show different components of the embodiments of the present invention. The following will disclose specific examples of the components of this specification and their arrangement to simplify the description of the present invention. Of course, these specific examples are not intended to limit the present invention. For example, if the following invention content of this specification describes forming a first component on or above a second component, it means that it includes an embodiment in which the first and second components formed are in direct contact, and also includes an embodiment in which an additional component can be formed between the above-mentioned first and second components, and the first and second components are not in direct contact. In addition, the various examples in the description of the present invention may use repeated reference symbols and / or words. The purpose of these repeated symbols or words is to simplify and clarify, and is not used to limit the relationship between the various embodiments and / or the configurations.

[0031] Furthermore, in order to conveniently describe the relationship between a device or component and another device or component in the drawings, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used. In addition to the orientations depicted in the drawings, spatially relative terms also cover different orientations of the device in use or operation. When the device is turned to a different orientation (e.g., rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after the rotation.

[0032] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately" and "generally", the meaning of "about", "approximately" and "generally" can still be implied.

[0033] Some embodiments of the present invention are described below. Additional steps may be provided before, during, and / or after the various stages described in these embodiments. Some of the stages described may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

[0034] As used herein, the term "substantially" means that the value of a given quantity may vary based on a particular technology node associated with the target semiconductor device. In some embodiments, based on a particular technology node, the term "substantially" may mean that the value of a given quantity is within a range of, for example, ±5% of a target (or desired) value.

[0035] The present invention provides a method for forming a semiconductor structure, which can improve the ohmic contact properties between an electrode (such as a source or a drain) and a two-dimensional electron gas by forming an opening with an appropriate profile in an etching process. Specifically, the etching process forms an opening that exposes substantially vertical sidewalls of multiple semiconductor layers, thereby forming an ohmic contact with low contact resistance. In some cases, for example, the semiconductor layer is a film layer (including, for example, a buffer layer, a channel layer, a barrier layer, etc.) of a high electron mobility transistor (HEMT) device formed subsequently. If the interface between the semiconductor layer and the electrode structure is substantially vertical, the two-dimensional electron gas in the film layer will be well distributed near the interface between the semiconductor layer and the electrode structure, and the electrode material deposited subsequently can be well deposited on the sidewall of the semiconductor layer. In some embodiments, by selecting appropriate etching parameters to increase the depth of the vertical sidewall, the contact area between the electrode structure and the two-dimensional electron gas can be increased to further reduce the contact resistance between the electrode structure and the two-dimensional electron gas. Therefore, the method for forming a semiconductor structure of the present invention can form a high electron mobility transistor (HEMT) that meets electrical requirements, and can improve the product yield of the high electron mobility transistor.

[0036] Figure 1 1 is a cross-sectional view of a semiconductor structure 10 according to some embodiments of the present invention. According to the method for forming the semiconductor structure 10 of the present invention, first, a second semiconductor layer 120 may be formed on a first semiconductor layer 110, and the first semiconductor layer 110 and the second semiconductor layer 120 have different energy band gaps. Then, an etching process may be performed to form an opening O that exposes a first vertical sidewall 110S of the first semiconductor layer 110 and a second vertical sidewall 120S of the second semiconductor layer 120, respectively. Then, an electrode structure 140 may be formed in the opening O to cover the first vertical sidewall 110S and the second vertical sidewall 120S. According to some embodiments of the present invention, the features and details of each film layer of the semiconductor structure 10 and each stage of the manufacturing process will be further described below.

[0037] In some embodiments, the first semiconductor layer 110 and the second semiconductor layer 120 are respectively an electron transport layer and an electron supply layer for a high electron mobility transistor (HEMT) formed subsequently. x Ga 1-x N, and the second semiconductor layer 120 may be formed of Al y Ga 1-yformed by N, where x and y satisfy 0 ≤ x < y < 1. In a specific embodiment, for example, the material of the first semiconductor layer 110 is formed of undoped gallium nitride, and the material of the second semiconductor layer 120 is formed of aluminum-doped gallium nitride. In some other embodiments, the first semiconductor layer 110 and the second semiconductor layer 120 include In x Al y Ga 1-(x+y) N, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. Thus, the materials of the first semiconductor layer 110 and the second semiconductor layer 120 may include, for example, gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), or a combination of the foregoing.

[0038] The compositions of the first semiconductor layer 110 and the second semiconductor layer 120 can be appropriately adjusted such that the bandgap of the first semiconductor layer 110 is less than the bandgap of the second semiconductor layer 120. In this way, referring to Figure 1 , when the semiconductor structure 10 is turned on, a two-dimensional electron gas 112 is generated in the first semiconductor layer 110 and adjacent to the second semiconductor layer 120. That is, the two-dimensional electron gas 112 is formed near the interface between the first semiconductor layer 110 and the second semiconductor layer 120.

[0039] The first semiconductor layer 110 and the second semiconductor layer 120 can be formed by an epitaxial growth process, such as a metal-organic chemical vapor deposition (MOCVD) process, a hydride vapor phase epitaxy (HVPE) process, a molecular beam epitaxy (MBE) process, other suitable processes, or a combination of the foregoing.

[0040] In some embodiments, the thickness of the first semiconductor layer 110 is between about 250 nm and 380 nm, and the thickness of the second semiconductor layer 120 is between about 10 nm and 20 nm, where the thickness of the first semiconductor layer 110 is greater than the thickness of the two-dimensional electron gas 112. The thickness T of the two-dimensional electron gas 112 depends on the thickness of the second semiconductor layer 120. For example, in one embodiment, when the thickness of the second semiconductor layer 120 is 10 nm, the thickness of the two-dimensional electron gas 112 is about 7 nm to 10 nm. In another embodiment, when the thickness of the second semiconductor layer 120 is 20 nm, the thickness of the two-dimensional electron gas 112 is about 15 nm to 20 nm.

[0041] In some embodiments, the first semiconductor layer 110 is formed on a substrate (not shown). The substrate may be a semiconductor substrate or an insulating substrate, wherein the material of the semiconductor substrate may include: an elemental semiconductor, such as silicon or germanium; or a compound semiconductor, such as silicon carbide, gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination of the foregoing. The material of the insulating substrate may include sapphire or other suitable materials. The substrate may also be a multi-layered substrate, such as a silicon-on-insulator (SOI) substrate. Although not shown, a nucleation layer may also be formed on the substrate to improve the epitaxial quality of subsequently formed film layers (such as the first semiconductor layer 110 and the second semiconductor layer 120).

[0042] In addition, in some embodiments, a buffer layer is formed between the substrate and the first semiconductor layer 110 to alleviate the strain caused by lattice mismatch between the substrate and the first semiconductor layer 110 to prevent defects from being formed in the first semiconductor layer 110. The material of the buffer layer 102 includes aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), other suitable materials, or a combination of the foregoing. The buffer layer 102 can be formed by an epitaxial growth process, such as a metal organic chemical vapor deposition (MOCVD) process, a hydride vapor phase epitaxy (HVPE) process, a molecular beam epitaxy (MBE) process, other suitable processes, or a combination of the foregoing.

[0043] Next, after forming the first semiconductor layer 110 and the second semiconductor layer 120, a passivation layer 130 covering the top surface of the second semiconductor layer 120 may be formed on the second semiconductor layer 120. The passivation layer 130 can protect the first semiconductor layer 110 and the second semiconductor layer 120 directly below in the subsequent etching process. In addition, in some embodiments, the passivation layer 130 can be used to passivate the top surface of the second semiconductor layer 120, thereby significantly suppressing the current collapse effect and reducing the surface leakage current. In some embodiments, the thickness of the formed passivation layer 130 is between about 65nm and 300nm, for example, about 100nm.

[0044] The material of the passivation layer 130 may include oxide, nitride, oxynitride, other suitable materials, or a combination thereof. For example, in a specific embodiment, silicon nitride is used as the material of the passivation layer 130. The method for forming the passivation layer 130 may include a metal organic chemical vapor deposition (MOCVD) process, a hydride vapor phase epitaxy (HVPE) process, a molecular beam epitaxy (MBE) process, other suitable methods, or a combination thereof.

[0045] Next, refer to Figure 1, the second semiconductor layer 120 and the first semiconductor layer 110 may be etched to form a second vertical sidewall 120S and a first vertical sidewall 110S exposed in the opening O, respectively. Here, the term “vertical” means that the first vertical sidewall 110S and the second vertical sidewall 120S are substantially perpendicular to the horizontal direction of the semiconductor structure 10, for example Figure 1 In some embodiments, the first vertical sidewall 110S and the second vertical sidewall 120S are substantially perpendicular to the bottom surface of the opening O. In some embodiments, as Figure 1 As shown, the first vertical sidewall 110S extends from the bottom surface of the opening O to the junction between the first semiconductor layer 110 and the second semiconductor layer 120 , and the second vertical sidewall 120S extends from the above junction to the top surface of the second semiconductor layer 120 .

[0046] The etching process of the first semiconductor layer 110 and the second semiconductor layer 120 can be performed by anisotropic etching. For example, the etching process may include dry etching, such as reactive ion etching (RIE). In addition, the etching process may be performed in a low pressure environment, such as a pressure of about 10 to 50 mtorr. In some embodiments, the etching of the first semiconductor layer 110 and the second semiconductor layer 120 is performed at a power of 500 W to 1000 W, and the etching time may be between about 25 seconds and 60 seconds. The etchant used in the etching process may include CHF 3 , C 4 F 8 CF 4 , Cl 2 , other suitable etchants, or combinations thereof. For example, in a specific embodiment, CHF 3 As an etchant, and applying a radio frequency power of more than 500 W to etch the first semiconductor layer 110 and the second semiconductor layer 120, a first vertical sidewall 110S and a second vertical sidewall 120S with an inclination angle close to 90° can be formed. It should be understood that, herein, the so-called "inclination angle" refers to the angle between the sidewall of a specific film layer and the horizontal direction of the semiconductor structure 10. In the case where the opening O has a flat bottom, the "inclination angle" may also refer to the angle between the sidewall of the specific film layer and the bottom of the opening O.

[0047] A mask layer (not shown) may be further formed on the second semiconductor layer 120 (e.g., on the top surface of the passivation layer 130) before the etching process is performed. In some embodiments, the mask layer is formed of a dielectric material, including: an organic material, such as a photoresist (e.g., Su8), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer; an inorganic material, such as silicone, glass, aluminum oxide (Al2O3); 2 O 3 ), Silicon Nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ).

[0048] The formation of the mask layer may include using a photolithography process to pattern the material for the mask layer. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin-drying) and / or hard baking, other suitable photolithography steps, and / or combinations of the foregoing.

[0049] In the above etching process, the passivation layer 130, the second semiconductor layer 120, and the first semiconductor layer 110 can be etched in sequence. By using appropriate etchants and etching parameters, the passivation layer 130, the second semiconductor layer 120, and the first semiconductor layer 110 can be etched with the same etchant. That is, the materials of the passivation layer 130, the second semiconductor layer 120, and the first semiconductor layer 110 can be etched using a common device.

[0050] After the opening O is formed, an electrode structure 140 may be formed in the opening O to cover the first vertical sidewall 110S and the second vertical sidewall 120S. Figure 1As shown, the electrode structure 140 may be in direct contact with the first vertical sidewall 110S. The electrode structure 140 may form an ohmic contact with the two-dimensional electron gas 112 at the interface 112I. In some embodiments, the electrode structure 140 is a source or a drain of the semiconductor structure 10. Therefore, current may be conducted from the electrode structure 140 located laterally on one side of the two-dimensional electron gas 112 to the source or drain on the other side via the two-dimensional electron gas 112. In some embodiments, as Figure 1 As shown, in addition to the opening O, the electrode structure 140 further extends to directly above the first semiconductor layer 110 , the second semiconductor layer 120 , and the passivation layer 130 .

[0051] The electrode structure 140 may be formed as a multi-layer structure. Figure 1 , the formation of the electrode structure 140 may include conformally forming a bottom metal layer 142 in the opening O. The bottom metal layer 142 may include a conductive material with low resistance, such as a metal, a metal compound, or a combination of the foregoing. For example, the metal includes gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, silver, an alloy or a multilayer structure of the foregoing metals, or a combination of the foregoing; the metal compound includes, for example, titanium nitride. The formation method of the bottom electrode layer 142 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or a combination of the foregoing. The thickness of the bottom electrode layer 142 is between about 150nm and 300nm.

[0052] In some embodiments, the formation of the electrode structure 140 further includes sequentially forming an intermetallic dielectric layer 144 and a top metal layer 146 on the bottom metal layer 142. The material of the intermetallic dielectric layer 144 may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials, or a combination of the foregoing. The method for forming the intermetallic dielectric layer 144 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination of the foregoing. The material and formation method of the top metal layer 146 may be similar to the bottom metal layer 142, and a detailed description thereof is omitted here for the sake of brevity. In some embodiments, the thickness of the top electrode layer 146 is greater than the thickness of the bottom electrode layer 142. By further forming the intermetallic dielectric layer 144 and the top metal layer 146, compared with the electrode structure 140 in which only the bottom electrode layer 142 with a thinner thickness is formed, the high voltage resistance of the electrode structure 140 can be improved, and the ohmic contact of the semiconductor structure 10 can be further improved. However, in some other embodiments, the intermetallic dielectric layer 144 and the top metal layer 146 may not be formed on the conformal bottom electrode layer 142 , and a voltage may be applied to the first semiconductor layer 110 and the second semiconductor layer 120 directly through the bottom electrode layer 142 .

[0053] In some embodiments, each inclination angle of the first vertical sidewall 110S and the second vertical sidewall 120S is between 85° and 95°. By forming the first vertical sidewall 110S and the second vertical sidewall 120S to have substantially vertical sidewalls, the two-dimensional electron gas 112 in the first semiconductor layer 110 can also be well distributed near the interface 112I between the first semiconductor layer 110 and the electrode structure 140. In some embodiments, as Figure 1 and Figure 2A As shown, the first vertical sidewall 110S and the second vertical sidewall 120S have the same inclination angle. In some further embodiments, the side surface of the passivation layer 130 has the same inclination angle as the first vertical sidewall 110S and the second vertical sidewall 120S.

[0054] The following will refer to Figure 2A , Figure 2B The effect of the inclination angles of the first vertical sidewall 110S and the second vertical sidewall 120S on the performance of the semiconductor structure 10 is described. Figure 2A , Figure 2B Only the bottom electrode layer 142 of the electrode structure 140 is shown, and the intermetallic dielectric layer 144 and the top electrode layer 146 which may be omitted are not shown.

[0055] Figure 2A1 is a partial cross-sectional view of a semiconductor structure 10 according to some embodiments of the present invention. In the semiconductor structure 10 of the present invention, the first semiconductor layer 110 and the second semiconductor layer 120 respectively have substantially vertical first vertical sidewalls 110S and second vertical sidewalls 120S, so that the interface 112I between the bottom electrode layer 142 and the two-dimensional electron gas 112 can have a lower contact resistance. Specifically, since the inclination angles of the first vertical sidewalls 110S and the second vertical sidewalls 120S are close to 90°, the two-dimensional electron gas 112 can have a uniform electron concentration in the horizontal direction of the semiconductor structure 10, so that the two-dimensional electron gas 112 can have a sufficient electron concentration near the interface 112I of the adjacent electrode structure (for example, the interface between the two-dimensional electron gas 112 and the bottom electrode layer 142). Since the bottom electrode layer 142 can be electrically connected to the two-dimensional electron gas 112 with a higher electron concentration with a larger area, the semiconductor structure 10 of the present invention has a better ohmic contact property.

[0056] In contrast, Figure 2B According to some existing manufacturing processes of the semiconductor structure 10', a partial cross-sectional view of the semiconductor structure 10' without good ohmic contact between the electrode structure and the two-dimensional electron gas 112 is depicted. The electrode structure including the bottom electrode layer 142 is formed in the opening O' left after etching the first semiconductor layer 110 and the second semiconductor layer 120. In addition, the sidewalls of the first semiconductor layer 110 and the second semiconductor layer 120 of the semiconductor structure 10' have tilt angles θ1 and θ2, respectively, and θ1 and θ2 are less than 85°.

[0057] like Figure 2B As shown, since the inclination angle θ2 of the sidewall of the second semiconductor layer 120 is less than 85°, the thickness of the portion of the second semiconductor layer 120 adjacent to the bottom electrode layer 142 gradually becomes thinner. Therefore, the ability of the second semiconductor layer 120 to supply electrons to the first semiconductor layer 110 below is weakened near the bottom electrode layer 142, so that the electron concentration of the two-dimensional electron gas 112 near the bottom electrode layer 142 is low, and the thickness T' of the two-dimensional electron gas 112 in the vertical direction is also significantly reduced near the bottom electrode layer 142. That is, the two-dimensional electron gas 112 in the semiconductor structure 10' cannot have a uniform electron concentration in the horizontal direction of the semiconductor structure 10'. In addition, since the inclination angle θ1 of the sidewall of the first semiconductor layer 110 is less than 85°, the electron concentration near the interface between the first semiconductor layer 110 and the bottom electrode layer 142 becomes lower, making it difficult for the electrode structure to form a good ohmic contact with the two-dimensional electron gas 112.

[0058] If one of the first semiconductor layer 110 and the second semiconductor layer 120 has a vertical sidewall and the other has a tilt angle less than, for example, 85°, the two-dimensional electron gas 112 of the semiconductor structure 10′ cannot have a sufficiently uniform electron concentration in the horizontal direction of the semiconductor structure 10′ compared to the semiconductor structure 10 of the present invention. Therefore, in such a case, the contact resistance between the electrode structure and the two-dimensional electron gas 112 will also be higher than the contact resistance at the interface 112I of the semiconductor structure 10 of the present invention.

[0059] In some other semiconductor structures of the prior art (not shown in the drawings), the sidewalls of the first semiconductor layer 110 and / or the second semiconductor layer 120 are not vertical sidewalls, and the inclination angles θ1 and / or θ2 are greater than, for example, 95°. That is, the side ends of the first semiconductor layer 110 and the second semiconductor layer 120 have an undercut structure. In such a case, it is difficult for the material of the electrode structure 140 to be well deposited on the sidewalls of the first semiconductor layer 110 and / or the second semiconductor layer 120. As a result, a gap may be formed between the electrode structure 140 and the first semiconductor layer 110 and / or the second semiconductor layer 120, resulting in poor ohmic contact properties of the semiconductor structure.

[0060] As described above, by forming the first vertical sidewall 110S and the second vertical sidewall 120S substantially perpendicular to the horizontal direction of the semiconductor structure 10, the electrode structure 140 can form a good electrical contact with the two-dimensional electron gas 112, thereby providing a lower contact resistance. Therefore, the method for forming a semiconductor structure of the present invention can form a high electron mobility transistor (HEMT) that meets electrical requirements, and can improve the product yield of the high electron mobility transistor.

[0061] In addition to the tilt angles of the first vertical sidewall 110S and the second vertical sidewall 120S, the height H1 of the first vertical sidewall 110S and the thickness of the second semiconductor layer 12 may also affect the ohmic contact properties of the semiconductor structure 10 , as discussed below.

[0062] The height H1 of the first vertical sidewall 110S and the height H2 of the second vertical sidewall 120S may depend on the depth of the opening O formed in the etching process and the thickness of the second semiconductor layer 120, respectively. In some embodiments, the thickness of the second semiconductor layer 12 is equal to the height H2 of the second vertical sidewall 120S. In some embodiments, the depth of the opening O is the sum of the height H1, the height H2, and the thickness of the passivation layer 130. If the thickness of the second semiconductor layer 120 is thicker, the second semiconductor layer 120 will be able to supply more electrons to the two-dimensional electron gas 112 below. In this way, the concentration of the two-dimensional electron gas 112 is higher and the thickness is thicker, improving the ohmic contact properties of the interface 112I. If the height H1 of the first vertical sidewall 110S is higher, the electrode structure 140 will be able to be electrically connected to the two-dimensional electron gas 112 with a larger contact area, so that the contact resistance at the interface 112I is reduced and the performance of the semiconductor structure 10 is improved. In some embodiments, as Figure 2A As shown, the height H1 of the first vertical sidewall 110S is greater than the thickness T of the two-dimensional electron gas 112 .

[0063] Figure 3 1 is a graph showing the relationship between the vertical profile length and the contact resistance of the semiconductor structure 10 according to some embodiments of the present invention. The so-called vertical profile means that the inclination angles of the first vertical sidewall 110S and the second vertical sidewall 120S are substantially 90°, and the term "vertical profile length" may refer to the sum of the height H1 of the first vertical sidewall 110S and the height H2 of the second vertical sidewall 120S. By selecting an appropriate etchant and etching parameters for the etching process of the opening O, such as Figure 3 As shown, the total height of the first vertical sidewall 110S and the second vertical sidewall 120S may be greater than 20 nm. 3 As an etchant, the first semiconductor layer 110 and the second semiconductor layer 120 can be anisotropically etched to be substantially vertical and have a longer vertical profile. For example, the vertical profile can be about 40 nm. In addition, Figure 3 The relationship between the vertical profile length and the contact resistance shown in FIG. 1 is measured with the semiconductor structure 10 in which the electrode structure 140 only includes the compliant bottom electrode layer 142. It should be understood that the contact resistance (R C ) is measured by measuring the ohmic resistance at different gate distances, rather than by changing the applied voltage and measuring the ohmic resistance. In addition, the measured ohmic resistance is derived from the sheet resistance (R S ) and the contact resistance (R C ) is the sum of the gate distance and the measured ohmic resistance. The contact resistance (RC ) value.

[0064] like Figure 3 As shown, the contact resistance between the electrode structure 140 and the two-dimensional electron gas 112 decreases as the vertical profile length increases. When the vertical profile length increases to about 20 nm, the contact resistance between the electrode structure 140 and the two-dimensional electron gas 112 is less than 0.5 ohm·mm. In the existing semiconductor structure in which the semiconductor layer does not have a substantially vertical sidewall or the vertical profile is less than 20 nm, only a contact resistance of more than 0.5 ohm·mm can be measured. Therefore, the semiconductor structure 10 of the present invention can improve the ohmic contact property of the interface between the electrode structure 140 and the two-dimensional electron gas 112.

[0065] In other embodiments of the present invention, the contact resistance between the electrode structure 140 and the two-dimensional electron gas 112 can be further reduced by measuring the semiconductor structure 10 in which the electrode structure 140 further includes an intermetallic dielectric layer 144 and a top electrode layer 146. For example, when the vertical profile length increases to more than 20 nm, the contact resistance between the electrode structure 140 and the two-dimensional electron gas 112 can be less than 0.3 ohm·mm.

[0066] It is understood that by selecting appropriate etchants and etching parameters for the etching process of the opening O to increase the vertical profile length of the semiconductor structure 10 , the contact area between the electrode structure 140 and the two-dimensional electron gas 112 can be increased to further reduce the contact resistance at the interface 112I.

[0067] In summary, the present invention provides a method for forming a semiconductor structure, which can improve the ohmic contact properties between an electrode (such as a source or a drain) and a two-dimensional electron gas by forming an opening with an appropriate profile in an etching process. Specifically, the etching process forms an opening that exposes substantially vertical sidewalls of multiple semiconductor layers, thereby forming an ohmic contact with low contact resistance. In some cases, for example, the semiconductor layer is a film layer (including, for example, a buffer layer, a channel layer, a barrier layer, etc.) of a high electron mobility transistor (HEMT) device formed subsequently. If the interface between the semiconductor layer and the electrode structure is substantially vertical, the two-dimensional electron gas in the film layer will be able to be well distributed near the interface between the semiconductor layer and the electrode structure, and the electrode material deposited subsequently can be well deposited on the sidewalls of the semiconductor layer. In some embodiments, by selecting appropriate etching parameters to increase the depth of the vertical sidewalls, the contact area between the electrode structure and the two-dimensional electron gas can be increased to further reduce the contact resistance between the electrode structure and the two-dimensional electron gas. Therefore, the method for forming a semiconductor structure of the present invention can better form a high electron mobility transistor (HEMT) that meets electrical requirements and can improve the product yield of the high electron mobility transistor.

[0068] The features of several embodiments are summarized above so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and can be variously changed, replaced and substituted without violating the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Forming a second semiconductor layer on a first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have different energy band gaps; Performing an etching process to form an opening respectively exposing a first vertical sidewall of the first semiconductor layer and a second vertical sidewall of the second semiconductor layer; as well as An electrode structure is formed in the opening to cover the first vertical sidewall and the second vertical sidewall.

2. The method for forming a semiconductor structure according to claim 1, wherein: Each inclination angle of the first vertical sidewall and the second vertical sidewall is between 85° and 95°.

3. The method for forming a semiconductor structure according to claim 1, wherein: The first vertical side wall and the second vertical side wall have the same inclination angle.

4. The method for forming a semiconductor structure according to claim 1, wherein: The total height of the first vertical sidewall and the second vertical sidewall is greater than 20 nm.

5. The method for forming a semiconductor structure according to claim 1, wherein: The electrode structure is in direct contact with the first vertical sidewall.

6. The method for forming a semiconductor structure according to claim 1, wherein: The first vertical sidewall extends from the bottom surface of the opening to a junction between the first semiconductor layer and the second semiconductor layer, and the second vertical sidewall extends from the junction to the top surface of the second semiconductor layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: A two-dimensional electron gas is generated in the first semiconductor layer and adjacent to the second semiconductor layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The electrode structure forms an ohmic contact with the two-dimensional electron gas.

9. The method for forming a semiconductor structure according to claim 8, wherein: The contact resistance between the electrode structure and the two-dimensional electron gas is less than 0.5 ohm·mm.

10. The method for forming a semiconductor structure according to claim 7, wherein: The height of the first vertical sidewall is greater than the thickness of the two-dimensional electron gas.

11. The method for forming a semiconductor structure according to claim 7, wherein: The two-dimensional electron gas has a uniform electron concentration in the horizontal direction.

12. The method for forming a semiconductor structure according to claim 1, wherein: The method further includes forming a passivation layer on the second semiconductor layer to cover the top surface of the second semiconductor layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the etching process, the passivation layer, the second semiconductor layer, and the first semiconductor layer are etched in sequence, and the passivation layer, the second semiconductor layer, and the first semiconductor layer are etched using the same etchant.

14. The method for forming a semiconductor structure according to claim 12, wherein: The side surface of the passivation layer has the same inclination angle as the first vertical side wall and the second vertical side wall.

15. The method for forming a semiconductor structure according to claim 1, wherein: The etchants used in the etching process include CHF3, C4F8, CF4, and Cl2.

16. The method for forming a semiconductor structure according to claim 1, wherein: The formation of the electrode structure includes conformally forming a bottom metal layer in the opening.

17. The method for forming a semiconductor structure according to claim 16, wherein: The formation of the electrode structure further includes sequentially forming an intermetallic dielectric layer and a top metal layer on the bottom metal layer.

18. The method for forming a semiconductor structure according to claim 1, wherein: The electrode structure is a source or a drain of the semiconductor structure.

19. The method for forming a semiconductor structure according to claim 1, wherein: The energy band gap of the first semiconductor layer is smaller than the energy band gap of the second semiconductor layer.

20. The method for forming a semiconductor structure according to claim 1, wherein: The first semiconductor layer is formed of undoped gallium nitride, and the second semiconductor layer is formed of aluminum-doped gallium nitride.

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