VDMOS device

Abstract

The embodiment of the invention provides a VDMOS device. The VDMOS device comprises a substrate, an epitaxial layer located on the substrate and a drain electrode located on the back side of the substrate. The well region of the first doping type is formed downwards from the upper surface of the epitaxial layer; the source region of the second doping type is formed downwards from the upper surface of the well region; the first doping region of the first doping type is downwards formed in the source region from the upper surface of the source region, and the first doping region and the source region form a PN junction which is defined as a secondary PN junction; wherein the parts of the source region, which are positioned on the two sides of the first doped region, are a source region first side part and a source region second side part; the top of the first side portion of the source region is used for being grounded, and when the VDMOS device is switched on, the potential change of the second side portion of the source region is positive, and reverse bias of the second-level PN junction is achieved. The VDMOS device solves the technical problem that a traditional VDMOS device is insufficient in short circuit capacity along with increase of saturation current.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a VDMOS device. Background Art

[0002] The current VDMOS devices on planar silicon carbide substrates have short channel length, high current density, high saturation current, poor saturation linearity, and poor short-circuit capability.

[0003] Since the channel length of the VDMOS device on the planar silicon carbide substrate is short, as the drain voltage increases, the drain barrier lowering effect is obvious, and the saturation current continues to increase with the increase of the drain voltage, reducing the short-circuit capability.

[0004] Figure 1-1 This is a simulation diagram of a VDMOS device on a traditional planar silicon carbide substrate; Figure 1-2 1 is a schematic diagram of the conduction state of the VDMOS device shown in FIG. 1; Figure 2 FIG. 1 is a graph showing the drain voltage and saturation current of the VDMOS device shown in FIG. 1 .

[0005] in, Figure 1-2 The dotted line in the figure shows the current path of the on-current, the source region 3 and the well region 4. Figure 2 In the graph, curve ① is the drain-source voltage and saturation current curve at T = 400°C, and curve ② is the drain-source voltage and saturation current curve at T = 25°C. The horizontal axis is the drain-source voltage Vds, in V; the vertical axis is the saturation current Idsat, in A. Figure 2 It can be seen that with the increase of drain-source voltage Vds, the drain barrier lowering effect is obvious, and the saturation current Idsat continues to increase with the increase of drain-source voltage Vds, which reduces the short-circuit capability of the VDMOS device.

[0006] Therefore, the short-circuit capability of conventional VDMOS devices is insufficient as the saturation current increases, which is a technical problem that those skilled in the art urgently need to solve.

[0007] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0008] The embodiment of the present application provides a VDMOS device to solve the technical problem that the short-circuit capability of the conventional VDMOS device is insufficient as the saturation current increases.

[0009] The present application embodiment provides a VDMOS device, including:

[0010] A substrate, an epitaxial layer located on the substrate, and a drain located on the back side of the substrate;

[0011] A well region of a first doping type is formed downward from the upper surface of the epitaxial layer;

[0012] A source region of a second doping type is formed downward from the upper surface of the well region;

[0013] A first doping region of a first doping type is formed in the source region from the upper surface of the source region downward, the first doping region and the source region form a PN junction and are defined as a secondary PN junction;

[0014] Among them, the parts of the source region located on both sides of the first doped region are the first side of the source region and the second side of the source region; the top of the first side of the source region is used for grounding, and when the VDMOS device is turned on, the potential of the second side of the source region changes to positive to realize reverse bias of the secondary PN junction.

[0015] The embodiment of the present application adopts the above technical solution, which has the following technical effects:

[0016] The VDMOS device of the embodiment of the present application is no longer turned off by gate independent control, but when the VDMOS device is turned on and the on-current is small and less than the preset secondary turn-off current threshold, the gate controls the first-level turn-off; when the VDMOS device is turned on and the on-current abnormally increases to be greater than or equal to the secondary turn-off current threshold, the gate does not perform the first-level turn-off, and the second-level turn-off of the VDMOS device is realized by the reverse bias voltage of the secondary PN junction. In this way, when the VDMOS device of the embodiment of the present application is turned on, when the on-current abnormally increases to be greater than or equal to the secondary turn-off current threshold, that is, when the VDMOS device is in the on state and a short circuit occurs, the VDMOS device of the embodiment of the present application can realize the second-level turn-off of the VDMOS device through the reverse bias voltage of the secondary PN junction without the gate performing the first-level turn-off, so as to prevent the on-current greater than or equal to the secondary turn-off current threshold from burning the VDMOS device, thereby realizing the short-circuit protection of the VDMOS device, that is, the VDMOS device has a strong ability to adapt to short circuits, thereby making the reliability of the VDMOS device higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1-1 This is a simulation diagram of a VDMOS device on a traditional planar silicon carbide substrate;

[0019] Figure 1-2 for Figure 1-1 Schematic diagram of the on-state of the VDMOS device shown;

[0020] Figure 2 is a graph of the drain-source voltage Vds and the saturation current Idsat of the VDMOS device shown in FIG1 ;

[0021] Figure 3 A schematic top view showing position A of a VDMOS device according to an embodiment of the present application;

[0022] Figure 4-1 for Figure 3 Partial cross-sectional view at position A in the middle;

[0023] Figure 4-2 for Figure 4-1 A partial enlarged view of

[0024] Figure 5 A schematic top view showing position B of a VDMOS device according to an embodiment of the present application;

[0025] Figure 6-1 for Figure 5 Partial cross-sectional view at position B;

[0026] Figure 6-2 for Figure 6-1 A partial enlarged view of

[0027] Figure 7-1 A simulation diagram of a VDMOS device according to an embodiment of the present application;

[0028] Figure 7-2 for Figure 7-1 Schematic diagram of the on-state of the VDMOS device shown;

[0029] Figure 8 It is a schematic diagram of the step 2 in the method for preparing a VDMOS device in the background technology;

[0030] Fig. 9 It is a schematic diagram of the step 3 in the method for preparing a VDMOS device in the background technology;

[0031] Fig.10 It is a schematic diagram of the step 4 in the method for preparing a VDMOS device in the background technology;

[0032] Fig.11 This is a schematic diagram of the step 2 in the method for preparing a VDMOS device of the present application;

[0033] Fig.12 This is a schematic diagram of the step 3 in the method for preparing the VDMOS device of the present application;

[0034] Fig.13This is a schematic diagram of the step 4 in the method for preparing the VDMOS device of the present application;

[0035] Fig.14 It is a simulation diagram of the first specific embodiment in the comparison table of the VDMOS device of the present application under the conditions of ambient temperature T=25°C, gate-source voltage Vgs=18V, and drain current Id=16A;

[0036] Fig.15 It is a simulation diagram of the first specific embodiment in the comparison table of the VDMOS device of the present application under the conditions of ambient temperature T=400° C., gate-source voltage Vgs=18V, and drain-source voltage Vds=800V;

[0037] Fig.16 This is a simulation diagram of the first specific embodiment in the VDMOS device comparison table of the present application under the conditions of ambient temperature T=25°C, gate-source voltage Vgs=18V, and drain-source voltage Vds=800V;

[0038] Fig.17 for Fig.15 The VDMOS device shown and Figure 1-1 The graph of drain-source voltage Vds and saturation current Idsat of the VDMOS device shown in FIG. 1 is a graph of drain-source voltage Vds and saturation current Idsat under the conditions of ambient temperature T=400°C, gate-source voltage Vgs=18V, and drain current Id=16A;

[0039] Fig.18 for Fig.15 The VDMOS device shown and Figure 1-1 A curve diagram of the drain-source voltage Vds and the saturation current Idsat of the VDMOS device shown in FIG. 1 under the conditions of an ambient temperature T = 25° C., a gate-source voltage Vgs = 18V, and a drain current Id = 16A;

[0040] Fig.19 The first specific embodiment and Figure 1-1 A graph of drain-source voltage Vds and saturation current Idsat of the VDMOS device shown in FIG. 1 under the conditions of ambient temperature T=175°C, gate-source voltage Vgs=18V, and drain-source voltage Vds=800V;

[0041] Fig. 20 The first specific embodiment and Figure 1-1 The VDMOS device shown is a curve diagram of the drain-source voltage Vds and the saturation current Idsat under the conditions of ambient temperature T=175°C, gate-source voltage Vgs=18V, and drain-source voltage Vds=800V.

[0042] Reference numerals:

[0043] In the background technology:

[0044] Source region 3, well region 4;

[0045] This application:

[0046] Gate 1, gate oxide 2,

[0047] source region 3, source region first side portion 3-1, source region second side portion 3-2, source region bottom portion 3-3,

[0048] Well region 4 , source contact region 5 , epitaxial layer 6 , source contact hole 7 , first doped region 8 . DETAILED DESCRIPTION

[0049] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0050] Embodiment 1

[0051] like Figure 3 , Figure 4-1 , Figure 4-2 , Figure 5 , Figure 6-1 , Figure 6-2 , Figure 7-1 , Figure 7-2 As shown, a VDMOS device according to an embodiment of the present application includes:

[0052] A substrate, an epitaxial layer 6 located on the substrate, and a drain located on the back side of the substrate;

[0053] A well region 4 of a first doping type is formed in the epitaxial layer from the upper surface of the epitaxial layer downward;

[0054] A source region 3 of a second doping type is formed downward from the upper surface of the well region 4 in the well region 4;

[0055] A first doping region 8 of a first doping type is formed in the source region 3 from the upper surface of the source region 3 downward, the first doping region 8 and the source region 3 form a PN junction and are defined as a secondary PN junction; the portion of the source region 3 located below the first doping region 8 is a source region bottom portion 3-3, and the portions of the source region 3 located on both sides of the first doping region 8 are a source region first side portion 3-1 and a source region second side portion 3-2;

[0056] The top of the first side portion 3-1 of the source region is used for grounding. When the VDMOS device is turned on, the potential of the second side portion 3-2 of the source region changes to positive to achieve reverse bias of the secondary PN junction.

[0057] Specifically, Figure 4-1 and Figure 4-2 As shown, there are two source regions 3 on both sides of the dotted line. Figure 4-1 and Figure 4-2 In the example, the source regions 3 are connected together. Figure 6-1 and Figure 6-2 As shown, two source regions 3 are arranged with an interval therebetween, a source contact region 5 is arranged between the two source regions 3 , and the source contact region 5 is respectively connected to the two source regions 3 on both sides.

[0058] The working process of the VDMOS device of the present application as the drain-source voltage Vds increases is described below:

[0059] Phase 1: The VDMOS device is turned on. At this time, the drain-source voltage Vds is small. When the on-current increases from zero and remains small, the on-current flows from the drain through the second side portion 3-2 of the source region and the bottom portion 3-3 of the source region (i.e., the portion of the source region 3 located below the first doped region 8) to the first side portion 3-1 of the source region. Since the top of the first side portion 3-1 of the source region is grounded, the potential Vs1 at the position where the first side portion 3-1 of the source region is grounded (i.e., the top) is zero. The on-current flows through the second side portion 3-2 of the source region and the bottom portion 3-3 of the source region to the first side portion 3-1 of the source region. Since the on-current is small, the potential Vs2 of the second side portion 3-2 of the source region is raised to change to positive, but Vs2 is still small. That is, the potential Vs2 of the second side portion 3-2 of the source region is raised to change to positive, realizing the reverse bias of the secondary PN junction. At this time, the non-depleted region of the secondary PN junction formed by the first doped region 8 and the source region 3 becomes narrower, and the resistance of the secondary PN junction becomes larger, but the on-current can still pass through. Because the resistance presented by the secondary PN junction at this time is still small, that is, it will not cause the on-resistance Rdson to become very large. If the on-resistance Rdson is very large, it will have a bad effect on the performance of the VDMOS device. Therefore, the VDMOS device does not want the on-resistance Rdson to become very large.

[0060] The second stage: the drain-source voltage Vds continues to increase, the on-current continues to increase, the potential Vs2 of the second side portion 3-2 of the source region, that is, the reverse bias voltage of the secondary PN junction increases, so that the gate-source voltage Vgs decreases and the saturation current decreases. At this time, the depletion region of the secondary PN junction becomes wider and wider, and the resistance of the secondary PN junction becomes larger and larger, but the on-current can still pass through.

[0061] The third stage: when the drain-source voltage Vds increases abnormally, the on-current increases abnormally, causing the reverse bias voltage of the secondary PN junction to increase, resulting in the width of the depletion region of the secondary PN junction being larger than the source region, and the current path being cut off, resulting in the on-current being unable to pass through the source region 3. At this time, the secondary PN junction shuts down the VDMOS device at the secondary level and it is no longer turned on. The on-current drops sharply to the leakage current level, and the leakage current is a very small current.

[0062] In order to distinguish the shutdown of the VDMOS device by the reverse bias voltage of the secondary PN junction and the shutdown of the VDMOS device by the gate control, the shutdown of the VDMOS device by the gate control is defined as the primary shutdown, and the shutdown of the VDMOS device by the reverse bias voltage of the secondary PN junction is the secondary shutdown. When the depletion region of the secondary PN junction is disconnected, the corresponding on-current value is used as the preset secondary shutdown current threshold.

[0063] Therefore, the following conclusions are drawn:

[0064] As the drain-source voltage Vds continues to increase, the VDMOS device is turned on and the on-current increases;

[0065] When the drain-source voltage Vds abnormally increases to a large value, causing the on-current to abnormally increase to be greater than or equal to the preset secondary shutdown current threshold, the reverse bias voltage of the secondary PN junction performs secondary shutdown on the VDMOS device, and the on-current drops to the leakage current level.

[0066] The VDMOS device is turned on, and when the on current is less than the secondary turn-off current threshold, the primary turn-off of the VDMOS device is controlled by the gate.

[0067] The VDMOS device of the embodiment of the present application is no longer turned off by independent gate control, but the drain-source current Ids (i.e., drain current Id) continues to increase during the process of continuous increase of the drain-source voltage Vds:

[0068] When the VDMOS device is turned on and the on current is small and less than the preset secondary turn-off current threshold, the gate controls the primary turn-off;

[0069] When the drain-source voltage Vds increases abnormally to a large value and the on-current increases abnormally to a value greater than or equal to the secondary shutdown current threshold, the reverse bias voltage of the secondary PN junction is used to realize the secondary shutdown of the VDMOS device when the gate does not perform the primary shutdown. In this way, in the on-state of the VDMOS device of the embodiment of the present application, the drain-source voltage Vds continues to increase, and when the on-current increases abnormally to a value greater than or equal to the secondary shutdown current threshold, that is, when the VDMOS device is short-circuited in the on-state, the VDMOS device of the embodiment of the present application can realize the secondary shutdown of the VDMOS device through the reverse bias voltage of the secondary PN junction when the gate does not perform the primary shutdown, thereby preventing the on-current greater than or equal to the secondary shutdown current threshold from burning the VDMOS device, thereby realizing short-circuit protection of the VDMOS device, and further making the VDMOS device more reliable. In addition, from the simulation of the VDMOS device of the present application, it can be seen that as the drain-source voltage Vds continues to increase, the on-current increases from small to large, and after increasing to the saturation current, the saturation current remains basically unchanged, making the short-circuit capability of the VDMOS device of the present application stronger.

[0070] Specifically, the first doping type is P-type doping, and the second doping type is N-type doping; or, the first doping type is N-type doping, and the second doping type is P-type doping.

[0071] In implementation, the first doped region 8 is floating; or the first doped region 8 is grounded.

[0072] It is better to float the first doped region 8 than to ground it.

[0073] Specifically, the conduction of the VDMOS device is controlled by the gate of the VDMOS device.

[0074] Specifically, when the secondary PN junction is reverse biased, the secondary PN junction presents a high resistance.

[0075] Since the top of the first side portion 3 - 1 of the source region is used for grounding, the potential Vs1 of the first side portion 3 - 1 of the source region at the grounding position (ie, the top) is zero;

[0076] like Figure 4-2 and Figure 6-2 As shown, the on-current (indicated by a curved line with an arrow in the figure) flows from the drain through the second side portion 3-2 of the source region and the bottom portion 3-3 of the source region to the top of the first side portion 3-1 of the source region.

[0077] Since the secondary PN junction presents high resistance when the secondary PN junction is reverse biased, the resistance of the secondary PN junction cannot be ignored and must be taken into consideration. This is exactly what the present application makes use of. In the process of conducting the current through the source region, the potential reduction generated cannot be ignored. That is, the potential Vs2 of the second side portion 3-2 of the source region is higher than the potential Vs1 of the first side portion 3-1 of the source region at the ground position (i.e., the top), and the secondary PN junction realizes the reverse bias of the secondary PN junction through the potential Vs2 of the second side portion 3-2 and the potential Vs1 of the first side portion 3-1 of the source region at the ground position (i.e., the top).

[0078] In implementation, such as Figure 6-1 and Figure 6-2 As shown, the first doped region 8 and the bottom portion 3-3 of the source region form a PN junction and are defined as a secondary third PN junction;

[0079] The first doped region 8 and the first side portion 3-1 of the source region form a PN junction and are defined as a secondary first PN junction, and the first doped region 8 and the second side portion 3-2 of the source region form a PN junction and are defined as a secondary second PN junction;

[0080] The secondary PN junction includes a secondary first PN junction, a secondary second PN junction, and a secondary third PN junction.

[0081] That is, the secondary PN junction actually includes three PN junctions formed by the source region and the bottom and both sides of the first doped region: the secondary first PN junction, the secondary second PN junction, and the secondary third PN junction. When the VDMOS device is turned on and the on-current abnormally increases to be greater than or equal to the preset secondary off-current threshold, at least one of the three PN junctions is pinched off, thereby disconnecting the current path of the on-current and achieving secondary off-current.

[0082] By controlling the doping concentration and width of the first doping region 8 and the source region 3 , it is possible to control which one or two of the secondary first PN junction, the secondary second PN junction, and the secondary third PN junction are pinched off first, thereby achieving secondary shutdown.

[0083] As a preferred manner, when the VDMOS device is turned on, when the potential of the second side portion 3 - 2 of the source region changes to positive, the secondary third PN junction is pinched off first.

[0084] In the process of preparing the source region, even if the goal is to prepare a uniformly doped source region, due to the limitation of the preparation process, the doping concentration at the deeper position of the source region is also less than the doping concentration at the shallower position of the source region. Therefore, the doping concentration of the bottom portion 3-3 of the source region is less than the doping concentration of the top portion of the source region. Therefore, when the width d3 of the bottom portion 3-3 of the source region, the width d1 of the first side portion 3-1 of the source region, and the width d2 of the second side portion 3-2 of the source region are the same, the secondary third PN junction is pinched off first.

[0085] As an optional method, when the VDMOS device is turned on, when the potential of the second side portion 3-2 of the source region changes to positive, the secondary first PN junction, the secondary second PN junction, and the secondary third PN junction are simultaneously pinched off.

[0086] As another optional method, when the VDMOS device is turned on, when the potential of the second side portion 3-2 of the source region changes to positive, any one of the secondary first PN junction, the secondary second PN junction, and the secondary third PN junction is pinched off first.

[0087] As another optional method, when the VDMOS device is turned on, when the potential of the second side portion 3-2 of the source region changes to positive, any two of the secondary first PN junction, the secondary second PN junction, and the secondary third PN junction are first pinched off simultaneously.

[0088] Specifically, by controlling the doping concentration and width of the first doping region 8 and the source region 3, the I 二级关断电流阈值 Numerical control. The doping concentration and width of the first doping region 8 and the source region 3 can be controlled by theoretical calculation or experimental simulation. In actual operation, experimental simulation is more efficient.

[0089] In implementation, the secondary shutdown current threshold I 二级关断电流阈值 , meeting the following requirements:

[0090] I 放大区导通电流 二级关断电流阈值 饱和电流 ;

[0091] Among them, I 放大区导通电流 is the conduction current of the VDMOS device working in the amplification region, I 饱和电流 is the saturation current of the VDMOS device.

[0092] The saturation current of the VDMOS device, that is, the saturation current under high voltage, refers to the maximum value at which the drain current of the device tends to stabilize when the drain-source voltage of the VDMOS device reaches a sufficiently high value, that is, the saturation current I 饱和电流 .

[0093] The VDMOS device is turned on under gate control. With the increase of the drain-source voltage Vds, when the on-current of the VDMOS device abnormally increases to be greater than or equal to the preset secondary turn-off current threshold, the secondary turn-off is achieved through the secondary PN junction. In this way, the on-current of the VDMOS device is prevented from abnormally increasing to exceed the secondary turn-off current threshold, thereby preventing the on-current of the VDMOS device from abnormally increasing to the saturation current.

[0094] I 二级关断电流阈值 The value of determines the timing of secondary shutdown of the VDMOS device. ​​

[0095] If I 二级关断电流阈值 If the value of is too small, the on-state current of the VDMOS device will increase abnormally (i.e. reach I 放大区导通电流 ) will achieve secondary shutdown, the VDMOS device will stop working, and the fault tolerance of the VDMOS device is low.

[0096] If I 二级关断电流阈值 If the value of is too large, the on-state current of the VDMOS device will increase abnormally and approach I 饱和电流 Only then can the secondary shutdown be realized, and the VDMOS device is easily damaged. 二级关断电流阈值 If the value of is too large, the resistance of the secondary PN junction will be too large, which will in turn make the on-resistance of the VDMOS device too large, which will have a bad impact on the performance of the VDMOS device.

[0097] Therefore, in practice, the secondary shutdown current threshold I 二级关断电流阈值 , meeting the following requirements:

[0098]

[0099] In this way, I 二级关断电流阈值 in I 放大区导通电流 and I 饱和电流 and is located in the middle, so that I 二级关断电流阈值 To I 放大区导通电流 and I 饱和电流 The distance between them is close.

[0100] Thus, on the one hand, the on-state current of the VDMOS device increases abnormally to a considerable extent (i.e., reaches I 二级关断电流阈值 ) will realize the secondary shutdown, and the VDMOS device will stop working. The fault tolerance of the VDMOS device is moderate and will not be too low. On the other hand, the resistance of the secondary PN junction is also moderate and will not be too large, so that the on-resistance of the VDMOS device will not be too large, and will not have a bad impact on the performance of the VDMOS device.

[0101] In the implementation, the doping concentration of the source region 3 has a value range of greater than or equal to 10 18 cm -3 Less than or equal to 10 19 cm -3 .

[0102] The doping concentration of the first doping region 8 is one order of magnitude or half an order of magnitude higher than the doping concentration of the source region 3 .

[0103] The source region 3 and the first doping region 8 satisfying the above doping concentration can realize a secondary PN junction in a smaller size.

[0104] In implementation, such as Figure 6-2 and Figure 7-2 As shown, the width d3 of the bottom portion 3-3 of the source region is greater than the width of the depletion layer of the secondary third PN junction when no voltage is applied;

[0105] The width d1 of the first side portion 3-1 of the source region is greater than the width of the depletion layer of the secondary first PN junction when no voltage is applied;

[0106] The width d2 of the second side portion 3 - 2 of the source region is greater than the width of the depletion layer of the secondary second PN junction when no voltage is applied.

[0107] In implementation, such as Figure 3 , Figure 5 , Figure 6-1 As shown, the source region 3 is a strip-shaped source region 3;

[0108] VDMOS devices also include:

[0109] A plurality of source contact regions 5 of a first doping type are formed downward from the upper surface of the well region 4 in the well region 4, and the source contact region 5 is connected to the first side portion 3-1 of the source region; the plurality of source contact regions 5 are arranged at intervals along the length direction of the source region 3;

[0110] A source contact hole 7 is formed on the source contact region 5;

[0111] A grounded source metal is formed on the source contact hole 7;

[0112] The source contact region 5 , the source contact hole 7 and the source metal are connected to connect the first side portion 3 - 1 of the source region to the ground.

[0113] In this way, the first side portion 3 - 1 of the source region is connected to the ground, and the other parts of the source region are not connected to the ground.

[0114] In implementation, such as Figure 3 , Figure 4-1 , Figure 5 , Figure 6-1 As shown, the VDMOS device also includes:

[0115] A gate oxide layer 2 is formed on the well region 4, the source region and the first doped region (8);

[0116] A gate 1, formed on the gate oxide layer 2;

[0117] A gate metal is formed on the gate 1 .

[0118] In practice, the substrate is a silicon carbide substrate. In practical applications, it is not limited to a silicon carbide substrate, but may also be a silicon substrate.

[0119] Specifically, the anode of the MOSFET integrated with HJD includes the P-poly region 33-1 and the second P+ injection region 33-2; the ohmic contact region 41 serves as the anode of the MOSFET integrated with SBD;

[0120] The drain electrode disposed on the back side of the substrate serves as the cathode of the MOSFET integrated with the HJD and the cathode of the MOSFET integrated with the SBD.

[0121] The saturation current of a semiconductor device refers to the maximum current at which the device can operate stably under specific conditions. In semiconductor devices, the saturation current usually refers to the current of a transistor (such as a field effect transistor (FET) and a bipolar junction transistor (BJT)) in a saturated state.

[0122] For Field Effect Transistors (FETs):

[0123] Saturation current I dsat :In the saturation region of the field effect transistor, the drain current (Id) reaches its maximum value, which is called the saturation current. It depends on the gate-source voltage (Vgs), drain-source voltage (Vds), transistor process parameters, etc. Saturation current I dsat The source satisfies the following relationship:

[0124]

[0125] Among them, V gs is the gate-source voltage, V th is the threshold voltage, Z is the channel width, μ ni is the channel electron mobility, C ox is the gate oxide capacitance, L ch is the channel length. For the VDMOS device of the present embodiment, only V gs is a variable, the others are constants.

[0126] In the field of semiconductor devices, V gs =V g —V s . V g is the potential at the gate, V s is the source potential.

[0127] In the background art, the potential change at each position of the source is very small, so it is approximately considered that V s is zero.

[0128] In the VDMOS device of the embodiment of the present application, the potential of the source region changes, as follows:

[0129] The top of the first side portion 3-1 of the source region is grounded, and the potential at each position of the first side portion 3-1 of the source region becomes extremely small, so it is approximately considered that the potential Vs1 at the top of the first side portion 3-1 of the source region is zero;

[0130] The potential difference of the source region 3 is the potential Vs2 at the top of the second side of the source region and the potential Vs1 at the top of the first side 3-1 of the source region, and can also be expressed by on-current × resistance. Resistance is the resistance of the secondary PN junction. After the secondary PN junction is determined, the resistance of the secondary PN junction is fixed. The greater the on-current, the greater the potential difference of the source region 3.

[0131] V gs =V g —Vs2.

[0132] In a VDMOS device of an embodiment of the present application, Vs2 is greater than zero. Thus, in the background technology and the VDMOS device of the embodiment of the present application, Vs2 is greater than zero. g When the values ​​are the same, the VDMOS device of the embodiment of the present application under high current gs smaller, thereby making the saturation current I dsat (i.e. I 饱和电流 ) is smaller. Saturation current I dsat The smaller it is, the better the short-circuit characteristics are.

[0133] In addition, the saturation current I of the VDMOS device of the embodiment of the present application is dsat More linear and will not increase with increasing leak pressure.

[0134] Take the structure at position B as an example to describe the process flow (original process):

[0135] Original process: ion implantation of P-type well region 4:

[0136] Step 1: The first epitaxial growth forms an N-type epitaxial layer 6;

[0137] Step 2: Perform P-type well region ion implantation based on the hard mask 9 to form a P-type well region 4. Figure 8 As shown; Figure 8 Middle: 4 is the P-type well region of the channel, 6 is the N-type epitaxial layer, and 9 is the hard mask;

[0138] Step 3: Based on the hard mask of the P-type well region, a spacer tape of about 0.3um is deposited to perform ion implantation in the N-type source region, thereby forming an N-type doped source region 3 and a channel. Fig. 9 As shown, 3 is an N-type doped source region, 4 is a P-type well region of a channel, 5 is a heavily doped P-type source contact region, 6 is an epitaxial layer, 9 is a hard mask, and 10 is a photoresist.

[0139] Step 4: Perform ion implantation of heavily doped P-type contact region 5 based on hard mask 9 to form a P-type contact region. Fig.10 As shown, 3 is an N-type doped source region, 4 is a P-type well region of a channel, 5 is a heavily doped P-type source contact region, 6 is an epitaxial layer, and 9 is a hard mask;

[0140] Take the interface structure at B as an example to describe the process flow (current process):

[0141] Step 1: The first epitaxial growth forms an N-type epitaxial layer;

[0142] Step 2: Perform ion implantation into the channel P-type well region based on the hard mask 9 to form a P-well region; Fig.11 As shown, 4 is a P-type well region of a channel, 6 is an N-type epitaxial layer, and 9 is a hard mask.

[0143] Step 3: Deposit a spacer of about 0.3um based on the hard mask of the P-type well region to perform ion implantation in the N-type source region, thereby forming an N-type doped source region and channel. Fig.12 As shown, 3 is an N-type doped source region, 4 is a P-type well region of a channel, 6 is an N-type epitaxial layer, 9 is a hard mask, and 10 is a photoresist.

[0144] Step 4: Perform ion implantation into the P-type contact region and the heavily doped P-type region based on the hard mask 9 to form the P-type contact region and the heavily doped P-type region. Fig.13 As shown, 3 is an N-type doped source region, 4 is a P-type well region of a channel, 5 is a heavily doped P-type source contact region, 6 is an N-type epitaxial layer, 8 is a heavily doped P-type first doping region, and 9 is a hard mask.

[0145] Step 6: Annealing to activate the ion-implanted impurities;

[0146] Step 7: thermal oxidation to form a gate oxide layer;

[0147] Step 8: Deposition to form a polysilicon gate;

[0148] Step nine: Etching to form a source contact hole.

[0149] The following table shows the VDMOS devices and background technologies of this application. Figure 1-1 Parameter comparison table of VDMOS devices:

[0150]

[0151] From the above table, it can be seen that the VDMOS device of the present application and the background technology Figure 1-1 The VDMOS device has a gate threshold voltage of 2.84V, a breakdown voltage of 1770V, and an ambient temperature of 25°C:

[0152] The on-resistance Rdson (43.07 mΩ, 40.56 mΩ, 40.33 mΩ) of the VDMOS device of the present application, the gate-source voltage Vgs=18V, the drain current Id=16A, increases very little compared to the on-resistance Rdson (40.12 mΩ) of the VDMOS device of the background art;

[0153] The VDMOS device of the present application has a Vgs=18V Vds=800V saturation current Idsat (3.6×10 -14 A, 634A, 649A) is much smaller than the saturation current Idsat (723A) of the VDMOS device in the background technology.

[0154] From the above table, it can be seen that the VDMOS device of the present application and the background technology Figure 1-1 The VDMOS device has a gate threshold voltage of 2.38V, a breakdown voltage of 1810V, and a temperature of 175°C:

[0155] The on-resistance Rdson (82.68 mΩ, 75.77 mΩ, 76.32 mΩ) of the VDMOS device of the present application increases only slightly compared to the on-resistance Rdson (77.00 mΩ) of the VDMOS device of the background art;

[0156] The saturation current Idsat (161A, 590A, 654A) of the VDMOS device of the present application is much smaller than the saturation current Idsat (776A) of the VDMOS device of the background art.

[0157] Fig.14 This is a simulation diagram of the first specific embodiment in the comparison table of the VDMOS device of the present application under the conditions of ambient temperature T=25°C, gate-source voltage Vgs=18V, and drain current Id=16A.

[0158] Fig.15 This is a simulation diagram of the first specific embodiment in the comparison table of the VDMOS device of the present application under the conditions of ambient temperature T=400°C, gate-source voltage Vgs=18V, and drain-source voltage Vds=800V.

[0159] Fig.16 This is a simulation diagram of the first specific embodiment in the VDMOS device comparison table of the present application under the conditions of ambient temperature T=25°C, gate-source voltage Vgs=18V, and drain-source voltage Vds=800V.

[0160] Fig.17 for Fig.15 The VDMOS device shown and Figure 1-1The graph shown is a graph of the drain-source voltage Vds and the saturation current Idsat of the VDMOS device under the conditions of ambient temperature T=400°C, gate-source voltage Vgs=18V, and drain current Id=16A.

[0161] Fig.17 In the figure, curve ① is Fig.15 The drain-source voltage and saturation current curve of the VDMOS device (T = 400 ° C, gate-source voltage Vgs = 18V, drain-source voltage Vds = 800V) shown in FIG. 2 is Figure 1-1 The drain-source voltage and saturation current curve of the VDMOS device (T = 400 ° C, gate-source voltage Vgs = 18V, drain-source voltage Vds = 800V) shown in FIG. The horizontal axis is the drain-source voltage Vds, in V; the vertical axis is the saturation current Idsat, in A.

[0162] from Fig.17 It can be seen from the curve ② that the background technology Figure 1-1 As the drain-source voltage Vds of the VDMOS device shown increases, the saturation current Idsat continues to increase.

[0163] from Fig.17 It can be seen from the curve ① that this application Fig.15 As the drain-source voltage Vds increases, the saturation current Idsat of the VDMOS device shown in the figure increases a little and then remains unchanged, which corresponds to the data of the background technology and the first specific embodiment in the eighth row of the comparison table.

[0164] Fig.18 for Fig.15 The VDMOS device shown and Figure 1-1 The graph of the drain-source voltage Vds and the saturation current Idsat of the VDMOS device shown is under the conditions of ambient temperature T=25°C, gate-source voltage Vgs=18V, and drain current Id=16A.

[0165] Fig.18 In the figure, curve ① is Fig.14 The curve of drain-source voltage Vds and saturation current Idsat of the VDMOS device (T = 25 ° C, gate-source voltage Vgs = 18V, drain current Id = 16A) shown in FIG. 2 is Figure 1-1 2 is a curve of drain-source voltage Vds and saturation current Idsat of a VDMOS device (T=25°C, gate-source voltage Vgs=18V, drain current Id=16A).

[0166] from Fig.18 It can be seen from curves ① and ② that this application Fig.15The VDMOS device shown and Figure 1-1 As the drain-source voltage Vds of the VDMOS device shown in the figure increases, the saturation current Idsat increases proportionally, and this proportion is the on-resistance Rdson, and the on-resistance Rdson is a fixed value. Fig.14 The on-resistance Rdson of the VDMOS device shown is greater than Figure 1-1 The on-resistance Rdson of the VDMOS device is shown.

[0167] Fig.18 yes Fig.17 A partial enlarged view of .

[0168] Fig.19 The first specific embodiment and Figure 1-1 The graph of the drain-source voltage Vds and the saturation current Idsat of the VDMOS device shown in the figure is under the conditions of ambient temperature T=175°C, gate-source voltage Vgs=18V, and drain-source voltage Vds=800V.

[0169] Fig.19 In the figure, curve ① is the curve of drain-source voltage and saturation current of the VDMOS device (T = 175 ° C, gate-source voltage Vgs = 18V, drain-source voltage Vds = 800V) of the present application, and curve ② is Figure 1-1 The drain-source voltage and saturation current curve of the VDMOS device (T = 175 ° C, gate-source voltage Vgs = 18V, drain-source voltage Vds = 800V) shown in FIG. The horizontal axis is the drain-source voltage Vds, in V; the vertical axis is the saturation current Idsat, in A.

[0170] from Fig.19 It can be seen from the curve ② that the background technology Figure 1-1 As the drain-source voltage Vds of the VDMOS device shown increases, the saturation current Idsat continues to increase.

[0171] from Fig.19 It can be seen from the curve ① that this application Fig.16 In the VDMOS device shown, as the drain-source voltage Vds increases, the saturation current Idsat increases a little, then decreases, and then remains constant.

[0172] Fig. 20 The first specific embodiment and Figure 1-1 The VDMOS device shown is a curve diagram of the drain-source voltage Vds and the saturation current Idsat under the conditions of ambient temperature T=175°C, gate-source voltage Vgs=18V, and drain-source voltage Vds=800V.

[0173] Fig. 20 In the figure, curve ① is a curve of drain-source voltage Vds and saturation current Idsat of the VDMOS device (T = 175 ° C, gate-source voltage Vgs = 18V, drain current Id = 16A) of the present application, and curve ② is Figure 1-1 2 is a curve of drain-source voltage Vds and saturation current Idsat of a VDMOS device (T=175°C, gate-source voltage Vgs=18V, drain current Id=16A).

[0174] from Fig. 20 It can be seen from the curves ① and ② that the VDMOS device of the present application and Figure 1-1 As the drain-source voltage Vds increases, the saturation current Idsat increases proportionally, and this ratio is the on-resistance Rdson, and the on-resistance Rdson is a fixed value. Curve ① and curve ② show that the on-resistance Rdson of the VDMOS device of the present application is less than Figure 1-1 The on-resistance Rdson of the VDMOS device is shown.

[0175] Fig. 20 yes Fig.19 A partial enlarged view of .

[0176] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0177] The present application is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, and the combination of the process and / or box in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0178] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0179] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce computer-implemented processing, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0180] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0181] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A VDMOS device, characterized in that: include: A substrate, an epitaxial layer (6) located on the substrate, and a drain located on the back side of the substrate; A well region (4) of a first doping type formed downward from the upper surface of the epitaxial layer; A source region (3) of a second doping type is formed downward from the upper surface of the well region (4); A first doping region (8) of a first doping type is formed downwardly from the upper surface of the source region (3) in the source region, the first doping region (8) and the source region (3) forming a PN junction and being defined as a secondary PN junction; The parts of the source region (3) located on both sides of the first doped region (8) are a first side portion (3-1) of the source region and a second side portion (3-2) of the source region; the top of the first side portion (3-1) of the source region is used for grounding, and when the VDMOS device is turned on, the potential of the second side portion (3-2) of the source region changes to positive to realize reverse bias of the secondary PN junction.

2. The VDMOS device according to claim 1, characterized in that: The portion of the source region (3) located below the first doping region (8) is the source region bottom portion (3-3), and the first doping region (8) and the source region bottom portion (3-3) form a PN junction and are defined as a secondary third PN junction; The first doping region (8) and the first side portion (3-1) of the source region form a PN junction and are defined as a secondary first PN junction, and the first doping region (8) and the second side portion (3-2) of the source region form a PN junction and are defined as a secondary second PN junction; The secondary PN junction includes a secondary first PN junction, a secondary second PN junction, and a secondary third PN junction.

3. The VDMOS device according to claim 2, characterized in that: The VDMOS device is turned on, and when the on-current abnormally increases to be greater than or equal to a preset secondary shutdown current threshold, the secondary PN junction is reverse biased to perform secondary shutdown on the VDMOS device, and the on-current drops to a leakage current level; The VDMOS device is turned on, and when the on current is less than the secondary current turn-off threshold, the primary turn-off of the VDMOS device is controlled by the gate.

4. The VDMOS device according to claim 3, characterized in that: When the VDMOS device is turned on, when the potential change of the second side portion (3-2) of the source region is positive, the third PN junction of the secondary stage is pinched off first.

5. The VDMOS device according to claim 3, characterized in that: When the VDMOS device is turned on, the potential change of the second side of the source region (3-2) is positive: The first PN junction of the secondary stage, the second PN junction of the secondary stage, and the third PN junction of the secondary stage are cut off at the same time. Or any one of the secondary first PN junction, the secondary second PN junction, and the secondary third PN junction is pinched off first; Or any two of the secondary first PN junction, the secondary second PN junction, and the secondary third PN junction are pinched off simultaneously.

6. The VDMOS device according to claim 3, characterized in that: Secondary shutdown current threshold I 二级关断电流阈值 , meeting the following requirements: I 放大区导通电流 <I 二级关断电流阈值 <I 饱和电流 ; Among them, I 放大区导通电流 is the conduction current of the VDMOS device working in the amplification region, I 饱和电流 is the saturation current of the VDMOS device.

7. The VDMOS device according to claim 3, characterized in that: Secondary shutdown current threshold I 二级关断电流阈值 , meeting the following requirements:

8. The VDMOS device according to claim 3, characterized in that: The doping concentration of the source region (3) has a value range of greater than or equal to 10 18 cm -3 Less than or equal to 10 19 cm -3 ; The doping concentration of the first doping region (8) is one order of magnitude or half an order of magnitude higher than the doping concentration of the source region (3).

9. The VDMOS device according to claim 8, characterized in that: The width d3 of the bottom portion (3-3) of the source region is greater than the width of the depletion layer of the secondary third PN junction when no voltage is applied; The width d1 of the first side portion (3-1) of the source region is greater than the width of the depletion layer of the secondary first PN junction when no voltage is applied; The width d2 of the second side portion (3-2) of the source region is greater than the width of the depletion layer of the secondary second PN junction when no voltage is applied.

10. The VDMOS device according to any one of claims 1 to 9, characterized in that: The first doped region (8) is floating; Alternatively, the first doped region (8) is grounded.

11. The VDMOS device according to any one of claims 1 to 9, characterized in that: The substrate is a silicon carbide substrate.

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