Transistor and preparation method thereof, integrated circuit and electronic equipment

Abstract

The embodiment of the invention discloses a transistor and a preparation method thereof, an integrated circuit and electronic equipment, and relates to the technical field of semiconductors. The transistor comprises a first electrode, a first grid electrode, a first grid dielectric layer, a channel layer, a second grid dielectric layer, a second grid electrode and a second electrode. The first gate is located on the first pole. The channel layer is located on the side, away from the first gate, of the first gate dielectric layer. The second gate dielectric layer is located on the side, away from the first gate, of the channel layer. The second gate is located at one side of the second gate dielectric layer away from the first gate. The second electrode is at least partially located on the side, away from the first electrode, of the second grid electrode and makes contact with the channel layer. The transistor adjusts a threshold voltage thereof in response to a gate signal on one of the first gate and the second gate; and generate a drive current in response to a gate signal on the other of the first gate and the second gate. The threshold voltage of the transistor is continuously adjustable in a large range, and the balance requirements for high performance and low energy consumption in circuit design can be met at the same time.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a transistor and a method for manufacturing the same, an integrated circuit, and an electronic device. Background Art

[0002] With the development of semiconductor technology, the requirements for the performance and power consumption of integrated circuits are getting higher and higher. Among them, the threshold voltage of each complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) in the integrated circuit is basically a fixed value, and the CMOSFET device with a single threshold voltage (Vt) can hardly meet the balanced requirements of high performance and low energy consumption in circuit design at the same time. Therefore, how to meet the balanced requirements of high performance and low energy consumption in circuit design at the same time has become a problem that needs to be solved urgently. Summary of the invention

[0003] The embodiments of the present application provide a transistor and a method for preparing the same, an integrated circuit, and an electronic device. The threshold voltage of the transistor can be continuously adjusted within a large range, and can simultaneously meet the balance requirements for high performance and low energy consumption in circuit design.

[0004] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0005] In a first aspect, a transistor is provided, the transistor comprising: a first electrode, a first gate, a first gate dielectric layer, a channel layer, a second gate dielectric layer, a second gate, and a second electrode. The first gate is located on the first electrode. The first gate dielectric layer is located between the first electrode and the first gate, and the first gate dielectric layer also covers at least part of the side of the first gate. The channel layer is located on a side of the first gate dielectric layer away from the first gate, and is in contact with the first electrode. The second gate dielectric layer is located on a side of the channel layer away from the first gate, and is insulated from the first electrode. The second gate is located on a side of the second gate dielectric layer away from the first gate, and is insulated from the first electrode. The second electrode is at least partially located on a side of the second gate away from the first electrode, and is in contact with the channel layer.

[0006] The transistor provided in some embodiments of the present application can constitute a vertical channel transport transistor by arranging the first electrode, the channel layer, and the second electrode in sequence along the direction Z. This can not only reduce the area of ​​the transistor, but also effectively suppress the short channel effect and reduce the parasitic capacitance and dynamic power consumption of the device.

[0007] Moreover, by setting the first gate and the second gate, the embodiment of the present application can adjust the voltage of the gate signal on one of the first gate and the second gate, and control the potential and energy band of the channel layer, thereby changing the threshold voltage of the transistor. For example, by increasing the voltage of the gate signal on one of the first gate and the second gate, the transistor can have a lower threshold voltage; by reducing the voltage of the gate signal on one of the first gate and the second gate, the transistor can have a higher threshold voltage. Among them, the voltage of the gate signal on one of the first gate and the second gate is continuously adjustable, and accordingly, the threshold voltage of the transistor is continuously adjustable within a larger range. The first gate and the second gate in different transistors are set independently of each other, so that the threshold voltage of the transistor can be individually regulated, the design freedom of the threshold voltage of the transistor can be improved, and then the threshold voltage of the transistor can be regulated according to the requirements of different circuits in the integrated circuit for different threshold voltages, and the balance requirements for high performance and low energy consumption in circuit design can be met at the same time.

[0008] Furthermore, the manufacturing process of the first gate and the second gate is simple, so that the manufacturing difficulty and manufacturing cost of the transistor are relatively low.

[0009] In a possible implementation of the first aspect, the first gate dielectric layer includes a first dielectric pattern and a second dielectric pattern. The first dielectric pattern is located between the first electrode and the first gate, and the second dielectric pattern surrounds the side of the first gate. The channel layer surrounds the second dielectric pattern and the first gate. This is conducive to increasing the overlapping area between the channel layer and the first gate, and increasing the ability of the first gate to control the threshold voltage of the transistor.

[0010] In a possible implementation of the first aspect, the second gate dielectric layer surrounds the channel layer, and the second gate surrounds the second gate dielectric layer. This is equivalent to increasing the effective channel width of the channel layer, which is not only conducive to increasing the control capability of the second gate, but also conducive to increasing the on-state current of the transistor and improving the device performance of the transistor.

[0011] In a possible implementation of the first aspect, the channel layer is also located between the first electrode and the first gate dielectric layer, and is in contact with a surface of the first gate dielectric layer on one side close to the first electrode, which is conducive to simplifying the preparation process of the channel layer.

[0012] In a possible implementation of the first aspect, the second electrode is located on a side of the channel layer away from the first gate, and is in contact with a surface of the channel layer on a side away from the first gate. The second electrode has a simple structure and is easy to prepare.

[0013] In a possible implementation of the first aspect, the second electrode surrounds the channel layer, which is beneficial to increase the contact area between the second electrode and the channel layer and reduce the contact resistance between the second electrode and the channel layer.

[0014] In a possible implementation of the first aspect, the second pole includes: a first electrode pattern and a second electrode pattern. The first electrode pattern is located on a side of the first gate dielectric layer away from the first gate electrode, and is located on a side of the channel layer away from the first pole. The first electrode pattern is in contact with a surface of a side of the channel layer away from the first pole. The second electrode pattern is located on a side of the second gate electrode away from the first pole, and is located on a side of the first electrode pattern away from the first gate electrode. The second electrode pattern is in contact with a surface of a side of the first electrode pattern away from the first gate electrode. In this way, the distance between the surface of the side of the channel layer away from the first pole and the surface of the side of the second gate electrode away from the first pole can be reduced, thereby reducing the distance between the first pole and the second pole. When the transistor is turned on, the flow path of the driving current can be shortened, the on-resistance of the transistor can be effectively reduced, and the device performance of the transistor can be improved.

[0015] In a possible implementation of the first aspect, the first electrode pattern surrounds the first gate dielectric layer and the first gate electrode. The second electrode pattern surrounds the first electrode pattern. This is conducive to increasing the contact area between the second electrode and the channel layer and reducing the contact resistance between the second electrode and the channel layer.

[0016] In a possible implementation of the first aspect, the second electrode includes: a third electrode pattern and a fourth electrode pattern. The third electrode pattern is located on a side of the first gate dielectric layer away from the first gate electrode, and is located on a side of the channel layer away from the first electrode. The third electrode pattern is in contact with a surface of a side of the channel layer away from the first electrode. The fourth electrode pattern covers the third electrode pattern. This is conducive to increasing the positive projection area of ​​the second electrode on the reference plane, and then when the second electrode is subsequently led out, it is conducive to increasing the contact area between the second electrode and the lead-out contact, thereby avoiding increasing the contact resistance.

[0017] In a possible implementation of the first aspect, the third electrode pattern surrounds the first gate dielectric layer and the first gate electrode. A portion of the fourth electrode pattern surrounds the third electrode pattern, and another portion of the fourth electrode pattern surrounds the first gate dielectric layer and the first gate electrode. This is conducive to increasing the contact area between the second electrode and the channel layer and reducing the contact resistance between the second electrode and the channel layer.

[0018] In a second aspect, a method for preparing a transistor is provided, the method comprising: forming a stacked structure, the stacked structure comprising a first electrode and a semiconductor layer stacked in sequence. Forming a second gate dielectric layer and a second gate electrode on the side of the semiconductor layer; the second gate electrode is located on a side of the second gate dielectric layer away from the semiconductor layer, and either the second gate electrode or the second gate dielectric layer is insulated from the first electrode. Forming a groove penetrating at least part of the semiconductor layer to obtain a channel layer; the groove extends along the arrangement direction of the first electrode and the semiconductor layer. Forming a first gate dielectric layer and a first gate electrode in the groove; the first gate dielectric layer is located between the channel layer and the first gate electrode.

[0019] In the embodiment of the present application, a first gate is prepared in the channel layer, and the threshold voltage of the transistor can be regulated within a relatively large range by adjusting the voltage of the first gate signal on the first gate, and within the relatively large range, the threshold voltage is continuously adjustable. The first gates of different transistors prepared in the embodiment of the present application are independently arranged, so that the threshold voltages of different transistors can be individually regulated, which can simultaneously meet the balance requirements for high performance and low energy consumption in circuit design.

[0020] Moreover, in the above-mentioned preparation method, the process of preparing and forming the first gate dielectric layer and the first gate is simple. On the one hand, there is no need to use an ion implantation process, which can reduce the difficulty of preparing the transistor and the integrated circuit to which it is applied; on the other hand, there is no need to define the areas corresponding to different modules, which can reduce the use of masks and reduce the preparation cost; on the other hand, there is no need to prepare a dipole oxide layer, which reduces the control of the thickness of the second gate in different transistors, reduces the requirements of the corresponding preparation process, and thus reduces the difficulty of preparing the transistor and the integrated circuit to which it is applied.

[0021] In a possible implementation manner of the second aspect, the preparation method further includes: forming a second electrode on a side of the channel layer away from the first gate; and the second electrode is in contact with a surface of a side of the channel layer away from the first gate.

[0022] In a possible implementation of the second aspect, the stacked structure further includes an electrode layer located on the semiconductor layer. Forming a groove that penetrates at least part of the semiconductor layer includes: forming a groove that penetrates the electrode layer and penetrates at least part of the semiconductor layer to obtain a first electrode pattern and a channel layer. After forming a first gate dielectric layer and a first gate electrode in the groove, the preparation method further includes: forming a second electrode pattern on a side of the first electrode pattern away from the first gate electrode; the second electrode pattern is also located on a side of the second gate electrode away from the first electrode; the second electrode pattern is in contact with the first electrode pattern to form a second electrode.

[0023] In a possible implementation of the second aspect, forming a first gate dielectric layer and a first gate electrode in the trench includes: forming a first gate dielectric layer and a sacrificial gate in sequence in the trench; the first gate dielectric layer and the sacrificial gate both protrude from the channel layer. Forming a third electrode pattern on a side of the first gate dielectric layer away from the sacrificial gate. The third electrode pattern is also located on a side of the channel layer away from the first pole, and contacts a surface of a side of the channel layer away from the first pole. Forming a fourth electrode pattern covering the third electrode pattern; the fourth electrode pattern and the third electrode pattern constitute a second pole.

[0024] In a possible implementation manner of the second aspect, a first gate dielectric layer and a first gate are formed in the trench, and further comprising: replacing the sacrificial gate with the first gate.

[0025] In a possible implementation of the second aspect, forming a second gate dielectric layer and a second gate electrode on the side of the semiconductor layer includes: sequentially forming a second gate dielectric film and a second gate film on the side of the semiconductor layer and on the side of the semiconductor layer away from the first electrode. Etching the second gate dielectric film and the second gate film to remove portions of the second gate dielectric film and the second gate film located on the side of the semiconductor layer away from the first electrode, and retaining portions of the second gate dielectric film and the second gate film covering the side of the semiconductor layer, to form a second gate dielectric layer and a second gate electrode.

[0026] In a third aspect, an integrated circuit is provided, the integrated circuit comprising a packaging structure and one or more transistors packaged inside the packaging structure. The transistor comprises the transistor as described in any one of the embodiments of the first aspect.

[0027] In a fourth aspect, an electronic device is provided, the electronic device comprising: a circuit board and an integrated circuit electrically connected to the circuit board. The integrated circuit comprises the integrated circuit as described in any embodiment of the third aspect.

[0028] The technical effects brought about by the second and fourth aspects can refer to the technical effects brought about by the different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application;

[0030] Figure 2 A partial structural diagram of an electronic device provided in an embodiment of the present application;

[0031] Figure 3 A structural diagram of an integrated circuit provided in an embodiment of the present application;

[0032] Figure 4 A structural diagram of a transistor provided in an embodiment of the present application;

[0033] Figure 5 A structural diagram of another transistor provided in an embodiment of the present application;

[0034] Figure 6 A structural diagram of another transistor provided in an embodiment of the present application;

[0035] Figure 7a for Figure 6 A cross-sectional structural diagram of the transistor shown along the AA direction;

[0036] Figure 7b for Figure 6 Another cross-sectional structural diagram of the transistor shown along the AA direction;

[0037] Figure 7c for Figure 6 Another cross-sectional structural diagram of the transistor shown along the AA direction;

[0038] Figure 8 for Figure 6 A cross-sectional structural diagram of the transistor shown along the BB direction;

[0039] Fig. 9 A structural diagram of another transistor provided in an embodiment of the present application;

[0040] Fig.10 for Fig. 9 A cross-sectional structural diagram of the transistor shown along the CC direction;

[0041] Fig.11 A structural diagram of another transistor provided in an embodiment of the present application;

[0042] Fig.12 A characteristic curve diagram of a transistor provided in an embodiment of the present application;

[0043] Fig.13 A characteristic curve diagram of another transistor provided in an embodiment of the present application;

[0044] Fig.14 A flowchart of a method for preparing a transistor provided in an embodiment of the present application;

[0045] Figure 15a to Figure 15i A structural diagram corresponding to each step in a method for preparing a transistor provided in an embodiment of the present application;

[0046] Figure 16a to Figure 16b A structural diagram corresponding to each step in another method for preparing a transistor provided in an embodiment of the present application;

[0047] Figure 17a to Figure 17i A structural diagram corresponding to each step in another method for preparing a transistor provided in an embodiment of the present application;

[0048] Figure 18a to Figure 18f A structural diagram corresponding to each step in another method for preparing a transistor provided in an embodiment of the present application;

[0049] Fig.19 A structural diagram of a transistor and an interconnection layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0051] In the description of the embodiments of the present application, unless otherwise specified, "multiple" refers to two or more than two. "At least one item" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one item of a, b, and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0052] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0053] When describing some embodiments, the expression "connected" and its derivatives are used. The term "connected" should be understood in a broad sense. For example, "connected" can be fixedly connected, detachably connected, or integrated; it can be directly connected or indirectly connected through an intermediate medium. In addition, the use of "based on" means openness and inclusiveness, because the process, step, calculation or other action "based on" one or more of the conditions or values ​​can be based on additional conditions or values ​​beyond the described values ​​in practice.

[0054] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0055] In the embodiments of the present application, "up", "down", "left" and "right" are not limited to being defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms can be relative concepts, which are used for description and clarification relative to the components, and can change accordingly according to the change in the orientation of the components in the drawings. In the drawings, for the sake of clarity, the thickness of the layers and regions is exaggerated, and the dimensional ratio relationship between the parts in the drawings does not reflect the actual dimensional ratio relationship. Therefore, changes in the shape relative to the drawings due to, for example, manufacturing technology and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be interpreted as being limited to the shape of the areas shown in the present application, but include shape deviations caused by, for example, manufacturing. For example, an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the areas of the device, and are not intended to limit the scope of the exemplary embodiments.

[0056] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0057] The embodiment of the present application provides an electronic device. The electronic device may be a mobile phone, a tablet computer (pad), a television, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device (e.g., a smart watch, a smart bracelet), an in-vehicle device, a smart home device and / or a smart city device, etc. The embodiment of the present application does not impose any special restrictions on the specific type of the electronic device.

[0058] Figure 1 The following is a schematic diagram of the architecture of an electronic device provided in an embodiment of the present application. Figure 1 As shown, the electronic device 1000 includes: a memory 100, a processor 200, an input device 300, an output device 400 and other components. Those skilled in the art can understand that Figure 1 The structure of the electronic device shown in the figure does not constitute a limitation on the electronic device 1000. The electronic device 1000 may include, for example Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0059] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device (such as audio data, image data, phone book, etc.), etc. In addition, the memory 100 includes an external memory 110 and an internal memory 120. The data stored in the external memory 110 and the internal memory 120 can be transmitted to each other. The external memory 110 includes, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 120 includes, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a read-only memory, etc.

[0060] The processor 200 is the control center of the electronic device 1000. It uses various interfaces and lines to connect various parts of the entire electronic device 1000. By running or executing software programs and / or modules stored in the memory 100, and calling data stored in the memory 100, it performs various functions of the electronic device 1000 and processes data, thereby monitoring the electronic device 1000 as a whole. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, and may also be other specific integrated circuits (application specific integrated circuits, ASICs), etc. Figure 1 In the example, the processor 200 is a CPU, and the CPU may include an operator 210 and a controller 220. The operator 210 obtains data stored in the internal memory 120, processes the data stored in the internal memory 120, and generally sends the processed result back to the internal memory 120. The controller 220 may control the operator 210 to process the data, and the controller 220 may also control the external memory 110 and the internal memory 120 to store data or read data. The memory 100 may store data generated by the processor 200.

[0061] The input device 300 is used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device 1000. Exemplarily, the input device 300 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect the user's touch operation on or near the touch screen (such as the user's operation on or near the touch screen using any suitable object or accessory such as a finger, a stylus, etc.), and drive the corresponding connection device according to a pre-set program. Optionally, the touch screen may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch direction, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into the touch point coordinates, and then sends it to the processor 200, and can receive and execute the command sent by the processor 200. In addition, the touch screen can be implemented using multiple types such as resistive, capacitive, infrared and surface acoustic waves. Other input devices may include but are not limited to one or more of a physical keyboard, function keys (such as a volume control key, a power switch key, etc.), a trackball, a mouse, a joystick, etc. The controller 220 in the processor 200 can also control the input device 300 to receive input signals or not receive input signals. In addition, the input digital or character information received by the input device 300, and the key signal input related to the user settings and function control of the electronic device can be stored in the internal memory 120.

[0062] The output device 400 is used to output a signal corresponding to the data input by the input device 300 and stored in the internal memory 120. For example, the output device 400 outputs a sound signal or a video signal. The controller 220 in the processor 200 can also control the output device 400 to output a signal or not output a signal.

[0063] It should be noted that Figure 1 The thick arrows in the figure are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, the one-way arrow between the input device 300 and the internal memory 120 indicates that the data received by the input device 300 is transmitted to the internal memory 120. For another example, the two-way arrow between the operator 210 and the internal memory 120 indicates that the data stored in the internal memory 120 can be transmitted to the operator 210, and the data processed by the operator 210 can be transmitted to the internal memory 120. Figure 1 The thin arrows in the figure represent components that can be controlled by the controller 220. For example, the controller 220 can control the external memory 110, the internal memory 120, the operator 210, the input device 300, the output device 400, and the like.

[0064] Alternatively, if Figure 1The electronic device 1000 shown may also include various sensors, such as a gyroscope sensor, a hygrometer sensor, an infrared sensor, a magnetometer sensor, etc., which are not described in detail here. Optionally, the electronic device 1000 may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which are not described in detail here.

[0065] Figure 2 FIG. 1 schematically shows a partial structure of the electronic device 1000. Figure 2 As shown, the electronic device 1000 may further include a circuit board 500 and an integrated circuit 600 . The integrated circuit 600 is disposed on the circuit board 500 and is electrically connected to the circuit board 500 .

[0066] like Figure 2 As shown, the electronic device 1000 further includes a connector disposed between the circuit board 500 and the integrated circuit 600, and the integrated circuit 600 is electrically connected to the circuit board 500 via the connector. The connector may be, for example, a ball grid array (BGA).

[0067] Optionally, other structures, such as a packaging substrate, may be provided between the connector and the circuit board 500. That is, the integrated circuit 600 may be packaged on the packaging substrate and then connected to the circuit board 500 via the packaging substrate.

[0068] The number of the integrated circuit 600 may be one or more. When the number of the integrated circuit 600 is more than one, the integrated circuits 600 may be arranged in a flat pattern or in a stacked pattern.

[0069] The integrated circuit 600 can be a wafer or a chip. When the integrated circuit 600 is a chip, the chip can be a bare chip (also referred to as a grain or particle) obtained by cutting the wafer, or a packaged chip obtained by packaging the bare chip. The integrated circuit 600 can be applied to logic devices (such as the above-mentioned operator 210, controller 220, sensor, etc.), and can also be applied to storage devices (such as the above-mentioned external memory 110, internal memory 120, etc.), which is not limited in the embodiments of the present application.

[0070] Figure 3 The structure of an integrated circuit 600 is shown. The integrated circuit 600 may include a transistor 610 and a packaging structure 620. The transistor 610 is packaged inside the packaging structure 620. The number of the transistor 610 may be one or more. Figure 3 The diagram shows a transistor 610. The transistor 610 is, for example, a CMOSFET, and the transistor 610 can be an NMOS transistor (NFET) or a PMOS transistor (PFET).

[0071] It is understandable that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the integrated circuit 600. In other embodiments of the present application, the integrated circuit 600 may include more or fewer components than shown, or combine some components, or separate some components, or arrange the components differently.

[0072] In some examples, such as Figure 3 As shown, the packaging structure 620 may include a substrate 621 and a packaging shell 622 , and the packaging shell 622 is bonded to the substrate 621 by an insulating adhesive.

[0073] Exemplarily, the substrate 621 has high heat dissipation and electrical conductivity. The material of the substrate 621 may include a composite material, and the structure of the substrate 621 may be a laminated structure. Optionally, the material of the substrate 621 may include copper and molybdenum, and the substrate 621 is composed of a copper layer / molybdenum layer / copper layer stacked in sequence.

[0074] Exemplarily, the transistor 610 may be bonded to a substrate 621 and packaged in a space formed by a package shell 622 and the substrate 621. Some electrodes (e.g., source) of the transistor 610 may be conductive with the substrate 621, and some electrodes (e.g., drain and gate) of the transistor 610 may be connected to a pin by conductive wire bonding, and the pin is disposed on an insulating layer (e.g., insulating ceramic), and the insulating layer is bonded to the substrate 621 by an insulating adhesive. In addition, one end of the pin is exposed from the package structure 620 to connect to other circuits.

[0075] in, Figure 3 The transistor 610 shown in the figure is a transistor with a two-dimensional (2D) planar structure. As Moore's Law continues to advance, the feature size of the transistor 610 in the integrated circuit 600 continues to shrink to improve PPAC (performance, power, area cost) and meet the increasing performance, power consumption, etc. requirements of the integrated circuit 600. However, as the feature size of the transistor 610 gradually approaches the physical limit, the shrinking of the feature size encounters a bottleneck. Therefore, the transistor 610 is reduced from Figure 3 The two-dimensional (2D) planar structure shown in FIG has gradually evolved into a three-dimensional (3D) fin field-effect transistor (FinFET) structure, and further evolved into a gate-all-around (GAA) structure. Compared with the fin field-effect transistor, the transistor with a gate-all-around structure has better current driving capability and gate control performance, thus having greater advantages in terms of feature size miniaturization, layout area, and power consumption.

[0076] It is understandable that, according to the requirements of different circuits in the integrated circuit 600 for performance and power consumption, the integrated circuit 600 may include a high-performance module and a low static power consumption module. The high-performance module has a relatively high requirement for current, and accordingly, the transistor included in the high-performance module has a relatively low threshold voltage to provide a relatively large on-state current. The low static power consumption module has a relatively high requirement for leakage current and static power consumption, and accordingly, the transistor included in the low static power consumption module has a relatively high threshold voltage to ensure that it has a relatively low leakage current in the off state, meeting the requirement for low static power consumption.

[0077] However, for transistors that have already been fabricated, their threshold voltage is basically fixed regardless of how the transistor architecture changes. As power consumption and performance requirements increase, transistor devices with a single threshold voltage can no longer meet the balance requirements of high performance and low energy consumption in circuit design.

[0078] Therefore, the embodiments of the present application provide multiple possible implementations to simultaneously meet the balance requirements of high performance and low energy consumption in circuit design. In different implementations, the architecture of the transistor 610 included in the integrated circuit 600 is different.

[0079] In a first possible implementation, the transistor 610 included in the integrated circuit 600 is a two-dimensional planar structure device. At this time, an ion implantation process can be used to adjust the doping concentration of the channel of the transistor 610, or to adjust the doping concentration of the source and drain regions of the transistor 610 to adjust the threshold voltages of different transistors 610, so that the transistor 610 in the high-performance module has a lower threshold voltage, and the transistor included in the low static power consumption module has a higher threshold voltage.

[0080] However, this will increase the manufacturing cost of the integrated circuit 600. Moreover, in the process of adjusting the doping concentration by the ion implantation process, a relatively precise control level needs to be achieved, which increases the difficulty of manufacturing the integrated circuit 600.

[0081] In a second possible implementation, the transistor 610 included in the integrated circuit 600 is a fin field effect transistor. In this case, the work function of the gate metal material of the transistor 610 can be adjusted, and a dipole (for example, lanthanum (La) is doped in a high-k (HK) dielectric layer) can be used to adjust the threshold voltage of different transistors 610, so that the transistor 610 in the high-performance module has a lower threshold voltage, and the transistor included in the low static power consumption module has a higher threshold voltage.

[0082] However, in the process of preparing the integrated circuit 600 including the fin field effect transistor, it is necessary to use multiple masks for multiple exposure operations to define the areas corresponding to different modules, which not only increases the preparation cost of the integrated circuit 600, but also increases the preparation complexity of the integrated circuit 600. In addition, it is necessary to achieve more precise control over the thickness of the gates of different fin field effect transistors (such as the titanium nitride film in the PMOS transistor), the diffusion between different metal materials (such as the titanium aluminum alloy and titanium nitride in the NMOS transistor to form aluminum titanium nitride), and the thickness and diffusion of the dipole oxide layer (such as the lanthanum oxide film in the NMOS transistor, or the aluminum oxide film in the PMOS transistor, etc.). This undoubtedly increases the requirements for the corresponding process and increases the difficulty of preparing the integrated circuit 600.

[0083] In a third possible implementation, the transistor 610 included in the integrated circuit 600 is a fully depleted silicon-on-insulator (FD-SOI) transistor. In this case, a back gate may be provided in the transistor 610 to adjust the threshold voltage of the transistor 610 using the back gate.

[0084] However, each transistor 610 included in the integrated circuit 600 shares the same back gate. Thus, in the process of regulating the threshold voltage of the transistor 610 through the back gate, the threshold voltage of each transistor 610 will be regulated at the same time (it can also be considered that only the global threshold voltage can be regulated), and it is difficult to separately regulate the threshold voltages of different transistors 610. In this way, the demand for a balance between high performance and low energy consumption of the same integrated circuit 600 cannot be met.

[0085] Based on this, an embodiment of the present application also provides a transistor. Figure 4 , Figure 5 , Figure 6 and Fig. 9 A cross-sectional structure of a transistor is schematically shown respectively. Figure 7a , Figure 7b and Figure 7c They respectively indicated Figure 6 The transistor shown is a cross-sectional structure along the AA direction. Figure 8 Indicated Figure 6 The transistor shown is a cross-sectional structure along the BB direction. Fig.10 Indicated Fig. 9 The transistor shown is a cross-sectional structure along the CC direction.

[0086] like Figure 4 , Figure 5 , Figure 6 and Fig. 9As shown, the transistor 610 includes: a first electrode 1, a first gate 2, a first gate dielectric layer 3, a channel layer 4, a second gate dielectric layer 5, a second gate 6, and a second electrode 7. Among them, one of the first electrode 1 and the second electrode 7 is a drain, and the other is a source, which can be determined according to the type of the transistor 610.

[0087] The first gate 2 is located on the first electrode 1, and the first gate 2 is insulated from the first electrode 1, and the first gate 2 and the first electrode 1 are not in direct contact. The first gate 2 is, for example, a strip-shaped structure, and extends along the direction Z. The orthographic projection of the first gate 2 on the reference plane is located within the orthographic projection range of the first electrode 1 on the reference plane. The direction Z is the arrangement direction of the first electrode 1 and the first gate 2. For example, Figure 4 , Figure 5 , Figure 6 and Fig. 9 The direction X and the direction Y are also indicated, wherein any two of the directions X, Y and Z are perpendicular to each other; and the direction X and the direction Y are both parallel to the reference plane.

[0088] The first gate dielectric layer 3 is located between the first electrode 1 and the first gate 2 to separate the first electrode 1 from the first gate 2 and realize electrical insulation between the first electrode 1 and the first gate 2. The first gate dielectric layer 3 also covers at least part of the side surface of the first gate 2 and is in direct contact with at least part of the side surface of the first gate 2. For example, the cross-sectional view of the first gate dielectric layer 3 is U-shaped, and the first gate dielectric layer 3 covers two side surfaces of the first gate 2 that are arranged at intervals along the direction X. Further, as Figure 7a and Figure 7b As shown, the first gate dielectric layer 3 also covers two side surfaces of the first gate 2 that are arranged in a spaced relationship along the Y direction.

[0089] The channel layer 4 is located on the side of the first gate dielectric layer 3 away from the first gate electrode 2. The first gate dielectric layer 3 separates the channel layer 4 from the first gate electrode 2 to achieve electrical insulation between the channel layer 4 and the first gate electrode 2. The channel layer 4 may cover at least a portion of the first gate dielectric layer 3. The channel layer 4 is located above the first electrode 1, and the channel layer 4 and the first electrode 1 are in contact to achieve electrical connection between the channel layer 4 and the first electrode 1. Optionally, the channel layer 4 and the first electrode 1 may be in direct contact or in indirect contact through other media.

[0090] The second gate dielectric layer 5 is located on a side of the channel layer 4 away from the first gate 2. The second gate dielectric layer 5, for example, covers a portion of the side surface of the channel layer 4. The orthographic projection of the second gate dielectric layer 5 on the reference plane does not overlap with the orthographic projection of the channel layer 4 on the reference plane. In the direction Z, the second gate dielectric layer 5 is insulated from the first electrode 1, that is, the second gate dielectric layer 5 is not in direct contact with the first electrode 1.

[0091] The second gate 6 is located on the side of the second gate dielectric layer 5 away from the first gate 2, and the second gate dielectric layer 5 separates the second gate 6 and the channel layer 4 to achieve electrical insulation between the second gate 6 and the channel layer 4. In the direction Z, the second gate 6 is insulated from the first electrode 1, that is, the second gate 6 is not in direct contact with the first electrode 1. There are many positional relationships between the second gate 6 and the second gate dielectric layer 5, which can be selected according to actual needs. For example, the second gate dielectric layer 5 is only located between the second gate 6 and the channel layer 4, and the orthographic projection of the second gate 6 on the reference plane does not overlap with the orthographic projection of the second gate dielectric layer 5 on the reference plane. For another example, Figure 5 As shown, a portion of the second gate dielectric layer 5 is located between the second gate 6 and the channel layer 4, and another portion is located between the second gate 6 and the first electrode 1. The orthographic projection of the second gate 6 on the reference plane is located within the orthographic projection range of the second gate dielectric layer 5 on the reference plane.

[0092] Optionally, the transistor 610 further includes a first isolation layer 8, and the orthographic projection of the first isolation layer 8 on the reference plane, for example, surrounds the orthographic projection of the channel layer 4 on the reference plane. The first isolation layer 8 is located between the second gate 6 and the first pole 1, and is in direct contact with the channel layer 4. The first isolation layer 8 separates the second gate 6 and the first pole 1 to achieve electrical insulation between the second gate 6 and the first pole 1. In the case where the second gate dielectric layer 5 is also located between the second gate 6 and the first pole 1, the first isolation layer 8 is located between the second gate dielectric layer 5 and the first pole 1. By providing the first isolation layer 8, it is beneficial to improve the insulation effect between the second gate 6 and the first pole 1, thereby improving the performance of the transistor 610.

[0093] At least part of the second pole 7 is located on the side of the second gate 6 away from the first pole 1, that is, part of the second pole 7 is located on the side of the second gate 6 away from the first pole 1, or the second pole 7 is located on the side of the second gate 6 away from the first pole 1. The part of the second pole 7 located on the side of the second gate 6 away from the first pole 1 is insulated from the second gate 6. This means that along the direction Z, the first pole 1, the second gate 6, and at least part of the second pole 7 are arranged in sequence. Among them, the second pole 7 is in contact with the channel layer 4 to achieve electrical connection between the second pole 7 and the channel layer 4. Optionally, the second pole 7 and the channel layer 4 can be in direct contact or indirectly contacted through other media.

[0094] Optionally, the transistor 610 further includes a second isolation layer 9, and the orthographic projection of the second isolation layer 9 on the reference plane, for example, surrounds the orthographic projection of the channel layer 4 on the reference plane. The second isolation layer 9 is located between the second gate 6 and the second pole 7, and is in direct contact with the channel layer 4. The second isolation layer 9 separates the second gate 6 and the second pole 7 to achieve electrical insulation between the second gate 6 and the second pole 7. By providing the second isolation layer 9, it is beneficial to improve the insulation effect between the second gate 6 and the second pole 7, and improve the performance of the transistor 610.

[0095] Exemplarily, the material of the first pole 1 includes a doped semiconductor material, such as an N-type doped or P-type doped semiconductor material. The material of the second pole 7 includes a doped semiconductor material, such as an N-type doped or P-type doped semiconductor material. Of course, the materials of the first pole 1 and the second pole 7 are not limited thereto.

[0096] Exemplarily, the materials of the first gate 2 and the second gate 6 are both conductive materials, such as metal materials. Optionally, the material of either the first gate 2 or the second gate 6 may be titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc., or any combination thereof. The materials of the first gate 2 and the second gate 6 may be the same or different.

[0097] Exemplarily, the materials of the above-mentioned first gate dielectric layer 3, the second gate dielectric layer 5, the first isolation layer 8 and the second isolation layer 9 are all insulating materials. Optionally, the material of any one of the first gate dielectric layer 3, the second gate dielectric layer 5, the first isolation layer 8 and the second isolation layer 9 may be silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium dioxide, yttrium trioxide, silicon nitride, etc., or any combination thereof. In addition, any one of the first gate dielectric layer 3, the second gate dielectric layer 5, the first isolation layer 8 and the second isolation layer 9 may be a single-layer structure or a multi-layer stacked structure. The material of the single-layer structure and the material of each layer in the multi-layer stacked structure may be silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium dioxide, yttrium trioxide, silicon nitride, etc., or any combination thereof. The materials of the first gate dielectric layer 3, the second gate dielectric layer 5, the first isolation layer 8 and the second isolation layer 9 may be the same or different.

[0098] Exemplarily, the material of the channel layer 4 includes but is not limited to silicon-based semiconductor materials such as silicon, silicon germanium, polysilicon, amorphous silicon, or oxide semiconductor materials such as indium gallium zinc oxide, or Group III-V compound semiconductor materials.

[0099] The transistor 610 adjusts its threshold voltage in response to a gate signal on one of the first gate 2 and the second gate 6 , and generates a driving current in response to a gate signal on the other of the first gate 2 and the second gate 6 .

[0100] For example, the first gate 2 may receive a first gate signal, and the second gate 6 may receive a second gate signal. The transistor 610 may adjust its threshold voltage in response to the first gate signal on the first gate 2, and generate a driving current in response to the second gate signal on the second gate 6. Alternatively, the transistor 610 may adjust its threshold voltage in response to the second gate signal on the second gate 6, and generate a driving current in response to the first gate signal on the first gate 2.

[0101] The embodiment of the present application takes the transistor 610 adjusting its threshold voltage in response to the first gate signal on the first gate 2 and generating a driving current in response to the second gate signal on the second gate 6 as an example for schematic illustration. At this time, the first gate 2 can also be called a regulating gate, and the second gate 6 can also be called a driving gate. The same applies when the transistor 610 adjusts its threshold voltage in response to the second gate signal on the second gate 6 and generates a driving current in response to the first gate signal on the first gate 2.

[0102] Further, among the film layers included in the transistor 610, the first gate 2, the first gate dielectric layer 3 and the channel layer 4 may form a first MOS structure. For example, during the operation of the transistor 610, the first gate 2 may receive a first gate signal, which may control the potential and energy band of the channel layer 4 to regulate the threshold voltage of the transistor 610.

[0103] In addition, the second gate 6, the second gate dielectric layer 5 and the channel layer 4 can form a second MOS structure. For example, during the operation of the transistor 610, the second gate 6 can receive a second gate signal. The transistor 610 can be turned on under the control of the second gate signal, and a driving current (also referred to as an on-state current) is formed between the first electrode 1 and the second electrode 7; or, the transistor 610 can be turned off under the control of the first gate signal, and the driving current between the first electrode 1 and the second electrode 7 is cut off. Among them, the magnitude of the on-state current and the magnitude of the leakage current are related to the threshold voltage of the transistor 610.

[0104] Exemplarily, the threshold voltage of the transistor 610 is negatively correlated with the voltage value of the first gate signal on the first gate 2. That is, as the voltage value of the first gate signal on the first gate 2 gradually increases, the threshold voltage of the transistor 610 gradually decreases; as the voltage value of the first gate signal on the first gate 2 gradually decreases, the threshold voltage of the transistor 610 gradually increases. When the voltage value of the first gate signal on the first gate 2 is a fixed value, the threshold voltage of the transistor 610 remains substantially unchanged.

[0105] The embodiment of the present application adopts different first gate signals. Fig.11The transistor 610 shown in FIG. 1 is subjected to TCAD (technology computer aided design, computer-aided design) simulation verification, and the simulation results are shown in FIG. Fig.12 and Fig.13 As shown. Fig.12 In FIG. 6 , the horizontal axis represents the voltage value Vg of the second gate signal on the second gate 6 of the transistor 610, and the vertical axis represents the logarithm Log(Id) of the driving current generated by the transistor 610. Fig.13 In FIG. 6 , the horizontal axis represents the voltage value Vg of the second gate signal on the second gate 6 of the transistor 610, and the vertical axis represents the driving current Id generated by the transistor 610. Fig.12 and Fig.13 , the voltage of the first gate signal corresponding to the characteristic curve ① is 0V, the voltage of the first gate signal corresponding to the characteristic curve ② is 0.3V, and the voltage of the first gate signal corresponding to the characteristic curve ③ is 0.6V.

[0106] from Fig.12 and Fig.13 It can be seen that different characteristic curves will move with the change of the voltage of the first gate signal. And, as the voltage of the first gate signal increases, the characteristic curve moves to the left. This means that the larger the voltage value of the first gate signal, the smaller the voltage required for the transistor 610 to turn on (that is, the voltage of the second gate signal), the smaller the threshold voltage of the transistor 610, and accordingly, the larger the on-state current of the transistor 610 (such as Fig.13 As shown in FIG. 1 ). The smaller the voltage value of the first gate signal is, the larger the voltage required for turning on the transistor 610 (i.e., the voltage of the second gate signal) is, the larger the threshold voltage of the transistor 610 is, and accordingly, the smaller the leakage current of the transistor 610 is (as shown in FIG. 1 ). Fig.12 ). When the voltage value of the first gate signal is 0V, the voltage required for turning on the transistor 610 is substantially unchanged, and the threshold voltage of the transistor 610 is also substantially unchanged. When the voltage value of the first gate signal is 0.3V, the voltage required for turning on the transistor 610 is substantially unchanged, and the threshold voltage of the transistor 610 is also substantially unchanged. When the voltage value of the first gate signal is 0.6V, the voltage required for turning on the transistor 610 is substantially unchanged, and the threshold voltage of the transistor 610 is also substantially unchanged.

[0107] That is to say, the embodiment of the present application sets the first gate 2, and the threshold voltage of the transistor 610 can be regulated within a larger range by adjusting the voltage of the first gate signal on the first gate 2, and within the larger range, the threshold voltage is continuously adjustable. In this way, the same transistor 610 can have a scheme of multiple threshold voltages (multiple Vt scheme). Moreover, the first gates 2 in different transistors 610 are set independently of each other, so that the threshold voltage of the transistor 610 can be regulated separately, and the design freedom of the threshold voltage of the transistor 610 is improved, and then the threshold voltage of the transistor 610 can be regulated according to the requirements of different circuits in the integrated circuit 600 for different threshold voltages (for example, the same transistor 610 is only applied to high-performance modules, or the same transistor 610 is only applied to low static power consumption modules, or the same transistor 610 is simultaneously applied to high-performance modules and low static power consumption modules), which can also meet the balance requirements for high performance and low energy consumption in circuit design.

[0108] It is understandable that the embodiment of the present application can adopt a deposition process, an etching process, etc. to prepare and form the first gate 2. That is to say, in the process of preparing and forming the first gate 2, the ion implantation process can be avoided, which is conducive to reducing the preparation cost and preparation difficulty of the transistor 610 and the integrated circuit 600. Moreover, the structures of different transistors 610 in the integrated circuit 600 can be the same. In this way, in the process of preparing and forming different transistors 610, not only is it unnecessary to define the areas corresponding to different circuit modules, but the use of masks can be reduced, the preparation cost and preparation complexity of the transistor 610 can be reduced, and the control degree of the thickness of the gate 2 can be reduced, and the preparation difficulty of the transistor 610 can be further reduced.

[0109] Continue reading Figure 4 , Figure 5 , Figure 6 and Fig. 9In each figure, the first pole 1 and the second pole 7 are arranged at intervals along the direction Z, and the two are located in different layers. Moreover, along the direction Z, the channel layer 4 is located between the first pole 1 and the second pole 7. In this way, when the transistor 610 is turned on, the current between the first pole 1 and the second pole 7 flows along the direction Z, and accordingly, the channel layer 4 can be called a vertical channel. The transistor 610 in the embodiment of the present application is a vertical channel transport transistor (vertical transport field-effect transistor, VTFET). Compared with the transistor of the planar channel, the transistor 610 provided in the embodiment of the present application has a smaller positive projection area on the reference plane, which can reduce the area occupied by the transistor 610 on the reference plane and improve the area utilization. Moreover, in the transistor of the planar channel, the miniaturization of the gate length (that is, the size of the gate in the direction X or direction Y) and the thickness of the isolation layer (that is, the thickness of the first isolation layer or the second isolation layer in the direction Z) will be limited. The embodiment of the present application adopts a vertical channel, which not only removes the restrictions of the length of the first gate 2 or the second gate 6 (i.e., the size in the direction Z) and the thickness of the first isolation layer 8 or the second isolation layer 9 (i.e., the size in the direction Z), but also makes the length of the first gate 2 or the second gate 6 no longer limited by the limitation of the photolithography limit, which can effectively suppress the short channel effect and reduce the parasitic capacitance and dynamic power consumption of the device. This is also conducive to significantly improving the PPAC of the transistor 610 and the integrated circuit 600 to which it is applied.

[0110] The channel layer 4 can be arranged in a variety of ways, and can be selected according to actual needs. The following is a schematic illustration of the arrangement of the channel layer 4 in conjunction with the accompanying drawings. The arrangement of the channel layer 4 is not limited to the following illustration.

[0111] In some embodiments, Figure 4 As shown, the channel layer 4 includes a first sub-portion 41 and a second sub-portion 42. The first sub-portion 41 and the second sub-portion 42 are respectively arranged on opposite sides of the first gate 2. The first sub-portion 41 and the second sub-portion 42 are both in contact with the first electrode 1.

[0112] In other embodiments, Figure 5 As shown, the channel layer 4 includes a first sub-portion 41, a second sub-portion 42 and a third sub-portion 43. The first sub-portion 41 and the second sub-portion 42 are respectively arranged on opposite sides of the first gate 2, and the third sub-portion 43 is located between the first sub-portion 41 and the second sub-portion 42, and connects the first sub-portion 41 and the second sub-portion 42. The third sub-portion 43 is also located between the first gate dielectric layer 3 and the first pole 1, and contacts the surface of the first gate dielectric layer 3 on one side close to the first pole 1, so that the channel layer 4 has a U-shaped structure. The first sub-portion 41, the second sub-portion 42 and the third sub-portion 43 are all in contact with the first pole 1.

[0113] In some other embodiments, in combination Figure 4 and Figure 7c , the first gate dielectric layer 3 includes a first dielectric pattern 31 and a second dielectric pattern 32. The first dielectric pattern 31 and the second dielectric pattern 32 are connected and form an integral structure; or, the first dielectric pattern 31 and the second dielectric pattern 32 are prepared separately. The first dielectric pattern 31 is located between the first pole 1 and the first gate 2, and the second dielectric pattern 32 is tubular, sleeved on the first gate 2, and surrounds the side of the first gate 2. The channel layer 4 is, for example, tubular, sleeved on the second dielectric pattern 32, and surrounds the second dielectric pattern 32 and the first gate 2.

[0114] This is beneficial for increasing the overlapping area between the channel layer 4 and the first gate 2 , and increasing the ability of the first gate 2 to regulate the threshold voltage of the transistor 610 .

[0115] In some other embodiments, in combination Figure 6 , Figure 7b and Figure 7c , the first gate dielectric layer 3 includes a first dielectric pattern 31 and a second dielectric pattern 32. The first dielectric pattern 31 and the second dielectric pattern 32 are arranged in the same manner as in some of the above embodiments, and are not described in detail here. A portion of the channel layer 4 is, for example, tubular, and is sleeved on the second dielectric pattern 32, surrounding the second dielectric pattern 32 and the first gate 2, and another portion of the channel layer 4 is located between the first dielectric pattern 31 and the first electrode 1. For example, the cross-sectional view of the channel layer 4 is U-shaped. Accordingly, the channel layer 4 overlaps both the side surface of the first gate 2 and the bottom surface of the first gate 2.

[0116] This is beneficial for further increasing the overlapping area between the channel layer 4 and the first gate 2 , and further increasing the ability of the first gate 2 to regulate the threshold voltage of the transistor 610 .

[0117] In various configurations of the channel layer 4, such as Figure 7a , Figure 7b and Figure 7c As shown, the second gate dielectric layer 5 is, for example, tubular and surrounds the channel layer 4. The second gate electrode 6 is, for example, tubular and surrounds the second gate dielectric layer 5. The cross-sectional view of the second gate dielectric layer 5 and the second gate electrode 6 is, for example, as shown in FIG. Figure 7c The circular shape shown can also be Figure 7a , Figure 7b In this case, transistor 610 can be called a vertical ring channel structure transistor.

[0118] This is equivalent to increasing the effective channel width of the channel layer 4 , which is not only beneficial to increasing the regulation capability of the second gate 6 , but also beneficial to increasing the on-state current of the transistor 610 , thereby improving the device performance of the transistor 610 .

[0119] The second pole 7 can be arranged in a variety of ways, and can be selected according to actual needs. The following is a schematic illustration of the arrangement of the second pole 7 in conjunction with the accompanying drawings. The arrangement of the second pole 7 is not limited to the following illustration.

[0120] In some embodiments, Figure 4 and Figure 5 As shown, the second electrode 7 is located on the side of the channel layer 4 away from the first gate 2, and is in contact with the surface of the channel layer 4 on the side away from the first gate 2. At this time, the second electrode 7 is located on the side of the second gate 6 away from the first electrode 1. The second isolation layer 9 is located between the second electrode 7 and the driving electrode 6.

[0121] In this example, if Figure 4 and Figure 5 As shown, a surface of the second electrode 7 that is away from the first electrode 1 is flush with a surface of the channel layer 4 that is away from the first electrode 1 .

[0122] Further, the second pole 7 is, for example, in a ring shape, surrounding the channel layer 4. The cross-sectional shape of the second pole 7 is, for example, a circular ring shape, or a square ring shape. This is conducive to increasing the contact area between the second pole 7 and the channel layer 4, and reducing the contact resistance between the second pole 7 and the channel layer 4.

[0123] In other embodiments, Figure 6 and Figure 8 As shown, the second electrode 7 includes a first electrode pattern 71 and a second electrode pattern 72. The first electrode pattern 71 and the second electrode pattern 72 are connected.

[0124] The first electrode pattern 71 is located on a side of the first gate dielectric layer 3 away from the first gate 2, and on a side of the channel layer 4 away from the first pole 1. The side surface of the first electrode pattern 71 away from the first gate 2 is, for example, flush with the side surface of the channel layer 4 away from the first gate 2; the side surface of the first electrode pattern 71 close to the first gate 2 is, for example, flush with the side surface of the channel layer 4 close to the first gate 2. Accordingly, along the direction X, the size of the first electrode pattern 71 is equal to the size of the portion of the channel layer 4 covering the side of the first gate 2. The side surface of the first electrode pattern 71 close to the first pole 1 is, for example, flush with the side surface of the second gate 6 away from the first pole 1. Accordingly, the side surface of the channel layer 4 away from the first pole 1 is flush with the side surface of the second gate 6 away from the first pole 1.

[0125] The second electrode pattern 72 is located on the side of the second grid 6 away from the first grid 1, and is located on the side of the first electrode pattern 71 away from the first grid 2. The cross-sectional view of the second electrode pattern 72 and the first electrode pattern 71 is, for example, as shown in FIG. Figure 6The second isolation layer 9 is located between the second electrode pattern 72 and the driving electrode 6 , and is in contact with the first electrode pattern 71 .

[0126] The first electrode pattern 71 contacts the side surface of the channel layer 4 away from the first electrode 1, and the second electrode pattern 72 contacts the side surface of the first electrode pattern 71 away from the first gate 2. Thus, an electrical connection between the second electrode 7 and the channel layer 4 is formed.

[0127] In this embodiment, the first electrode pattern 71 is provided to reduce the distance between the side surface of the channel layer 4 away from the first electrode 1 and the side surface of the second gate 6 away from the first electrode 1, thereby reducing the distance between the first electrode 1 and the second electrode 7. When the transistor 610 is turned on, the flow path of the driving current can be shortened. In this way, the on-resistance of the transistor 610 can be effectively reduced, and the device performance of the transistor 610 can be improved.

[0128] Alternatively, if Figure 8 As shown, the first electrode pattern 71 is, for example, in a ring shape, surrounding the first gate dielectric layer 3 and the first gate 2. The second electrode pattern 72 is, for example, in a ring shape, surrounding the first electrode pattern 71. This is conducive to increasing the contact area between the second electrode 7 and the channel layer 4 and reducing the contact resistance between the second electrode 7 and the channel layer 4.

[0129] In some other embodiments, Fig. 9 and Fig.10 As shown, the second electrode 7 includes a third electrode pattern 73 and a fourth electrode pattern 74. The third electrode pattern 73 is in direct contact with the fourth electrode pattern 74. The material of the fourth electrode pattern 74 is, for example, a metal material.

[0130] The third electrode pattern 73 is located on a side of the first gate dielectric layer 3 away from the first gate 2 and on a side of the channel layer 4 away from the first electrode 1. In the direction X, the third electrode pattern 73 is located on a side surface away from the first gate 2, for example, protruding from a side surface of the channel layer 4 away from the first gate 2.

[0131] The third electrode pattern 73 is also in contact with a side surface of the channel layer 4 away from the first electrode 1. The fourth electrode pattern 74 covers the third electrode pattern 73. Specifically, the fourth electrode pattern 74 covers a side surface of the third electrode pattern 73 away from the first electrode 1, and covers a side surface of the third electrode pattern 73 away from the first gate 2. Further, the fourth electrode pattern 74 also covers the second isolation layer 9.

[0132] This helps to increase the positive projection area of ​​the second pole 7 on the reference plane, and when the second pole 7 is subsequently led out, it helps to increase the contact area between the second pole 7 and the lead-out contact (such as the second lead-out contact mentioned below), thereby avoiding increasing the contact resistance.

[0133] Optionally, combined Fig. 9 and Fig.10 The third electrode pattern 73 is, for example, in a ring shape, surrounding the first gate dielectric layer 3 and the first gate electrode 2. A portion of the fourth electrode pattern 74 (for example, a portion of the fourth electrode pattern 74 that contacts the second isolation layer 9) is, for example, in a ring shape, surrounding the third electrode pattern 73; another portion of the fourth electrode pattern 74 (for example, a portion of the fourth electrode pattern 74 that contacts a surface of the third electrode pattern 73 that is away from the first electrode) is, for example, in a ring shape, surrounding the first gate dielectric layer 3 and the first gate electrode 2.

[0134] The present application also provides a method for preparing a transistor, which is used, for example, to prepare a transistor 610 as described in any of the above embodiments. Fig.14 A flow chart of a method for preparing a transistor is shown; Figure 15a to Figure 15i A structural diagram corresponding to each step in a method for preparing a transistor is schematically shown; Figure 16a to Figure 16b A structural diagram corresponding to each step in another method for preparing a transistor is shown; Figure 17a to Figure 17i A structural diagram corresponding to each step in another method for preparing a transistor is shown; Figure 18a to Figure 18f The structure diagram corresponding to each step in another method for preparing a transistor is shown. It should be understood that Fig.14 The steps shown are not exclusive and can also be performed in Fig.14 Other steps may be performed before, after or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different order. Fig.14 Executed in the order shown.

[0135] The following is a schematic illustration of the method for manufacturing a transistor in conjunction with the accompanying drawings. Fig.14 As shown, the preparation method includes: S100~S400.

[0136] S100, such as Fig.15a As shown, a stacked structure 10 is formed. The stacked structure 10 includes a first electrode 1 and a semiconductor layer 4a stacked in sequence.

[0137] Exemplarily, the method for forming the stacked structure 10 includes: providing a substrate; then using an epitaxial growth process to sequentially form a first electrode film and a semiconductor film on the substrate; then using an etching process (including but not limited to a photolithography process) to simultaneously etch the semiconductor film and the first electrode film to form a plurality of stacked structures 10. One stacked structure 10 corresponds to, for example, one transistor 610 to be formed.

[0138] S200, such as Figure 15b to Figure 15fAs shown, a second gate dielectric layer 5 and a second gate electrode 6 are formed on the side of the semiconductor layer 4a. The second gate electrode 6 is located on the side of the second gate dielectric layer 5 away from the semiconductor layer 4a. Either the second gate electrode 6 or the second gate dielectric layer 5 is insulated from the first electrode 1.

[0139] Exemplarily, before forming the second gate dielectric layer 5 and the second gate electrode 6, the preparation method provided in the embodiment of the present application further includes: Fig.15b As shown, the semiconductor layer 4a is etched to reduce the size of the semiconductor layer 4a in a direction perpendicular to the direction Z (including but not limited to the direction X and the direction Y), exposing a portion of the first pole 1. In the direction perpendicular to the direction Z, the first pole 1 protrudes from the semiconductor layer 4a. For example, Fig.15b (a) is a cross-sectional view of the structure prepared according to the above steps, Fig.15b (b) in Fig.15b A top view of the structure shown in (a) in Fig.15b In (b), the first electrode 1 surrounds the semiconductor layer 4a. Fig.15c and Fig.15d As shown, a first isolation film 8a is formed on the exposed portion of the first electrode 1, and then the first isolation film 8a is etched back to obtain a first isolation layer 8. For example, Fig.15d (a) is a cross-sectional view of the structure prepared according to the above steps, Fig.15d (b) in Fig.15d A top view of the structure shown in (a) in Fig.15d In (b), the first isolation layer 8 surrounds the semiconductor layer 4a.

[0140] Exemplarily, forming the second gate dielectric layer 5 and the second gate 6 on the side of the semiconductor layer 4 a includes: S210 - S220 .

[0141] S210, such as Fig.15e As shown, a second gate dielectric film 5a and a second gate film 6a are sequentially formed on the side of the semiconductor layer 4a and on the side of the semiconductor layer 4a away from the first electrode 1.

[0142] Exemplarily, the embodiment of the present application may adopt a deposition process to sequentially form the second gate dielectric film 5a and the second gate film 6a. The second gate dielectric film 5a and the second gate film 6a are, for example, both whole film layers, the second gate dielectric film 5a covers the semiconductor layer 4a and the first isolation layer 8, and the second gate film 6a covers the second gate dielectric film 5a. The orthographic projection of the second gate dielectric film 5a on the reference plane, for example, coincides with the orthographic projection of the second gate film 6a on the reference plane.

[0143] S220, such as Fig.15fAs shown, the portions of the second gate dielectric film 5a and the second gate film 6a located on the side of the semiconductor layer 4a away from the first electrode 1 are removed, and the portions of the second gate dielectric film 5a and the second gate film 6a covering the side surfaces of the semiconductor layer 4a are retained to form a second gate dielectric layer 5 and a second gate 6.

[0144] For example, the embodiment of the present application may use a chemical mechanical polishing (CMP) process to grind the second gate film 6a and the second gate dielectric film 5a to make them flush with the surface of the side of the semiconductor layer 4a away from the first electrode 1. Then, the second gate film 6a and the second gate dielectric film 5a are etched back to expose part of the side of the semiconductor layer 4a, thereby obtaining the second gate dielectric layer 5 and the second gate 6.

[0145] S300, such as Figure 15h As shown, a groove A is formed penetrating at least part of the semiconductor layer 4a to obtain the channel layer 4. The groove A extends along the arrangement direction of the first electrode 1 and the semiconductor layer 4a (ie, direction Z).

[0146] For example, the embodiment of the present application may use an etching process (including but not limited to a photolithography process) to etch the semiconductor layer 4a. The structures of the grooves A formed by etching include various structures, which can be selected and set according to actual needs.

[0147] For example, the trench A penetrates the semiconductor layer 4a along the direction Z, and the trench A penetrates the semiconductor layer 4a along the direction Y. At this time, the channel layer 4 includes a first sub-portion 41 and a second sub-portion 42 arranged at intervals along the direction X.

[0148] For another example, the groove A penetrates the semiconductor layer 4a along the direction Z, and the groove A penetrates a portion of the semiconductor layer 4a along the direction perpendicular to the direction Z. At this time, the channel layer 4 has a tubular structure.

[0149] For another example, the groove A penetrates a portion of the semiconductor layer 4a along the direction Z, and the groove A penetrates the semiconductor layer 4a along the direction Y. At this time, the channel layer 4 has a U-shaped structure.

[0150] For another example, the groove A penetrates a portion of the semiconductor layer 4a along the direction Z, and the groove A penetrates a portion of the semiconductor layer 4a along the direction perpendicular to the direction Z. At this time, the cross-sectional shape of the channel layer 4 along the direction perpendicular to the direction Z is U-shaped.

[0151] S400, such as Fig.15i As shown, a first gate dielectric layer 3 and a first gate electrode 2 are formed in the trench A. The first gate dielectric layer 3 is located between the channel layer 4 and the first gate electrode 2 .

[0152] Illustratively, the embodiment of the present application may adopt a deposition process, an etching process, etc. to form the first gate dielectric layer 3 and the first gate 2 .

[0153] The transistor formed by the above-mentioned manufacturing method can adjust its threshold voltage in response to the first gate signal on the first gate 2, and can generate a driving current (also called an on-state current) in response to the second gate signal on the second gate 6. The magnitude of the on-state current and the magnitude of the leakage current are related to the threshold voltage of the transistor 610.

[0154] The threshold voltage of the transistor is, for example, negatively correlated with the voltage value of the first gate signal on the first gate 2. That is, the greater the voltage value of the first gate signal on the first gate 2, the smaller the threshold voltage of the transistor; and the smaller the voltage value of the first gate signal on the first gate 2, the greater the threshold voltage of the transistor.

[0155] That is to say, in the embodiment of the present application, the first gate 2 is prepared and formed in the channel layer 4, and the threshold voltage of the transistor 610 can be adjusted within a larger range by adjusting the voltage of the first gate signal on the first gate 2, and within the larger range, the threshold voltage is continuously adjustable. Compared with the third implementation method described above, the first gates 2 of different transistors 610 prepared and formed in the embodiment of the present application are set independently of each other, so that the threshold voltages of different transistors 610 can be adjusted separately, which can simultaneously meet the balance requirements for high performance and low energy consumption in circuit design.

[0156] Moreover, in the above-mentioned preparation method, the process for preparing the first gate dielectric layer 3 and the first gate 2 is simple. Compared with the above-mentioned first possible implementation method, there is no need to adopt an ion implantation process, which can reduce the difficulty of preparing the transistor 610 and the integrated circuit 600 used therein. Compared with the above-mentioned second possible implementation method, there is no need to define the areas corresponding to different modules, which can reduce the use of photomasks and reduce the preparation cost. Moreover, there is no need to prepare a dipole oxide layer, which reduces the control of the thickness of the second gate 2 in different transistors, reduces the requirements of the corresponding preparation process, and thus reduces the difficulty of preparing the transistor 610 and the integrated circuit 600 used therein.

[0157] It is understandable that the method for preparing the transistor provided in the embodiment of the present application further includes: forming the second pole 7. Among them, there are multiple methods for forming the second pole 7, which can be selected and set according to actual needs. In addition, in the above S400, the method for forming the first gate dielectric layer 3 and the first gate 2 is related to the method for forming the second pole 7. In conjunction with the accompanying drawings, different methods for forming the second pole 7, the first gate dielectric layer 3 and the first gate 2 are schematically described below.

[0158] In a first possible embodiment, Fig.16a and Fig.16b As shown, the manufacturing method further includes: forming a second electrode 7 on a side of the channel layer 4 away from the first gate 2. The second electrode 7 is in contact with a surface of the channel layer 4 on a side away from the first gate 2.

[0159] Exemplarily, before forming the second electrode 7, the above preparation method further includes: Figure 15g As shown, a second isolation film 9a is formed, and the second isolation film 9a covers the second gate electrode 6 and the second gate dielectric layer 5. The surface of the second isolation film 9a on one side away from the first electrode 1 is, for example, flush with the surface of the channel layer 4 on one side away from the first electrode 1; Fig.16a As shown, the second isolation film 9a is then etched back to obtain a second isolation layer 9. The second isolation layer 9 exposes a portion of the side surface of the channel layer 4.

[0160] For example, Fig.16b As shown, the embodiment of the present application can adopt an epitaxial growth process to form a second electrode 7 on the second isolation layer 9. The second electrode 7 is in contact with a surface of the channel layer 4 away from the first gate 2, and a surface of the second electrode 7 away from the first electrode 1 is, for example, flush with a surface of the channel layer 4 away from the first electrode 1.

[0161] In a second possible embodiment, Fig.17a As shown, the stacked structure 10 further includes an electrode layer 11 located on the semiconductor layer 4a. Accordingly, in the above S100, after growing the first electrode film and the semiconductor film, the second electrode film can be grown on the semiconductor film; in the process of etching the semiconductor film and the first electrode film, the second electrode film can be etched synchronously to form the electrode layer 11.

[0162] Furthermore, if Fig.17b and Fig.17c As shown, before the above S210, the first isolation film 8a formed on the exposed portion of the first electrode 1, for example, also surrounds the side of the electrode layer 11. The first isolation layer 8 formed after the first isolation film 8a is etched back, for example, covers part of the side of the semiconductor layer 4a and surrounds the semiconductor layer 4a. Fig.17d As shown, the upper surfaces of the second gate dielectric layer 5 and the second gate electrode 6 formed in the above S220 are, for example, flush with the upper surface of the semiconductor layer 4 a .

[0163] Furthermore, if Fig.17e and Fig.17fAs shown, in the above S300, forming the groove A penetrating at least part of the semiconductor layer 4a includes: forming the groove A penetrating the electrode layer 11 and penetrating at least part of the semiconductor layer 4a to obtain the first electrode pattern 71 and the channel layer 4. Since the first electrode pattern 71 and the channel layer 4 are formed by synchronous etching, the side surface of the first electrode pattern 71 and the side surface of the channel layer 4 are flush.

[0164] After the above S400, that is, after the first gate dielectric layer 3 and the first gate electrode 2 are formed in the trench A, as shown in FIG. Fig.17i As shown, the preparation method further includes: forming a second electrode pattern 72 on a side of the first electrode pattern 71 away from the first grid 2. The second electrode pattern 72 is also located on a side of the second grid 6 away from the first pole 1; the second electrode pattern 72 contacts the first electrode pattern 71 to form a second pole 7.

[0165] For example, Fig.17e and Fig.17f As shown, before forming the trench A, the above preparation method further includes: forming a second isolation film 9a, the second isolation film 9a covers the second gate electrode 6 and the second gate dielectric layer 5, and the surface of the second isolation film 9a away from the first electrode 1 is, for example, flush with the surface of the electrode layer 11 away from the first electrode 1. Then, as Figure 17g and Figure 17h As shown, after forming the first gate dielectric layer 3 and the first gate electrode 2, a protective layer 12 is formed to cover the first gate electrode 2, the first gate dielectric layer 3 and the first electrode pattern 71. Then, the second isolation film 9a is etched back to obtain the second isolation layer 9. The second isolation layer 9 exposes part of the side surface of the channel layer 4.

[0166] Exemplarily, the embodiment of the present application may adopt an epitaxial growth process to form a second electrode pattern 72 on the second isolation layer 9. The second electrode pattern 72 is in contact with a side surface of the first electrode pattern 71 away from the first gate 2, and a side surface of the second electrode pattern 72 away from the first electrode 1 is, for example, flush with a side surface of the first electrode pattern 71 away from the first electrode 1.

[0167] In the first possible embodiment and the second possible embodiment, the method for forming the first gate dielectric layer 3 and the first gate electrode 2 in the trench A includes, for example, using a deposition process to sequentially form a first gate dielectric film and a first gate film in the trench A. The first gate dielectric film and the first gate film are, for example, both whole film layers, the first gate dielectric film covers the channel layer 4 and the second isolation layer 9, and the first gate film covers the first gate dielectric film. Then, a CMP process can be used to planarize the first gate dielectric film and the first gate film, and stop at the surface of the second isolation layer 9 away from the first electrode 1 to obtain the first gate dielectric layer 3 and the first gate electrode 2.

[0168] In a third possible embodiment, in the above S400 , a first gate dielectric layer 3 and a first gate 2 are formed in the trench A, including: S410 - S430 .

[0169] S410, such as Figure 18a to Figure 18c As shown, a first gate dielectric layer 3 and a sacrificial gate 13 are sequentially formed in the trench A. Both the first gate dielectric layer 3 and the sacrificial gate 13 protrude from the channel layer 4 .

[0170] For example, Figure 15g and Figure 15h As shown, before forming the groove A, the above preparation method also includes: forming a second isolation layer 9, which covers the second gate 6 and the second gate dielectric layer 5, and the side surface of the second isolation layer 9 away from the first electrode 1 is, for example, flush with the side surface of the semiconductor layer 4a away from the first electrode 1.

[0171] Exemplarily, the method of forming the first gate dielectric layer 3 and the sacrificial gate 13 includes: Fig.18a As shown, a deposition process is used to sequentially form a first gate dielectric film 3a and a sacrificial gate film 13a in the trench A. Fig.18b As shown, an etching process is then used to remove the first gate dielectric film 3a and the sacrificial gate film 13a covering the channel layer 4 and the second isolation layer 9, thereby obtaining a third dielectric pattern 33 and a sacrificial gate 13; the sacrificial gate 13 protrudes from the third dielectric pattern 33. Fig.18c As shown, a fourth dielectric pattern 34 is then formed on the portion of the sacrificial gate 13 protruding from the third dielectric pattern 33 , and the fourth dielectric pattern 34 and the third dielectric pattern 33 are connected to form the first gate dielectric layer 3 together.

[0172] S420, such as Fig.18d As shown, a third electrode pattern 73 is formed on a side of the first gate dielectric layer 3 away from the sacrificial gate 13. The third electrode pattern 73 is also located on a side of the channel layer 4 away from the first electrode 1 and contacts a surface of the channel layer 4 away from the first electrode 1.

[0173] Exemplarily, the embodiment of the present application may adopt an epitaxial growth process to form the third electrode pattern 73. A portion of the third electrode pattern 73 is also located on the second isolation layer 9.

[0174] S430, such as Fig.18e As shown, a fourth electrode pattern 74 is formed to cover the third electrode pattern 73. The fourth electrode pattern 74 and the third electrode pattern 73 constitute the second electrode 7.

[0175] For example, the embodiment of the present application can use a deposition process or a sputtering process to deposit a metal material on the third electrode pattern 73 to form a fourth electrode pattern 74. The fourth electrode pattern 74 is also in contact with the second isolation layer 9. In this way, the second electrode 7 is prepared and formed.

[0176] In the above embodiment, if Fig.18f As shown, a first gate dielectric layer 3 and a first gate 2 are formed in the trench A, and the method further includes: replacing the sacrificial gate 13 with the first gate 2 .

[0177] The materials of the first gate dielectric film 3a and the sacrificial gate film 13a are different. For example, the material of the first gate dielectric film 3a includes but is not limited to silicon oxide, and the material of the sacrificial gate film 13a includes but is not limited to polysilicon, silicon nitride, amorphous silicon, spin-on carbon, photothermal material, etc. The materials of the first gate dielectric film 3a and the sacrificial gate film 13a have different etching selectivities.

[0178] By selecting a suitable etching selectivity, only the sacrificial gate 13 can be removed, and the first gate dielectric layer 3 can be retained. After the sacrificial gate 13 is removed, a sacrificial gap is formed, and a conductive material can be backfilled in the sacrificial gap to form the first gate 2.

[0179] It can be understood that after the transistor 610 is prepared and formed, an interconnection layer can be formed on the transistor 610 to lead out each electrode of the transistor 610. Fig.19 The structure of an interconnection layer is schematically shown, and the interconnection layer includes an insulating layer 14, a first lead-out contact 15 and a second lead-out contact 16 located in the insulating layer 14. The first lead-out contact 15 contacts the first gate 2 to lead out the first gate 2. The second lead-out contact 16 contacts the second pole 7 to lead out the second pole 7. There are multiple second lead-out contacts 16, which is conducive to reducing the contact resistance between the second lead-out contact 16 and the second pole 7.

[0180] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present disclosure should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A transistor, characterized in that: The transistor comprises: first pole; A first grid electrode, located on the first electrode; a first gate dielectric layer, located between the first electrode and the first gate; the first gate dielectric layer also covers at least a portion of a side surface of the first gate; a channel layer, located on a side of the first gate dielectric layer away from the first gate electrode and in contact with the first electrode; A second gate dielectric layer is located on a side of the channel layer away from the first gate and is insulated from the first electrode; A second gate electrode is located at a side of the second gate dielectric layer away from the first gate electrode and is insulated from the first electrode; The second electrode is at least partially located on a side of the second gate away from the first electrode and in contact with the channel layer.

2. The transistor according to claim 1, characterized in that The first gate dielectric layer includes a first dielectric pattern and a second dielectric pattern; the first dielectric pattern is located between the first electrode and the first gate, and the second dielectric pattern surrounds the side of the first gate; The channel layer surrounds the second dielectric pattern and the first gate.

3. The transistor according to claim 1 or 2, characterized in that: The second gate dielectric layer surrounds the channel layer, and the second gate surrounds the second gate dielectric layer.

4. The transistor according to any one of claims 1 to 3, characterized in that The channel layer is also located between the first electrode and the first gate dielectric layer, and is in contact with a surface of the first gate dielectric layer on one side close to the first electrode.

5. The transistor according to any one of claims 1 to 4, characterized in that The second electrode is located on a side of the channel layer away from the first gate, and is in contact with a surface of the channel layer on a side away from the first gate.

6. The transistor according to claim 5, characterized in that The second electrode surrounds the channel layer.

7. The transistor according to any one of claims 1 to 4, characterized in that The second electrode comprises: a first electrode pattern and a second electrode pattern; The first electrode pattern is located on a side of the first gate dielectric layer away from the first gate electrode, and is located on a side of the channel layer away from the first electrode; the first electrode pattern is in contact with a surface of a side of the channel layer away from the first electrode; The second electrode pattern is located on a side of the second grid electrode away from the first electrode, and is located on a side of the first electrode pattern away from the first grid electrode; the second electrode pattern contacts a surface of a side of the first electrode pattern away from the first grid electrode.

8. The transistor according to claim 7, characterized in that The first electrode pattern surrounds the first gate dielectric layer and the first gate; The second electrode pattern surrounds the first electrode pattern.

9. The transistor according to any one of claims 1 to 4, characterized in that: The second electrode includes: a third electrode pattern and a fourth electrode pattern; The third electrode pattern is located on a side of the first gate dielectric layer away from the first gate electrode, and is located on a side of the channel layer away from the first electrode; the third electrode pattern is in contact with a surface of a side of the channel layer away from the first electrode; The fourth electrode pattern covers the third electrode pattern.

10. The transistor according to claim 9, characterized in that The third electrode pattern surrounds the first gate dielectric layer and the first gate; A portion of the fourth electrode pattern surrounds the third electrode pattern, and another portion of the fourth electrode pattern surrounds the first gate dielectric layer and the first gate.

11. A method for preparing a transistor, characterized in that: The preparation method comprises: forming a stacked structure, the stacked structure comprising a first electrode and a semiconductor layer stacked in sequence; A second gate dielectric layer and a second gate electrode are formed on the side of the semiconductor layer; the second gate electrode is located on a side of the second gate dielectric layer away from the semiconductor layer, and either the second gate electrode or the second gate dielectric layer is insulated from the first electrode; Forming a groove penetrating at least a portion of the semiconductor layer to obtain a channel layer; the groove extends along an arrangement direction of the first electrode and the semiconductor layer; A first gate dielectric layer and a first gate electrode are formed in the trench; the first gate dielectric layer is located between the channel layer and the first gate electrode.

12. The preparation method according to claim 11, characterized in that: The preparation method further comprises: A second electrode is formed on a side of the channel layer away from the first gate; the second electrode is in contact with a surface of the channel layer away from the first gate.

13. The preparation method according to claim 11, characterized in that: The stacked structure further includes an electrode layer located on the semiconductor layer; The forming of the groove penetrating at least a portion of the semiconductor layer comprises: forming a groove penetrating the electrode layer and penetrating at least a portion of the semiconductor layer to obtain a first electrode pattern and the channel layer; After forming the first gate dielectric layer and the first gate in the trench, the preparation method further includes: A second electrode pattern is formed on a side of the first electrode pattern away from the first grid; the second electrode pattern is also located on a side of the second grid away from the first pole; the second electrode pattern contacts the first electrode pattern to form a second pole.

14. The preparation method according to claim 11, characterized in that: The forming of a first gate dielectric layer and a first gate in the trench comprises: A first gate dielectric layer and a sacrificial gate are sequentially formed in the trench; the first gate dielectric layer and the sacrificial gate both protrude from the channel layer; A third electrode pattern is formed on a side of the first gate dielectric layer away from the sacrificial gate; the third electrode pattern is also located on a side of the channel layer away from the first electrode, and is in contact with a surface of the channel layer away from the first electrode; A fourth electrode pattern is formed to cover the third electrode pattern; the fourth electrode pattern and the third electrode pattern constitute a second electrode.

15. The preparation method according to claim 14, characterized in that: The forming of a first gate dielectric layer and a first gate in the trench further includes: The sacrificial gate is replaced by the first gate.

16. The preparation method according to any one of claims 11 to 15, characterized in that: The forming of a second gate dielectric layer and a second gate on the side of the semiconductor layer comprises: Sequentially forming a second gate dielectric film and a second gate film on a side of the semiconductor layer and a side of the semiconductor layer away from the first electrode; The second gate dielectric film and the portion of the second gate film located on the side of the semiconductor layer away from the first electrode are removed, and the second gate dielectric film and the portion of the second gate film covering the side of the semiconductor layer are retained to form the second gate dielectric layer and the second gate.

17. An integrated circuit, characterized in that: The integrated circuit includes a packaging structure and one or more transistors packaged inside the packaging structure, wherein the transistor includes the transistor according to any one of claims 1 to 10.

18. An electronic device, characterized in that: The electronic device comprises: a circuit board, and an integrated circuit electrically connected to the circuit board, wherein the integrated circuit comprises the integrated circuit as claimed in claim 17.

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