Light emitting diode and preparation method thereof
By adopting a double-layer passivation layer structure in the light emitting diode and using the combination of silicon-aluminum oxide layer and silicon oxide layer, the problem of insufficient moisture resistance of the passivation layer is solved, and the yield and reliability of the LED are significantly improved.
Patent Information
- Application Number
- CN202411372643.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-02-25
AI Technical Summary
The passivation layer of existing light emitting diodes lacks moisture resistance, resulting in low chip reliability and low LED yield.
A double-layer passivation layer structure is adopted, wherein the first passivation sub-layer is a silicon-aluminum oxide layer and the second passivation sub-layer is an oxide layer of silicon. Through a specific deposition process and laminated structure, the moisture-resistant corrosion resistance of the passivation layer is improved.
It significantly improves the internal structural stability of LED devices in high humidity environments, and improves the yield and reliability of LEDs.
Smart Images
Figure CN119521884A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for preparing the same. Background Art
[0002] Light Emitting Diode (LED) is a semiconductor device that can emit light. It has the advantages of energy saving, high brightness, high durability, long life and light weight. It has been widely used in fields such as lighting and display.
[0003] The related art provides a light emitting diode, the light emitting diode structure includes an epitaxial structure, an electrode structure and a passivation layer, wherein the passivation layer covers the epitaxial structure, and the electrode structure passes through the passivation layer and is electrically connected to the epitaxial structure.
[0004] The moisture resistance of the passivation layer directly affects the reliability of the chip. Insufficient moisture resistance of the passivation layer in related technologies leads to low chip reliability and low LED yield. Summary of the invention
[0005] The embodiment of the present disclosure provides a light emitting diode and a method for manufacturing the same, which can improve the moisture resistance of the passivation layer of the light emitting diode and improve the reliability of the chip. The technical solution is as follows:
[0006] In one aspect, a light emitting diode is provided, the light emitting diode comprising: the light emitting diode comprising: an epitaxial structure, an electrode structure and a passivation layer;
[0007] The passivation layer covers the epitaxial structure, the electrode structure is electrically connected to the epitaxial structure through the passivation layer, the passivation layer includes a first passivation sublayer and a second passivation sublayer sequentially stacked on the epitaxial structure, the first passivation sublayer is a silicon aluminum oxide layer, and the second passivation sublayer is a silicon oxide layer.
[0008] Optionally, the first passivation sublayer is SiAl x O y Layer, where both x and y are greater than 0.
[0009] Optionally, the second passivation sublayer is a SiO2 layer.
[0010] Optionally, the epitaxial structure is provided with a step structure and a packaging groove, the step structure includes a step top surface and a step bottom surface; the passivation layer covers the step bottom surface, the step top surface and the packaging groove.
[0011] Optionally, the thickness of the first passivation sublayer is 2.5-6 nm, and the thickness of the second passivation sublayer is 5.6-8.5 nm.
[0012] In another aspect, a method for preparing a light emitting diode comprises:
[0013] Fabricating epitaxial structures;
[0014] Fabricating an electrode structure on the surface of the epitaxial structure;
[0015] A passivation layer is manufactured, wherein the passivation layer covers the epitaxial structure, and the electrode structure is electrically connected to the epitaxial structure through the passivation layer. The passivation layer includes a first passivation sublayer and a second passivation sublayer sequentially stacked on the epitaxial structure, wherein the first passivation sublayer is a silicon aluminum oxide layer, and the second passivation sublayer is a silicon oxide layer.
[0016] Optionally, manufacturing the first passivation sublayer includes:
[0017] Controlling the temperature of the reaction chamber so that the temperature of the substrate where the epitaxial structure is located is 90-110° C. and the temperature of the inner wall of the reaction chamber is 110-130° C.;
[0018] A silicon precursor is introduced, wherein the pulse time is 20 to 40 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds;
[0019] The oxidative precursor is introduced, wherein the pulse time is 40 to 60 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds;
[0020] An aluminum source precursor is introduced, wherein the pulse time is 10 to 30 milliseconds, the purge time is 13 to 17 seconds, and the waiting time is 3 to 7 seconds;
[0021] The oxidative precursor is introduced again. When the oxidative precursor is introduced, the pulse time is 40 to 60 milliseconds, the purge time is 13 to 17 seconds, and the waiting time is 3 to 7 seconds.
[0022] Optionally, manufacturing the second passivation sublayer includes:
[0023] Controlling the temperature of the reaction chamber so that the temperature of the substrate where the epitaxial structure is located is 90-110° C. and the temperature of the inner wall of the reaction chamber is 110-130° C.;
[0024] A silicon precursor is introduced, wherein the pulse time is 20 to 40 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds;
[0025] An oxidative precursor is introduced, wherein the pulse time is 40 to 60 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds.
[0026] Optionally, when the first passivation sublayer is manufactured, each precursor is introduced in a periodic cycle, and the cycle period is 8 to 12.
[0027] Optionally, when manufacturing the second passivation sub-layer, each precursor is introduced periodically and cyclically, and the cycle period is 28 to 32.
[0028] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0029] In the disclosed embodiment, the passivation layer includes a first passivation sublayer and a second passivation sublayer, the first passivation sublayer is a silicon aluminum oxide layer, and the second passivation sublayer is a silicon oxide layer. The first passivation sublayer formed by silicon aluminum oxidation has good surface density, and as a buffer layer of the second passivation sublayer, it greatly improves the deposition quality of the subsequent growth of the second passivation sublayer. The second passivation sublayer formed by silicon oxide is an amorphous film, which is dense and defect-free, stable in nature, and is conducive to isolating water vapor. The above double-layer passivation layer has a good coating effect, a uniform and compact film, and good moisture and corrosion resistance, which greatly improves the stability of the internal structure of the LED device in a high humidity environment and improves the LED yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0031] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;
[0032] Figure 2 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;
[0033] Figure 3 is a flow chart of another method for preparing a light emitting diode provided by an embodiment of the present disclosure;
[0034] Figure 4 This is a structural schematic diagram of a light emitting diode manufacturing process provided by an embodiment of the present disclosure;
[0035] Figure 5 This is a structural schematic diagram of a light emitting diode manufacturing process provided by an embodiment of the present disclosure;
[0036] Figure 6 This is a structural schematic diagram of a light emitting diode manufacturing process provided by an embodiment of the present disclosure;
[0037] Figure 7It is a structural schematic diagram of a light emitting diode manufacturing process provided by an embodiment of the present disclosure.
[0038] The reference numerals are as follows:
[0039] 100: epitaxial structure; 200: electrode structure; 300: passivation layer; 400: current blocking layer; 500: transparent conductive layer; 600: substrate;
[0040] 101: first semiconductor layer; 102: active layer; 103: second semiconductor layer; 201: first electrode; 202: second electrode; 301: first passivation sublayer; 302: second passivation sublayer;
[0041] 1001: step structure; 1002: packaging groove. DETAILED DESCRIPTION
[0042] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0043] Figure 1 is a schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 The light emitting diode includes: an epitaxial structure 100 , an electrode structure 200 and a passivation layer 300 .
[0044] The passivation layer 300 covers the epitaxial structure 100, and the electrode structure 200 is electrically connected to the epitaxial structure 100 through the passivation layer 300. The passivation layer 300 includes a first passivation sublayer 301 and a second passivation sublayer 302 sequentially stacked on the epitaxial structure 100. The first passivation sublayer 301 is a silicon aluminum oxide layer, and the second passivation sublayer 302 is a silicon oxide layer.
[0045] In the disclosed embodiment, the passivation layer includes a first passivation sublayer and a second passivation sublayer, the first passivation sublayer is a silicon aluminum oxide layer, and the second passivation sublayer is a silicon oxide layer. The first passivation sublayer formed by silicon aluminum oxidation has good surface density, and as a buffer layer of the second passivation sublayer, it greatly improves the deposition quality of the subsequent growth of the second passivation sublayer. The second passivation sublayer formed by silicon oxide is an amorphous film, which is dense and defect-free, stable in nature, and is conducive to isolating water vapor. The above double-layer passivation layer has a good coating effect, a uniform and compact film, and good moisture and corrosion resistance, which greatly improves the stability of the internal structure of the LED device in a high humidity environment and improves the LED yield.
[0046] exist Figure 1 In the structure shown, the electrode structure 200 does not extend out of the passivation layer 300. In other embodiments, the electrode structure 200 may also extend out of the passivation layer 300.
[0047] In the embodiment of the present disclosure, the first passivation sublayer 301 may be SiAl x O y Layer, where both x and y are greater than 0.
[0048] Exemplarily, x=2, y=1.
[0049] In this implementation, SiAl x O y The chemical properties are stable, and the formed passivation sublayer has good surface density. As a buffer layer for the second passivation sublayer, it greatly improves the deposition quality of the subsequent growth of the second passivation sublayer and greatly improves the ability to isolate water vapor.
[0050] In other embodiments, the first passivation sublayer 301 may also be other types of silicon aluminum oxide layers.
[0051] In the embodiment of the present disclosure, the second passivation sublayer 302 may be a SiO 2 layer.
[0052] In this implementation, SiO2 is an amorphous film that is dense, defect-free, and stable in nature, which is conducive to isolating water vapor.
[0053] In other embodiments, the second passivation sublayer 302 may also be an oxide layer of other types of silicon.
[0054] In the disclosed embodiment, the thickness of the first passivation sublayer 301 may be 2.5 to 6 nm, and the thickness of the second passivation sublayer 302 may be 5.6 to 8.5 nm. The thickness is neither too thin to reduce the ability to isolate water vapor nor too thick to make the overall thickness of the device too thick.
[0055] Exemplarily, the thickness of the first passivation sublayer 301 is 4 nm or 5 nm, and the thickness of the second passivation sublayer 302 is 6 nm or 7 nm.
[0056] In the disclosed embodiment, the epitaxial structure 100 is provided with a step structure 1001 and a packaging groove 1002 , and the step structure 1001 includes a step top surface and a step bottom surface; the passivation layer 300 covers the step bottom surface, the step top surface and the packaging groove 1002 .
[0057] In this implementation, the epitaxial structure opens a step structure for setting electrodes, and the packaging groove allows the passivation layer to be better combined with the epitaxial structure to achieve sealing, preventing water vapor from entering through the gap between the epitaxial and passivation layers, so that the passivation layer has good moisture and corrosion resistance and can effectively isolate water vapor.
[0058] Optionally, the light emitting diode further includes a current blocking layer 400 and a transparent conductive layer 500 .
[0059] Among them, the current blocking layer 400 and the transparent conductive layer 500 are provided on the surface of the epitaxial structure 100 , the transparent conductive layer 105 covers the current blocking layer 104 , and through holes are provided in the current blocking layer 400 and the transparent conductive layer 500 .
[0060] In this implementation, the current blocking layer and the transparent conductive layer are combined to achieve uniform current diffusion and provide effective current conduction.
[0061] In the embodiment of the present disclosure, the epitaxial structure 100 includes a first semiconductor layer 101 , an active layer 102 and a second semiconductor layer 103 .
[0062] In the embodiment of the present disclosure, the electrode structure 200 includes a first electrode 201 and a second electrode 202 .
[0063] In the embodiment of the present disclosure, the first electrode 201 is connected to the second semiconductor layer 103 through the through holes of the current blocking layer 400 and the transparent conductive layer 500 , and the second electrode 202 is connected to the first semiconductor layer 101 .
[0064] Optionally, the light emitting diode further includes a substrate 600 , and the epitaxial structure 100 is located on the substrate 600 .
[0065] In the embodiment of the present disclosure, the substrate 600 may be any one of substrates such as a sapphire substrate, a Si substrate, and a SiC substrate. The embodiment of the present disclosure does not limit the material of the substrate 600.
[0066] Exemplarily, the substrate 600 is a sapphire substrate.
[0067] In the embodiment of the present disclosure, the first semiconductor layer 101 may be an N-type semiconductor layer, and the second semiconductor layer 103 may be a P-type semiconductor layer.
[0068] For example, the first semiconductor layer 101 may be an N-type GaN layer, and the second semiconductor layer 103 may be a P-type GaN layer.
[0069] In other embodiments, the first semiconductor layer 101 may be a P-type semiconductor layer, and the second semiconductor layer 103 may be an N-type semiconductor layer.
[0070] In the embodiment of the present disclosure, the active layer 102 may be a multi-quantum well layer, such as an InGaN / GaN multi-quantum well structure.
[0071] In the embodiment of the present disclosure, the first electrode 201 and the second electrode 202 may be a combination of one or more metal or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt and Au.
[0072] Exemplarily, the first electrode 201 and the second electrode 202 are stacked layers of Cr, Al, AlCu, Ti, Ni, Pt, and Au.
[0073] When the first electrode and the second electrode are made of metals such as Al, the passivation layer can prevent the electrode structure from forming an alloy at high temperature, which would cause chip reliability failure, thereby greatly improving the stability of the internal structure of the LED device in a high humidity environment.
[0074] In the embodiment of the present disclosure, the current blocking layer 400 may be an AlGaN or SiO 2 layer.
[0075] Exemplarily, the current blocking layer 400 is an AlGaN current blocking layer.
[0076] In the embodiment of the present disclosure, the transparent conductive layer 500 may be an indium tin oxide (ITO) layer. ITO has good transparency and conductivity and can conduct current to form an electrical connection while allowing light to pass through.
[0077] It is worth noting that in the embodiments of the present disclosure, structures may be selectively increased or decreased based on the structure of the above-mentioned light emitting diode, and the present disclosure does not impose any limitation on this.
[0078] Figure 2 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 2 The method steps include:
[0079] S11. Fabricating an epitaxial structure.
[0080] S12. Fabricating an electrode structure on the surface of the epitaxial structure.
[0081] S13. Prepare a passivation layer, wherein the passivation layer covers the epitaxial structure, and the electrode structure is electrically connected to the epitaxial structure through the passivation layer. The passivation layer includes a first passivation sublayer and a second passivation sublayer sequentially stacked on the epitaxial structure, wherein the first passivation sublayer is a silicon aluminum oxide layer, and the second passivation sublayer is a silicon oxide layer.
[0082] In the disclosed embodiment, the passivation layer includes a first passivation sublayer and a second passivation sublayer, the first passivation sublayer is a silicon aluminum oxide layer, and the second passivation sublayer is a silicon oxide layer. The first passivation sublayer formed by silicon aluminum oxidation has good surface density, and as a buffer layer of the second passivation sublayer, it greatly improves the deposition quality of the subsequent growth of the second passivation sublayer. The second passivation sublayer formed by silicon oxide is an amorphous film, which is dense and defect-free, stable in nature, and is conducive to isolating water vapor. The above double-layer passivation layer has a good coating effect, a uniform and compact film, and good moisture and corrosion resistance, which greatly improves the stability of the internal structure of the LED device in a high humidity environment and improves the LED yield.
[0083] Figure 3 is a flow chart of another method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 3 The method steps include:
[0084] S21. Forming a first semiconductor layer, an active layer, and a second semiconductor layer in sequence on a substrate, wherein the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure.
[0085] The substrate may be any one of a sapphire substrate, a Si substrate, a SiC substrate and the like.
[0086] Exemplarily, the substrate is a sapphire substrate.
[0087] In one example, step S21 includes:
[0088] The first step is to make the first semiconductor layer.
[0089] In the embodiment of the present disclosure, the first semiconductor layer is an N-type GaN layer.
[0090] The second step is to make the active layer.
[0091] In the embodiment of the present disclosure, the active layer is a multi-quantum well layer, such as an InGaN / GaN multi-quantum well structure.
[0092] The third step is to make the second semiconductor layer.
[0093] In the embodiment of the present disclosure, the second semiconductor layer is a P-type GaN layer.
[0094] In the embodiment of the present disclosure, the first semiconductor layer, the active layer, and the second semiconductor layer are sequentially stacked on the substrate.
[0095] In the disclosed embodiment, VeecoK465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition (MOCVD)) equipment or AIXTRON metal organic compound chemical vapor deposition equipment can be used to achieve the growth of the above semiconductor layer. High-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixed gas of high-purity H2 and high-purity N2 is used as a carrier gas, high-purity NH3 is used as an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) are used as gallium sources, trimethyl indium (TMIn) is used as an indium source, silane (SiH4) is used as an N-type dopant, trimethylaluminum (TMAl) is used as an aluminum source, and bis(cyclopentadienyl) magnesium (CP2Mg) is used as a P-type dopant.
[0096] S22, performing graphic processing on the epitaxial structure to form a step structure and a packaging groove, wherein the step structure includes a step top surface and a step bottom surface.
[0097] Figure 4 Schematic diagram of a light emitting diode manufacturing process provided by the embodiment of the present disclosure. Figure 4 The epitaxial structure 100 includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103, which are sequentially grown on a substrate 600. The epitaxial structure 100 is provided with a step structure 1001 and a packaging groove 1002. The step structure 1001 includes a step top surface and a step bottom surface.
[0098] In the disclosed embodiment, the first semiconductor layer, the active layer, and the second semiconductor layer are sequentially stacked on the substrate. The first semiconductor layer, the active layer, and the second semiconductor layer are provided with a step structure extending to the first semiconductor, that is, the bottom surface of the step is located in the first semiconductor layer. The first semiconductor layer, the active layer, and the second semiconductor layer are also provided with a packaging groove extending to the first semiconductor layer.
[0099] Exemplarily, step S22 may include:
[0100] A patterned mask layer is formed on the surface of the second semiconductor layer; under the protection of the mask layer, the epitaxial structure is etched to form a step extending to the first semiconductor layer and a packaging groove extending to the first semiconductor layer.
[0101] S23. Fabricate a current blocking layer on the surface of the epitaxial structure.
[0102] Figure 5 Schematic diagram of a light emitting diode manufacturing process provided by the embodiment of the present disclosure. Figure 5 The current blocking layer 400 is located on the first semiconductor layer 101. The current blocking layer 400 on the second semiconductor layer 103 is provided with a through hole.
[0103] In the embodiment of the present disclosure, the current blocking layer may be an AlGaN or SiO2 layer.
[0104] Exemplarily, the current blocking layer is an AlGaN current blocking layer.
[0105] Exemplarily, step S23 may include:
[0106] In the first step, a current blocking layer is deposited.
[0107] A current blocking layer is deposited on the surface of the second semiconductor layer of the epitaxial structure using a plasma enhanced chemical vapor deposition (PECVD) device.
[0108] The second step is to perform graphic processing on the current blocking layer.
[0109] In the embodiment of the present disclosure, a through hole is etched on the current blocking layer by photolithography and wet etching.
[0110] S24. Making a transparent conductive layer on the surface of the epitaxial structure, wherein the transparent conductive layer covers the current blocking layer.
[0111] Figure 6 Schematic diagram of a light emitting diode manufacturing process provided by the embodiment of the present disclosure. Figure 6 The transparent conductive layer 500 is located on the second semiconductor layer 103 and covers the current blocking layer 400 . The transparent conductive layer 500 on the second semiconductor layer 103 is provided with a through hole.
[0112] In the embodiment of the present disclosure, the transparent conductive layer may be an ITO layer. ITO has excellent transparency and conductivity. It allows light to pass through while also conducting current to form an electrical connection.
[0113] Exemplarily, step S24 may include:
[0114] Depositing an ITO film; and patterning the ITO film to obtain an ITO conductive layer.
[0115] The ITO film may be formed by evaporation. Patterning the ITO film may include: spin coating photoresist; forming a mask pattern by exposure and development; and wet etching the ITO film under the protection of the mask pattern.
[0116] S25. Fabricate an electrode structure.
[0117] Figure 7 Schematic diagram of a light emitting diode manufacturing process provided by the embodiment of the present disclosure. Figure 7 The first electrode 201 is connected to the second semiconductor layer 103 through the through holes of the current blocking layer 400 and the transparent conductive layer 500 , and the second electrode 202 is connected to the first semiconductor layer 101 .
[0118] In the embodiment of the present disclosure, the first electrode and the second electrode may be manufactured by a sputtering process.
[0119] In the embodiment of the present disclosure, the first electrode and the second electrode may be a combination of one or more metal or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt and Au.
[0120] Exemplarily, the first electrode and the second electrode are stacked layers of Cr, Al, AlCu, Ti, Ni, Pt and Au.
[0121] S26, manufacturing a first passivation sublayer.
[0122] In the embodiment of the present disclosure, the first passivation sublayer may be SiAl x O y Layer, where both x and y are greater than 0.
[0123] Exemplarily, x=2, y=1.
[0124] In this implementation, SiAl x O y The chemical properties are stable, and the formed passivation sublayer has good surface density. As a buffer layer for the second passivation sublayer, it greatly improves the deposition quality of the subsequent growth of the second passivation sublayer and greatly improves the ability to isolate water vapor.
[0125] In other embodiments, the first passivation sublayer may also be other types of silicon aluminum oxide layers.
[0126] In the disclosed embodiment, the thickness of the first passivation sublayer may be 2.5 to 6 nm, which is neither too thin to reduce the ability to isolate water vapor nor too thick to make the overall thickness of the device too thick.
[0127] Exemplarily, the thickness of the first passivation sublayer is 4 nm or 5 nm.
[0128] In the embodiment of the present disclosure, the first passivation sublayer and the second passivation sublayer are manufactured by atomic layer deposition (ALD).
[0129] Exemplarily, step S26 may include:
[0130] The first step is to control the temperature of the reaction chamber so that the temperature of the substrate where the epitaxial structure is located is 90-110°C and the temperature of the inner wall of the reaction chamber is 110-130°C.
[0131] In the disclosed embodiment, the cavity temperature refers to the reaction cavity temperature.
[0132] Exemplarily, the temperature of the reaction chamber is controlled so that the temperature of the substrate where the epitaxial structure is located is 100°C and the temperature of the inner wall of the reaction chamber is 120°C.
[0133] In the disclosed embodiment, the cavity temperature of the reaction chamber is controlled so that during the manufacturing process, insufficient element reaction due to too low a temperature and device damage due to too high a temperature will not occur.
[0134] The second step is to introduce a silicon precursor. When the silicon precursor is introduced, the pulse time is 20 to 40 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds.
[0135] Wherein, the silicon precursor may be tetrabutyl silicate.
[0136] Among them, pulse time refers to the length of time that the silicon precursor is introduced into the reaction chamber; pulse time refers to the time required to purge the reaction chamber with an inert gas (such as nitrogen or argon) after each precursor pulse; waiting time refers to the waiting time after purging.
[0137] Exemplarily, a silicon precursor is introduced with a pulse time of 30 milliseconds, a purge time of 10 seconds, and a waiting time of 5 seconds.
[0138] The third step is to introduce an oxidative precursor. When the oxidative precursor is introduced, the pulse time is 40 to 60 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds.
[0139] The oxidative precursor may be H2O.
[0140] Exemplarily, the oxidative precursor is introduced with a pulse time of 50 milliseconds, a purge time of 10 seconds, and a waiting time of 5 seconds.
[0141] The fourth step is to introduce an aluminum source precursor. When the aluminum source precursor is introduced, the pulse time is 10 to 30 milliseconds, the purge time is 13 to 17 seconds, and the waiting time is 3 to 7 seconds.
[0142] Wherein, the aluminum source precursor may be trimethylaluminum.
[0143] Exemplarily, an aluminum source precursor is introduced with a pulse time of 20 milliseconds, a purge time of 15 seconds, and a waiting time of 5 seconds.
[0144] The fifth step is to introduce an oxidative precursor. When the oxidative precursor is introduced, the pulse time is 40 to 60 milliseconds, the purge time is 13 to 17 seconds, and the waiting time is 3 to 7 seconds.
[0145] Exemplarily, the oxidative precursor is introduced with a pulse time of 50 milliseconds, a purge time of 15 seconds, and a waiting time of 5 seconds.
[0146] In the embodiment of the present disclosure, a silicon source can be provided by introducing a silicon precursor, an oxygen source can be provided by introducing an oxidizing precursor, and an aluminum source precursor can be provided by introducing an aluminum source, and a silicon-aluminum oxide layer is generated by introducing the above materials. In the above-mentioned introduction process, a pulse time that is too short may result in incomplete reaction, affecting the uniformity and quality of the film, while a pulse time that is too long may result in overreaction or unnecessary material consumption; insufficient purge time may result in residues of precursors or reactants, affecting the purity of subsequent reactions and the quality of the film, while a purge time that is too long may slow down the entire deposition process and reduce production efficiency.
[0147] In the embodiment of the present disclosure, when the first passivation sublayer is produced, each precursor is periodically cyclically introduced with a cycle period of 8 to 12. This cycle will not cause the passivation layer to be too thick or the device to be too thick due to a too long cycle, nor will it cause insufficient airtightness due to a too short cycle.
[0148] Exemplarily, when the first passivation sub-layer is manufactured, each precursor is introduced in a periodic cycle, and the cycle period is 10.
[0149] The first passivation sub-layer is generated by repeatedly repeating the first to fifth steps.
[0150] S27, manufacturing a second passivation sublayer.
[0151] In the embodiment of the present disclosure, the second passivation sublayer may be a SiO2 layer.
[0152] In this implementation, SiO2 is an amorphous film that is dense, defect-free, and stable in nature, which is conducive to isolating water vapor.
[0153] In other embodiments, the second passivation sublayer may also be an oxide layer of other types of silicon.
[0154] In the disclosed embodiment, the thickness of the second passivation sublayer may be 5.6-8.5 nm, which is neither too thin to reduce the ability to isolate water vapor nor too thick to make the overall thickness of the device too thick.
[0155] Exemplarily, the thickness of the second passivation sublayer is 6 nm or 7 nm.
[0156] Exemplarily, step S27 may include:
[0157] The first step is to control the temperature of the reaction chamber so that the temperature of the substrate where the epitaxial structure is located is 90-110°C and the temperature of the inner wall of the reaction chamber is 110-130°C.
[0158] Exemplarily, the temperature of the reaction chamber is controlled so that the temperature of the substrate where the epitaxial structure is located is 100°C and the temperature of the inner wall of the reaction chamber is 120°C.
[0159] In the disclosed embodiment, the cavity temperature of the reaction chamber is controlled so that during the manufacturing process, insufficient element reaction due to too low a temperature and device damage due to too high a temperature will not occur.
[0160] The second step is to introduce a silicon precursor. When the silicon precursor is introduced, the pulse time is 20 to 40 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds.
[0161] Exemplarily, a silicon precursor is introduced with a pulse time of 30 milliseconds, a purge time of 10 seconds, and a waiting time of 5 seconds.
[0162] The third step is to introduce an oxidative precursor. When the oxidative precursor is introduced, the pulse time is 40 to 60 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds.
[0163] Exemplarily, when the oxidative precursor is introduced, the pulse time is 50 milliseconds, the purge time is 10 seconds, and the waiting time is 5 seconds.
[0164] In the disclosed embodiment, the introduction of a silicon precursor can provide a silicon source, the introduction of an oxidizing precursor can provide an oxygen source, and the introduction of the above materials can generate a silicon oxide layer. In the above introduction process, a pulse time that is too short may result in an incomplete reaction, affecting the uniformity and quality of the film, while a pulse time that is too long may result in an overreaction or unnecessary material consumption; insufficient purge time may result in the residue of precursors or reactants, affecting the purity of subsequent reactions and the quality of the film, while a purge time that is too long may slow down the entire deposition process and reduce production efficiency.
[0165] In the embodiment of the present disclosure, when the second passivation sublayer is produced, each precursor is periodically cyclically introduced with a cycle period of 28 to 32. This cycle will not cause the passivation layer to be too thick or the device to be too thick due to a too long cycle, nor will it cause insufficient airtightness due to a too short cycle.
[0166] Exemplarily, when the second passivation sub-layer is manufactured, each precursor is introduced in a periodic cycle, and the cycle period is 30.
[0167] The second passivation sub-layer is generated by repeatedly repeating the first to third steps.
[0168] S28, opening holes corresponding to the electrode structures on the first passivation sublayer and the second passivation sublayer.
[0169] In the disclosed embodiment, the passivation sublayer is opened by wet etching or dry etching.
[0170] The first electrode openings in the corresponding electrode structure are formed on the first passivation sublayer and the second passivation sublayer, and the second electrode openings in the corresponding electrode structure are formed on the first passivation sublayer and the second passivation sublayer.
[0171] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A light emitting diode, characterized in that: The light emitting diode comprises: an epitaxial structure (100), an electrode structure (200) and a passivation layer (300); The passivation layer (300) covers the epitaxial structure (100), the electrode structure (200) passes through the passivation layer (300) and is electrically connected to the epitaxial structure (100), the passivation layer (300) comprises a first passivation sublayer (301) and a second passivation sublayer (302) sequentially stacked on the epitaxial structure (100), the first passivation sublayer (301) is a silicon aluminum oxide layer, and the second passivation sublayer (302) is a silicon oxide layer.
2. The light emitting diode according to claim 1, characterized in that: The first passivation sublayer (301) is SiAl x O y Layer, where both x and y are greater than 0.
3. The light emitting diode according to claim 1, characterized in that: The second passivation sublayer (302) is a SiO2 layer.
4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The epitaxial structure (100) is provided with a step structure (1001) and a packaging groove (1002), wherein the step structure (1001) comprises a step top surface and a step bottom surface; and the passivation layer (300) covers the step bottom surface, the step top surface and the packaging groove (1002).
5. The light emitting diode according to any one of claims 1 to 3, characterized in that: The thickness of the first passivation sublayer (301) is 2.5-6 nm, and the thickness of the second passivation sublayer (302) is 5.6-8.5 nm.
6. A method for preparing a light emitting diode, characterized in that: The method comprises: fabricating epitaxial structures; Fabricating an electrode structure on the surface of the epitaxial structure; A passivation layer is manufactured, wherein the passivation layer covers the epitaxial structure, and the electrode structure is electrically connected to the epitaxial structure through the passivation layer. The passivation layer comprises a first passivation sublayer and a second passivation sublayer sequentially stacked on the epitaxial structure, wherein the first passivation sublayer is a silicon aluminum oxide layer, and the second passivation sublayer is a silicon oxide layer.
7. The method for preparing a light emitting diode according to claim 6, characterized in that: Producing the first passivation sublayer includes: Controlling the temperature of the reaction chamber so that the temperature of the substrate where the epitaxial structure is located is 90-110° C. and the temperature of the inner wall of the reaction chamber is 110-130° C.; A silicon precursor is introduced, wherein the pulse time is 20 to 40 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds; The oxidative precursor is introduced, wherein the pulse time is 40 to 60 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds; An aluminum source precursor is introduced, wherein the pulse time is 10 to 30 milliseconds, the purge time is 13 to 17 seconds, and the waiting time is 3 to 7 seconds; The oxidative precursor is introduced again. When the oxidative precursor is introduced, the pulse time is 40 to 60 milliseconds, the purge time is 13 to 17 seconds, and the waiting time is 3 to 7 seconds.
8. The method for preparing a light emitting diode according to claim 6, characterized in that: The method comprises: manufacturing the second passivation sublayer, comprising: Controlling the temperature of the reaction chamber so that the temperature of the substrate where the epitaxial structure is located is 90-110° C. and the temperature of the inner wall of the reaction chamber is 110-130° C.; A silicon precursor is introduced, wherein the pulse time is 20 to 40 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds; An oxidative precursor is introduced, wherein the pulse time is 40 to 60 milliseconds, the purge time is 8 to 12 seconds, and the waiting time is 3 to 7 seconds.
9. The method for preparing a light emitting diode according to claim 7, characterized in that: When the first passivation sublayer is produced, each precursor is introduced periodically and cyclically, and the cycle period is 8 to 12.
10. The method for preparing a light emitting diode according to claim 8, characterized in that: When the second passivation sub-layer is produced, each precursor is introduced periodically and cyclically, and the cycle period is 28 to 32.