Impurity removal method and single crystal furnace
By using a single crystal furnace to remove impurities during the single crystal silicon drawing process, the electric field is used to adsorb and enrich impurities, the problem of impurities entering the crystal is solved, and the quality and life of the crystal and photovoltaic cells are improved.
Patent Information
- Application Number
- CN202411707601.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-02-28
AI Technical Summary
During the drawing process of single crystal silicon, impurity elements enter the crystal through the solid-liquid interface, resulting in a decrease in crystal quality, which in turn affects the efficiency and life of the photovoltaic cell.
A single crystal furnace is designed to gradually adsorb impurities to the inner wall of the crucible by setting the first and second impurity removal stages during the crystal drawing process, and to enrich the impurities to the tail of the crystal during the finishing stage, and then cut off the impurities to improve the crystal purity.
It effectively reduces the impurity content in the drawn crystal, improves the quality of the crystal and the efficiency of the photovoltaic cell, and extends the service life of the cell.
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to the technical field of single crystal manufacturing, and in particular to an impurity removal method and a single crystal furnace. Background Art
[0002] At present, with the gradual depletion of fossil energy, photovoltaic cells are increasingly used as a new energy alternative. Photovoltaic cells are devices that convert sunlight into electrical energy. Photovoltaic cells use the principle of photovoltaics to generate carriers, and then use electrodes to lead out the carriers, which is conducive to the effective use of electrical energy. As a basic material for photovoltaic power generation, single-crystal silicon wafers have a wide market demand. The preparation process of single-crystal silicon materials is mainly based on the Czochralski process (CZ), which uses the Czochralski process to refine polycrystalline silicon raw materials into single-crystal silicon. The process of generating rod-shaped single-crystal silicon crystals in the Czochralski process is divided into the steps of loading, melting, adding, temperature adjustment, seeding, shoulder release, shoulder rotation, equal diameter, and finishing to obtain single-crystal silicon rods.
[0003] However, in the crystal pulling step, although the silicon material has extremely high purity, the on-site environment involves thermal fields and complex material environments that will introduce impurities. These impurity elements will exist in the silicon liquid in ionic and complex states, resulting in these impurity elements entering the pulled crystal through the solid-liquid interface during the crystal pulling process, reducing the quality of the pulled crystal. As the crystal is processed into silicon wafers, these impurity elements will eventually form various defects in the silicon wafers, greatly reducing battery efficiency and service life. Summary of the invention
[0004] The embodiments of the present disclosure provide an impurity removal method and a single crystal furnace, which are at least beneficial for purifying silicon materials and improving the quality of pulled crystals.
[0005] According to some embodiments of the present disclosure, on the one hand, an impurity removal method is provided, comprising: providing a single crystal furnace, the single crystal furnace comprising a pulling head, a pulling rope with a seed crystal at one end, a crucible, and a crucible side located below the crucible and insulated from the crucible, and the pulling head and the pulling rope are insulated; detecting the real-time position of the seed crystal in the single crystal furnace, and if the real-time position is a preset position, controlling the single crystal furnace to be in a first impurity removal stage, the first impurity removal stage comprising: controlling the seed crystal to have a first voltage and the crucible side to have a second voltage, the first voltage being greater than the second voltage, and using the seed crystal to energize the silicon material in the crucible, so that The silicon material, the crucible and the crucible side constitute a capacitor to form a first electric field, and cause the inner wall of the crucible to adsorb positively charged impurities in the silicon material during the crystal pulling stage of the single crystal furnace; when it is detected that the crystal pulling stage ends and enters the closing stage, the single crystal furnace is controlled to be in a second impurity removal stage, and the second impurity removal stage includes: controlling the seed crystal to have a third voltage and the crucible side to have a fourth voltage, the third voltage is less than the fourth voltage, so that the silicon material, the crucible and the crucible side constitute a capacitor to form a second electric field, causing the impurities adsorbed on the inner wall of the crucible to be enriched at the tail of the pulled crystal; and removing the impurities enriched at the tail of the pulled crystal.
[0006] In some embodiments, the single crystal furnace further includes a guide tube, and along the height direction of the single crystal furnace, the preset position is a distance between the seed crystal and the bottom surface of the guide tube of any value between 50 mm and 800 mm.
[0007] In some embodiments, the first impurity removal stage further includes: introducing hydrogen into the single crystal furnace, so that the impurities in the silicon material with positive charge are aggregated into ion clusters under the induction of the hydrogen and adsorbed on the inner wall of the crucible.
[0008] In some embodiments, the silicon material is in a molten liquid state during the crystal pulling stage, and the center temperature of the liquid surface of the silicon material is controlled to be 1400° C. to 1450° C.
[0009] In some embodiments, as the crystal pulling process in the single crystal furnace continues, the crystal pulling stage in the first impurity removal stage at least includes in sequence: a first equal-diameter stage, a second equal-diameter stage, and a third equal-diameter stage, and the voltage value of at least one of the first voltage and the second voltage in the first equal-diameter stage, the second equal-diameter stage, and the third equal-diameter stage changes; wherein the difference between the voltage values of the first voltage and the second voltage in the first equal-diameter stage is a first pressure difference, the difference between the voltage values of the first voltage and the second voltage in the second equal-diameter stage is a second pressure difference, and the difference between the voltage values of the first voltage and the second voltage in the third equal-diameter stage is a third pressure difference, the first pressure difference is smaller than the second pressure difference, and the second pressure difference is smaller than the third pressure difference.
[0010] In some embodiments, the first voltage difference is 5V to 10V, the second voltage difference is 10V to 20V, and the third voltage difference is 20V to 30V.
[0011] In some embodiments, the first equal-diameter stage is a stage in which the equal-diameter length of the pulled crystal increases from a first preset value to a second preset value; the second equal-diameter stage is a stage in which the equal-diameter length of the pulled crystal increases from the second preset value to a third preset value; the third equal-diameter stage is a stage in which the equal-diameter length of the pulled crystal increases from the third preset value to a fourth preset value; wherein the difference between the first preset value and the second preset value is smaller than the difference between the third preset value and the second preset value, and the difference between the third preset value and the second preset value is smaller than the difference between the fourth preset value and the third preset value.
[0012] In some embodiments, the difference between the voltage values of the first voltage and the second voltage in the first de-doping stage is a fourth voltage difference; the difference between the voltage values of the third voltage and the fourth voltage in the second de-doping stage is a fifth voltage difference; and the fifth voltage difference is greater than the fourth voltage difference.
[0013] In some embodiments, the fourth voltage difference is 5V to 30V, and the fifth voltage difference is 40V to 60V.
[0014] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a single crystal furnace, comprising: a pulling head, a pulling rope with a seed crystal provided at one end, a crucible, and a crucible side located below the crucible and insulated from the crucible, and the pulling head and the pulling rope are insulated; a monitoring device is configured to monitor the real-time position of the seed crystal in the single crystal furnace, and to monitor the crystal pulling stage and the finishing stage; an impurity removal device is configured to enable the single crystal furnace to have a first impurity removal stage and a second impurity removal stage in the process of preparing a single crystal; wherein, in the first impurity removal stage, the impurity removal device controls the seed crystal to have a first voltage and the crucible side to have a second voltage, and the first impurity removal stage a voltage greater than the second voltage, and the silicon material in the crucible is electrified by means of the seed crystal, so that the silicon material, the crucible and the crucible side form a capacitor to form a first electric field, and the inner wall of the crucible is caused to adsorb positively charged impurities in the silicon material during the crystal pulling stage; the impurity removal equipment controls the seed crystal to have a third voltage and the crucible side to have a fourth voltage during the second impurity removal stage, and the third voltage is less than the fourth voltage, and the silicon material in the crucible is electrified by means of the seed crystal, so that the silicon material, the crucible and the crucible side form a capacitor to form a second electric field, and the impurities adsorbed on the inner wall of the crucible are enriched at the tail of the pulled crystal.
[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:
[0016] First, based on the existing single crystal furnace, the process of preparing the crystal is designed to include at least a continuous first impurity removal stage and a second impurity removal stage. In the first impurity removal stage, the seed crystal is first controlled to have a first voltage and the crucible side is controlled to have a second voltage to form a first electric field at the crucible, so that the impurities in the silicon material are gradually approached to the inner wall of the crucible under the action of the first electric field, thereby reducing the impurity concentration at the liquid surface of the molten silicon material in the crystal pulling stage, so as to further reduce the impurity content in the pulled crystal, thereby facilitating the improvement of the quality of the pulled crystal. Then, in the second impurity removal stage, the seed crystal is controlled to have a third voltage and the crucible side is controlled to have a fourth voltage to form a second electric field at the crucible, so that the impurities in the silicon material are caused to migrate from the inner wall of the crucible to the tail of the pulled crystal under the action of the second electric field, thereby facilitating the improvement of the purity of the remaining silicon material and preparing for the next crystal pulling.
[0017] Secondly, when it is detected that the real-time position of the seed crystal in the single crystal furnace is the preset position, the single crystal furnace is controlled to be in the first impurity removal stage. At this time, the seed crystal is descending and the crystal pulling has not yet begun. The seed crystal is controlled in advance to have a first voltage and the crucible side to have a second voltage, so that the impurities in the silicon material are close to the inner wall of the crucible in advance, to ensure that when the crystal pulling stage begins, the impurity concentration at the liquid surface of the molten silicon material has been reduced to the expected requirement, thereby further ensuring the quality of the head of the pulled crystal. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0019] Figure 1 A first flow chart of a method for removing impurities provided in one embodiment of the present disclosure;
[0020] Figure 2 A schematic diagram of a partial cross-sectional structure of a single crystal furnace in a method for removing impurities provided in one embodiment of the present disclosure;
[0021] Figure 3 A second flow chart of the impurity removal method provided in one embodiment of the present disclosure;
[0022] Figure 4 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible ridge designed in the first equal diameter stage in the impurity removal method provided in an embodiment of the present disclosure;
[0023] Figure 5 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible ridge designed in the second equal diameter stage in the impurity removal method provided in one embodiment of the present disclosure;
[0024] Figure 6 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible ridge designed in the third equal diameter stage in the impurity removal method provided in an embodiment of the present disclosure;
[0025] Figure 7 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible ridge designed for the first impurity removal stage in the impurity removal method provided in one embodiment of the present disclosure;
[0026] Figure 8 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible side designed for the second impurity removal stage in the impurity removal method provided in one embodiment of the present disclosure. DETAILED DESCRIPTION
[0027] As can be seen from the background technology, the purity of silicon liquid and the quality of pulled crystals need to be improved.
[0028] According to analysis, in the process of pulling single crystal silicon by the Czochralski method, due to the segregation of elements in the silicon material, some impurities will exist at the crystallization liquid surface, so as the crystal pulling progresses, the impurities will enter the pulled crystal. At the end of the crystal pulling step, due to the continuous enrichment of impurities at the crystallization liquid surface, as the crystal pulling time increases, the quality of the pulled crystal becomes worse and worse. Moreover, at the end of the crystal pulling step, due to the excessive enrichment of impurities at the tail of the pulled crystal, the resistivity is difficult to control accurately, and even the tail is scrapped due to unqualified resistivity.
[0029] The present disclosure provides a method for removing impurities and a single crystal furnace. In the method for removing impurities, first, based on the existing single crystal furnace, the process of preparing the crystal is designed to include at least a first and a second continuous stage of removing impurities. In the first stage of removing impurities, the seed crystal is first controlled to have a first voltage and the crucible side is controlled to have a second voltage to form a first electric field at the crucible, so that the impurities in the silicon material are gradually approached to the inner wall of the crucible under the action of the first electric field, so that the impurity concentration at the liquid surface of the molten silicon material in the crystal pulling stage can be reduced, so as to further reduce the impurity content in the pulled crystal, which is beneficial to improve the quality of the pulled crystal. Then, in the second stage of removing impurities, the seed crystal is controlled to have a third voltage and the crucible side is controlled to have a fourth voltage to form a second electric field at the crucible, so that the impurities in the silicon material are caused to migrate from the inner wall of the crucible to the tail of the pulled crystal under the action of the second electric field, so as to improve the purity of the remaining silicon material and prepare for the next crystal pulling. Secondly, when it is detected that the real-time position of the seed crystal in the single crystal furnace is the preset position, the single crystal furnace is controlled to be in the first impurity removal stage. At this time, the seed crystal is descending and the crystal pulling has not yet begun. The seed crystal is controlled in advance to have a first voltage and the crucible side to have a second voltage, so that the impurities in the silicon material are close to the inner wall of the crucible in advance, to ensure that when the crystal pulling stage begins, the impurity concentration at the liquid surface of the molten silicon material has been reduced to the expected requirement, thereby further ensuring the quality of the head of the pulled crystal.
[0030] In the description of the embodiments of the present disclosure, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present disclosure, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.
[0031] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0032] In the description of the embodiments of the present disclosure, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0033] In the description of the embodiments of the present disclosure, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).
[0034] In the description of the embodiments of the present disclosure, the orientations or positional relationships indicated by technical terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description. They do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the embodiments of the present disclosure.
[0035] In the description of the embodiments of the present disclosure, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.
[0036] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of the layers are magnified for better understanding and ease of description. When describing a component (such as a layer, a film, a region or a substrate) on another component or on the surface of another component, the component may be "directly" located on the surface of the other component, or a third component may be present between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.
[0037] In the description of the embodiments of the present disclosure, when a component "includes" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, a film, a region, or a plate is referred to as being "on / located on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may exist in between. In addition, when a component such as a layer, a film, a region, a plate, etc. is "directly located on" another component, or when a component such as a layer, a film, a region, a plate, etc. is located on the surface of another component, it means that no other components are located in between.
[0038] The terms used in the description of the various embodiments described herein are only used to describe specific embodiments and are not intended to be limiting. As used in the description of the various embodiments described and in the appended claims, "the components" are also intended to include plural forms unless the context clearly indicates otherwise. Among them, components include components such as layers, films, regions, or plates.
[0039] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.
[0040] An embodiment of the present disclosure provides an impurity removal method, which will be described in detail below with reference to the accompanying drawings.
[0041] Combined with reference Figure 1 and Figure 2 , Figure 1 A first flow chart of a method for removing impurities provided in an embodiment of the present disclosure is shown in FIG. Figure 2 A partial cross-sectional structural schematic diagram of a single crystal furnace in a doping method provided in an embodiment of the present disclosure, wherein the doping method comprises at least the following steps:
[0042] S1: Provide a single crystal furnace 100, which includes a pulling head (not shown in the figure), a pulling rope 102 with a seed crystal 101 at one end, a crucible 103, and a crucible side 104 located below the crucible and insulated from the crucible 103, and the pulling head and the pulling rope 102 are insulated.
[0043] S2: Detect the real-time position of the seed crystal 101 in the single crystal furnace 100. If the real-time position is the preset position, control the single crystal furnace 100 to be in the first impurity removal stage. The first impurity removal stage includes: controlling the seed crystal 101 to have a first voltage U1 and the crucible side 104 to have a second voltage U2, wherein the first voltage U1 is greater than the second voltage U2, and the silicon material 105 in the crucible 103 is energized by means of the seed crystal 101, so that the silicon material 105, the crucible 103 and the crucible side 104 form a capacitor to form a first electric field, and promote the inner wall of the crucible 103 to absorb positively charged impurities in the silicon material 105 during the crystal pulling stage of the single crystal furnace 100.
[0044] S3: When it is detected that the crystal pulling stage ends and enters the finishing stage, the single crystal furnace 100 is controlled to be in the second impurity removal stage. The second impurity removal stage includes: controlling the seed crystal 101 to have a third voltage U3 and the crucible side 104 to have a fourth voltage U4, the third voltage U3 is less than the fourth voltage U4, so that the silicon material 105, the crucible 103 and the crucible side 104 form a capacitor to form a second electric field, so as to cause the impurities adsorbed on the inner wall of the crucible 103 to be enriched at the tail of the pulled crystal.
[0045] S4: Cutting off impurities enriched in the tail of the pulled crystal.
[0046] It is worth noting that, based on the existing single crystal furnace 100, the process of preparing crystals is designed to include at least a continuous first impurity removal stage and a second impurity removal stage. In the first impurity removal stage, the seed crystal 101 is first controlled to have a first voltage U1 and the crucible side 104 is controlled to have a second voltage U2 to form a first electric field at the crucible 103, so that the impurities in the silicon material 105 are gradually approached to the inner wall of the crucible 103 under the action of the first electric field and are adsorbed on the inner wall of the crucible 103, thereby reducing the impurity concentration at the liquid surface of the molten silicon material 105 in the crystal pulling stage, so as to further reduce the impurity content in the pulled crystal, which is beneficial to improving the quality of the pulled crystal. Then, in the first impurity removal stage, the seed crystal 101 is controlled to have a third voltage U3 and the crucible side 104 is controlled to have a fourth voltage U4 to form a second electric field at the crucible 103, so that the impurities in the silicon material 105 migrate from the inner wall of the crucible 103 to the tail of the pulled crystal under the action of the second electric field, so that the impurities are completely separated from the silicon material 105, which is conducive to improving the purity of the remaining silicon material 105, that is, to purify the silicon material 105 and prepare for the next crystal pulling. In addition, for the impurities enriched at the tail of the pulled crystal, they can be cut off and reused as downgraded silicon material.
[0047] Among them, the first voltage U1 is greater than the second voltage U2, so that a first electric field is formed in the crucible 103 from the silicon material 105 to the crucible side 104, which promotes the positively charged impurities in the silicon material 105 to approach the inner wall of the crucible 103, thereby achieving the effect of adsorbing impurities. It is worth emphasizing that the first impurity removal stage in step S2 includes at least a crystal pulling stage. In the crystal pulling stage, the silicon material 105 contained in the crucible 103 is in a molten liquid state. In other words, the silicon material 105 at this time can be regarded as silicon liquid. Under the action of the first electric field, the electric field force on the positively charged impurities in the silicon material 105 is greater than the force formed by the convection inside the silicon liquid, thereby achieving the adsorption effect of the inner wall of the crucible 103 on the positively charged impurities in the silicon material 105, so as to improve the quality of the crystal pulled in the first impurity removal stage. In other words, in the crystal pulling stage, the first electric field is used to synchronously realize the impurity removal work at the liquid surface of the molten silicon liquid, so as to improve the quality of the pulled crystal in real time.
[0048] The third voltage U3 is less than the fourth voltage U4, thereby forming a second electric field in the crucible 103 that is directed from the crucible side 104 toward the silicon material 105. In other words, the electric field direction of the second electric field is opposite to that of the first electric field, so that the positively charged impurities originally enriched on the inner wall of the crucible 103 are enriched at the tail of the pulled crystal, so as to improve the purity of the silicon material 105 remaining in the crucible 103.
[0049] It can be seen that in order to form the first electric field and the second electric field with similar electric field directions, it is only necessary that the first voltage U1 is greater than the second voltage U2, and the third voltage U3 is less than the fourth voltage U4. As for whether the voltage values of the first voltage U1, the second voltage U2, the third voltage U3 and the fourth voltage U4 are positive or negative compared to the zero level, they can be selected according to actual conditions.
[0050] It should be noted that the impurity removal method provided in an embodiment of the present disclosure not only realizes the impurity removal of the crystals pulled in the first impurity removal stage, that is, significantly reduces the impurity concentration in the crystals pulled in the first impurity removal stage, but also realizes the impurity removal of the silicon material 105 remaining in the crucible 103 after the second impurity removal stage, that is, significantly reduces the impurity concentration in the silicon material 105 remaining in the crucible 103 after the second impurity removal stage.
[0051] It is worth noting that step S2 and step S3 can be seamlessly connected in time. When step S3 detects that the crystal pulling stage ends and enters the final stage, the seed crystal 101 is directly controlled to change from the first voltage U1 to the third voltage U3, and the crucible 104 is directly controlled to change from the second voltage U2 to the fourth voltage U4, so as to match the continuous progress of the crystal pulling step. The crystal pulling step includes the crystal pulling stage and the final stage.
[0052] In addition, in step S2, when it is detected that the real-time position of the seed crystal 101 in the single crystal furnace 100 is the preset position, the single crystal furnace 100 is controlled to be in the first impurity removal stage. At this time, the seed crystal 101 is descending and the crystal pulling has not yet started. The seed crystal 101 is controlled in advance to have a first voltage U1 and the crucible side 104 is controlled to have a second voltage U2, so that the impurities in the silicon material 105 are close to the inner wall of the crucible 103 in advance, so as to ensure that when the crystal pulling stage begins, the impurity concentration at the liquid surface of the molten silicon material 105 has been reduced to the expected requirement, thereby further ensuring the quality of the head of the pulled crystal.
[0053] It is worth emphasizing that, while controlling the seed crystal 101 to have the first voltage U1 or the third voltage U3, and the crucible side 104 to have the second voltage U2 or the fourth voltage U4, the crucible side 104 is designed to be insulated from the crucible 103, and the pulling head and the pulling rope 102 are insulated, which is beneficial to avoid the seed crystal 101 and the crucible side 104 from forming a passage with the furnace body 110 of the single crystal furnace 100 after being energized, thereby affecting the first electric field formed in the first impurity removal stage and the second electric field formed in the second impurity removal stage on the removal effect of impurities in the silicon material 105. Among them, the pulling rope 102 is in electrical contact with the seed crystal 101.
[0054] In some cases, the pulled crystal is a pulled N-type single crystal, and thus the positively charged impurities in the silicon material 105 have a greater impact on the quality of the pulled crystal. Therefore, designing a first electric field with a direction from the silicon material 105 to the crucible side 104 and a second electric field with a direction from the crucible side 104 to the silicon material 105 is beneficial to reducing the impurity concentration in the pulled crystal and reducing the impurity concentration in the remaining silicon material 105.
[0055] In some embodiments, the impurity removal method provided in an embodiment of the present disclosure is used to improve the quality of the pulled crystals, such as increasing the minority carrier lifetime of the pulled crystals by about 1000us; it is also beneficial to improve the yield of the pulled crystals, such as increasing the yield of the pulled crystals by about 10kg / day, that is, the yield of the pulled crystals increases by about 10kg every day; it is also beneficial to reduce the risk of wire breaks caused by impurity enrichment during the preparation of the crystals, for example, the wire break rate during the preparation of the crystals is reduced by about 0.2; it is also beneficial to improve the photoelectric conversion efficiency of the battery cells formed based on the pulled high-quality crystals, for example, the photoelectric conversion efficiency of the battery cells is increased by about 0.04%.
[0056] Each step of the impurity removal method provided in one embodiment of the present disclosure will be described in detail below.
[0057] In some embodiments, the single crystal furnace 100 further includes a guide tube (not shown in the figure), and along the height direction of the single crystal furnace 100, the preset position is that the distance between the seed crystal 101 and the bottom surface of the guide tube is any value between 50 mm and 800 mm. For example, the preset position can be that the distance between the seed crystal 101 and the bottom surface of the guide tube is 100 mm, 200 mm, 300 mm, 400 mm, 500 mm, 600 mm or 700 mm, etc.
[0058] It should be noted that the guide tube can also be called an external guide, and the bottom surface of the guide tube can be regarded as the seed crystal solidification site.
[0059] It is worth noting that before the seed crystal 101 is used to pull the crystal from the molten silicon material 105, the seed crystal 101 is gradually lowered from the head area of the furnace body 110 of the single crystal furnace 100 to below the liquid surface of the molten silicon material 105 by means of the pulling head and the pulling rope 102. In the stage of the seed crystal 101 descending, a preset position is set. When it is detected that the seed crystal 101 descends to the preset position, the seed crystal 101 is controlled to have a first voltage U1 and the crucible side 104 is controlled to have a second voltage U2 to form a first electric field, which is beneficial to promote the impurities in the silicon material 105 to approach the inner wall of the crucible 103 in advance before the crystal is pulled, so as to ensure that the impurity concentration at the liquid surface of the molten silicon material 105 has been reduced to the expected requirement when the crystal pulling stage begins, thereby further ensuring the quality of the head of the pulled crystal.
[0060] On this basis, the preset position is designed so that the distance between the seed crystal 101 and the bottom surface of the guide tube is any value between 50 mm and 800 mm. On the one hand, it can avoid the phenomenon that when the distance between the seed crystal 101 and the bottom surface of the guide tube is too large, the seed crystal 101 and the crucible side 104 are energized when the silicon material 105 is not yet in a molten state. At this time, the silicon material 105 has a stronger ability to block the migration of impurities inside it, that is, it can avoid the premature formation of the first electric field and avoid unnecessary power loss. On the other hand, it is helpful to avoid the phenomenon that when the distance between the seed crystal 101 and the bottom surface of the guide tube is too small, when the step of pulling the crystal is about to begin, the seed crystal 101 and the crucible side 104 are only energized for a short time, and sufficient time is not reserved for the impurity concentration at the liquid surface of the molten silicon material 105 to be reduced to the expected requirement, that is, it can avoid the late formation of the first electric field and avoid the reduction in the quality of the head of the pulled crystal.
[0061] In some embodiments, reference Figure 3 , Figure 3The second flow diagram of the impurity removal method provided in one embodiment of the present disclosure, the first impurity removal stage may also include step S11: hydrogen is introduced into the single crystal furnace 100, and the positively charged impurities in the silicon material 105 are gathered into ion clusters under the induction of hydrogen, and adsorbed on the inner wall of the crucible 103. In this way, it is beneficial to use hydrogen as a reducing agent to induce the positively charged impurities in the silicon material 105 to gather into ion clusters, so that they are more quickly adsorbed on the inner wall of the crucible 103, that is, the bottom of the silicon liquid, so as to further reduce the impurity concentration at the liquid surface of the molten silicon material 105, so as to further improve the quality of the pulled crystal; in addition, part of the hydrogen elements in the hydrogen can also enter the pulled crystal as the crystal pulling stage proceeds, so as to reduce the surface recombination of the pulled crystal and further improve the life of the minority carriers.
[0062] In some cases, hydrogen is introduced at least during the entire crystal pulling stage.
[0063] In some cases, the gas flow rate of the introduced hydrogen gas may be 1 slpm-20 slpm, for example, the gas flow rate of the introduced hydrogen gas may be 5 slpm, 8 slpm, 10 slpm, 12 slpm, 15 slpm, 16 slpm or 18 slpm, etc.
[0064] In some cases, the hydrogen gas may be introduced directly into the silicon liquid through a pipe dedicated for introducing hydrogen gas, or may be introduced through an existing pipe for introducing argon gas in the single crystal furnace 100 .
[0065] In some embodiments, reference Figure 2 In the crystal pulling stage, the silicon material 105 is in a molten liquid state, and the temperature of the center of the liquid surface of the silicon material 105 is controlled to be 1400° C. to 1450° C. It is worth noting that in the crystal pulling stage, the temperature of the center of the liquid surface of the silicon material 105 is almost unchanged, generally fluctuating between 1400° C. and 1450° C. In other words, in the crystal pulling stage, the temperature of the center of the liquid surface of the silicon material 105 can be roughly regarded as a constant temperature.
[0066] In some examples, during the crystal pulling stage, the center temperature of the liquid surface of the silicon material 105 can be 1402°C, 1405°C, 1410°C, 1413°C, 1415°C, 1418°C, 1420°C, 1421°C, 1425°C, 1427°C, 1430°C, 1432°C, 1435°C, 1436°C or 1439°C, etc.
[0067] In some embodiments, the pulling rope 102 is in electrical contact with the seed crystal 101 ; the step of controlling the seed crystal 101 to have a first voltage U1 includes: controlling the pulling rope 102 to have a first voltage U1 .
[0068] In some embodiments, continue to refer to Figure 2The single crystal furnace 100 may further include a crucible shaft 106 located below the crucible 103 and in electrical contact with the crucible side 104; the step of controlling the crucible side 104 to have a second voltage U2 includes: controlling the crucible shaft 106 to have a second voltage U2. In other embodiments, the crucible side may also be provided with a second voltage in other ways.
[0069] In some embodiments, the material of the pull rope 102 may be an inert metal that can withstand temperatures above 1500° C. For example, the material of the pull rope 102 may be at least one of inert metals such as tungsten, tantalum, niobium, or titanium.
[0070] The first impurity removal stage is described in detail below.
[0071] In some embodiments, reference Figures 4 to 6 As the crystal pulling process in the single crystal furnace 100 continues, the crystal pulling stage in the first impurity removal stage at least includes: a first equal diameter stage, a second equal diameter stage and a third equal diameter stage in sequence, and the voltage value of at least one of the first voltage U1 and the second voltage U2 in the first equal diameter stage, the second equal diameter stage and the third equal diameter stage changes. Among them, the difference between the voltage values of the first voltage U1 and the second voltage U2 in the first equal diameter stage is the first pressure difference ΔU1, the difference between the voltage values of the first voltage U1 and the second voltage U2 in the second equal diameter stage is the second pressure difference ΔU2, and the difference between the voltage values of the first voltage U1 and the second voltage U2 in the third equal diameter stage is the third pressure difference ΔU3, the first pressure difference ΔU1 is less than the second pressure difference ΔU2, and the second pressure difference ΔU2 is less than the third pressure difference ΔU3.
[0072] in, Figure 4 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible ridge designed in the first equal diameter stage in the impurity removal method provided in an embodiment of the present disclosure, Figure 5 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible ridge designed in the second equal diameter stage in the impurity removal method provided in an embodiment of the present disclosure, Figure 6 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible rib designed in the third equal diameter stage in the impurity removal method provided in one embodiment of the present disclosure.
[0073] In other words, the first equal diameter stage, the second equal diameter stage and the third equal diameter stage each correspond to a set of first voltage U1 and second voltage U2, and the voltage values of the first voltage U1 corresponding to different equal diameter stages can be the same or different, and the voltage values of the second voltage U2 corresponding to different equal diameter stages can be the same or different. However, it is necessary to satisfy that the difference between the voltage values of the first voltage U1 and the second voltage U2 corresponding to different equal diameter stages is different.
[0074] It is worth noting that the first electric field formed by the first voltage U1 and the second voltage U2 in the first equal-diameter stage is called the first sub-electric field, the first electric field formed by the first voltage U1 and the second voltage U2 in the second equal-diameter stage is called the second sub-electric field, and the first electric field formed by the first voltage U1 and the second voltage U2 in the third equal-diameter stage is called the third sub-electric field. Since the thickness of the crucible 103 is unchanged in the three equal-diameter stages, the first pressure difference ΔU1 is designed to be smaller than the second pressure difference ΔU2, and the second pressure difference ΔU2 is smaller than the third pressure difference ΔU3, then the electric field strength of the first sub-electric field is smaller than the electric field strength of the second sub-electric field, and the electric field strength of the second sub-electric field is smaller than the electric field strength of the third sub-electric field. In other words, the electric field strength of the first electric field composed of the first voltage U1 and the second voltage U2 in the first equal-diameter stage, the second equal-diameter stage and the third equal-diameter stage increases successively, which is beneficial to gradually improve the adsorption capacity of the inner wall of the crucible 103 to impurities in the silicon material 105, thereby further improving the quality of the pulled crystal; in addition, with the gradual progress of the crystal pulling stage, the impurity content enriched on the inner wall of the crucible 103 gradually increases. The electric field strength of the first electric field in the first equal-diameter stage, the second equal-diameter stage and the third equal-diameter stage is designed to increase successively, which is beneficial to ensure that enough impurities can be firmly adsorbed on the inner wall of the crucible 103, and ensure that the impurity concentration at the liquid surface of the molten silicon material 105 is sufficiently low.
[0075] In some examples, the first voltage difference ΔU1 may be 5V to 10V, for example, the first voltage difference ΔU1 may be 6V, 7V, 8V or 9V, etc.; the second voltage difference ΔU2 may be 10V to 20V, for example, the second voltage difference ΔU2 may be 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V or 19V, etc.; the third voltage difference ΔU3 may be 20V to 30V, for example, the third voltage difference ΔU3 may be 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V or 29V, etc.
[0076] In some embodiments, the first equal-diameter stage is a stage in which the equal-diameter length of the pulled crystal increases from the second preset value to the third preset value; the second equal-diameter stage is a stage in which the equal-diameter length of the pulled crystal increases from the third preset value to the fourth preset value; wherein the difference between the first preset value and the second preset value is smaller than the difference between the third preset value and the second preset value, and the difference between the third preset value and the second preset value is smaller than the difference between the fourth preset value and the third preset value.
[0077] It is worth noting that the difference between the first preset value and the second preset value is the growth length of the crystal pulled in the first equal diameter stage; the difference between the third preset value and the second preset value is the growth length of the crystal pulled in the second equal diameter stage; the difference between the fourth preset value and the third preset value is the growth length of the crystal pulled in the third equal diameter stage. Based on this, the difference between the first preset value and the second preset value is designed to be smaller than the difference between the third preset value and the second preset value, and the difference between the third preset value and the second preset value is smaller than the difference between the fourth preset value and the third preset value. Then, the growth length of the crystal pulled in the first equal diameter stage, the second equal diameter stage and the third equal diameter stage increases successively, which is conducive to gradually improving the adsorption capacity of the inner wall of the crucible 103 for impurities in the silicon material 105, while gradually improving the durability of the pulled crystal, which is conducive to the efficient production of high-quality crystals.
[0078] In one example, the first preset value may be 1mm, the second preset value may be 1000mm, the third preset value may be 3000mm, and the fourth preset value may be 6000mm. Thus, when the equal diameter length of the pulled single crystal increases from 1mm to 1000mm, the difference between the voltage values of the first voltage U1 and the second voltage U2 is controlled to be 5V to 10V; when the equal diameter length of the pulled single crystal increases from 1000mm to 3000mm, the difference between the voltage values of the first voltage U1 and the second voltage U2 is controlled to be 10V to 20V; when the equal diameter length of the pulled single crystal increases from 3000mm to 6000mm, the difference between the voltage values of the first voltage U1 and the second voltage U2 is controlled to be 20V to 30V.
[0079] In some embodiments, the duration of power-on in the first equal diameter stage is shorter than that in the second equal diameter stage, and the duration of power-on in the second equal diameter stage is shorter than that in the third equal diameter stage. This is conducive to gradually increasing the time of pulling the crystal under the stable first electric field, avoiding the adverse effect of too frequent changes in the first electric field on the pulled crystal, and is also conducive to the efficiency of crystal pulling.
[0080] In the above various embodiments, the crystal pulling speed in the crystal pulling stage can be 100 mm / h to 110 mm / h. For example, the crystal pulling speed in the crystal pulling stage can be 101 mm / h, 102 mm / h, 103 mm / h, 104 mm / h, 105 mm / h, 106 mm / h, 107 mm / h, 108 mm / h or 109 mm / h, etc.
[0081] In the above various embodiments, the power-on time of the first equal diameter stage can be 9h~10h, for example, it can be 9.08h, 9.2h, 9.3h, 9.4h, 9.42h, 9.5h, 9.6h, 9.7h, 9.8h, 9.9h or 9.99h; the power-on time of the second equal diameter stage can be 18h~20h, for example, it can be 18.2h, 18.5h, 18.8 h, 18.9h, 19h, 19.2h, 19.5h, 19.6h or 19.8h, etc.; the power-on time of the third equal-diameter stage can be 27h to 30h, for example, 27.2h, 27.5h, 27.8h, 28h, 28.2h, 28.3h, 28.5h, 28.8h, 29h, 29.3h, 29.5h, 29.7h or 29.8h, etc.
[0082] In the above-mentioned various embodiments, the thickness of the crucible 103 along the direction perpendicular to the inner wall of the crucible 103 may be 10 mm to 30 mm, for example, 12 mm, 13 mm, 15 mm, 17 mm, 20 mm, 24 mm, 25 mm, 26 mm, or 28 mm.
[0083] In some embodiments, reference Figure 7 , the difference between the voltage values of the first voltage U1 and the second voltage U2 in the first impurity removal stage is the fourth voltage difference ΔU4; Figure 8 , the difference between the voltage values of the third voltage U3 and the fourth voltage U4 in the second impurity removal stage is a fifth voltage difference ΔU5; the fifth voltage difference ΔU5 is greater than the fourth voltage difference ΔU4.
[0084] in, Figure 7 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible designed for the first impurity removal stage in the impurity removal method provided in one embodiment of the present disclosure, Figure 8 An equivalent circuit diagram of a capacitor formed by a seed crystal and a crucible side designed for the second impurity removal stage in the impurity removal method provided in one embodiment of the present disclosure.
[0085] It is worth noting that the duration of the crystal pulling stage is generally longer than that of the closing stage. Therefore, compared with the action time of the second electric field on the impurities in the silicon material 105, the action time of the first electric field on the impurities in the silicon material 105 is longer. Based on this, in the crystal pulling stage, the impurities adsorbed on the inner wall of the crucible 103 based on the action of the first electric field need to be enriched as much as possible in the tail of the pulled crystal in the short closing stage. Therefore, the fifth pressure difference ΔU5 is designed to be greater than the fourth pressure difference ΔU4, so that the electric field strength of the second electric field is greater than the electric field strength of the first electric field, so that the driving force of the second electric field on the impurities in the silicon material 105 is greater than the driving force of the first electric field on the impurities in the silicon material 105, which is beneficial to ensure that a large amount of impurities in the silicon material 105 can migrate from the inner wall of the crucible 103 to the tail of the pulled crystal in a short time, so as to facilitate the subsequent thorough removal of impurities in the silicon material 105.
[0086] In some embodiments, the fourth voltage difference ΔU4 may be 5V to 30V. For example, the fourth voltage difference ΔU4 may be 10V, 15V, 20V or 25V, etc. The fifth voltage difference ΔU5 may be 40V to 60V. For example, the fifth voltage difference ΔU5 may be 41V, 42V, 43V, 44V, 45V, 46V, 47V, 48V, 49V, 50V, 51V, 52V, 53V, 54V, 55V, 56V, 57V, 58V or 59V, etc.
[0087] In some cases, the crystal pulling stage includes at least a first equal-diameter stage, a second equal-diameter stage and a third equal-diameter stage in sequence, and the difference in voltage values between the first voltage U1 and the second voltage U2 in the first equal-diameter stage, the second equal-diameter stage and the third equal-diameter stage are all in the range of 5V to 30V.
[0088] To summarize, firstly, based on the existing single crystal furnace 100, the process of preparing crystals is designed to include at least a continuous first impurity removal stage and a second impurity removal stage. In the first impurity removal stage, the seed crystal 101 is first controlled to have a first voltage U1 and the crucible side 104 is controlled to have a second voltage U2 to form a first electric field at the crucible 103, so that the impurities in the silicon material 105 are gradually approached to the inner wall of the crucible 103 under the action of the first electric field, and are adsorbed on the inner wall of the crucible 103, thereby reducing the impurity concentration at the liquid surface of the molten silicon material 105 in the crystal pulling stage, so as to further reduce the impurity content in the pulled crystal, which is beneficial to improve the quality of the pulled crystal. Then, in the second impurity removal stage, the seed crystal 101 is controlled to have a third voltage U3 and the crucible side 104 is controlled to have a fourth voltage U4 to form a second electric field at the crucible 103, so that the impurities in the silicon material 105 migrate from the inner wall of the crucible 103 to the tail of the pulled crystal under the action of the second electric field, so that the impurities are completely separated from the silicon material 105, which is conducive to improving the purity of the remaining silicon material 105, that is, to purify the silicon material 105 and prepare for the next crystal pulling. In addition, for the impurities enriched at the tail of the pulled crystal, they can be cut off and reused as downgraded silicon material.
[0089] Secondly, in step S2, when it is detected that the real-time position of the seed crystal 101 in the single crystal furnace 100 is the preset position, the single crystal furnace 100 is controlled to be in the first impurity removal stage. At this time, the seed crystal 101 is descending and the crystal pulling has not started yet. The seed crystal 101 is controlled in advance to have a first voltage U1 and the crucible side 104 is controlled to have a second voltage U2, so that the impurities in the silicon material 105 are close to the inner wall of the crucible 103 in advance, so as to ensure that when the crystal pulling stage begins, the impurity concentration at the liquid surface of the molten silicon material 105 has been reduced to the expected requirement, thereby further ensuring the quality of the head of the pulled crystal.
[0090] Another embodiment of the present disclosure further provides a single crystal furnace for implementing the impurity removal method provided in the above embodiment. The single crystal furnace provided in another embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above embodiment will not be repeated here.
[0091] refer to Figure 2 The single crystal furnace 100 includes: a pulling head (not shown in the figure), a pulling rope 102 with a seed crystal 101 at one end, a crucible 103, and a crucible side 104 located below the crucible 103 and insulated from the crucible 103, and the pulling head and the pulling rope 102 are insulated; a monitoring device (not shown in the figure) is configured to monitor the real-time position of the seed crystal 101 in the single crystal furnace 100, and monitor the crystal pulling stage and the finishing stage; an impurity removal device (not shown in the figure) is configured to enable the single crystal furnace 100 to have a first impurity removal stage and a second impurity removal stage in the process of preparing a single crystal; wherein the impurity removal device controls the seed crystal 101 to have a first voltage and the crucible side 104 to have a second voltage in the first impurity removal stage , the first voltage U1 is greater than the second voltage U2, and the silicon material in the crucible 103 is energized with the help of the seed crystal 101, so that the silicon material 105, the crucible 103 and the crucible side 104 form a capacitor to form a first electric field, and promote the inner wall of the crucible 103 to adsorb positively charged impurities in the silicon material 105 during the crystal pulling stage; the impurity removal equipment controls the seed crystal 101 to have a third voltage and the crucible side 104 to have a fourth voltage in the second impurity removal stage, the third voltage U3 is less than the fourth voltage U4, and the silicon material in the crucible 103 is energized with the help of the seed crystal 101, so that the silicon material 105, the crucible 103 and the crucible side 104 form a capacitor to form a second electric field, and promote the impurities adsorbed on the inner wall of the crucible 103 to be enriched at the tail of the pulled crystal.
[0092] It should be noted that, in actual applications, the main part of the monitoring device and / or the main part of the impurity removal device can be arranged outside the furnace body 110 of the single crystal furnace 100, or can be arranged in a spare area inside the single crystal furnace 100. The sensor of the monitoring device is arranged in the furnace body 110 of the single crystal furnace 100, and the voltage application probe or circuit of the impurity removal device is arranged in the furnace body 110 of the single crystal furnace 100, and is electrically connected to the seed crystal 101 and the crucible 104 respectively.
[0093] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.
Claims
1. A method for removing impurities, characterized in that: include: A single crystal furnace is provided, the single crystal furnace comprising a pulling head, a pulling rope with a seed crystal arranged at one end, a crucible, and a crucible side located below the crucible and insulated from the crucible, wherein the pulling head and the pulling rope are insulated; Detecting the real-time position of the seed crystal in the single crystal furnace, and if the real-time position is a preset position, controlling the single crystal furnace to be in a first impurity removal stage, wherein the first impurity removal stage includes: controlling the seed crystal to have a first voltage and the crucible side to have a second voltage, wherein the first voltage is greater than the second voltage, and the silicon material in the crucible is electrified by means of the seed crystal, so that the silicon material, the crucible and the crucible side constitute a capacitor to form a first electric field, and causing the inner wall of the crucible to adsorb positively charged impurities in the silicon material during the crystal pulling stage of the single crystal furnace; When the crystal pulling stage is detected to be finished and the end stage is entered, the single crystal furnace is controlled to be in the second impurity removal stage, and the second impurity removal stage includes: controlling the seed crystal to have a third voltage and the crucible to have a fourth voltage, wherein the third voltage is less than the fourth voltage, so that the silicon material, the crucible and the crucible constitute a capacitor to form a second electric field, thereby causing the impurities adsorbed on the inner wall of the crucible to be enriched at the tail of the pulled crystal; The impurities concentrated in the tail of the pulled crystal are cut off.
2. The impurity removal method according to claim 1, characterized in that: The single crystal furnace further includes a guide tube. Along the height direction of the single crystal furnace, the preset position is a distance between the seed crystal and the bottom surface of the guide tube of any value between 50 mm and 800 mm.
3. The impurity removal method according to claim 1, characterized in that: The first impurity removal stage also includes: introducing hydrogen into the single crystal furnace, and the impurities in the silicon material with positive charge are gathered into ion clusters under the induction of the hydrogen and adsorbed on the inner wall of the crucible.
4. The impurity removal method according to claim 1, characterized in that: In the crystal pulling stage, the silicon material is in a molten liquid state, and the center temperature of the liquid surface of the silicon material is controlled to be 1400° C. to 1450° C.
5. The impurity removal method according to any one of claims 1 to 4, characterized in that: As the crystal pulling process in the single crystal furnace continues, the crystal pulling stage in the first impurity removal stage at least sequentially includes: a first equal diameter stage, a second equal diameter stage, and a third equal diameter stage, and the voltage value of at least one of the first voltage and the second voltage in the first equal diameter stage, the second equal diameter stage, and the third equal diameter stage changes; Among them, the difference between the voltage values of the first voltage and the second voltage in the first equal-diameter stage is a first pressure difference, the difference between the voltage values of the first voltage and the second voltage in the second equal-diameter stage is a second pressure difference, and the difference between the voltage values of the first voltage and the second voltage in the third equal-diameter stage is a third pressure difference, the first pressure difference is smaller than the second pressure difference, and the second pressure difference is smaller than the third pressure difference.
6. The impurity removal method according to claim 5, characterized in that: The first voltage difference is 5V to 10V, the second voltage difference is 10V to 20V, and the third voltage difference is 20V to 30V.
7. The impurity removal method according to claim 5, characterized in that: The first equal-diameter stage is a stage in which the equal-diameter length of the pulled crystal increases from a first preset value to a second preset value; the second equal-diameter stage is a stage in which the equal-diameter length of the pulled crystal increases from the second preset value to a third preset value; the third equal-diameter stage is a stage in which the equal-diameter length of the pulled crystal increases from the third preset value to a fourth preset value; wherein, the difference between the first preset value and the second preset value is smaller than the difference between the third preset value and the second preset value, and the difference between the third preset value and the second preset value is smaller than the difference between the fourth preset value and the third preset value.
8. The impurity removal method according to any one of claims 1 to 4, characterized in that: The difference between the voltage values of the first voltage and the second voltage in the first impurity removal stage is a fourth voltage difference; the difference between the voltage values of the third voltage and the fourth voltage in the second impurity removal stage is a fifth voltage difference; The fifth pressure difference is greater than the fourth pressure difference.
9. The impurity removal method according to claim 8, characterized in that: The fourth voltage difference is 5V to 30V, and the fifth voltage difference is 40V to 60V.
10. A single crystal furnace, characterized in that: include: A lifting head, a lifting rope with a seed crystal at one end, a crucible, and a crucible side located below the crucible and insulated from the crucible, wherein the lifting head and the lifting rope are insulated; A monitoring device configured to monitor the real-time position of the seed crystal in the single crystal furnace, and monitor the crystal pulling stage and the finishing stage; The impurity removal device is configured to ensure that the process of preparing single crystals in the single crystal furnace has a first impurity removal stage and a second impurity removal stage; The impurity removal device controls the seed crystal to have a first voltage and the crucible side to have a second voltage in the first impurity removal stage, the first voltage being greater than the second voltage, and the silicon material in the crucible is electrified by means of the seed crystal, so that the silicon material, the crucible and the crucible side constitute a capacitor to form a first electric field, and causes the inner wall of the crucible to adsorb positively charged impurities in the silicon material in the crystal pulling stage; The impurity removal equipment controls the seed crystal to have a third voltage and the crucible side to have a fourth voltage in the second impurity removal stage, wherein the third voltage is less than the fourth voltage. The seed crystal is used to energize the silicon material in the crucible, so that the silicon material, the crucible and the crucible side form a capacitor to form a second electric field, thereby causing the impurities adsorbed on the inner wall of the crucible to be enriched at the tail of the pulled crystal.