Preparation method of waveguide integrated three-lamination graphene electro-optical modulator

Abstract

The invention discloses a preparation method of a waveguide-integrated three-lamination graphene electro-optical modulator, which adopts a three-lamination graphene capacitor structure, enhances the interaction between graphene and light, and can improve the device modulation efficiency and reduce the insertion loss under the same device size. The first graphene layer and the third graphene layer adopt an interconnection design, and after the third graphene layer is transferred, residual water is removed by adopting a vacuum annealing process, so that the third graphene layer can be attached to the surfaces of the first graphene layer and the dielectric layer, a device control circuit is simplified, and device miniaturization is facilitated.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor optoelectronic devices, and in particular relates to a method for preparing a waveguide-integrated triple-stacked graphene electro-optical modulator. Background Art

[0002] Optical modulators are key functional components in microwave photonics signal generation and processing systems. Exploring high-speed, high-bandwidth, and small-volume integrated optical modulators for interconnecting optical devices on a chip has become a development trend for modulators. In recent years, integrated photonics, which aims at on-chip functional integrated systems, has developed rapidly. In the chip-based process of optical signal processing systems, developing efficient modulators is an important research topic.

[0003] As a two-dimensional material that has been widely studied in recent years, graphene has many superior properties that are different from traditional electro-optical materials, such as excellent mechanical properties, high thermal conductivity, ultra-wideband optical response spectrum, extremely high carrier mobility, and large current density carrying capacity. It is expected to meet the requirements of small size, low power consumption, and large bandwidth for modulators at the same time, and is an ideal material for integrated microwave photonics. Because single-layer graphene has the problem of insufficient light absorption, combining graphene with waveguides and using evanescent waves around the waveguides to enhance the interaction between graphene and light and increase the action distance is an important way to improve the efficiency of graphene optoelectronic devices. These excellent properties give graphene a unique advantage in the field of new optical and optoelectronic devices.

[0004] At present, the research on graphene-based electro-optic modulators is progressing rapidly. The structural design combining capacitor-like graphene and waveguide is generally adopted. The active area of ​​the device shows the advantage of small size. However, there are also many problems with graphene electro-optic modulators. For example, high modulation bandwidth and high extinction ratio are difficult to achieve at the same time, and the modulation efficiency of the device needs to be further optimized. Summary of the invention

[0005] The present invention aims to provide a method for preparing a waveguide-integrated three-layer graphene electro-optic modulator, thereby improving modulation efficiency, reducing insertion loss, and simplifying device control circuits.

[0006] In order to achieve the object of the present invention, the present invention provides a method for preparing a waveguide-integrated three-layer graphene electro-optic modulator, comprising the following steps:

[0007] Step 1, preparing Si waveguide on SOI substrate: obtaining Si waveguide pattern by planar photolithography and development technology, and completing etching of the Si waveguide by dry etching process;

[0008] Step 2, planarizing the Si waveguide surface: using plasma enhanced chemical vapor deposition to grow a SiO2 layer on the Si waveguide surface, and then using chemical mechanical polishing technology to polish the Si waveguide surface until its surface is flat;

[0009] Step 3, first graphene layer transfer: using a wet transfer process to transfer the first graphene layer to the SiO2 surface;

[0010] Step 4, patterning the first graphene layer: preparing an isolation pattern on the surface of the first graphene layer by using a planar photolithography development technology, and then using dry oxidation to remove the first graphene layer outside the isolation pattern area;

[0011] Step 5, dielectric layer growth: growing a dielectric layer on the surface of the first graphene layer using an atomic layer deposition process;

[0012] Step 6: Transfer and patterning of the second graphene layer, the process repeats steps 3 and 4;

[0013] Step 7, preparation of the first metal electrode: preparing an electrode pattern on the surface of the second graphene layer by using a planar photolithography development technology, wherein the electrode pattern is located in the edge region of the second graphene layer pattern, and completing metallization after evaporation, and using a sol-gel stripping technology to prepare the first metal electrode;

[0014] Step 8, dielectric layer growth: growing a dielectric layer on the surface of the second graphene layer using an atomic layer deposition process;

[0015] Step 9, opening holes in the dielectric layer: preparing an opening pattern on the surface of the dielectric layer by using a planar photolithography development technology, wherein the opening pattern is located above the first graphene layer, and removing the dielectric layer under the opening pattern by using a wet etching process until the surface of the first graphene layer is exposed;

[0016] Step 10, transfer and patterning of the third graphene layer: the process repeats step 3, and a vacuum high temperature annealing process is adopted after the third graphene layer is transferred, and the subsequent process repeats step 4;

[0017] Step 11, preparation of the second metal electrode: an electrode pattern is prepared on the surface of the third graphene layer using a planar photolithography development technique, wherein the electrode pattern is located in the edge region of the third graphene layer pattern, and metallization is completed after evaporation, assisted by sol-gel stripping technology, to prepare a second metal electrode, thereby completing the preparation of the graphene electro-optic modulator.

[0018] Compared with the prior art, the significant progress of the present invention lies in: (1) the present invention adopts a three-layer graphene design, which enhances the interaction between graphene and light compared to the traditional two-layer graphene electro-optical modulator, can improve the device modulation efficiency and reduce insertion loss under the same device size; (2) the first graphene layer and the second graphene layer of the present invention adopt an interconnected design, and a vacuum annealing process is used to remove residual water after the third graphene layer is transferred, so as to ensure that the third graphene layer can be attached to the surface of the first graphene layer and the dielectric layer, simplify the device control circuit, and facilitate the miniaturization of the device.

[0019] In order to more clearly illustrate the functional characteristics and structural parameters of the present invention, further description is given below in conjunction with the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0021] Figure 1 is a schematic diagram of a three-layer graphene electro-optic modulator of the present invention;

[0022] Figure 2 is a schematic diagram of the waveguide structure of the present invention;

[0023] Figure 3 is a schematic diagram of the waveguide surface flattening of the present invention;

[0024] Figure 4 is a schematic diagram of the structure of the first graphene layer of the present invention;

[0025] Figure 5 is a schematic diagram of a growing alumina medium of the present invention;

[0026] Figure 6 is a schematic diagram of the second graphene layer and the first metal electrode of the present invention;

[0027] Figure 7 It is a schematic diagram of the growing alumina medium and opening holes of the present invention. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0029] A method for preparing a waveguide-integrated three-layer graphene electro-optic modulator of the present invention comprises the following steps:

[0030] Step 1: Prepare Si waveguide on SOI substrate: Use planar photolithography to obtain Si waveguide pattern, use dry etching process to complete the etching of Si waveguide, and combine Figure 2 ;

[0031] Step 2: Planarization of the Si waveguide surface: Use plasma enhanced chemical vapor deposition to grow a SiO2 layer on the surface of the Si waveguide, and then use chemical mechanical polishing technology to polish the Si waveguide surface until it is flat. Figure 3 ;

[0032] Step 3, first graphene layer transfer: using a wet transfer process to transfer the first graphene layer to the SiO2 surface;

[0033] Step 4: Patterning the first graphene layer: Prepare an isolation pattern on the surface of the first graphene layer by using a planar photolithography development technique, and then use dry oxidation and oxygen plasma to remove the first graphene layer outside the isolation pattern area. Figure 4 ;

[0034] Step 5: Dielectric layer growth: Use atomic layer deposition technology to grow a dielectric layer on the surface of the first graphene layer. Figure 5 ;

[0035] Step 6: Transfer and patterning of the second graphene layer, the process repeats steps 3 and 4;

[0036] Step 7, preparation of the first metal electrode: an electrode pattern is prepared on the surface of the second graphene layer by using a planar photolithography development technique, the electrode pattern is located in the edge region of the second graphene layer pattern, metallization is completed after evaporation, and the first metal electrode is prepared by using a sol-gel stripping technique, and then Figure 6 ;

[0037] Step 8, dielectric layer growth: growing a dielectric layer on the surface of the second graphene layer using an atomic layer deposition process;

[0038] Step 9, opening holes in the dielectric layer: using a planar photolithography development technology to prepare an opening pattern on the surface of the dielectric layer, the opening pattern is located above the first graphene layer, and a wet etching process is used to remove the dielectric layer under the opening pattern until the surface of the first graphene layer is exposed, and then Figure 7 ;

[0039] Step 10, transfer and patterning of the third graphene layer: the process repeats step 3, and water may remain in the dielectric hole during the wet transfer of the third graphene layer. After the third graphene layer is transferred, a vacuum high-temperature annealing process is used to ensure that the third graphene layer is bonded to the surface of the first graphene layer and the dielectric layer, and the subsequent process repeats step 4;

[0040] Step 11, preparation of the second metal electrode: an electrode pattern is prepared on the surface of the third graphene layer by using a planar photolithography development technique, the electrode pattern is located at the edge region of the third graphene layer pattern, metallization is completed after evaporation, and a sol-gel stripping technique is used to prepare a second metal electrode, and the preparation of the graphene electro-optical modulator is completed. Figure 1 .

[0041] Furthermore, in step 10, a vacuum high temperature annealing process is adopted, wherein the annealing temperature is 200-300° C., the pressure is less than 1 Pa, and the time is 2-4 hours.

[0042] Furthermore, the thickness of the SiO2 layer in step 2 is 1-2 μm, and the surface is polished by chemical mechanical polishing technology until 50-100 nm of the SiO2 layer remains.

[0043] Furthermore, the medium of the dielectric layer in step 5 and step 8 is a high-K medium with a thickness of 10-30 nm.

[0044] Furthermore, the high-K medium is Al2O3 or HfO2.

[0045] Furthermore, the metal electrode material in step 7 and step 11 is Au, and the thickness is 200nm-1μm.

[0046] Furthermore, the step height of the Si waveguide in step 1 is 200-300 nm, and the width of the Si waveguide is 400-600 nm.

[0047] When the capacitor structure with four or more graphene layers realizes electro-optic modulation, the process becomes more difficult, the distance from the waveguide is far, and the modulation efficiency is reduced.

[0048] In the drawings, graphene 1 is the first graphene layer, graphene 2 is the second graphene layer, and graphene 3 is the third graphene layer; electrode 1 is the first metal electrode, and electrode 2 is the second metal electrode.

[0049] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0050] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for preparing a waveguide-integrated triple-stack graphene electro-optic modulator, characterized in that: The following steps are involved: Step 1, preparing Si waveguide on SOI substrate: obtaining Si waveguide pattern by planar photolithography and development technology, and completing etching of the Si waveguide by dry etching process; Step 2, planarizing the Si waveguide surface: using plasma enhanced chemical vapor deposition to grow a SiO2 layer on the Si waveguide surface, and then using chemical mechanical polishing technology to polish the Si waveguide surface until its surface is flat; Step 3, first graphene layer transfer: using a wet transfer process to transfer the first graphene layer to the SiO2 surface; Step 4, patterning the first graphene layer: preparing an isolation pattern on the surface of the first graphene layer by using a planar photolithography development technology, and then using dry oxidation to remove the first graphene layer outside the isolation pattern area; Step 5, dielectric layer growth: growing a dielectric layer on the surface of the first graphene layer using an atomic layer deposition process; Step 6: Transfer and patterning of the second graphene layer, the process repeats steps 3 and 4; Step 7, preparation of the first metal electrode: preparing an electrode pattern on the surface of the second graphene layer by using a planar photolithography development technology, wherein the electrode pattern is located in the edge region of the second graphene layer pattern, and completing metallization after evaporation, and using a sol-gel stripping technology to prepare the first metal electrode; Step 8, dielectric layer growth: growing a dielectric layer on the surface of the second graphene layer using an atomic layer deposition process; Step 9, opening holes in the dielectric layer: preparing an opening pattern on the surface of the dielectric layer by using a planar photolithography development technology, wherein the opening pattern is located above the first graphene layer, and removing the dielectric layer under the opening pattern by using a wet etching process until the surface of the first graphene layer is exposed; Step 10, transfer and patterning of the third graphene layer: the process repeats step 3, and a vacuum high temperature annealing process is adopted after the third graphene layer is transferred, and the subsequent process repeats step 4; Step 11, preparation of the second metal electrode: an electrode pattern is prepared on the surface of the third graphene layer using a planar photolithography development technique, wherein the electrode pattern is located in the edge region of the third graphene layer pattern, and metallization is completed after evaporation, assisted by sol-gel stripping technology, to prepare a second metal electrode, thereby completing the preparation of the graphene electro-optic modulator.

2. The method for preparing a waveguide-integrated triple-stack graphene electro-optic modulator according to claim 1, characterized in that: In step 10, a vacuum high temperature annealing process is used to remove the residual water after transfer to ensure that the third graphene layer can be attached to the surface of the first graphene layer and the dielectric layer. The annealing temperature is 200-300° C., the pressure is less than 1 Pa, and the time is 2-4 hours.

3. The method for preparing a waveguide-integrated three-layer graphene electro-optic modulator according to claim 1, characterized in that: The thickness of the SiO2 layer in step 2 is 1-2 μm, and the surface is polished by chemical mechanical polishing technology until 50-100 nm of the SiO2 layer remains.

4. The method for preparing a waveguide-integrated three-layer graphene electro-optic modulator according to claim 1, characterized in that: The medium of the dielectric layer in step 5 and step 8 is a high-K dielectric with a thickness of 10-30 nm.

5. The method for preparing a waveguide-integrated three-layer graphene electro-optic modulator according to claim 4, characterized in that: The high-K dielectric is Al2O3 or HfO2.

6. The method for preparing a waveguide-integrated three-layer graphene electro-optic modulator according to claim 1, characterized in that: The metal electrode material in step 7 and step 11 is Au, and the thickness is 200nm-1μm.

7. The method for preparing a waveguide-integrated three-layer graphene electro-optic modulator according to claim 1, characterized in that: The step height of the Si waveguide in step 1 is 200-300 nm, and the width of the Si waveguide is 400-600 nm.

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