Interrupt vector acquisition method and device based on DPU, equipment and storage medium

Abstract

The invention relates to a DPU-based interrupt vector acquisition method, apparatus and device, and a storage medium. According to the method and the device, the first storage space is expanded on the basis of the original storage space to store the function node identifier, so that the queues in the system are allocated to different function nodes, each function node does not need to occupy all interrupt vectors in the system, and the RAM storage space occupied by an interrupt vector table is greatly saved.

Description

Technical Field

[0001] The present disclosure relates to the field of virtualization technology, and in particular to a DPU-based interrupt vector acquisition method, device, equipment and storage medium. Background Art

[0002] The most powerful feature of PCI Express is I / O virtualization, which allows virtual machines (VMs) to directly access I / O hardware devices, improving the performance of enterprise-level servers. At the same time, the SR-IOV (Single Root I / O Virtualization) technical specification allows a PCI Express device to appear as multiple different "virtual function" nodes in the host. Therefore, in existing smart network cards such as DPU (Data Processing Unit), the SR-IOV (Single Root I / O Virtualization) system based on the PCIE architecture can implement multiple functional nodes. At the same time, there are multiple data stream transmit and receive queues (RXQ / TXQ) in the system to support the data flow of each functional node.

[0003] MSI-X (PCI Express Message Signaled Interrupts with Extension) is an interrupt technology for high-performance computing devices. It is part of the PCIe specification and is designed to improve system responsiveness and performance and reduce the load on the central processor. MSI-X allows devices to request multiple interrupt vectors, which can better spread the interrupt load across multiple cores or processors in the system, thereby improving system performance and scalability. When the system needs to support the PCIESR-IOV function in order to implement multiple functional nodes, each transceiver queue requires an independent MSI-X interrupt vector for efficient operation. For example, for 16 physical function nodes (PF) and 512 VFs, each function node requires 1024 send queues and 1024 receive queues, and they can be arbitrarily configured for use by different function nodes. Therefore, each function node requires 2048 queues, that is, 2048 MSI-X interrupt vectors. Each MSI-X interrupt vector occupies 128 bits of storage space. Then 16 PFs and 512 VFs occupy 138,412,032 bits, that is, 138Mbits of storage space.

[0004] In the design of Field Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC), block storage RAM (Random Access Memory) resources are very valuable. For example, some FPGA models on the market only provide 68Mbit RAM resources at most, which is simply unable to meet the space requirements of the above 138Mbit interrupt vector table. At the same time, even for ASIC chip design, the cost of silicon wafers required for such a large RAM capacity is also very huge. Summary of the invention

[0005] In order to solve the above technical problems, the present disclosure provides a DPU-based interrupt vector acquisition method, device, equipment and storage medium to save the storage space occupied by the interrupt vector table.

[0006] In a first aspect, an embodiment of the present disclosure provides a method for obtaining an interrupt vector based on a DPU, including:

[0007] Expanding a first storage space based on an original storage space corresponding to a vector table, wherein the vector table includes a plurality of vector table entries, and the first storage space is used to store a function node identifier corresponding to each of the vector table entries;

[0008] Initialize the original storage space and the first storage space according to the vector table configuration information to obtain a vector table configuration result;

[0009] When interrupt source input information is received, determining a target table entry in the vector table configuration result based on table lookup information in the interrupt source input information;

[0010] Read the interrupt vector content in the target table entry.

[0011] In some embodiments, the original storage space is the product of the original width and the original depth of the vector table, and the step of expanding the first storage space based on the original storage space corresponding to the vector table includes:

[0012] A preset extended width is added on the basis of the original width, and the size of the first storage space is the product of the preset extended width and the original depth.

[0013] In some embodiments, the vector table entry corresponds to the queue one by one, the first storage space includes multiple first storage subspaces, the first storage subspaces correspond to the vector table entry one by one, and the original storage space and the first storage space are initialized according to the vector table configuration information to obtain the vector table configuration result, including:

[0014] Acquire vector table configuration information, where the vector table configuration information includes at least one function node identifier, a queue start position corresponding to each function node, and the number of queues;

[0015] For each functional node identifier, determining at least one allocated table entry corresponding to the functional node from the multiple vector table entries according to the queue starting position and the number of queues;

[0016] The function node identifier is stored in a first storage subspace corresponding to each of the allocated entries.

[0017] In some embodiments, the queue starting position includes a sending queue starting position and a receiving queue starting position, the number of queues includes a sending queue number and a receiving queue number, and for each functional node identifier, determining at least one allocated table entry corresponding to the functional node from the multiple vector table entries according to the queue starting position and the queue number, includes:

[0018] Determine, according to the starting position of the sending queue and the number of the sending queues, an allocated table entry corresponding to at least one sending queue;

[0019] According to the starting position of the receiving queue and the number of the receiving queues, an allocated table entry corresponding to at least one receiving queue is determined.

[0020] In some embodiments, the original storage space is used to store an interrupt vector identifier, and the method further includes:

[0021] Starting from the allocated table entry corresponding to the starting position of the sending queue, sequentially setting an interrupt vector identifier for the sending queue corresponding to each of the allocated table entries;

[0022] Starting from the allocated table entry corresponding to the start position of the receiving queue, sequentially setting an interrupt vector identifier for the receiving queue corresponding to each of the allocated table entries;

[0023] The interrupt vector identifier of the last transmit queue is adjacent to the interrupt vector identifier of the first receive queue; or

[0024] The interrupt vector identifier of the last receive queue is adjacent to the interrupt vector identifier of the first transmit queue.

[0025] In some embodiments, storing the function node identifier in the first storage subspace corresponding to each of the allocated entries includes:

[0026] For any vector table entry, if the vector table entry is not an allocated table entry, the first storage subspace corresponding to the vector table entry is not written.

[0027] In some embodiments, the table lookup information includes a target function node identifier and a target interrupt vector identifier, and determining a target table entry in the vector table configuration result based on the table lookup information in the interrupt source input information includes:

[0028] Determine, according to the target function node identifier and the function node identifiers stored in the first storage space, at least one allocated table entry corresponding to the target function node identifier;

[0029] According to the target interrupt vector identifier, a target table entry is searched from at least one allocated table entry corresponding to the target function node identifier.

[0030] In a second aspect, an embodiment of the present disclosure provides an interrupt vector acquisition device based on a DPU, comprising:

[0031] An expansion module, used to expand a first storage space based on an original storage space corresponding to a vector table, wherein the vector table includes a plurality of vector table entries, and the first storage space is used to store a function node identifier corresponding to each of the vector table entries;

[0032] An initialization module, used to initialize the original storage space and the first storage space according to the vector table configuration information to obtain a vector table configuration result;

[0033] A determination module, configured to determine a target table entry in the vector table configuration result based on table lookup information in the interrupt source input information when interrupt source input information is received;

[0034] The reading module is used to read the interrupt vector content in the target table entry.

[0035] In a third aspect, an embodiment of the present disclosure provides an electronic device, including:

[0036] Memory;

[0037] Processor; and

[0038] Computer programs;

[0039] The computer program is stored in the memory and is configured to be executed by the processor to implement the method as described in the first aspect.

[0040] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the method described in the first aspect.

[0041] In a fifth aspect, an embodiment of the present disclosure further provides a computer program product, which includes a computer program or instructions, and when the computer program or instructions are executed by a processor, the DPU-based interrupt vector acquisition method as described above is implemented.

[0042] The DPU-based interrupt vector acquisition method, apparatus, device and storage medium provided in the embodiments of the present disclosure store function node identifiers by expanding a first storage space based on the original storage space, thereby allocating queues in the system to different function nodes. Therefore, each function node does not need to occupy all interrupt vectors in the system, which greatly saves the RAM storage space occupied by the interrupt vector table. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0045] Figure 1 A flow chart of a DPU-based interrupt vector acquisition method provided in an embodiment of the present disclosure;

[0046] Figure 2 A schematic diagram of an application scenario provided by an embodiment of the present disclosure;

[0047] Figure 3 A schematic diagram of an example of configuration information provided in an embodiment of the present disclosure;

[0048] Figure 4 A schematic diagram of a computing logic example provided for an embodiment of the present disclosure;

[0049] Figure 5 A schematic diagram of the structure of a DPU-based interrupt vector acquisition device provided in an embodiment of the present disclosure;

[0050] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0052] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0053] The embodiment of the present disclosure provides a method for obtaining an interrupt vector based on a DPU, which is introduced below in conjunction with a specific embodiment.

[0054] When the system needs to support PCIE SR-IOV function in order to realize multiple functional nodes, in order to achieve efficient work, each transceiver queue requires an independent MSI-X interrupt vector. For example, for the characteristic indicators of 16 physical function nodes (PF) and 512 VFs unique to the DPU scenario, each functional node requires 1024 sending queues and 1024 receiving queues, and they can be arbitrarily configured for different functional nodes. Therefore, each functional node requires 2048 queues, that is, 2048 MSI-X interrupt vectors. Each MSI-X interrupt vector occupies 128 bits of storage space, and 16 PFs and 512 VFs occupy 138,412,032 bits, that is, 138Mbit of storage space. Such a huge RAM demand is difficult to achieve for current hardware design, especially for DPU chips.

[0055] Figure 1 The flowchart of the interrupt vector acquisition method based on DPU provided in the embodiment of the present disclosure. The method can be applied to hardware devices such as FPGA or ASIC supporting SR-IOV system, and the hardware device can be DPU, including Figure 2 The RAM storage space shown includes an original storage space and a first storage space.

[0056] It can be understood that the DPU-based interrupt vector acquisition method provided in the embodiments of the present disclosure can also be applied in other scenarios.

[0057] Combine the following Figure 2 The application scenario shown is Figure 1 The interrupt vector acquisition method based on DPU is introduced as shown in the figure. The specific steps of the method are as follows:

[0058] S101. Expand a first storage space based on an original storage space corresponding to a vector table, wherein the vector table includes a plurality of vector table entries, and the first storage space is used to store a function node identifier corresponding to each of the vector table entries.

[0059] The vector table includes multiple vector table entries, each of which corresponds to an interrupt vector required by a receive queue (RXQ) or a transmit queue (TXQ). In other words, each vector table entry corresponds to an RXQ or TXQ, and each RXQ corresponds to an interrupt vector, and each TXQ corresponds to an interrupt vector.

[0060] Function nodes are divided into physical function nodes (PF) and virtual function nodes (VF), where PF is a complete PCIe device with SR-IOV capability, which is responsible for configuring and managing VF, and VF is a function node virtualized from PF. The first storage space is used to store the function node identifier (pfvf_id) corresponding to each vector table entry, so that each function node does not need to connect to all queues, but only needs to connect to several queues corresponding to the function node.

[0061] It should be noted that the SRIOV feature indicators of 16PF and 512VF configurations are only applied to DPU.

[0062] The original storage space is used to store each vector table entry, that is, the interrupt vector corresponding to each queue. The original storage space is the product of the original width and the original depth of the vector table, and the original depth is the number of vector table entries, that is, the number of queues in the system.

[0063] Optionally, a preset extended width is added on the basis of the original width, and the size of the first storage space is the product of the preset extended width and the original depth.

[0064] like Figure 2 As shown, Figure 2 The example shows the receive queue and transmit queue corresponding to the 16PF and 512VF configurations in the system, with a total of 2048 queues, including 1024 RXQs and 1024 TXQs. The storage space bit0-bit127 is the original storage space, and its original width is 128 bits occupied by each vector table entry (interrupt vector); its original depth is the number of queues (addr_0-addr_2047).

[0065] Taking the preset extension width of 8 bits as an example, the position of bit128-bit135 is the first storage space, and its depth is still the original depth. Therefore, the size of the first storage space is the product of the preset extension width and the original depth.

[0066] At this time, the unit storage space corresponding to each vector table entry is expanded from the original 128 bits to 128+8 bits. The total space occupied by the original storage space and the first storage space is 278,528 bits, i.e. 0.3 Mbit, which is significantly reduced compared to the 138 Mbit storage space required in the original design.

[0067] S102: Initialize the original storage space and the first storage space according to the vector table configuration information to obtain a vector table configuration result.

[0068] The vector table configuration information includes the correspondence between each queue and the functional node, and each queue can be allocated to a corresponding functional node according to the correspondence.

[0069] Specifically, Figure 2 As shown, the hardware device searches for the vector table entry according to the configuration information and configuration instructions sent by the central processing unit (CPU) through the advanced peripheral bus (APB) based on the APB MAP logic according to the configuration information provided by the APB bus according to established rules, and configures the rxdma_pfvf_cfg and / or txdma_pfvf_cfg registers to write the specified function node identifier into the first storage space corresponding to at least one vector table entry.

[0070] The APB bus is an interface used to connect various components such as sensors, memory and peripherals to a microcontroller or system on chip (SoC). The width of the APB bus is 32 bits, while the content width of a vector table entry is 128 bits, requiring four write operations to complete the initialization of the vector table entry.

[0071] At the same time, the original storage space is initialized according to the native logic of the SR-IOV system, and the corresponding interrupt vector is set for each queue.

[0072] S103: When interrupt source input information is received, determine a target table entry in the vector table configuration result based on table lookup information in the interrupt source input information.

[0073] The IRQ Bus provides interrupt source input information, including table lookup information.

[0074] The table lookup information is used to determine the target table entry where the interrupt vector corresponding to the interrupt source input information is located.

[0075] Specifically, the target function node corresponding to the interrupt source input information is determined based on the table lookup information, and a target table entry among a plurality of vector table entries corresponding to the target function node is further determined.

[0076] S104: Read the interrupt vector content in the target table entry.

[0077] The interrupt vector content in the target table entry is sent to the CPU through the corresponding interface, and the interrupt service process can be executed by jumping to the address pointed to by the vector according to the interrupt vector.

[0078] The disclosed embodiment expands a first storage space based on an original storage space corresponding to a vector table, the vector table includes a plurality of vector table entries, and the first storage space is used to store a function node identifier corresponding to each of the vector table entries; the original storage space and the first storage space are initialized according to vector table configuration information to obtain a vector table configuration result; when interrupt source input information is received, a target table entry in the vector table configuration result is determined based on table lookup information in the interrupt source input information; the interrupt vector content in the target table entry is read, and the function node identifier is stored by expanding the first storage space based on the original storage space, thereby allocating queues in the system to different function nodes, so that each function node does not need to occupy all interrupt vectors in the system, which greatly saves the RAM storage space occupied by the interrupt vector table.

[0079] Specifically, for the same 2048 interrupt vectors and corresponding function node identifiers, only 0.3 Mbit is needed, which saves a lot of storage space compared to 138 Mbit. Therefore, this method is easy to implement in FPGA or ASIC without additional silicon chip costs.

[0080] On the basis of the above embodiment, the vector table entries correspond one-to-one to the queues, the first storage space includes multiple first storage subspaces, the first storage subspaces correspond one-to-one to the vector table entries, and the original storage space and the first storage space are initialized according to the vector table configuration information to obtain the vector table configuration result, including: obtaining the vector table configuration information, the vector table configuration information includes at least one functional node identifier, the queue starting position and the number of queues corresponding to each functional node; for each functional node identifier, according to the queue starting position and the number of queues, determining at least one allocated table entry corresponding to the functional node from the multiple vector table entries; storing the functional node identifier in the first storage subspace corresponding to each of the allocated table entries.

[0081] Continue to refer Figure 2 The original storage space includes multiple original storage subspaces, each vector table entry occupies an original storage subspace, and each vector table entry includes an interrupt vector of a queue; the first storage space includes multiple first storage subspaces, and the first storage subspace corresponds to the vector table entry one by one, and is used to store the function node identifier (pfvf_id) corresponding to the vector table entry.

[0082] The vector table configuration information includes at least one functional node identifier, a queue start position corresponding to each functional node, and the number of queues. Specifically, the queues are divided into a transmit queue (TXQ) and a receive queue (RXQ), the corresponding queue start position includes a transmit queue start position and a receive queue start position, and the number of queues includes a transmit queue number and a receive queue number.

[0083] Determine at least one allocated table entry corresponding to the to-be-allocated functional node from the multiple vector table entries, including: determining the allocated table entry corresponding to at least one sending queue according to the starting position of the sending queue and the number of the sending queues; and determining the allocated table entry corresponding to at least one receiving queue according to the starting position of the receiving queue and the number of the receiving queues.

[0084] For a functional node, it is usually necessary to allocate at least one sending queue and at least one receiving queue. Taking the sending queue as an example, starting from the vector table entry corresponding to the starting position of the sending queue, a number of consecutive vector table entries are used as allocated table entries, where the total number of allocated table entries is the number of the sending queues; the allocation of the receiving queue is similar.

[0085] It should be noted that the starting position of the above-mentioned sending queue and the number of sending queues need to meet the limit of the total number of all sending queues in the system, that is, starting from the vector table entry corresponding to the starting position of the sending queue, there must be at least a number of consecutive vector table entries equal to the number of sending queues that are sending queues, and the limit on the total number of receiving queues is the same.

[0086] Here is a set of vector table configuration information examples:

[0087] txdma_pfvf_cfg[0]={1'b1,10'd4,10'd0};

[0088] rxdma_pfvf_cfg[0]={1'b1,10'd2,10'd0};

[0089] txdma_pfvf_cfg[1]={1'b1,10'd4,10'd4};

[0090] rxdma_pfvf_cfg[1]={1'b1,10'd2,10'd2};

[0091] txdma_pfvf_cfg

[15] ={1'b1,10'd4,10'd8};

[0092] rxdma_pfvf_cfg

[15] ={1'b1,10'd2,10'd4};

[0093] Among them, the relevant configuration information of the txdma_pfvf_cfg register is used to allocate TXQ, and the relevant configuration information of the rxdma_pfvf_cfg register is used to allocate RXQ.

[0094] like Figure 2 As shown, each queue in the system has a unique queue number (TXQ_0-TXQ_1023 and RXQ_0-RXQ_1023), the interrupt vectors (TXQ_0Vector-TXQ_1023Vector) corresponding to the transmit queues are located in two adjacent vector table entries, and the interrupt vectors (RXQ_0Vector-RXQ_1023Vector) corresponding to the receive queues are located in two adjacent vector table entries.

[0095] Taking "txdma_pfvf_cfg[0]={1'b1,10'd4,10'd0}" as an example, the configuration information indicates that TXQ is allocated to the functional node with the functional node identification of 0, the starting position of the transmit queue is the position where TXQ_0 is located, and the number of transmit queues is 4, so the four transmit queues TXQ_0-TXQ_3 are allocated to the functional node with the functional node identification of 0.

[0096] Optionally, for any vector table entry, if the vector table entry is not an allocated table entry, the first storage subspace corresponding to the vector table entry is not written.

[0097] If the vector table entry is not an allocated table entry, it means that the queue corresponding to the vector table entry has not been allocated to any functional node. At this time, the first storage subspace corresponding to the vector table entry still maintains a default state, and no functional node identifier is written.

[0098] For the function node to which no queue is assigned, the configuration is performed through the value range of the function node identifier. For example, the relevant configuration information is:

[0099] rxdma_pfvf_cfg[n]={1'b0,10'd0,10'd0};

[0100] The value range of n is [2-14, 16-527].

[0101] Further, a corresponding interrupt vector identifier is configured for each allocated table entry. For the allocated table entry of each functional node, a unified interrupt vector identifier setting principle is followed, for example, the identifier is set sequentially starting from 0 according to the position of the allocated table entry in the interrupt vector table.

[0102] That is to say, for the same functional node, the interrupt vector identifiers of the multiple allocated table entries corresponding thereto are not repeated and are adjacent to each other; but for different functional nodes, the interrupt vector identifiers of the allocated table entries corresponding thereto may be repeated.

[0103] Specifically, starting from the allocated table entry corresponding to the starting position of the sending queue, the interrupt vector identifier is set for the sending queue corresponding to each of the allocated table entries in turn; starting from the allocated table entry corresponding to the starting position of the receiving queue, the interrupt vector identifier is set for the receiving queue corresponding to each of the allocated table entries in turn.

[0104] The interrupt vector identifier of the last sending queue is adjacent to the interrupt vector identifier of the first receiving queue; or the interrupt vector identifier of the last receiving queue is adjacent to the interrupt vector identifier of the first sending queue.

[0105] Based on the above vector table configuration information, the functional node is assigned a fixed receive queue and / or transmit queue. For example, if the number of TXQs is N and the number of RXQs is M, then this functional node needs to support N+M interrupt vectors. The interrupt vector identifier of TXQ is assigned a value of 0-(N-1), and the vector VecID value of the RXQ queue is assigned to N-(N+M-1).

[0106] That is, for the same functional node, the interrupt vector identifiers of the queues corresponding to it all start from the first identifier in the preset rule until each queue is equipped with its own interrupt vector identifier.

[0107] Furthermore, the queue_vec_cfg register is configured to configure the interrupt vector identifier (MSI-X vector Index) of each queue.

[0108] Figure 3 A schematic diagram of an example of configuration information provided in an embodiment of the present disclosure, such as Figure 3 As shown, based on the above vector table configuration information, for the sending queue, a total of 4 sending queues TXQ_0-TXQ_3 are allocated to functional node 0; a total of 4 sending queues TXQ_4-TXQ_7 are allocated to functional node 1; a total of 4 sending queues TXQ_8-TXQ_11 are allocated to functional node 15.

[0109] For the receiving queue, a total of 2 receiving queues RXQ_0-RXQ_1 are allocated to functional node 0; a total of 2 receiving queues RXQ_2-RXQ_3 are allocated to functional node 1; a total of 2 receiving queues RXQ_4-RXQ_5 are allocated to functional node 15.

[0110] For function node 0, its corresponding TXQ_0-TXQ_3, a total of 4 transmission queues, and RXQ_0-RXQ_1, a total of 2 reception queues are sequentially configured with interrupt vector identifiers (VeclID) 0-5; the same is true for function nodes 1 and 15.

[0111] Based on the above vector table configuration information, when the relevant configuration content is written to the MSI-X interrupt vector table RAM through the APB bus, only the queue assigned to any functional node will have its corresponding allocated table entry content rewritten, and the interrupt vector identifier corresponding to the queue will be written into the original storage subspace of the vector table entry, while the content in the original storage subspace corresponding to the unassigned queue will not be rewritten.

[0112] When initializing the MSI-X interrupt vector through the APB bus, apb_pfvf_id[31:24] in the vector table configuration information indicates the function node identifier (fid); apb_addr_offset[23:4] is the APB address offset, which is used to configure the interrupt vector identifier for multiple queues corresponding to the same function node. Combined with the configuration rules introduced in the above embodiment, the position (ram_addr) of each allocated table entry in the vector table, that is, the index of the sending queue (txq_index) and the index of the receiving queue (rxq_index) can be calculated, so as to initialize the corresponding vector table entry, and write the corresponding information in the first storage subspace corresponding to the specified vector table entry and the original storage subspace.

[0113] by Figure 2 Taking the 1024 sending queues and 1024 receiving queues shown as an example, the specific calculation logic is as follows:

[0114] TXQ: txdma_pfvf_cfg[fid]={1'b1,qnum,qbase};

[0115] The starting address is: txq_index_base=0+txdma_fid_qbase+0;

[0116] The end address is: txq_index_top=0+txdma_fid_qbase+qnum-1;

[0117] RXQ rule: rxdma_pfvf_cfg[fid]={1'b1,qnum,qbase};

[0118] The starting address is: rxq_index_base=1024+rxdma_fid_qbase+0;

[0119] The end address is: rxq_index_top=1024+rxdma_fid_qbase+qnum-1

[0120] Where qnum represents the number of queues of the corresponding type.

[0121] Accordingly, Figure 4 A schematic diagram of a computing logic example provided in an embodiment of the present disclosure, Figure 4 The content in is Figure 3 The configuration example given in the embodiment is specifically implemented under the above calculation logic. Among them, the calculation logic of the vector table entry that is not allocated is ignored by the hardware device.

[0122] The embodiment of the present disclosure reorganizes the storage space corresponding to each functional node to occupy as little RAM resources as possible while meeting the functional requirements of the hardware device. At the same time, the initialization method provided by the embodiment of the present disclosure only needs to reconfigure the corresponding vector table entry column according to the above logic when the correspondence between the functional node and the transceiver queue changes. The functional nodes are isolated from each other and are not affected by each other, which further improves the flexibility of the interrupt vector acquisition method.

[0123] On the basis of the above embodiment, the table lookup information includes a target function node identifier and a target interrupt vector identifier, and determining the target table entry in the vector table configuration result based on the table lookup information in the interrupt source input information includes: determining at least one allocated table entry corresponding to the target function node identifier according to the target function node identifier and the function node identifier stored in the first storage space; and searching for the target table entry from at least one allocated table entry corresponding to the target function node identifier according to the target interrupt vector identifier.

[0124] Corresponding to the calculation logic in the initialization process, when performing a table lookup operation based on the table lookup information in the interrupt source input information, first determine the target function node corresponding to the interrupt source input information, and then search the queue position where the target interrupt vector identifier is located from the multiple queues assigned to the target function node, that is, the vector table entry where the queue is located is the target vector table entry.

[0125] Specifically, the interrupt source input information of the IRQ Bus input includes rxdma_irq_* and txdma_irq_*, where *_irq_pfvfid[7:0] provides the target function node identifier of the interrupt source, and *_irq_vector[9:0] indicates the target interrupt vector identifier assigned to the interrupt source; the interrupt source input information also includes *_irq_valid, which is a single pulse signal, indicating that the interrupt input information is valid.

[0126] Wherein * represents the connection relationship between the meanings of the information items, for example, rxdma_irq_* and *_irq_pfvfid[7:0] provide the target function node identifier of the receive queue, and txdma_irq_* and *_irq_pfvfid[7:0] provide the target function node identifier of the transmit queue.

[0127] When the interrupt source input signal is valid, according to the IRQ bus signal definition, the vector table entry addresses txdma_ram_addr and rxdma_ram_addr of the corresponding queue in the interrupt vector table are found according to the established rules.

[0128] Likewise Figure 2 Taking the 1024 sending queues and 1024 receiving queues shown as an example, the specific search rules are:

[0129] txdma_ram_addr=0+txdma_fid_qbase+txdma_irq_vector

[0130] rxdma_ram_addr=1024+rxdma_fid_qbase+(rxdma_irq_vector-rxdma_fid_qnum)

[0131] Based on the above formula, the target table entry of the corresponding MSI-X interrupt vector can be quickly found in the interrupt vector table, and the interrupt vector content can be read out, and the interrupt request can be sent to the CPU through the corresponding interface.

[0132] The disclosed embodiment can quickly find the target table entry based on the interrupt source input information and read the interrupt vector content through the algorithm corresponding to the initialization process, thereby further improving the efficiency of the interrupt vector acquisition method.

[0133] Figure 5 The structure diagram of the interrupt vector acquisition device based on DPU provided in the embodiment of the present disclosure. The interrupt vector acquisition device may be a hardware device as described in the above embodiment, or the interrupt vector acquisition device may be a component or assembly in the hardware device. The interrupt vector acquisition device based on DPU provided in the embodiment of the present disclosure may execute the processing flow provided in the interrupt vector acquisition embodiment based on DPU, such as Figure 5As shown, the interrupt vector acquisition device 50 includes: an expansion module 51, an initialization module 52, a determination module 53, and a reading module 54; the expansion module 51 is used to expand a first storage space based on the original storage space corresponding to the vector table, the vector table includes multiple vector table items, and the first storage space is used to store the function node identifier corresponding to each of the vector table items; the initialization module 52 is used to initialize the original storage space and the first storage space according to the vector table configuration information to obtain the vector table configuration result; the determination module 53 is used to determine the target table item in the vector table configuration result based on the table lookup information in the interrupt source input information when receiving the interrupt source input information; the reading module 54 is used to read the interrupt vector content in the target table item.

[0134] Optionally, the original storage space is the product of the original width and the original depth of the vector table, the expansion module 51 is specifically used to increase a preset expansion width based on the original width, and the size of the first storage space is the product of the preset expansion width and the original depth.

[0135] Optionally, the vector table entries correspond one-to-one to the queues, the first storage space includes multiple first storage subspaces, the first storage subspaces correspond one-to-one to the vector table entries, and the initialization module 52 includes an acquisition unit 521, a determination unit 522, and a storage unit 523; the acquisition unit 521 is used to acquire vector table configuration information, the vector table configuration information includes at least one functional node identifier, a queue starting position corresponding to each functional node, and the number of queues; the determination unit 522 is used to determine, for each functional node identifier, at least one allocated table entry corresponding to the functional node from the multiple vector table entries according to the queue starting position and the number of queues; the storage unit 523 is used to store the functional node identifier in the first storage subspace corresponding to each of the allocated table entries.

[0136] Optionally, the queue starting position includes the sending queue starting position and the receiving queue starting position, the queue number includes the sending queue number and the receiving queue number, and the determination unit 522 is used to determine the allocated table entry corresponding to at least one sending queue based on the sending queue starting position and the sending queue number; determine the allocated table entry corresponding to at least one receiving queue based on the receiving queue starting position and the receiving queue number.

[0137] Optionally, the original storage space is used to store interrupt vector identifiers, and the initialization module 52 also includes an allocation unit 524, which is used to set the interrupt vector identifier for each sending queue corresponding to the allocated table entry corresponding to the starting position of the sending queue in turn; starting from the allocated table entry corresponding to the starting position of the receiving queue, the interrupt vector identifier is set for each receiving queue corresponding to the allocated table entry in turn; wherein the interrupt vector identifier of the last sending queue is adjacent to the interrupt vector identifier of the first receiving queue; or, the interrupt vector identifier of the last receiving queue is adjacent to the interrupt vector identifier of the first sending queue.

[0138] Optionally, the storage unit 523 is used for not writing into the first storage subspace corresponding to any vector table entry if the vector table entry is not an allocated table entry.

[0139] Optionally, the table lookup information includes a target function node identifier and a target interrupt vector identifier, and the determination module 53 is used to determine at least one allocated table entry corresponding to the target function node identifier based on the target function node identifier and the function node identifier stored in the first storage space; and according to the target interrupt vector identifier, search for the target table entry from the at least one allocated table entry corresponding to the target function node identifier.

[0140] Figure 5 The DPU-based interrupt vector acquisition device of the illustrated embodiment can be used to execute the technical solution of the above-mentioned method embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0141] Figure 6 The electronic device provided in the embodiment of the present disclosure may be a hardware device as described in the above embodiment. The electronic device provided in the embodiment of the present disclosure may execute the processing flow provided in the embodiment of the interrupt vector acquisition method based on the DPU, such as Figure 6 As shown, the electronic device 60 includes: a memory 61, a processor 62, a computer program and a communication interface 63; wherein the computer program is stored in the memory 61 and is configured so that the processor 62 executes the DPU-based interrupt vector acquisition method as described above.

[0142] In addition, an embodiment of the present disclosure further provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the DPU-based interrupt vector acquisition method described in the above embodiment.

[0143] In addition, an embodiment of the present disclosure further provides a computer program product, which includes a computer program or instructions, and when the computer program or instructions are executed by a processor, the DPU-based interrupt vector acquisition method as described above is implemented.

[0144] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0145] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A DPU-based interrupt vector acquisition method, characterized in that: The method is applied to a DPU chip, and the method comprises: Expanding a first storage space based on an original storage space corresponding to a vector table, wherein the vector table includes a plurality of vector table entries, and the first storage space is used to store a function node identifier corresponding to each of the vector table entries; Initialize the original storage space and the first storage space according to the vector table configuration information to obtain a vector table configuration result; When interrupt source input information is received, determining a target table entry in the vector table configuration result based on table lookup information in the interrupt source input information; Read the interrupt vector content in the target table entry.

2. The method according to claim 1, characterized in that: The original storage space is the product of the original width and the original depth of the vector table, and the first storage space is expanded based on the original storage space corresponding to the vector table, including: A preset extended width is added on the basis of the original width, and the size of the first storage space is the product of the preset extended width and the original depth.

3. The method according to claim 1, characterized in that: The vector table entries correspond to the queues one by one, the first storage space includes a plurality of first storage subspaces, the first storage subspaces correspond to the vector table entries one by one, and the original storage space and the first storage space are initialized according to the vector table configuration information to obtain a vector table configuration result, including: Acquire vector table configuration information, where the vector table configuration information includes at least one function node identifier, a queue start position corresponding to each function node, and the number of queues; For each functional node identifier, determining at least one allocated table entry corresponding to the functional node from the multiple vector table entries according to the queue starting position and the number of queues; The function node identifier is stored in a first storage subspace corresponding to each of the allocated entries.

4. The method according to claim 3, characterized in that The queue starting position includes a sending queue starting position and a receiving queue starting position, the number of queues includes a sending queue number and a receiving queue number, and for each functional node identifier, determining at least one allocated table entry corresponding to the functional node from the multiple vector table entries according to the queue starting position and the queue number, including: Determine, according to the starting position of the sending queue and the number of the sending queues, an allocated table entry corresponding to at least one sending queue; According to the starting position of the receiving queue and the number of the receiving queues, an allocated table entry corresponding to at least one receiving queue is determined.

5. The method according to claim 4, characterized in that The original storage space is used to store the interrupt vector identifier, and the method further includes: Starting from the allocated table entry corresponding to the starting position of the sending queue, sequentially setting an interrupt vector identifier for the sending queue corresponding to each of the allocated table entries; Starting from the allocated table entry corresponding to the start position of the receiving queue, sequentially setting an interrupt vector identifier for the receiving queue corresponding to each of the allocated table entries; The interrupt vector identifier of the last transmit queue is adjacent to the interrupt vector identifier of the first receive queue; or The interrupt vector identifier of the last receive queue is adjacent to the interrupt vector identifier of the first transmit queue.

6. The method according to claim 4, characterized in that The storing the function node identifier into the first storage subspace corresponding to each of the allocated entries includes: For any vector table entry, if the vector table entry is not an allocated table entry, the first storage subspace corresponding to the vector table entry is not written.

7. The method according to claim 5, characterized in that The table lookup information includes a target function node identifier and a target interrupt vector identifier, and determining a target table entry in the vector table configuration result based on the table lookup information in the interrupt source input information includes: Determine, according to the target function node identifier and the function node identifiers stored in the first storage space, at least one allocated table entry corresponding to the target function node identifier; According to the target interrupt vector identifier, a target table entry is searched from at least one allocated table entry corresponding to the target function node identifier.

8. A DPU-based interrupt vector acquisition device, characterized in that: include: An expansion module, used to expand a first storage space based on an original storage space corresponding to a vector table, wherein the vector table includes a plurality of vector table entries, and the first storage space is used to store a function node identifier corresponding to each of the vector table entries; An initialization module, used to initialize the original storage space and the first storage space according to the vector table configuration information to obtain a vector table configuration result; A determination module, configured to determine a target table entry in the vector table configuration result based on table lookup information in the interrupt source input information when interrupt source input information is received; The reading module is used to read the interrupt vector content in the target table entry.

9. An electronic device, characterized in that: include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and is configured to be executed by the processor to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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