FPGA satellite signal management information inter-chip interaction system
By designing an inter-chip interaction system for FPGA satellite signal management information, using the combination of data conversion, reception management and framing modules, the data diversity and complexity problems in multi-chip FPGA signal interaction are solved, and efficient and simplified signal interaction is achieved.
Patent Information
- Application Number
- CN202411556498.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-02-28
AI Technical Summary
In FPGA development, when signal interaction between multiple FPGAs, existing communication protocols such as SPI, UART and IIC have data diversity and complexity problems, making it difficult to achieve efficient signal interaction.
A FPGA satellite signal management information inter-chip interaction system is designed. Through multiple FPGA chips connected from top to bottom, a data conversion module, a data reception management module and a data framing module are used to realize parallel and serial signal processing, double-wire connection is used to reduce pin resources, and data management is used to reference the IIC addressing mechanism.
It realizes efficient signal interaction between FPGAs, saves pin resources, avoids synchronization timing problems, simplifies FPGA implementation, and improves modularity and portability.
Smart Images
Figure CN119537292A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of information interaction transmission, and in particular to an FPGA satellite signal management information inter-chip interaction system. Background Art
[0002] FPGA pin IO can only output high and low levels, and then use high level to represent data 1 information, and low level to represent data 0 information. For example, the FPGA pin outputs a voltage value of 3.3V / 1.8V to represent a high level and 1, and an output level of 0V represents a low level, that is, the digital circuit can only output and send binary 0 and 1 data. All network communication protocols, their underlying operating logic is to send and receive binary data 0 and 1. Because the data sent are 0 and 1 data, the task of receiving and parsing the signal is more complicated. To solve this problem, the signal can only be sent and received in a prescribed manner, which is what we often call a communication protocol.
[0003] For example, in the process of implementing signal transmission in FPGA, it is often encountered that the signal and the signal address information are transmitted together. Data[7:0] transmits 1 byte of data, Addr[14:0] is the address corresponding to the data, and End is a signal that is valid when the last byte is transmitted. The transmission of this signal can be completed according to common communication protocols, such as SPI, Uart, I2C, etc.
[0004] The commonly used communication protocols in FPGA handle signal interaction and the advantages and disadvantages of using this protocol. In the process of FPGA development, multiple FPGAs are often developed at the same time to complete a project. When exchanging status signals, SPI protocol (full name: Serial Peripheral Interface; abbreviated: SPI) or UART protocol (full name: Universal Asynchronous Receiver and Transmitter; abbreviated: UART) or IIC protocol (full name: Inter Integrated Circuit; abbreviated: IIC) are often used to exchange status signals between FPGA chips.
[0005] SPI is a high-speed, full-duplex, synchronous serial communication bus suitable for signal data exchange between multiple FPGA chips. SPI has the advantages of flexible data transmission and simultaneous data exchange between multiple devices, but time synchronization is a problem for simultaneous signal exchange between multiple chips; and there is no response mechanism to confirm whether the transmission signal has been completely received; and there are too many interfaces used at the same time.
[0006] UART is a universal asynchronous receiving and transmitting interface protocol. The interface does not need to share the same clock, but only needs the clock frequency of both communicating parties to be consistent during the transmission process. UART is asynchronous, avoiding the synchronization problem of multi-chip signal interaction time, using fewer pins, and has the advantage of response; but the interactive data needs to be managed separately, the versatility is poor, and different forms of data require different protocols.
[0007] IIC is a synchronous (with a clock bus that needs to synchronize the clock SCL), serial (sent one bit at a time in one direction) communication bus; IIC has the advantages of addressing function, less pin usage, and response; but the interactive data needs to be managed separately and the logic is complex. Summary of the invention
[0008] In view of the above-mentioned deficiencies in the prior art, the present invention provides an FPGA satellite signal management information inter-chip interaction system.
[0009] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is:
[0010] An FPGA satellite signal management information chip interaction system, comprising:
[0011] Multiple FPGA chips connected by two wires from top to bottom;
[0012] The upper FPGA chip includes a data conversion module and a data receiving management module; the bottom FPGA chip includes a data receiving management module and a data framing module; the data conversion module is used to cache the pulse signal containing the transmission data information, and when receiving the next level control permission signal to be pulled high, combine the pulse signal and the corresponding address of the pulse signal, and send the parallel-to-serial conversion; the data receiving management module is used to manage the parallel-to-serial conversion reception of different data conversion modules, and select and control the pulse signal transmission of different data conversion modules to the next level; the data framing module is used to perform serial-to-parallel operations on the pulse signal, and send data information after data framing according to the corresponding address of the pulse signal.
[0013] In a possible implementation manner, the pulse signal containing the transmission data information is specifically:
[0014] When the transmitted data information is 0, 10 high-level pulse signals are used to represent it, and when the transmitted data information is 1, 20 high-level pulse signals are used to represent it. The end bit information of the data information is represented by 40 clock units, and the last bit of the data information is represented by 30 high-level pulse signals.
[0015] In a possible implementation, each bit of data in the data information includes a corresponding address and a control signal indicating the end of the signal.
[0016] In a possible implementation, the data conversion module performs parallel-to-serial conversion as follows:
[0017] Starting from the low bit of the data, the conversion process is first expressed using 40 clocks as a digital symbol. The high level of 10 clocks represents 0, the high level of 20 clocks represents 1, and the high level of 30 clocks represents the last stop signal. When the last byte of data information is transmitted, the end enable signal is pulled high as the enable signal for the completion of the transmission.
[0018] In a possible implementation, the data conversion module includes:
[0019] Random access memory, registers, signal selection unit and state machine.
[0020] In a possible implementation, the data receiving management module includes:
[0021] Signal selection unit and state machine.
[0022] In a possible implementation, the data framing module includes:
[0023] State machine and framing management unit.
[0024] In a possible implementation, the frame management unit includes:
[0025] Random access memory and state machine.
[0026] The present invention has the following beneficial effects:
[0027] 1. Use two signal lines to complete the signal data interaction task, saving the scarce pin resources of FPGA;
[0028] 2. There will be no problems such as synchronization timing;
[0029] 3. Use the principle of IIC addressing slave to correspond each byte of data to the corresponding address, which is convenient for overall data management;
[0030] 4. FPGA is easy to implement;
[0031] 5. Easy to modularize and highly portable. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It is a schematic diagram of the structure of an FPGA satellite signal management information chip interaction system;
[0033] Figure 2 It is a schematic diagram of the principle of an FPGA satellite signal management information chip interaction system;
[0034] Figure 3 It is a schematic diagram of control signal;
[0035] Figure 4 A schematic diagram of an FPGA satellite signal management information chip interaction system architecture;
[0036] Figure 5 This is a schematic diagram of the data conversion module architecture;
[0037] Figure 6 It is a schematic diagram of the state machine of the data conversion module;
[0038] Figure 7 This is a schematic diagram of the data receiving management module architecture;
[0039] Figure 8 This is a schematic diagram of the state machine of the data receiving management module;
[0040] Fig. 9 This is a schematic diagram of the data framing module architecture;
[0041] Fig.10 It is a schematic diagram of the state machine of the data framing module;
[0042] Fig.11 This is a schematic diagram of the frame management unit architecture;
[0043] Fig.12 It is a schematic diagram of the state machine of the framing management unit;
[0044] Fig.13 This is the first bit transmission simulation diagram of the data conversion module;
[0045] Fig.14 This is the simulation diagram of the first byte transmission of the data conversion module;
[0046] Fig.15 It is a simulation diagram of a frame of data transmission of the data conversion module;
[0047] Fig.16 This is the first bit transmission simulation diagram of the data receiving management module;
[0048] Fig.17 It is a simulation diagram of a frame of data transmission of the data receiving management module;
[0049] Fig.18 This is the simulation diagram of the first byte received by the data framing module;
[0050] Fig.19 A simulation diagram of a frame of data receiving for the data framing module;
[0051] Fig. 20 Simulate the starting graph for the data framing module;
[0052] Fig.21 This is a simulation diagram of a complete frame of data for the data framing module. DETAILED DESCRIPTION
[0053] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.
[0054] like Figure 1 As shown, an embodiment of the present invention provides an FPGA satellite signal management information chip interaction system, including:
[0055] Multiple FPGA chips connected by two wires from top to bottom;
[0056] The upper FPGA chip includes a data conversion module and a data receiving management module; the bottom FPGA chip includes a data receiving management module and a data framing module; the data conversion module is used to cache the pulse signal containing the transmission data information, and when receiving the next level control permission signal to be pulled high, combine the pulse signal and the corresponding address of the pulse signal, and send the parallel-to-serial conversion; the data receiving management module is used to manage the parallel-to-serial conversion reception of different data conversion modules, and select and control the pulse signal transmission of different data conversion modules to the next level; the data framing module is used to perform serial-to-parallel operations on the pulse signal, and send data information after data framing according to the corresponding address of the pulse signal.
[0057] In an optional embodiment of the present invention, the pulse signal containing the transmission data information is specifically:
[0058] When the transmitted data information is 0, 10 high-level pulse signals are used to represent it, and when the transmitted data information is 1, 20 high-level pulse signals are used to represent it. The end bit information of the data information is represented by 40 clock units, and the last bit of the data information is represented by 30 high-level pulse signals.
[0059] This embodiment uses pulse signals as signal information that carries digital data 0 and 1, and redefines digital information 0 and 1 in discrete digital pulse signals. That is, when the transmitted data information is 0, 10 (self-defined) high-level pulse signals are used to represent it, and when the transmitted data information is 1, 20 (self-defined) high-level pulse signals are used to represent it, and the end bit information of the signal information is represented by 40 (self-defined) clock units, and the last bit of the signal information (specific position information) is represented by 30 (self-defined) high-level pulse signals. Representing the transmitted digital information by means of pulse signals can effectively improve the stability and accuracy of data transmission, and the efficiency of data information is also met through effective data management.
[0060] The present invention can solve the data diversity and complexity problems that occur during signal interaction. The system principle is as follows: Figure 2 The communication protocol of the present invention is to edit the data when sending a group of data, and each byte of data corresponds to the corresponding address and the control signal of the end of the submodule signal, such as Figure 3 shown.
[0061] In an optional embodiment of the present invention, the data receiving management module performs parallel-to-serial conversion specifically as follows:
[0062] Starting from the low bit of the data, the conversion process is first expressed using 40 clocks as a digital symbol. The high level of 10 clocks represents 0, the high level of 20 clocks represents 1, and the high level of 30 clocks represents the last stop signal. When the last byte of data information is transmitted, the end enable signal is pulled high as the enable signal for the completion of the transmission.
[0063] The present invention is designed in a top-down modular design, such as Figure 4 As shown. The data conversion module performs parallel-to-serial conversion on the data signal during transmission. Starting from the low bit of the data, the change process is first expressed as a digital symbol using 40 clocks. The high level of 10 clocks represents 0, the high level of 20 clocks represents 1, and the high level of 30 clocks represents the last stop signal. When the last byte of the signal data transmitted by each submodule is reached, the end enable signal is pulled high as the enable signal for the completion of the transmission. The data is transmitted to the next level through the signal line Data, and finally the data and the address corresponding to the data are converted and restored.
[0064] In an optional embodiment of the present invention, the data conversion module includes:
[0065] Random access memory, registers, signal selection unit and state machine.
[0066] Data conversion modules such as Figure 5As shown, it mainly realizes signal caching and signal parallel-to-serial transmission. The signal is cached through RAM. When the next-level control permission signal Take is pulled high, the signal and the corresponding address of the signal are combined through the state machine, and the parallel-to-serial transmission is performed. Data1, Addr, and En1 data are stored in RAM; Data2, Addr3, and En3 data are stored in registers; and are transmitted to the state machine through SEL selection. State machine logic: data framing {data end bit, data corresponding byte address information, data}, and then sent through the state machine.
[0067] The data conversion module state machine is as follows Figure 6 As shown. State machine: S0|S1|S2 receives the Take start signal and performs data framing; S3 sends data (signal from low to high); S4 determines what the sending signal is and then performs the corresponding state logic; S5 performs the state when sending 1 data; S6 performs the state when sending 0 data; S8|S10|S11 performs the state when the last bit of the data after framing is 0; S7|S12 performs the state when the last bit of the data after framing is 1, that is, a group of data is transmitted and returns to zero; S9 converts the state after transmitting 1 bit of data.
[0068] In an optional embodiment of the present invention, the data receiving management module includes:
[0069] Signal selection unit and state machine.
[0070] Data receiving management module such as Figure 7 As shown, its main function is to complete the parallel-to-serial conversion reception management of different StatusSource modules, and select and control the information transmission of different sub-modules StatusSourc to the next level through the state machine. Figure 5 The converted data is managed in this combination for transmission: Data1|Data2|Datan are data of different inputs; Take1|Take2|Taken respectively control the data input enable signals; Ctake[Idx]|Cdata[Idx] signals are the signals during transmission; STake transmits the enable signal, and SData transmits the data signal.
[0071] The data receiving management module state machine is as follows Figure 8 As shown. State machine: S0 receiving end receives STake permission signal to proceed Figure 7 The data selection and sending management function; the S1 state waits for the start of data transmission; the S2|S3 state performs data transmission; the S4 state is after transmitting a byte of data; the S5 state waits.
[0072] In an optional embodiment of the present invention, the data framing module includes:
[0073] State machine and framing management unit.
[0074] Data framing module such as Fig. 9 As shown in the figure, its main function is to realize serial-to-parallel conversion and data arrangement; restore serial data, frame the data at the address position corresponding to the data, and transmit the data information after framing. Data inputs the signal, Take sends the permission signal; RamData|RamEn state machine outputs data and enables; Manager module reassembles the data corresponding to the address into the frame structure required by the user to output data and enable.
[0075] The data framing module state machine is as follows Fig.10 As shown in the figure, S0 issues an idle command after the previous data transmission is completed; S1 starts to receive data and turns off the idle command; S2 determines the data operation status; S3 transmits data 0; S4 transmits data 1; and S5 transmits the last bit of data. Fig.10 The output data is used as RamData|RamEn input data and data enable; the data is stored in RAM corresponding to the data address; the state machine is used to read the data and frame it to send it out.
[0076] In an optional embodiment of the present invention, the frame management unit includes:
[0077] Random access memory and state machine.
[0078] Frame management unit Fig.11 As shown, it stores the data and the address corresponding to the data in the RAM, and then uses the state machine to control the RAM to read and frame.
[0079] The state machine of the framing management unit is as follows Fig.12 As shown. The S0 state waits for the trigger signal, and the trigger signal Trigger_En turns on the state to send the framing function; S1 sends the frame header; S2 sends the clock information; S3|S4|S5|S6|S7|S8|S9 states are all reading the data in RAM and framing and sending it.
[0080] The FPGA chip used in the present invention is Xilinx xcku060-ffva1156-2-i (active), and the design code uses the hardware description language Verilog. Signal communication interaction plays a very critical role in FPGA, and the complex and diverse signal interaction between a large number of FPGAs is a hot topic in the system. The technical protocol implementation environment is carried out in 9 FPGAs. The project also needs to summarize and process the information that each FPGA needs to interact with. The nine FPGAs are named F1, F2 to F9 respectively, and the signals from F2 to F9 need to be transmitted to F1 for data aggregation and framing.
[0081] The present invention plays a very good role in this environment. The information exchange between each FPGA only uses two lines to interact, which greatly reduces the application of FPGA pins and the use of resources. At the same time, it solves the timing synchronization problem between transmissions. The module design method used in this patent also has great advantages in code transplantation and management, and plays a role in accurately and efficiently transmitting data.
[0082] The design of the present invention adopts a top-down module design method. Each FPGA uses the StatusSource module to convert the signal to be transmitted into a serial signal, and then manages the transmission between FPGA chips through the serial transmission management module StatusCombin. The method of FPGA9 is used to transmit to FPGA8, then to FPGA7, and finally to FPGA1. FPGA1 uses the StatusCombin module for receiving management, and then uses the StatusTransFrame module to perform serial-to-parallel and framing operations.
[0083] The development environment uses Xilinx's Vivado 2019.1 for design development and simulation verification. The following is an explanation of the verification simulation diagram of each module when implementing this patent design.
[0084] The data conversion module performs encoding simulation according to the above state machine, and the results are as follows Fig.13 As shown:
[0085] In the first bit transmission simulation diagram, data is transmitted starting from the low bit. The following simulation diagram shows the case where the transmission bit value is 0, and the Data signal is the output signal.
[0086] The first byte transmission simulation diagram shows that data transmission is performed byte by byte, and its corresponding address and end signal are combined and then transmitted in parallel to serial. Fig.14 As shown, a total of 24 bits represent one byte of information.
[0087] A frame of data transmission simulation diagram, data transmission is carried out according to the amount of data that needs to be transmitted. After each transmission, the terminal information is pulled high to tell the next level module that the transmission is completed and the parallel-to-serial conversion of other modules can be carried out. Fig.15 Shown is a simulation diagram of completing a set of data parallel-to-serial conversion transmission.
[0088] The data receiving management module transmits and manages the first bit transmission simulation diagram. The data receiving management module controls the progress of each channel transmission by the length of the terminal signal being pulled high, and cyclically reads the data signal of the conversion module and transmits it to the next level receiving module. Fig.16 The figure shows the simulation diagram when the data receiving management module receives the first bit.
[0089] Transmission management of a frame of data simulation diagram, such as Fig.17 Shown is a simulation diagram of the data receiving management module after transmitting a group of data.
[0090] The data framing module serializes and receives the first byte of the simulation diagram, and receives the signal of the data receiving management module for serialization and translation. Each byte of data corresponds to a 24-bit signal, which contains 1 bit of end information, 15 bits of bytes corresponding to address information, and 8 bits of data information. Fig.18 The data transmission of 1 byte is shown.
[0091] The simulation diagram of serial conversion and receiving a frame of data is as follows: Fig.19 The following is a simulation diagram of a set of completed data transmissions.
[0092] The data framing module simulates the starting diagram, stores the serial data in RAM, and then reads the data from RAM at a fixed time and frames it. The data is sent out in the form of a frame structure, and the data is organized to facilitate information query. Fig. 20 Shown is a frame header simulation diagram of the framing.
[0093] The data framing module completes a frame of data simulation diagram, such as Fig.21 shown.
[0094] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0095] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0096] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0097] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
[0098] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.
Claims
1. An FPGA satellite signal management information chip interaction system, characterized in that: include: Multiple FPGA chips connected by two wires from top to bottom; The upper FPGA chip includes a data conversion module and a data receiving management module; the bottom FPGA chip includes a data receiving management module and a data framing module; the data conversion module is used to cache the pulse signal containing the transmission data information, and when receiving the next level control permission signal to be pulled high, combine the pulse signal and the corresponding address of the pulse signal, and send the parallel-to-serial conversion; the data receiving management module is used to manage the parallel-to-serial conversion reception of different data conversion modules, and select and control the pulse signal transmission of different data conversion modules to the next level; the data framing module is used to perform serial-to-parallel operations on the pulse signal, and send data information after data framing according to the corresponding address of the pulse signal.
2. The FPGA satellite signal management information chip interaction system according to claim 1, characterized in that: The pulse signal containing the transmission data information is specifically: When the transmitted data information is 0, 10 high-level pulse signals are used to represent it, and when the transmitted data information is 1, 20 high-level pulse signals are used to represent it. The end bit information of the data information is represented by 40 clock units, and the last bit of the data information is represented by 30 high-level pulse signals.
3. The FPGA satellite signal management information chip interaction system according to claim 1, characterized in that: Each bit of data in the data information includes a corresponding address and a control signal for signal end.
4. The FPGA satellite signal management information chip interaction system according to claim 1, characterized in that: The data conversion module performs parallel-to-serial conversion specifically as follows: Starting from the low bit of the data, the conversion process is first expressed using 40 clocks as a digital symbol. The high level of 10 clocks represents 0, the high level of 20 clocks represents 1, and the high level of 30 clocks represents the last stop signal. When the last byte of data information is transmitted, the end enable signal is pulled high as the enable signal for the completion of the transmission.
5. The FPGA satellite signal management information chip interaction system according to claim 1, characterized in that: The data conversion module comprises: Random access memory, registers, signal selection unit and state machine.
6. The FPGA satellite signal management information inter-chip interaction system according to claim 1, characterized in that: The data receiving management module comprises: Signal selection unit and state machine.
7. The FPGA satellite signal management information chip interaction system according to claim 1, characterized in that: The data framing module comprises: State machine and framing management unit.
8. The FPGA satellite signal management information chip interaction system according to claim 7, characterized in that: The frame management unit comprises: Random access memory and state machine.