Standard unit generation method and related equipment

Abstract

The invention discloses a standard unit generation method and related equipment. The standard unit generation method comprises the steps that a process file of a target process and behavior description of a standard unit needing to be generated are read; generating an adapter corresponding to the bottom-layer tool for the bottom-layer tool needing to be called; according to the target requirement and the target process of the standard unit, an execution strategy is determined, and the execution strategy is a combination of multi-level parameters related to the standard unit; and calling the underlying tool through the adapter to enable the underlying tool to execute according to each level of parameter in the execution strategy, the process file and the behavior description, and generating the standard unit. According to the technical scheme of the embodiment of the invention, the problems of complicated process, complicated tools, long development process and the like of standard unit development can be solved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and more specifically, to a standard cell generation method and related equipment. Background Art

[0002] With the continuous evolution of semiconductor technology, chip manufacturing processes are moving towards smaller feature sizes. FinFET technology has emerged and has become a key technology for modern integrated circuit manufacturing. FinFET technology emerged to overcome the limitations of traditional planar processes. Although its three-dimensional fin transistors improve performance and power consumption, they bring challenges to STD Cell development.

[0003] In terms of process, FinFET has a complex structure, difficult electrical characteristics analysis, and high manufacturing precision requirements, which affects unit performance and is not easy to coordinate process and physical implementation. EDA tools are complicated, and the functions, formats, and operations of tools in each link from logic to verification are different, making collaboration difficult and data conversion and adaptation cumbersome. The development process is serial and long, and each link is interdependent. If an error occurs in one link, it needs to be traced back, such as the iteration of physical design and timing analysis, which prolongs the cycle. Development is also highly dependent on expert experience. Due to the complexity of the process, experts need to weigh transistor parameters and be proficient in tools and processes, which not only raises the technical threshold, but also limits the size and efficiency of the team. In short, the problems faced by STDCell development in FinFET process, such as complex process, complicated EDA tools, long development process, and reliance on senior expert experience, need to be solved urgently. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present application proposes a standard cell generation method, comprising: Read the process file of the target process and the behavior description of the standard unit to be generated; For the underlying tool that needs to be called, generate an adapter corresponding to the underlying tool; Determining an execution strategy according to the target requirements of the standard cell and the target process, wherein the execution strategy is a combination of multiple levels of parameters related to the standard cell; The underlying tool is called through the adapter so that the underlying tool is executed according to the various levels of parameters in the execution strategy, the process file and the behavior description to generate the standard unit.

[0006] In a feasible implementation, an execution strategy is determined based on the target requirements of the standard unit generated as needed and the target process, including: determining first-level strategy parameters according to the target requirements of the standard unit generated as needed; determining second-level design parameters according to the first-level strategy parameters and the target process; determining third-level tool parameters of the underlying tool according to the first-level strategy parameters and the second-level design parameters, and using a combination of the first-level strategy parameters, the second-level design parameters and the third-level tool parameters as the execution strategy.

[0007] In a feasible implementation, for the underlying tool that needs to be called, an adapter corresponding to the underlying tool is generated, including: generating a corresponding script language for the underlying tool that needs to be called; encapsulating the script language to obtain an encapsulation body corresponding to the script language, and establishing an adapter corresponding to the underlying tool based on the encapsulation body.

[0008] In a feasible implementation, the method further includes: during the execution of the underlying tool, caching the output corresponding to each execution node, and if an error occurs in the current execution node, rolling back to the previous execution node based on the output corresponding to the previous execution node.

[0009] In a feasible implementation manner, during the execution of the underlying tool, if an alarm occurs, an alarm message is generated and the alarm message is recorded in a log file so that a user can view the alarm message.

[0010] In a feasible implementation, the method further includes: obtaining a result file corresponding to the standard unit, the result file being a file generated by the underlying tool executing according to the execution strategy and the process file; performing unified management operations on the result file, the unified management operations including inspection and verification operations, dynamic adjustment operations of read and write permissions, file flow management operations, and oversized text optimization operations.

[0011] In a feasible implementation manner, the method further includes: if the satisfaction rate of the generated standard unit for the target requirement exceeds a preset threshold, saving the execution strategy as a default strategy in a strategy library to update the strategy library.

[0012] In a second aspect, the present application proposes a standard cell generation device, comprising: A reading unit, configured to read a process file of a target process and a behavior description of a standard unit to be generated; A generating unit, configured to generate an adapter corresponding to the underlying tool that needs to be called; a determination unit configured to determine an execution strategy according to a target requirement of the standard cell and the target process, wherein the execution strategy is a combination of multiple levels of parameters related to the standard cell; The calling unit is configured to call the underlying tool through the adapter, so that the underlying tool is executed according to the various levels of parameters in the execution strategy, the process file and the behavior description to generate the standard unit.

[0013] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the standard unit generation method of any one of the first aspects described above when executing the computer program stored in the memory.

[0014] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the standard unit generation method of any one of the first aspects is implemented.

[0015] In summary, the technical solution proposed in this application, by reading the process files and the behavioral description of the standard unit to be generated, enables the underlying tools to accurately process the process information and design requirements with the help of adapter conversion, and effectively cope with the complexity of the process; generates corresponding adapters for complex underlying tools, converts the execution strategy into the format required by the underlying tools, realizes seamless docking and collaboration, and reduces the difficulty caused by tool differences; determines the execution strategy of multi-level parameter combinations according to the target process and target requirements, and calls the underlying tools to execute accordingly through the adapter, optimizes the development path, avoids trial and error, and significantly shortens the development process; and the solution standardizes and automates the process, reduces dependence on the experience of senior experts, and allows inexperienced engineers to work according to the process, reduces manpower dependence, promotes knowledge sharing, and reduces the risk of personnel turnover, and comprehensively solves the many problems faced by standard unit development. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 A schematic diagram of an exemplary system used in an embodiment of the present application.

[0017] Figure 2 A schematic diagram of the process of generating a standard cell provided in an embodiment of the present application.

[0018] Figure 3A schematic diagram of the process of generating a standard cell provided in an embodiment of the present application.

[0019] Figure 4 A schematic diagram of the process of generating a standard cell provided in an embodiment of the present application.

[0020] Figure 5 A schematic diagram of the structure of a standard cell generation device provided in an embodiment of the present application.

[0021] Figure 6 A schematic diagram of a standard unit generating electronic device structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0023] First, some nouns or terms that appear in the process of describing the embodiments of the present application are subject to the following explanations.

[0024] FinFET process: FinFET process is an advanced semiconductor manufacturing process. FinFET (Fin Field-Effect Transistor) refers to fin field-effect transistors. In this process, a raised fin-shaped structure is manufactured on the substrate as the channel of the transistor, and the gate surrounds the three sides of the fin. This unique three-dimensional structure can more effectively control the current in the channel, reduce leakage, and significantly improve device performance and integration. It is widely used in advanced processes and is one of the key process technologies for achieving smaller size, higher performance, and lower power consumption in modern integrated circuit manufacturing.

[0025] Standard Cell: Standard Cell (STDCell) refers to a basic unit module with certain logical functions that has been pre-designed, optimized and exists in a specific layout form, such as AND gate, OR gate, NOT gate, trigger, etc. These standard cells have fixed sizes and electrical characteristics, and they are widely used in very large-scale integrated circuit (VLSI) design. Designers can select appropriate cells from the existing standard cell library according to the functional requirements of the circuit, and combine and connect them according to certain rules, so as to quickly build a complex integrated circuit system.

[0026] Low-level tools: Electronic Design Automation (EDA) tools refer to the basic software tool set used to support integrated circuit (IC) and electronic system design. These tools help engineers automate and optimize the design process, including all stages from circuit design, verification to manufacturing preparation. They usually include circuit design tools, simulation tools, synthesis tools, layout and routing tools, verification tools, and manufacturing preparation tools.

[0027] Adapter: In computer system architecture, it is a software component whose main function is to enable two incompatible interfaces to work together. It is like a converter or translator that can build a bridge of communication between different systems, software, protocols or data formats.

[0028] Figure 1 An exemplary system for the method for generating a standard cell applicable to an embodiment of the present application is shown. Figure 1 As shown, the system 100 may include a server 102 , a communication network 104 , and a terminal device 106 .

[0029] The communication network 104 may be any suitable combination of one or more wired and / or wireless networks. For example, the communication network 104 may include any one or more of the following: the Internet, an intranet, a wide area network (WAN), a local area network (LAN), a wireless network, a digital subscriber line (DSL) network, a frame relay network, an asynchronous transfer mode (ATM) network, a virtual private network (VPN), and / or any other suitable communication network.

[0030] The server 102 may be an independent physical server, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms. The terminal device 106 may refer to a user-oriented terminal device, specifically a smart phone, tablet computer, portable personal computer, desktop computer, smart speaker, smart watch, bracelet, smart TV, and other smart devices.

[0031] The standard unit generation method provided in the embodiment of the present application is generally executed by the server 102, and accordingly, the standard unit generation device is generally set in the server 102. The bottom-level tool is installed in the server 102 and relies on the server's resources (such as CPU, memory) to work. The adapter also works in the server 102 to convert requests and responses between the upper-level application (terminal device 106) and the bottom-level tool.

[0032] It should be understood that Figure 1 The number of terminal devices, networks and servers in the embodiment is only illustrative, and any number of terminal devices, networks and servers may be provided according to the implementation requirements. For example, server 102 may be a server cluster consisting of multiple servers. Multiple servers may include, for example, a configuration management server, a GPU acceleration server and a storage server. The configuration management server is mainly responsible for managing various configuration information in the integrated circuit design process, the GPU acceleration server is used to accelerate the computationally intensive tasks in the integrated circuit design, and the storage server provides large-capacity, high-performance data storage support for the entire integrated circuit design process.

[0033] The embodiment of the present application mainly focuses on the process of the server 102 generating a standard unit, and the standard unit generating process will be described in detail hereinafter.

[0034] See also Figure 2 , is a schematic diagram of a process of generating a standard cell provided in an embodiment of the present application, the method comprising steps S210 to S240: Step S210, reading the process file of the target process and the behavior description of the standard unit to be generated; Step S220: Generate an adapter corresponding to the underlying tool for the underlying tool that needs to be called; Step S230, determining an execution strategy according to the target requirement of the standard cell and the target process, wherein the execution strategy is a combination of multiple levels of parameters related to the standard cell; Step S240: calling the underlying tool through the adapter so that the underlying tool is executed according to the various levels of parameters in the execution strategy, the process file and the behavior description to generate the standard unit.

[0035] These steps are described in detail below.

[0036] In step S210 , a process file of a target process and a behavior description of a standard cell to be generated are read.

[0037] The target process in this embodiment may be a FinFET process, which is an advanced semiconductor manufacturing process. FinFET (Fin Field-Effect Transistor) refers to a fin field-effect transistor. In this process, a raised fin-shaped structure is manufactured on a substrate as a channel of the transistor, and the gate surrounds three sides of the fin. This unique three-dimensional structure can more effectively control the current in the channel, reduce leakage, and significantly improve device performance and integration.

[0038] The process files of the target process refer to all the process files required to generate standard cells under the target process, including but not limited to Process Design Kit (PDK), Resistance-Capacitance (RC), Library Exchange Format (LEF), Interconnect Technology File (ITF), Integrated Circuit Test (ICT) and Circuit Description Language (CDL).

[0039] Under FinFET process, PDK, RC, LEF, ITF, ICT and CDL files have specific content and characteristics to adapt to the unique requirements of FinFET structure. Among them, PDK contains design rules, models, library files and other information for specific semiconductor processes; RC mainly refers to the resistance and capacitance between each metal connection and FinFET device in the chip; LEF is a standard format for describing the physical information of the unit library based on FinFET process, which contains the layout information of FinFET standard units (such as NAND gates, NOR gates and other logic units), such as the unit's boundary size, pin position, metal layer usage and the connection relationship between layers; ITF files are usually used to describe the interface information between different design tools or different FinFET-based design modules, including signal name, signal direction, signal electrical characteristics (such as voltage, current range, etc.) and protocol-related information; ICT mainly involves the connection method and technology between different FinFET devices inside the chip, including metal interconnection materials, interconnection structures, interconnection processes and many other aspects; CDL is a language used to describe the circuit structure of integrated circuits containing FinFET transistors in text form. It can describe the components in the circuit (such as FinFET transistors, resistors, capacitors, etc.) and the connection relationship between them.

[0040] The behavior description of the standard cell that needs to be generated here focuses on the design file level of the standard cell. Like the Verilog file, it is a file written in a hardware description language, which is used to describe the logical function and structure of the digital circuit, and is a design description of the standard cell from a logical perspective; the SDC (Synopsys Design Constraints) file is mainly used to define various design constraints, such as clock frequency, timing requirements, etc., and to standardize the performance of the standard cell in terms of time-related characteristics; the UPF (Unified Power Format) file focuses on describing and setting the power consumption-related characteristics of the standard cell, such as power consumption requirements under different working modes. In general, these design files describe the "behavior" of the standard cell in detail from different aspects (logic, timing, power consumption, etc.), that is, how it should work, what rules it should follow, what performance characteristics it should have, etc. In the process of generating standard cells, these files are indispensable and important references and bases, which can help accurately create standard cells that meet the requirements.

[0041] In this embodiment, the method of reading the process files of the target process and the behavior description of the standard cells to be generated can be to select appropriate EDA tools, use these tools to read the process files of the target process, and provide necessary information and support for the subsequent generation of standard cells.

[0042] In step S220, an adapter corresponding to the underlying tool that needs to be called is generated.

[0043] In a complex software system architecture and development environment, when faced with the need to call underlying tools, it is crucial to build an adapter that matches them. The core goal of the adapter is to seamlessly connect the upper-layer application system with the underlying tools to achieve efficient and accurate data transmission and instruction interaction between the two. In this embodiment, for the underlying tools that need to be called, adapters corresponding to different underlying tools can be generated, that is, an adapter for each underlying tool can be established.

[0044] In terms of data conversion, the adapter needs to have strong format conversion capabilities; in the interface adaptation stage, the adapter needs to create a calling interface that matches the upper-level application system, so that when the upper-level application calls the adapter, it feels as natural and smooth as interacting directly with the underlying tool. This means that the adapter needs to simplify and abstract the complex interface of the underlying tool, hide some unnecessary details and complexity of the underlying tool, and only expose the functional interface that the upper-level application really needs.

[0045] In some specific embodiments, the method of generating adapters corresponding to the underlying tools can adopt direct code adaptation, that is, directly writing the adaptation code through the underlying programming language, using the API of the underlying tool to package it according to the requirements of the upper-level application, and middleware adaptation can also be adopted. The middleware is introduced to connect the underlying tools and the upper-level applications. The middleware provides a unified interface specification and data conversion mechanism. Model-driven adaptation can also be adopted. An abstract model of the underlying tools and upper-level applications is established based on the model-driven architecture. The adaptation code is generated through a model conversion tool after being described in a unified modeling language.

[0046] In one embodiment of the present application, the method of generating the adapter corresponding to the underlying tool can also be a scripting language plus encapsulation method, such as Figure 3 As shown, step S220 may specifically include steps S310 to S320, which are described in detail as follows: Step S310: Generate a corresponding scripting language for the underlying tool that needs to be called.

[0047] In this embodiment, in order to establish an adapter, a corresponding script language can be first generated for the underlying tool that needs to be called. This is because it can provide a unified interface and simplify the integration process between different tools. Through the automatically generated scripts, the adapter can call each tool in a standardized manner, thereby improving maintainability and flexibility while reducing the incidence of human errors. In addition, this method also facilitates independent testing to ensure that the functions of each tool work properly in the adapter, thereby improving the overall stability and reliability of the system.

[0048] The generated scripting languages ​​can be, for example, Python, TCL, Shell scripts (such as Bash), etc. Among them, Python scripts, with their rich libraries and concise syntax, can use the relevant data processing libraries to read data and start tools with the help of API or system calls when calling underlying data analysis tools, and can also visualize the results; TCL scripts are often used in the field of electronic design automation to call chip design tools, which can set parameters, load files, and start operations to obtain results; Shell scripts are good at automating tasks at the operating system level, such as calling disk partitions, file system checks and other tools in server management.

[0049] For the underlying tools in chip design, TCL scripts can be generated accordingly. For example, for the layout and routing tool Virtuoso Layout Editor, a corresponding TCL script language can be generated. The TCL script language generated for the underlying tool can achieve operations such as automatically creating circuit schematics, setting chip layout parameters, and automatically routing modules. These TCL scripts can greatly improve the degree of automation in the chip design process, reduce the tediousness and error probability of manual operations, and make the chip design process more efficient and accurate.

[0050] In this embodiment, the method of automatically generating the script language can first obtain the interface definition of the underlying tool, then write a code generator, which dynamically generates code that conforms to the script language syntax according to the interface information, and finally saves the generated script as a file or directly outputs it for subsequent calling and integration.

[0051] Step S320: encapsulate the script language to obtain an encapsulation body corresponding to the script language, and establish an adapter corresponding to the underlying tool according to the encapsulation body.

[0052] In order to build an adapter, it is necessary to encapsulate the script language, because encapsulation can provide a unified interface, simplify the calling methods of different tools, hide the underlying implementation details, and enhance the reusability and maintainability of the code. Therefore, after obtaining the script language through the above step S310, the script language can be further encapsulated to obtain the encapsulation body corresponding to the script language. There are two main ways of encapsulation here: one is script encapsulation, that is, packaging the script function into a module or library for other code calls; the other is binary encapsulation, compiling the script into a binary file to improve execution efficiency and security.

[0053] After encapsulating the script language to obtain the encapsulation, the adapter corresponding to the underlying tool can be established. Specifically, when building the adapter corresponding to the underlying tool based on the encapsulation, the encapsulation must first be fully analyzed to deeply understand the interface methods, data structures and functional characteristics provided by it. If the encapsulation is in the form of a script module, the script module is imported into the adapter code, and corresponding adaptation functions are created in the adapter for each interface operation of the underlying tool. These functions call the relevant interface methods of the encapsulation internally, and at the same time, the parameters passed by the upper-level application are converted and sorted according to the requirements of the underlying tool and passed to the encapsulation interface, and the data returned by the encapsulation is processed to make it conform to the expected data format and processing logic of the upper-level application; if the encapsulation is in binary form, according to the API document provided by it, the corresponding library file is linked in the adapter, and the interaction with the underlying tool is realized by calling the API function. Similarly, the parameter adaptation and data conversion work are completed during the calling process, thereby effectively integrating the upper-level application and the underlying tool, so that they can work together seamlessly to ensure the smooth operation and functional realization of the entire software system.

[0054] The above-mentioned method of generating adapters through scripting language and encapsulation is, firstly, conducive to improving development efficiency, as the scripting language syntax is concise, and the development cycle is short and flexible; secondly, conducive to code maintenance, as encapsulation can hide complex logic, making it easier to cope with changes in underlying tools and in line with software engineering practice; thirdly, enhanced reusability, as encapsulated scripts can be reused in multiple scenarios to reduce repeated development; and fourthly, easy to integrate systems, as it can integrate underlying tools and make them better adapted to upper-level applications, thereby enhancing system stability.

[0055] Please continue to see Figure 2 In step S230, an execution strategy is determined according to the target requirements and target process of the standard cell to be generated, and the execution strategy is a combination of multiple levels of parameters related to the standard cell.

[0056] In the process of generating standard cells in chip design, the target requirements are the direction of the entire design and manufacturing process. These target requirements may include many aspects, such as performance indicators (such as computing speed, data processing capabilities), power consumption requirements (how low the power consumption should be), area restrictions (the physical space occupied by the standard cell in the entire chip), and many other factors. The target process refers to the specific technical means used to manufacture this standard cell. For example, in chip manufacturing, it may be a specific transistor process, such as FinFET process. These two are the basis for determining the execution strategy.

[0057] The execution strategy is a series of plans and methods adopted within the framework of the target process in order to achieve the target requirements. It is not a simple, single parameter, but a comprehensive system composed of multiple levels of parameters. These parameters cooperate and work together to control the generation process of standard cells from different angles and levels.

[0058] The parameters in the execution strategy are hierarchical. For example, in chip design, it can include the top-level system-level parameters, such as the power budget of the chip as a whole, performance expectations (such as how many instructions are executed per second); then the circuit-level parameters, which involve the parameters of the specific circuit structure, such as the type of logic gates (AND gates, OR gates, or NOT gates, etc.), the number and connection method, these parameters will affect the logical function and performance of the standard unit; then the transistor-level parameters, such as the size of the transistor (such as channel length, width), threshold voltage, etc., these parameters directly determine the electrical performance of the transistor, and thus affect the performance and power consumption of the standard unit.

[0059] These parameters at different levels do not exist in isolation, but need to be combined with each other. For example, in order to achieve the target requirement of low power consumption, a lower power consumption budget can be set at the system level. At the circuit level, it is necessary to choose a more energy-efficient logic gate connection method to reduce unnecessary signal flips. At the transistor level, appropriate transistor size and threshold voltage should be used to reduce leakage current. These parameters at different levels are combined together to form an execution strategy, which guides the entire standard cell generation process to ensure that the final generated standard cell can meet the target requirements and adapt to the target process.

[0060] In one embodiment of the present application, the execution strategy may be a combination of primary strategy parameters, secondary design parameters, and tertiary tool parameters, such as Figure 4 As shown, step S230 may specifically include steps S410 to S430, which are specifically described as follows: Step S410: Determine the primary strategy parameters according to the target requirements of the standard unit to be generated.

[0061] Standard cells are the basic building blocks in complex systems such as chips. The target requirement refers to the expected effect that this standard cell needs to achieve in the final application scenario. For example, in chip design, it may be a specific power, performance, and area (PPA) indicator. The first-level strategy parameters are the most direct and critical initial parameters determined to meet these target requirements. These parameters are like a top-level design guide that controls the design of standard cells from a relatively macro perspective.

[0062] Taking chip design as an example, if the target requirements are high performance and low power consumption, the first-level strategy parameters may include the initially set clock frequency range (for performance) and the upper limit of the power supply voltage (for power consumption). For example, in order to achieve high performance, the clock frequency is initially set between 3 and 5GHz; in order to control power consumption, the upper limit of the power supply voltage is set to 1.0V. These parameters are directly derived from the target requirements and are the important factors that must be determined first in the design process.

[0063] Step S420: Determine the secondary design parameters according to the primary strategy parameters and the target process.

[0064] After determining the first-level strategy parameters, the design needs to be further refined in combination with the target process. The target process refers to the specific technology used to manufacture the standard cell, such as the FINFET process in chip design. The second-level design parameters are based on the first-level strategy parameters, taking into account the characteristics and limitations of the target process, and designing the standard cell in more detail. These parameters are more specific and involve details related to the internal structure and process of the standard cell.

[0065] Assume that the power supply voltage upper limit is set to 1.0V in the first-level strategy parameters to control power consumption. Under the FinFET process, the second-level design parameters may include the specific value of the transistor threshold voltage (Vt), the geometric dimensions of the fin (such as fin height, width), etc. Because under the FinFET process, parameters such as the transistor threshold voltage and fin size directly affect the power consumption and performance of the chip. For example, according to the power supply voltage and target process in the first-level strategy parameters, the threshold voltage of the transistor is determined to be about 0.4V, the fin height is 30nm, etc. These second-level design parameters are further refinements of the first-level strategy parameters under the target process.

[0066] Step S430: Determine the third-level tool parameters of the underlying tool according to the first-level strategy parameters and the second-level design parameters, and use the combination of the first-level strategy parameters, the second-level design parameters and the third-level tool parameters as the execution strategy.

[0067] The underlying tools are the software or equipment used to actually generate standard cells, and they require specific parameters to perform operations. The third-level tool parameters are the most detailed and accurate parameters provided to the underlying tools based on the first-level strategy parameters and the second-level design parameters. These parameters are instructions that the underlying tools can understand and process to ultimately generate standard cells that meet the target requirements.

[0068] Continuing from the previous example, the first-level strategy parameters determine the clock frequency range and the upper limit of the power supply voltage, and the second-level design parameters determine the transistor threshold voltage and fin size, etc. Then the third-level tool parameters may include specific parameters for electronic design automation (EDA) tools, such as the precise layout size of transistors (including the specific size of the source, drain, and gate), the width and spacing of metal connections, etc. in layout design tools. These parameters are necessary for the underlying tools to perform physical layout drawing, circuit simulation, and other operations. Through these third-level tool parameters, the underlying tools can transform the design from an abstract concept into an actual standard unit physical structure.

[0069] After the first-level strategy parameters, second-level design parameters and third-level tool parameters are determined through the above scheme, the combination of the first-level strategy parameters, the second-level design parameters and the third-level tool parameters can be used as the execution strategy.

[0070] Please continue to see Figure 2 In step S240, the underlying tool is called through the adapter so that the underlying tool is executed according to the various levels of parameters, process files and behavior descriptions in the execution strategy to generate standard units.

[0071] In this embodiment, the underlying tools have specific interfaces, input formats and calling methods. They are usually relatively low-level and highly professional tools used for actual standard cell generation operations. The execution strategy contains parameters at all levels, and the process file contains detailed information about the target process, such as lithography accuracy, material properties, manufacturing steps and rules in the chip manufacturing process. The behavior description details how the standard cell should "act" from multiple perspectives such as logical functions, timing requirements, and power consumption characteristics, that is, it clarifies the specific working methods, performance requirements, etc. of the standard cell, which is also an important basis for the underlying tools to follow when generating standard cells. This information may not be completely consistent with the input expected by the underlying tools. The function of the adapter is to convert and adapt the execution strategy, process files, and behavior descriptions so that this information can be understood and received by the underlying tools.

[0072] After receiving the appropriate information converted by the adapter, the underlying tools will operate according to these instructions. For example, in the underlying tools of chip design, circuit simulation, layout drawing and other operations may be performed according to parameter information, process files and behavior descriptions, and finally generate standard cells that meet the requirements. In the process of generating standard cells, it is very likely that multiple underlying tools will be used. This is because the generation of standard cells is a complex process involving multiple aspects. From circuit design to physical layout generation, to performance verification and optimization, each link has its specific tasks and requirements. Through the collaborative work of these underlying tools, standard cells that meet the requirements are finally generated.

[0073] Based on the technical solution of the above embodiments, by reading the process files and the behavioral description of the standard unit to be generated, the underlying tools can accurately process the process information and design requirements with the help of adapter conversion, and effectively cope with the complexity of the process; corresponding adapters are generated for the complex underlying tools, and the execution strategy is converted into the format required by the underlying tools to achieve seamless docking and collaboration, and reduce the difficulty caused by tool differences; the execution strategy of the multi-level parameter combination is determined according to the target process and target requirements, and the underlying tools are called by the adapter to execute accordingly, thereby optimizing the development path, avoiding repeated trial and error, and significantly shortening the development process; and the solution standardizes and automates the process, reduces the dependence on the experience of senior experts, and allows inexperienced engineers to work according to the process, reduces manpower dependence, promotes knowledge sharing, and reduces the risk of personnel turnover, and comprehensively solves many problems faced by standard unit development.

[0074] In one embodiment of the present application, during the execution of the underlying tool, the output corresponding to each execution node can be cached. In this way, if an error occurs in the current execution node, it can roll back to the previous execution node based on the output corresponding to the previous execution node.

[0075] Specifically, in the process of the underlying tool carrying out the task execution, the system will automatically cache the output results corresponding to each execution node. These cached information will be properly stored in a specific cache area so that they can be quickly retrieved and used when needed later. If an error occurs in the current execution node during the execution process, whether it is due to data anomalies, program logic vulnerabilities, or external environmental interference, the system can accurately fall back to the previous execution node based on the output information corresponding to the previous cached execution node. In this way, it can effectively avoid the complete collapse of the entire execution process due to the error of a certain node, and at the same time provide convenient basic conditions for subsequent error troubleshooting and repair work, so that technicians can carry out in-depth analysis and debugging based on the correct output results of the previous node, thereby improving the stability and reliability of the entire underlying tool execution process, and ensuring that related businesses or operations can still maintain continuity and recoverability as much as possible when encountering error interference.

[0076] In one embodiment of the present application, if an alarm occurs during the execution of the underlying tool, an alarm message may be generated and recorded in a log file so that the user can view the alarm message.

[0077] During the execution of the underlying tool, once any abnormal situation occurs and triggers the alarm mechanism, the system will automatically generate detailed and accurate alarm information immediately. The alarm information will comprehensively cover the specific timestamp of the error, accurate to the millisecond level, to clarify the time when the abnormal event occurred; the name of the relevant execution module involved, clearly indicating which part of the functional module in the underlying tool triggered the alarm; the error code or error type description, through a specific code identifier or easy-to-understand text description to explain the nature and category of the error, such as memory overflow error, data format mismatch error, or network connection interruption error, etc.; as well as the data range or operation process information that may be affected, to help users quickly locate the level that the problem may affect.

[0078] Afterwards, the system will record the carefully organized alarm information in full into a dedicated log file. The log file will be stored in a rigorous format, with each alarm record arranged in chronological order, and detailed date and time stamps will be attached to the record to ensure the traceability of the information. In this way, when the user needs to view and analyze the alarm information later, he can easily open the log file, and quickly locate the target alarm record according to the chronological order or specific filtering conditions (such as according to the error type, execution module, etc.), so as to gain an in-depth understanding of the problems encountered by the underlying tools during the execution process, and provide a strong basis and reference for further troubleshooting, performance optimization and system maintenance work, so as to ensure the stable and efficient operation of the entire system.

[0079] In one embodiment of the present application, a result file corresponding to the standard cell is also generated during the process of generating the standard cell. The result file is an important file generated by the underlying tool after a series of complex and orderly operations such as calculation, processing, and data conversion according to the established execution strategy and the detailed process and specifications contained in the process file. In this embodiment, the result files can be managed uniformly.

[0080] Specifically, unified management operations include inspection and verification operations, dynamic adjustment of read and write permissions, file flow management operations, and large text optimization operations. Among them, the inspection and verification operations will use a variety of professional algorithms and verification rules to strictly check the integrity, accuracy, and data consistency of the result files. For example, a specific checksum algorithm is used to verify whether data loss or tampering occurs during the transmission or storage of the file, and the key data indicators in the file are compared with the predefined standard value range to ensure the accuracy of the data. The dynamic adjustment of read and write permissions will change the read and write permissions of the result files in real time and flexibly according to different user roles, the current system operation status, and the security level of the data. For example, ordinary users may only be granted the permission to read some key data, while professionals responsible for system maintenance and data analysis may be granted the permission to write or modify specific data areas under specific circumstances, and the allocation of these permissions will be adjusted at any time as the system security situation changes. The file flow management operation will orderly plan and manage all aspects of the entire life cycle of the result files, from generation to storage, transmission, use, and final archiving or destruction. For example, it is stipulated that the result file must go through a specific review process after being generated before it can enter the storage link, must follow specific encryption and transmission protocols during the transmission process, and must record detailed usage logs during use for traceability. For those result files with huge data volumes, the ultra-large text optimization operation uses technical means such as data compression, index optimization, and block storage to improve the file processing efficiency and storage performance. For example, use an efficient compression algorithm to compress the file to reduce storage space occupancy, and create a reasonable index structure to quickly locate the required data area when reading the file, or store and manage ultra-large files in blocks according to a certain logic to reduce the pressure of a single operation on system resources, thereby ensuring the efficient, stable and secure operation of the entire result file management system.

[0081] In one embodiment of the present application, if the satisfaction rate of the generated standard unit for the target requirement exceeds a preset threshold, the execution strategy is saved as a default strategy in the strategy library to update the strategy library.

[0082] For example, if the target requirement focuses on the area indicator in the PPA, the satisfaction rate can be a ratio used to measure the degree of fit between the area characteristics of the generated standard cell and the pre-set area target requirements. It is essentially a quantitative evaluation indicator that can intuitively show the extent to which the standard cell meets the target requirements in terms of area. If the target requirement focuses on the power consumption indicator in the PPA, the satisfaction rate can be a ratio used to measure the degree of match between the actual power consumption of the generated standard cell and the target power requirement. If the target requirement focuses on the performance indicator in the PPA, the satisfaction rate can be a ratio used to evaluate the degree of fit between the actual performance of the generated standard cell and the target performance requirements. Performance indicators are usually a combination of multiple sub-performance indicators, such as computing speed, data throughput, response time, etc.

[0083] As a key metric, the satisfaction rate exceeds the preset threshold, which means that the current execution strategy performs well and can effectively generate standard units that meet the target requirements. The setting of this threshold is usually based on the system's strictness of the target requirements and the overall performance.

[0084] When the satisfaction rate reaches the target, the execution strategy is saved to the strategy library as the default strategy. Repeating this successful strategy in subsequent operations can effectively reduce the uncertainty and trial-and-error costs in the strategy development and exploration process. Each time a task is executed, the system does not need to re-evaluate and screen the many possible execution paths, but directly enables the proven default strategy, which greatly shortens the startup time of the task and improves the consistency and stability of task execution. It is not limited to a single successful replication, but to further optimize the strategy itself through continuous application and feedback mechanisms. As the strategy is used multiple times, the system can collect more data about its performance in different scenarios and conditions, and then analyze possible room for improvement or potential optimization points. For example, through the monitoring and statistical analysis of relevant parameters in the generation process of a large number of standard cells, it is found that adjusting certain parameters within a specific range can further improve the satisfaction rate, thereby refining the strategy so that the subsequently generated standard cells can more accurately meet the target requirements, and achieve a better balance in terms of area, power and performance.

[0085] From the perspective of optimizing the performance of the entire system, a stable and efficient execution strategy helps to build a more orderly and efficient workflow. In hardware systems, such as chip manufacturing, this means that various production links can work together better and reduce production interruptions or process incompatibility problems caused by strategy changes. Because the generation of standard units is more in line with expectations, the overall integration and reliability of the chip can be improved, and key performance indicators such as the system's operating speed and response time will also improve. In software systems, it can ensure smoother interactions between different modules, reduce delays and errors caused by inconsistent data transmission or processing strategies, improve the operating efficiency and stability of the entire software system, and enhance user experience.

[0086] In terms of resource utilization efficiency, reusing successful strategies avoids repeated investment and waste of resources. On the one hand, computing resources are allocated more reasonably, and there is no need to consume a lot of CPU time, memory space and storage capacity to constantly try new strategies. For example, in complex simulation processes, unnecessary repeated calculations can be reduced, and limited computing resources can be concentrated on the precise analysis and optimization of key parameters. On the other hand, human resources can be liberated from tedious strategy development and debugging work and invested in more innovative and value-added work, such as in-depth research on system architecture, exploration and application of new technologies, etc., thereby comprehensively improving the overall efficiency of enterprises or organizations in technological innovation and project promotion, occupying a more advantageous position in the fierce market competition, and promoting the efficient operation and sustainable development of the entire industrial chain.

[0087] In a second aspect, the present application also proposes a standard unit generation device, such as Figure 5 As shown, the standard unit generating device includes a reading unit 501 , a generating unit 502 , a determining unit 503 and a calling unit 504 .

[0088] Among them, the reading unit 501 is configured to read the process file of the target process; the generating unit 502 is configured to generate an adapter corresponding to the underlying tool for the underlying tool that needs to be called; the determining unit 503 is configured to determine the execution strategy according to the target requirements of the standard unit to be generated and the target process, and the execution strategy is a combination of multiple levels of parameters related to the standard unit; the calling unit 504 is configured to call the underlying tool through the adapter, so that the underlying tool is executed according to the parameters at each level in the execution strategy and the process file to generate the standard unit.

[0089] In some embodiments of the present application, the determination unit 503 is also configured to determine the first-level strategy parameters according to the target requirements of the standard unit to be generated; determine the second-level design parameters according to the first-level strategy parameters and the target process; determine the third-level tool parameters of the underlying tool according to the first-level strategy parameters and the second-level design parameters, and use the combination of the first-level strategy parameters, the second-level design parameters and the third-level tool parameters as the execution strategy.

[0090] In some embodiments of the present application, the generating unit 502 is further configured to generate a corresponding scripting language for the underlying tool that needs to be called; encapsulate the scripting language to obtain an encapsulation body corresponding to the scripting language, and establish an adapter corresponding to the underlying tool based on the encapsulation body.

[0091] In some embodiments of the present application, the standard unit generation device also includes: a cache unit, which is configured to cache the output corresponding to each execution node during the execution of the underlying tool, and if an error occurs in the current execution node, it will fall back to the previous execution node according to the output corresponding to the previous execution node.

[0092] In some embodiments of the present application, the generation unit 502 is also configured to generate alarm information if an alarm occurs during the execution of the underlying tool, and record the alarm information in a log file so that the user can view the alarm information.

[0093] In some embodiments of the present application, the standard unit generation device also includes a result file acquisition unit and a management unit, the result file acquisition unit is configured to obtain the result file corresponding to the standard unit, the result file is a file generated by the underlying tool according to the execution strategy and the process file; the management unit is configured to perform unified management operations on the result file, and the unified management operations include inspection and verification operations, dynamic adjustment operations of read and write permissions, file flow management operations, and large text optimization operations.

[0094] In some embodiments of the present application, the standard unit generating device further includes a saving unit, which is configured to save the execution strategy as a default strategy in a strategy library to update the strategy library if the satisfaction rate of the generated standard unit for the target requirement exceeds a preset threshold.

[0095] like Figure 6As shown, an embodiment of the present application also provides an electronic device 600, including a memory 610, a processor 620, and a computer program 611 stored in the memory 610 and executable on the processor, and when the processor 620 executes the computer program 611, the steps of any method for generating the above-mentioned standard unit are implemented.

[0096] Since the electronic device introduced in this embodiment is a device used to implement a standard unit generation device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, the technical personnel in this field can understand the specific implementation method of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by the technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0097] In the specific implementation process, when the computer program 611 is executed by the processor, it can achieve Figures 2 to 4 Any implementation manner in the corresponding embodiments.

[0098] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0099] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0100] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0101] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0103] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes a process for generating a standard unit in a corresponding embodiment.

[0104] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)), etc.

[0105] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0106] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0107] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0108] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0109] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0110] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for generating a standard cell, characterized in that: include: Read the process file of the target process and the behavior description of the standard unit to be generated; For the underlying tool that needs to be called, generate an adapter corresponding to the underlying tool; Determining an execution strategy according to the target requirements of the standard cell and the target process, wherein the execution strategy is a combination of multiple levels of parameters related to the standard cell; The underlying tool is called through the adapter so that the underlying tool is executed according to the various levels of parameters in the execution strategy, the process file and the behavior description to generate the standard unit.

2. The method according to claim 1, characterized in that Determine the execution strategy based on the target requirements of the standard cells to be generated and the target process, including: Determine the primary strategy parameters according to the target requirements of the standard unit to be generated; Determining secondary design parameters according to the primary strategy parameters and the target process; According to the primary strategy parameters and the secondary design parameters, the tertiary tool parameters of the underlying tool are determined, and a combination of the primary strategy parameters, the secondary design parameters and the tertiary tool parameters is used as the execution strategy.

3. The method according to claim 1, characterized in that For the underlying tool that needs to be called, generate the adapter corresponding to the underlying tool, including: For the underlying tools that need to be called, generate the corresponding script language; The scripting language is encapsulated to obtain an encapsulation body corresponding to the scripting language, and an adapter corresponding to the underlying tool is established according to the encapsulation body.

4. The method according to claim 1, characterized in that: The method further comprises: During the execution of the underlying tool, the output corresponding to each execution node is cached. If an error occurs in the current execution node, the process rolls back to the previous execution node based on the output corresponding to the previous execution node.

5. The method according to claim 1, characterized in that The method further comprises: During the execution of the underlying tool, if an alarm occurs, an alarm message is generated and recorded in a log file so that the user can view the alarm message.

6. The method according to claim 1, characterized in that The method further comprises: Obtaining a result file corresponding to the standard cell, wherein the result file is a file generated by the underlying tool according to the execution strategy and the process file; The result file is uniformly managed, and the uniform management operation includes checking and verifying operation, dynamic adjustment operation of read and write permissions, file flow management operation and super large text optimization operation.

7. The method according to claim 1, characterized in that The method further comprises: If the satisfaction rate of the generated standard unit for the target requirement exceeds a preset threshold, the execution strategy is saved as a default strategy in a strategy library to update the strategy library.

8. A standard cell generation device, characterized in that: include: A reading unit, configured to read a process file of a target process and a behavior description of a standard unit to be generated; A generating unit, configured to generate an adapter corresponding to the underlying tool that needs to be called; a determination unit configured to determine an execution strategy according to a target requirement of the standard cell and the target process, wherein the execution strategy is a combination of multiple levels of parameters related to the standard cell; The calling unit is configured to call the underlying tool through the adapter, so that the underlying tool is executed according to the various levels of parameters in the execution strategy, the process file and the behavior description to generate the standard unit.

9. An electronic device, comprising: A memory and a processor, wherein the processor is used to implement the standard cell generation method according to any one of claims 1 to 7 when executing a computer program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the standard cell generation method according to any one of claims 1 to 7 is implemented.

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