Control system of vehicle-mounted display screen based on FPGA (Field Programmable Gate Array) and automobile

Abstract

The invention discloses a control system of a vehicle-mounted display screen based on an FPGA and an automobile, and belongs to the technical field of vehicle-mounted display screens, the system comprises an FPGA chip, a cabin area controller, a deserializer, a display screen, a Flash memory, a CAN module and a serial peripheral interface (SPI), the FPGA chip is connected with the cabin area controller through the CAN module; the FPGA chip is also connected with the display screen; the input end of the deserializer is connected with the output end of the cabin domain controller; the output end of the deserializer is connected with the input end of the FPGA chip; and the output end of the Flash memory is connected with the input end of the FPGA chip through the serial peripheral interface (SPI). Through the FPGA-based control system of the vehicle-mounted display screen, the space required by hardware layout of the control system of the vehicle-mounted display screen can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of vehicle-mounted display screens, and in particular, relates to a control system of a vehicle-mounted display screen based on FPGA and a vehicle. Background Art

[0002] With the continuous iteration of the in-vehicle display industry, end users have higher and higher requirements for the functions of in-vehicle displays. With the increasing functions of in-vehicle displays, more and more electronic components are required, resulting in an increase in the space required for the hardware layout of the control system of the in-vehicle display. At the same time, as the thickness of the in-vehicle display becomes thinner and thinner, the PCB board becomes smaller and smaller, and the prohibited layout area becomes larger and larger.

[0003] Patent CN105245818A discloses an FPGA-based LED display control system, which includes an FPGA chip, an SDI interface, a high-speed Serdes, a DDR controller and a 3D digital comb filter. The FPGA IO pin is in DDR mode. The control system uses the DSP module in the FPGA to implement high-speed multiplication operations and a scaling filtering algorithm, and realizes frame rate conversion by reading and writing control of the DDR memory.

[0004] However, the technologies disclosed in the above patents and the prior art cannot solve the problem of the increase in space required for the hardware layout of the control system of the vehicle display screen as the functions of the vehicle display screen increase. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a control system of a vehicle-mounted display screen based on FPGA and a vehicle in view of the deficiencies of the prior art, so as to achieve the purpose of reducing the space required for the hardware layout of the control system of the vehicle-mounted display screen.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] The present invention provides a control system for an on-vehicle display screen based on FPGA, comprising an FPGA chip, a cockpit domain controller, a deserializer, a display screen, a Flash memory, a CAN module and a serial peripheral interface (SPI), wherein the FPGA chip is connected to the cockpit domain controller via the CAN module; the FPGA chip is also connected to the display screen; the input end of the deserializer is connected to the output end of the cockpit domain controller; the output end of the deserializer is connected to the input end of the FPGA chip; and the output end of the Flash memory is connected to the input end of the FPGA chip via the serial peripheral interface (SPI).

[0008] Furthermore, the deserializer transmits the EDP signal to the FPGA chip, and the FPGA chip converts the received EDP signal into an LVDS signal.

[0009] Furthermore, the FPGA chip caches the LVDS signal.

[0010] Furthermore, the CAN module transmits the CAN signal to the FPGA chip, and the FPGA chip recognizes and obtains the corresponding mapping instruction from the received CAN signal.

[0011] Furthermore, the FPGA chip obtains icon data corresponding to the corresponding mapping instruction from the Flash memory through a serial peripheral interface (SPI).

[0012] Furthermore, the FPGA chip performs image fusion processing on the acquired icon data and the image data corresponding to the LVDS signal.

[0013] Furthermore, the FPGA chip performs image quality enhancement processing on the image data corresponding to the LVDS signal after the image fusion processing, and transmits the image data corresponding to the LVDS signal after the image quality enhancement processing to the display screen.

[0014] Furthermore, the FPGA chip performs local dimming on the display screen.

[0015] Furthermore, the FPGA chip and the display screen communicate with each other using an integrated circuit bus (IIC).

[0016] The present invention also mentions a car, which is equipped with the above-mentioned FPGA-based on-vehicle display screen control system.

[0017] The FPGA-based vehicle display screen control system of the present invention has the following advantages:

[0018] (1) The FPGA-based vehicle display screen control system of the present invention reduces the space required for the hardware layout of the vehicle display screen control system.

[0019] (2) The FPGA-based vehicle display screen control system of the present invention can enable the vehicle display screen to achieve high-contrast image quality.

[0020] (3) The present invention adopts FPGA chip, which enhances the timeliness and stability of data transmission, and also reduces the hardware cost of the control system of the vehicle display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] This specification includes the following drawings, which show the following contents:

[0022] Figure 1 It is a logical structure block diagram of the control system of the invented vehicle display screen based on FPGA.

[0023] Explanation of the accompanying drawings: 1. FPGA chip; 2. Cockpit domain controller; 3. Deserializer; 4. Display screen; 5. Flash memory; 6. CAN module; 7. Serial peripheral interface (SPI). DETAILED DESCRIPTION

[0024] The specific implementation methods of the present invention are further explained in detail below by describing the embodiments with reference to the accompanying drawings, with the aim of helping those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention and facilitating its implementation.

[0025] Figure 1 It is a logical structure block diagram of the control system of the FPGA-based vehicle display screen of the invention, including an FPGA chip 1, a cockpit domain controller 2, a deserializer 3, a display screen 4, a Flash memory 5, a CAN module 6 and a serial peripheral interface (SPI) 7. The FPGA chip 1 is connected to the cockpit domain controller 2 through the CAN module 6; the FPGA chip 1 is also connected to the display screen 4; the input end of the deserializer 3 is connected to the output end of the cockpit domain controller 2; the output end of the deserializer 3 is connected to the input end of the FPGA chip 1; the output end of the Flash memory 5 is connected to the input end of the FPGA chip 1 through the serial peripheral interface (SPI) 7.

[0026] In the present invention, by programming the FPGA chip 1, an IP core is designed in the FPGA chip 1, so that the FPGA chip 1 has the functions of a microcontroller (MCU), a bridge and a timing controller (TCON) on the original basis, wherein the IP core refers to a mature design of a circuit module with independent functions in a chip, and can also be understood as an intermediate component of a chip design. Specifically, the present invention designs an EDP signal to LVDS signal IP core, a picture cache IP core, an image fusion IP core, a picture quality enhancement IP core, a local dimming IP core, a CAN signal processing IP core and a control processing IP core in the FPGA chip 1, so that the FPGA chip 1 has the functions of a microcontroller (MCU), a bridge and a timing controller (TCON) on the original basis.

[0027] Combine the following Figure 1The working principle of the control system of the vehicle display screen based on FPGA of the present invention is introduced as follows: during the operation of the system, the cockpit domain controller 2 transmits a GMSL signal to the deserializer 3, and the deserializer 3 converts the received GMSL signal into two EDP signals. The deserializer 3 transmits the EDP signal to the FPGA chip 1, and the FPGA chip 1 converts the received EDP signal into an LVDS signal. Specifically, the deserializer 3 transmits two EDP signals to the FPGA chip 1, and the EDP signal to LVDS signal IP core in the FPGA chip 1 converts the EDP signal received by the FPGA chip 1 into an LVDS signal. After the EDP signal to LVDS signal IP core in the FPGA chip 1 converts the received EDP signal into an LVDS signal, the FPGA chip 1 caches the LVDS signal. Specifically, after the EDP signal to LVDS signal IP core in the FPGA chip 1 converts the received EDP signal into an LVDS signal, the picture cache IP core in the FPGA chip 1 caches the LVDS signal into the random access memory (RAM) in the FPGA chip 1. The CAN module 6 transmits the CAN signal to the FPGA chip 1, and the FPGA chip 1 identifies the corresponding mapping instruction from the received CAN signal. Specifically, the CAN module 6 transmits the CAN signal to the FPGA chip 1, and the CAN signal processing IP core in the FPGA chip 1 identifies the corresponding mapping instruction from the CAN signal received by the FPGA chip 1. After the CAN signal processing IP core in the FPGA chip 1 identifies the corresponding mapping instruction from the CAN signal received by the FPGA chip 1, the FPGA chip 1 obtains the icon data corresponding to the corresponding mapping instruction from the Flash memory 5 through the serial peripheral interface (SPI) 7. Specifically, after the CAN signal processing IP core in the FPGA chip 1 identifies the corresponding mapping instruction from the CAN signal received by the FPGA chip 1, the control processing IP core in the FPGA chip 1 obtains the icon data corresponding to the corresponding mapping instruction from the Flash memory 5 through the serial peripheral interface (SPI) 7. After the control processing IP core in the FPGA chip 1 obtains the icon data corresponding to the corresponding mapping instruction from the Flash memory 5 through the serial peripheral interface (SPI) 7, the FPGA chip 1 performs image fusion processing on the obtained icon data and the image data corresponding to the LVDS signal. Specifically, after the control processing IP core in the FPGA chip 1 obtains the icon data corresponding to the corresponding mapping instruction from the Flash memory 5 through the serial peripheral interface (SPI) 7, the image fusion IP core in the FPGA chip 1 performs image fusion processing on the aforementioned icon data and the image data corresponding to the LVDS signal cached in the random access memory (RAM) in the FPGA chip 1.FPGA chip 1 performs image quality enhancement processing on the image data corresponding to the LVDS signal after image fusion processing, and transmits the image data corresponding to the LVDS signal after image quality enhancement processing to the display screen 4. Specifically, after the aforementioned image fusion processing is completed, the image quality enhancement IP core in FPGA chip 1 performs image quality enhancement processing on the image data corresponding to the LVDS signal after image fusion processing, and transmits the image data corresponding to the LVDS signal after image quality enhancement processing to the display screen 4. Local dimming (Local Dimming) is performed on the display screen 4 by FPGA chip 1. Specifically, after the image quality enhancement IP core in FPGA chip 1 performs image quality enhancement processing on the image data corresponding to the LVDS signal after image fusion processing and transmits the image data corresponding to the LVDS signal after image quality enhancement processing to the display screen 4, the local dimming (Local Dimming) IP core in FPGA chip 1 will perform local dimming (Local Dimming) on ​​the display screen 4.

[0028] In addition, the cockpit domain controller 2 communicates with the display screen 4 through the CAN module 6 and the FPGA chip 1, wherein the FPGA chip 1 communicates with the display screen 4 in the form of an integrated circuit bus (IIC). The present invention also mentions a car, which is equipped with the above-mentioned FPGA-based vehicle display screen control system.

[0029] The present invention is described above by way of example in conjunction with the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-mentioned methods. As long as various non-substantial improvements are made using the method concept and technical solution of the present invention; or the above concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.

Claims

1. A control system for a vehicle display screen based on FPGA, characterized in that: It includes an FPGA chip, a cockpit domain controller, a deserializer, a display screen, a Flash memory, a CAN module and a serial peripheral interface (SPI), wherein the FPGA chip is connected to the cockpit domain controller via the CAN module; the FPGA chip is also connected to the display screen; the input end of the deserializer is connected to the output end of the cockpit domain controller; the output end of the deserializer is connected to the input end of the FPGA chip; the output end of the Flash memory is connected to the input end of the FPGA chip via the serial peripheral interface (SPI).

2. The control system of a vehicle display screen based on FPGA as claimed in claim 1, characterized in that: The deserializer transmits the EDP signal to the FPGA chip, and the FPGA chip converts the received EDP signal into an LVDS signal.

3. The control system of a vehicle display screen based on FPGA as claimed in claim 2, characterized in that: The FPGA chip caches the LVDS signal.

4. The control system of a vehicle display screen based on FPGA as claimed in claim 3, characterized in that: The CAN module transmits a CAN signal to the FPGA chip, and the FPGA chip identifies and obtains a corresponding mapping instruction from the received CAN signal.

5. The control system of a vehicle display screen based on FPGA as claimed in claim 4, characterized in that: The FPGA chip obtains the icon data corresponding to the corresponding mapping instruction from the Flash memory through the serial peripheral interface (SPI).

6. The control system of a vehicle display screen based on FPGA as claimed in claim 5, characterized in that: The FPGA chip performs image fusion processing on the acquired icon data and the image data corresponding to the LVDS signal.

7. The control system of a vehicle display screen based on FPGA as claimed in claim 6, characterized in that: The FPGA chip performs image quality enhancement processing on the image data corresponding to the LVDS signal after the image fusion processing, and transmits the image data corresponding to the LVDS signal after the image quality enhancement processing to the display screen.

8. The control system of the vehicle display screen based on FPGA as claimed in claim 7, characterized in that: The FPGA chip performs local dimming on the display screen.

9. The control system of a vehicle display screen based on FPGA as claimed in claim 8, characterized in that: The FPGA chip communicates with the display screen in an integrated circuit bus (IIC) manner.

10. An automobile, characterized in that: The automobile is equipped with a control system for an on-board display screen based on FPGA as described in any one of claims 1 to 9.

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