Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a device region and a mark region adjacent to the device region; forming a pad oxide layer on the substrate; forming an active region on the substrate of the device region, wherein the active region comprises the substrate exposed out of the pad oxide layer of the device region; in the step of forming the active region on the substrate of the device region, a groove is formed in the pad oxide layer of the mark region, the groove is exposed out of the surface of the substrate, and the groove is used as an alignment mark. By adopting the technical scheme, the detection difficulty of the alignment mark can be reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of integrated circuits, the characteristic size of semiconductor structures continues to shrink. During the photolithography process, how to control the overlay error between graphics of different layers so that the relative position of the current layer graphics and the previous layer graphics meets the overlay accuracy has become a crucial step in the photolithography process.

[0003] Currently, semiconductor structures usually have marks for achieving alignment of patterns on different layers. The positions of the alignment marks are detected to improve the overlay accuracy between different process layers.

[0004] However, the current formation scheme of the alignment mark still needs to be improved. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, which can reduce the difficulty of detecting an alignment mark.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a device area and a marking area adjacent to the device area; forming a pad oxide layer on the substrate; forming an active area on the substrate in the device area, the active area comprising the substrate with the pad oxide layer of the device area exposed; in the step of forming the active area on the substrate in the device area, forming a groove in the pad oxide layer of the marking area, the groove exposing the surface of the substrate, and using the groove as an alignment mark.

[0007] Optionally, in the step of forming an active area on the substrate of the device area, the step of forming a groove in the pad oxide layer of the mark area includes:

[0008] Forming a first initial trench and a second initial trench in the pad oxide layer, the first initial trench and the second initial trench serving as the trenches, the first initial trench and the second initial trench interpenetrating each other in a direction perpendicular to the surface of the substrate, and the second initial trench being located in the pad oxide layer below the first initial trench and exposing the surface of the substrate;

[0009] The angle between the sidewall of the first initial groove and the top surface of the second initial groove is greater than the angle between the sidewall of the second initial groove and the top of the substrate, and the top opening size of the first initial groove is greater than the top opening size of the second initial groove.

[0010] Optionally, the step of forming a first initial trench and a second initial trench in the pad oxide layer comprises:

[0011] Removing a portion of the pad oxide layer to form a first initial trench, wherein the first initial trench is located in the pad oxide layer;

[0012] The remaining portion of the pad oxide layer exposed by the first initial trench is removed to form a second initial trench, wherein the second initial trench is located in the pad oxide layer below the first initial trench and exposes the surface of the substrate.

[0013] Optionally, a wet etching process is used to remove a portion of the pad oxide layer to form the first initial trench.

[0014] Optionally, parameters of the wet etching process include: an etching solution including HF and NH4F, a time of 600s to 900s, and a temperature of 19 degrees Celsius to 25 degrees Celsius.

[0015] Optionally, a dry etching process is used to remove the remaining portion of the pad oxide layer exposed by the first initial trench to form the second initial trench.

[0016] Optionally, the parameters of the dry etching process include: etching gas includes CH3F and CF4, pressure is 500mtorr to 1000mtorr, and time is 15s to 30s.

[0017] Optionally, the angle between the sidewall of the second initial trench and the top of the substrate is determined according to the thickness of the pad oxide layer;

[0018] The greater the thickness of the pad oxide layer, the closer the angle between the sidewall of the second initial trench and the top of the substrate is to 90°, and the angle between the sidewall of the second initial trench and the top of the substrate is 80° to 90°.

[0019] Optionally, an angle between a sidewall of the first initial trench and a top of the second initial trench is 90° to 150°.

[0020] Optionally, the greater the thickness of the pad oxide layer, the greater the proportion of the thickness of the first initial trench.

[0021] Optionally, the pad oxide layer has a thickness of 1200 angstroms to 15000 angstroms.

[0022] Optionally, the material of the pad oxide layer includes: one or more of silicon oxide, silicon nitride, aluminum oxide or zirconium oxide.

[0023] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a device area and a marking area adjacent to the device area; a pad oxide layer, located on the substrate, and the pad oxide layer on the substrate in the marking area has a groove, the groove exposes the surface of the substrate, and the groove is used as an alignment mark; an active area, located in the device area, the active area includes the substrate with the pad oxide layer of the device area exposed.

[0024] Optionally, the groove comprises: a second initial groove and a first initial groove which penetrate each other in a direction perpendicular to the surface of the substrate, the second initial groove exposes the surface of the substrate, and the first initial groove is located above the second initial groove;

[0025] The angle between the sidewall of the first initial groove and the top surface of the second initial groove is greater than the angle between the sidewall of the second initial groove and the top of the substrate, and the top opening size of the first initial groove is greater than the top opening size of the second initial groove.

[0026] Optionally, the angle between the sidewall of the second initial trench and the top of the substrate is determined according to the thickness of the pad oxide layer;

[0027] The greater the thickness of the pad oxide layer, the further the angle between the sidewall of the second initial trench and the top of the substrate is from 90°, and the angle between the sidewall of the second initial trench and the top of the substrate is 80° to 90°.

[0028] Optionally, an angle between a sidewall of the first initial trench and a top of the second initial trench is 90° to 150°.

[0029] Optionally, the pad oxide layer has a thickness of 1200 angstroms to 15000 angstroms.

[0030] Optionally, the material of the pad oxide layer includes: one or more of silicon oxide, silicon nitride, aluminum oxide or zirconium oxide.

[0031] Optionally, the semiconductor structure further comprises: a silicate glass material layer, wherein the silicate glass material layer is located on the pad oxide layer;

[0032] Among them, the signal strength of the first feedback signal of the alignment mark obtained from the surface of the silicate glass material layer is 75% to 85%, and the first feedback signal is used to represent the ratio of the reflection signal and the detection signal obtained from the surface of the silicate glass material layer through the silicate glass material layer to detect the alignment mark.

[0033] Optionally, the semiconductor structure further comprises: a metal material layer, wherein the metal material layer is located on the silicate glass material layer;

[0034] Wherein, the signal strength of the second feedback signal of the alignment mark obtained from the surface of the metal material layer is 70% to 80%;

[0035] The second feedback signal is used to indicate the ratio of the reflection signal and the detection signal obtained by detecting the alignment mark from the surface of the metal material layer through the metal material layer and the silicate glass material layer.

[0036] Optionally, the material of the silicate glass material layer includes one or more of USG, PSG or BPSG.

[0037] Optionally, the alignment mark is an alignment mark of an ASML lithography machine.

[0038] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0039] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a pad oxide layer is formed on a substrate. In the step of forming an active area on the substrate in the device area, a groove is formed in the pad oxide layer in the mark area, and the groove can be used as an alignment mark. Compared with the scheme of forming the alignment mark in the substrate, the optical path of the detection light can be shortened, the loss of the detection light can be reduced, and the intensity of the alignment signal can be increased, thereby reducing the difficulty of detecting the alignment mark; and by multiplexing the step of forming the active area to form the alignment mark, at least one patterning process is reduced, thereby reducing the implementation cost.

[0040] In the semiconductor structure provided by the embodiment of the present invention, the pad oxide layer is located on the substrate, and the pad oxide layer on the substrate in the mark area has a groove, which can be used as an alignment mark, and the alignment mark is a zero-layer mark. Compared with the solution of forming the alignment mark in the substrate, the optical path of the detection light can be shortened, the loss of the detection light can be reduced, and the intensity of the alignment signal can be increased, thereby reducing the difficulty of detecting the alignment mark. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figures 1 to 4 It shows a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0043] Figure 5A schematic diagram of a semiconductor structure corresponding to the second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0044] As can be seen from the background technology, the current formation scheme of alignment marks still needs to be improved. This is because:

[0045] In a process of forming an alignment mark, the alignment mark is usually formed inside a substrate, which adds at least one additional patterning step, lengthens the semiconductor formation process, and increases the implementation cost.

[0046] Moreover, in the actual lithography process, since the alignment mark is formed in the substrate, the optical path of the detection light is increased, and the intensity of the reflected light formed by reflection is lower (for example, the ratio between the intensity of the reflected light and the set standard intensity is only 40%). When matching the intensity of the acquired reflected light with the set standard intensity, it is far from meeting the requirements, thereby increasing the detection requirements of the alignment mark.

[0047] For example, for one type of lithography machine, when the ratio between the intensity of the reflected light and the set standard intensity reaches 70% or even 90% (based on the lithography machine's own state), the alignment operation is considered successful and the lithography machine is able to perform the lithography process; otherwise, the alignment operation fails and the lithography machine cannot perform the lithography process.

[0048] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a device area and a marking area adjacent to the device area; forming a pad oxide layer on the substrate; forming an active area on the substrate in the device area, the active area comprising a pad oxide layer located in the device area; in the step of forming the active area on the substrate in the device area, forming a groove in the pad oxide layer in the marking area, the groove exposing the surface of the substrate, and using the groove as an alignment mark.

[0049] In other words, a pad oxide layer is formed on the substrate, and in the step of forming an active area on the substrate in the device area, a groove is formed in the pad oxide layer in the mark area, and the groove can be used as an alignment mark. Compared with the scheme of forming the alignment mark in the substrate, the optical path of the detection light can be shortened, the loss of the detection light can be reduced, and the intensity of the alignment signal can be increased, thereby reducing the difficulty of detecting the alignment mark; and by multiplexing the step of forming the active area to form the alignment mark, at least one patterning process is reduced, thereby reducing the implementation cost.

[0050] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below in conjunction with the accompanying drawings.

[0051] Figures 1 to 4It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0052] See also Figure 1 , providing a substrate 100, wherein the substrate 100 includes a device region I and a marking region II adjacent to the device region I.

[0053] The substrate 100 may provide a process operation basis for a formation process of a semiconductor structure.

[0054] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0055] In this embodiment, the device region I of the substrate 100 is used to prepare and form a semiconductor device (eg, a transistor), and the mark region II of the substrate 100 is used to form an alignment mark to achieve an alignment operation between patterns of different layers.

[0056] See also Figure 2 , a pad oxide layer 110 is formed on the substrate 100 .

[0057] The pad oxide layer 110 is used to provide a process basis for the subsequent formation of alignment marks (or trenches) and active areas.

[0058] In this embodiment, the material of the pad oxide layer 110 may include: one or more of silicon oxide, silicon nitride, aluminum oxide or zirconium oxide.

[0059] In a specific embodiment, the material of the pad oxide layer 110 is silicon oxide. By selecting silicon oxide as the material of the pad oxide layer 110, process compatibility can be improved and process risks can be reduced; moreover, compared with organic materials, silicon oxide has greater hardness and density, which is conducive to improving the protective effect of the pad oxide layer 110 on the surface of the substrate 100.

[0060] In this embodiment, a thermal oxidation process is used to form a pad oxide layer 110 on the substrate 100 .

[0061] In some other embodiments, a vapor deposition process is used to form the pad oxide layer 110 on the substrate 100 .

[0062] In this embodiment, the thickness D of the pad oxide layer 110 is 1200 angstroms to 15000 angstroms.

[0063] By making the thickness D of the pad oxide layer 110 to be 1200 angstroms to 15000 angstroms, on the one hand, the voltage resistance requirements of different types of semiconductor structures can be met, so that the breakdown voltage of the semiconductor structure can meet the design requirements; on the other hand, by making the thickness D of the pad oxide layer 110 to be 1200 angstroms to 15000 angstroms and the alignment mark being located in the pad oxide layer 110, the optical path of the detection light can be reduced, the light loss can be reduced, and the difficulty of detecting the alignment mark can be reduced while meeting the design requirements.

[0064] As a non-limiting example, by adopting the present solution to set the alignment mark on the substrate 100, when the intensity of the feedback signal is greater than 40%, the alignment is considered successful, which is much smaller than the 70% required by the existing solution, thereby reducing the difficulty of detecting the alignment mark.

[0065] It should be noted that the thickness D in this embodiment is a value based on the surface of the substrate 100 .

[0066] See also Figure 3 and Figure 4 An active area 140 is formed on the substrate 100 in the device area I, and the active area 140 includes a pad oxide layer 110 located in the device area I.

[0067] The active region 140 defines a formation area for active devices.

[0068] In this embodiment, the step of forming the active area 140 on the substrate 100 in the device area I includes:

[0069] See also Figure 3 , a barrier layer 120 is formed on the pad oxide layer 110 .

[0070] See next Figure 3 , a photoresist layer 130 is formed on the barrier layer 120 , wherein the photoresist layer 130 exposes a portion of the top of the barrier layer 120 to define an active region pattern.

[0071] See also Figure 4 , using the photoresist layer 130 as a mask, the barrier layer 120 and the pad oxide layer 110 located below the barrier layer 120 are etched in sequence to form an active area 140 on the substrate 100 of the device area I.

[0072] See next Figure 4 After the active region 140 is formed, a step of removing the photoresist layer 130 and the barrier layer 120 may be performed to expose the surface of the pad oxide layer 110 .

[0073] And by Figure 4It can be seen that the active region 140 includes the substrate 100 exposed by the pad oxide layer 110 in the device region I. In other words, the pad oxide layer 110 can define the region of the active region 140 .

[0074] In some other embodiments, during the step of forming the active region 140 , a shallow trench isolation structure (not shown) may be further formed in the substrate 100 , or in other words, the region between adjacent shallow trench isolation structures is the active region 140 .

[0075] In this embodiment, see Figure 3 and Figure 4 In the step of forming the active area 140 on the substrate 100 of the device area I, a groove G is formed in the pad oxide layer 110 of the mark area II, the groove G exposes the surface of the substrate 100, and the groove G is used as an alignment mark, such as a zero mark. In this way, the step of forming the active area 140 can be reused, at least one patterning process is reduced, thereby reducing the implementation cost.

[0076] It should be noted that, in the step of forming the active area 140 on the substrate 100 in the device area I, the trench G is formed in the pad oxide layer 110 in the marking area II” described in this embodiment means that in the process of forming the active area 140 by performing at least one patterning process, the trench G is formed in the pad oxide layer 110 by means of the patterning process of the active area 140, but there are some differences in the formation process of the active area 140 and the trench G:

[0077] For example, when performing a patterning process on the pad oxide layer 110 of the marking region II, the patterning processes of the pad oxide layer 110 of the marking region II and the device region I may be different.

[0078] As a non-limiting example, first, after forming the trench G, in the remaining steps of forming the active area 140, the pad oxide layer 110 located in the marking area II can be shielded to remove the pad oxide layer 110 in the area where the active area 140 is not located; second, when performing the patterning process, the actual etching process used is different, so as to form the following: Figure 4 The structure shown.

[0079] For another example, the formation timing of the trench G may be different from or the same as the formation timing of the active region 140 .

[0080] As a non-limiting example, the trench G is formed before performing the last step of forming the active region 140 ; ​​alternatively, the active region 140 and the trench G are formed at the same time.

[0081] In other words, it is only necessary to form the trench G in the pad oxide layer 110 of the marking region II during the step of forming the active region 140 .

[0082] In this embodiment, see Figure 3 and Figure 4 In the step of forming the active area 140 on the substrate 100 in the device area I, the step of forming the trench G in the pad oxide layer 110 in the marking area II may include:

[0083] A first initial trench G1 and a second initial trench G2 are formed in the pad oxide layer 110 , and the first initial trench G1 and the second initial trench G2 serve as the trench G.

[0084] The groove G is used as an alignment mark. During the photolithography process, the groove G serves as a target to be detected by the detection light.

[0085] In this embodiment, the alignment mark is an alignment mark of an ASML lithography machine. By replacing the zero-layer mark, a layer of lithography-etching process is omitted, time and cost are saved, and the productivity of the lithography and etching areas is improved. In this embodiment, in a direction perpendicular to the surface of the substrate 100, the first initial trench G1 and the second initial trench G2 are interconnected, and the second initial trench G2 is located in the pad oxide layer 110 below the first initial trench G1 and exposes the surface of the substrate 100.

[0086] In other words, the groove G is composed of two initial groove parts that penetrate each other, and the two initial groove parts expose the surface of the substrate 100 , so that the detection light can pass through the groove G and be incident on the surface of the substrate 100 .

[0087] In this embodiment, the angle α between the side wall of the first initial groove G1 and the top surface of the second initial groove G2 is greater than the angle ε between the side wall of the second initial groove G2 and the top of the substrate 100, and the top opening size of the first initial groove G1 is greater than the top opening size of the second initial groove G2.

[0088] That is to say, when the detection light is incident on the groove G, since the angle α is greater than the angle ε, and the top opening size of the first initial groove G1 is greater than the top opening size of the second initial groove G2, the detection light is concentrated from the large entrance to the small entrance, so that the detection light can be fully utilized, and since the top opening size of the second initial groove G2 is smaller, most of the detection light can be reflected by the second initial groove G2, which increases the intensity of the reflected signal and thereby reduces the difficulty of alignment.

[0089] The formation process of the groove G is described in detail below with reference to the accompanying drawings.

[0090] See also Figure 4 The step of forming the first initial trench G1 and the second initial trench G2 in the pad oxide layer 110 may include:

[0091] A portion of the pad oxide layer 110 is removed to form a first initial trench G1 , where the first initial trench G1 is located in the pad oxide layer 110 .

[0092] In this embodiment, a wet etching process is used to remove a portion of the pad oxide layer 110 to form the first initial trench G1.

[0093] In a specific embodiment, the parameters of the wet etching process include: the etching solution includes HF and NH4F, the time is 600s to 900s, and the temperature is 19 degrees Celsius to 25 degrees Celsius. Then, the remaining portion of the pad oxide layer 110 exposed by the first initial trench G1 is removed to form a second initial trench G2, which is located in the pad oxide layer 110 below the first initial trench G1 and exposes the surface of the substrate 100.

[0094] In this embodiment, a dry etching process is used to remove the remaining portion of the pad oxide layer 110 exposed by the first initial trench G1 to form the second initial trench G2.

[0095] In a specific embodiment, the parameters of the dry etching process include: etching gas includes CH3F and CF4, pressure is 500mtorr to 1000mtorr, and time is 15s to 30s.

[0096] From the above content, it can be seen that the second initial groove G2 and the first initial groove G1 are obtained by etching the pad oxide layer 110 using different etching methods, and the reason for using different etching methods is that the wet etching process has an isotropic etching characteristic, thereby increasing the opening size of the first initial groove G1, and the dry etching process has good anisotropic etching characteristics, which can improve the fidelity of the pattern transfer, so that the second initial groove G2 has a smoother side wall, which is very important for enhancing the intensity of the reflected signal. This is because: the smoother the side wall of the second initial groove G2, the lower the stray or diffraction of the detection light and the reflected light, so that the detection light can be fully reflected.

[0097] As mentioned above, the thickness D of the pad oxide layer 110 is 1200 angstroms to 15000 angstroms, and the difference in thickness D is too large. The groove G is located in the pad oxide layer 110, so the depth of the groove G also varies in the range of 1200 angstroms to 15000 angstroms. Therefore, how to make the depth of the groove G meet the alignment requirements within such a large variation range becomes a difficulty.

[0098] In actual applications, the inventors found that the closer the angle ε between the side wall of the second initial groove G2 and the top of the substrate 100 is to 90°, the more obvious the step formed in the second initial groove G2 when a film layer is formed in the groove G. In this way, under the same other conditions, the intensity of light reflected by the second initial groove G2 can be increased to further reduce the difficulty of alignment.

[0099] In other words, the angle ε between the side wall of the second initial groove G2 and the top of the substrate 100 is determined according to the thickness of the pad oxide layer 110; wherein, the greater the thickness of the pad oxide layer 110, the further the angle ε between the side wall of the second initial groove G2 and the top of the substrate 100 is from 90°, and the angle between the side wall of the second initial groove and the top of the substrate is 80° to 90°.

[0100] This is because: as the thickness of the pad oxide layer 110 increases, during the etching process, the angle between the side wall of the first initial trench G1 and the top of the second initial trench G2 becomes larger (for example, from approaching 90° to 150°), so that when the second initial trench G2 is formed, the angle ε is away from 90°.

[0101] It can be understood that, ideally, when other conditions are the same, when the angle ε between the sidewall of the second initial groove G2 and the top of the substrate 100 is 90°, the intensity of the reflected signal is stronger.

[0102] In the present embodiment, the angle α between the side wall of the first initial groove G1 and the top of the second initial groove G2 is 90° to 150°. In this way, the top opening size of the first initial groove G1 is larger than the top opening size of the second initial groove G2, so that the junction of the first initial groove G1 and the second initial groove G2 presents a characteristic of being from large to small, which increases the entrance of the detection light. Moreover, since the opening size of the second initial groove G2 is smaller, most of the detection light can be converged on the substrate 100 exposed by the second initial groove G2, thereby improving the utilization rate of the detection light.

[0103] In this embodiment, the thickness D of the pad oxide layer 110 varies in the range of 1200 angstroms to 15000 angstroms, so the depth of the trench G also varies accordingly.

[0104] In a specific embodiment, the greater the thickness of the pad oxide layer 110, the greater the proportion of the thickness of the first initial groove G1, so that the angle α between the side wall of the first initial groove G1 and the top of the second initial groove G2 is greater, which can further increase the step depth, make the depression more obvious, enhance the intensity of the reflected light, and reduce the difficulty of detection. More specifically, as the thickness of the pad oxide layer 110 increases, the thickness of the first initial groove G1 increases, while the thickness of the second initial groove G2 remains unchanged. That is: the increased thickness of the oxide layer 110 is used as the first initial groove G1.

[0105] In order to solve the above technical problem, the present invention also provides a semiconductor structure.

[0106] Figure 4 is a schematic diagram of a semiconductor structure corresponding to the first embodiment of the semiconductor structure of the present invention, see Figure 4 The semiconductor structure includes: a substrate 100, wherein the substrate 100 includes a device region I and a mark region II adjacent to the device region I; a pad oxide layer 110, located on the substrate 100, and the pad oxide layer 110 on the substrate 100 located in the mark region II has a groove G, wherein the groove G exposes the surface of the substrate 100, and the groove G is used as an alignment mark; an active region 140, located in the device region I, and the active region 140 includes the substrate 100 where the pad oxide layer 110 of the device region I is exposed.

[0107] The substrate 100 may provide a process operation basis for a formation process of a semiconductor structure.

[0108] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0109] In this embodiment, the device region I of the substrate 100 is used to prepare and form a semiconductor device (eg, a transistor), and the mark region II of the substrate 100 is used to form an alignment mark to achieve an alignment operation between patterns of different layers.

[0110] The pad oxide layer 110 is used to provide a process basis for the subsequent formation of alignment marks (or trenches) and active areas.

[0111] In this embodiment, the material of the pad oxide layer 110 may include: one or more of silicon oxide, silicon nitride, aluminum oxide or zirconium oxide.

[0112] In a specific embodiment, the material of the pad oxide layer 110 is silicon oxide. By selecting silicon oxide as the material of the pad oxide layer 110, process compatibility can be improved and process risks can be reduced; moreover, compared with organic materials, silicon oxide has greater hardness and density, which is conducive to improving the protective effect of the pad oxide layer 110 on the surface of the substrate 100.

[0113] In this embodiment, the thickness D of the pad oxide layer 110 is 1200 angstroms to 15000 angstroms.

[0114] By making the thickness D of the pad oxide layer 110 to be 1200 angstroms to 15000 angstroms, on the one hand, the voltage resistance requirements of different types of semiconductor structures can be met, so that the breakdown voltage of the semiconductor structure can meet the design requirements; on the other hand, by making the thickness D of the pad oxide layer 110 to be 1200 angstroms to 15000 angstroms and the alignment mark being located in the pad oxide layer 110, the optical path of the detection light can be reduced, the light loss can be reduced, and the difficulty of detecting the alignment mark can be reduced while meeting the design requirements.

[0115] As a non-limiting example, by adopting the present solution to set the alignment mark on the substrate 100, when the intensity of the feedback signal is greater than 40%, the alignment is considered successful, which is much smaller than the 70% required by the existing solution, thereby reducing the difficulty of detecting the alignment mark.

[0116] It should be noted that the thickness D in this embodiment is a value based on the surface of the substrate 100 .

[0117] The active region 140 defines a region for forming active devices, and the active region 140 includes a pad oxide layer 110 located in the device region I.

[0118] In some other embodiments, the substrate 100 further has a shallow trench isolation structure (not shown), and the area between adjacent shallow trench isolation structures is the active area 140 .

[0119] The groove G is used as an alignment mark. During the photolithography process, the groove G serves as a target to be detected by the detection light.

[0120] In this embodiment, the alignment mark is an alignment mark of an ASML lithography machine. By replacing the zero-layer mark, a layer of lithography-etching process is omitted, time and cost are saved, and the productivity of the lithography-etching area is improved.

[0121] In this embodiment, the groove G may include: a second initial groove G2 and a first initial groove G1 that penetrate each other in a direction perpendicular to the surface of the substrate 100, the second initial groove G2 exposes the surface of the substrate 100, and the first initial groove G1 is located above the second initial groove G2.

[0122] In other words, the groove G is composed of two initial groove parts that penetrate each other, and the two initial groove parts expose the surface of the substrate 100 , so that the detection light can pass through the groove G and be incident on the surface of the substrate 100 .

[0123] In this embodiment, the angle α between the side wall of the first initial groove G1 and the top surface of the second initial groove G2 is greater than the angle ε between the side wall of the second initial groove G2 and the top of the substrate 100, and the top opening size of the first initial groove G1 is greater than the top opening size of the second initial groove G2.

[0124] That is to say, when the detection light is incident on the groove G, since the angle α is greater than the angle ε, and the top opening size of the first initial groove G1 is greater than the top opening size of the second initial groove G2, the detection light is concentrated from the large entrance to the small entrance, so that the detection light can be fully utilized, and since the top opening size of the second initial groove G2 is smaller, most of the detection light can be reflected by the second initial groove G2, which increases the intensity of the reflected signal and thereby reduces the difficulty of alignment.

[0125] As mentioned above, the thickness D of the pad oxide layer 110 is 1200 angstroms to 15000 angstroms, and the difference in thickness D is too large. The groove G is located in the pad oxide layer 110, so the depth of the groove G also varies in the range of 1200 angstroms to 15000 angstroms. Therefore, how to make the depth of the groove G meet the alignment requirements within such a large variation range becomes a difficulty.

[0126] In actual applications, the inventors found that the closer the angle ε between the side wall of the second initial groove G2 and the top of the substrate 100 is to 90°, the more obvious the step formed in the second initial groove G2 when a film layer is formed in the groove G. In this way, under the same other conditions, the intensity of light reflected by the second initial groove G2 can be increased to further reduce the difficulty of alignment.

[0127] In other words, the angle ε between the side wall of the second initial groove G2 and the top of the substrate 100 is determined according to the thickness of the pad oxide layer 110; wherein, the greater the thickness of the pad oxide layer 110, the further the angle ε between the side wall of the second initial groove G2 and the top of the substrate 100 is away from 90°, and the angle between the side wall of the second initial groove and the top of the substrate is 80° to 90°.

[0128] This is because: as the thickness of the pad oxide layer 110 increases, during the etching process, the angle between the side wall of the first initial trench G1 and the top of the second initial trench G2 becomes larger (for example, from approaching 90° to 150°), so that when the second initial trench G2 is formed, the angle ε is away from 90°.

[0129] It can be understood that, ideally, when other conditions are the same, when the angle ε between the sidewall of the second initial groove G2 and the top of the substrate 100 is 90°, the intensity of the reflected signal is stronger.

[0130] In the present embodiment, the angle α between the side wall of the first initial groove G1 and the top of the second initial groove G2 is greater than 90° to 150°. In this way, the top opening size of the first initial groove G1 is larger than the top opening size of the second initial groove G2, so that the junction of the first initial groove G1 and the second initial groove G2 presents a characteristic of being from large to small, which increases the entrance of the detection light. Moreover, since the opening size of the second initial groove G2 is smaller, most of the detection light can be converged on the substrate 100 exposed by the second initial groove G2, thereby improving the utilization rate of the detection light.

[0131] In this embodiment, the thickness D of the pad oxide layer 110 varies in the range of 1200 angstroms to 15000 angstroms, so the depth of the trench G also varies accordingly.

[0132] In a specific embodiment, the greater the thickness of the pad oxide layer 110, the greater the proportion of the thickness of the first initial groove G1, so that the angle α between the side wall of the first initial groove G1 and the top of the second initial groove G2 is greater, which can further increase the step depth, make the depression more obvious, enhance the intensity of the reflected light, and reduce the difficulty of detection.

[0133] More specifically, as the thickness of the pad oxide layer 110 increases, the thickness of the first initial trench G1 increases, while the thickness of the second initial trench G2 remains unchanged. That is, the increased thickness portion of the oxide layer 110 is used as the first initial trench G1.

[0134] See also Figure 5 The semiconductor structure diagram corresponding to the second embodiment of the present invention is shown. The similarities between this embodiment and the previous embodiment are not described again. The difference is that:

[0135] See also Figure 5 The semiconductor structure may further include: a silicate glass material layer 150 , wherein the silicate glass material layer 150 is located on the pad oxide layer 110 .

[0136] The silicate glass material layer 150 can isolate the substrate 100 from other film layers (such as the metal layer 160 ), thereby improving the formation quality of the substrate 100 .

[0137] In this embodiment, the material of the silicate glass material layer 150 may include one or more of USG, PSG or BPSG.

[0138] In a specific embodiment, the material of the silicate glass material layer 150 is BPSG. Compared with common silicon oxide, PSG has better hole filling ability and lower reflow temperature, and can improve the density of the silicate glass material layer 150 .

[0139] In this embodiment, since the alignment mark is located above the substrate, the signal strength of the first feedback signal of the alignment mark obtained from the surface of the silicate glass material layer 150 is 75% to 85%, thereby meeting the alignment requirement of the lithography machine.

[0140] The first feedback signal is used to represent the ratio of the reflection signal and the detection signal obtained by detecting the alignment mark from the surface of the silicate glass material layer 150 through the silicate glass material layer 150 .

[0141] In other words, the detection signal corresponding to the detection light has a preset intensity value. When the detection light passes through the silicate glass material layer 150 and is incident on the alignment mark and is reflected by the alignment mark, the reflected signal can be received at the receiving end, and the reflected signal has a detection intensity value. The ratio of the detection intensity value of the reflected signal to the preset intensity value is used as the signal strength of the first feedback signal.

[0142] See also Figure 5 The semiconductor structure may further include: a metal material layer 160 , wherein the metal material layer 160 is located on the silicate glass material layer 150 .

[0143] The metal material layer 160 is used to realize the connection between the substrate 100 and the subsequently formed semiconductor device.

[0144] In this embodiment, the material of the metal material layer 160 is AlSi or AlSiCu.

[0145] In a specific embodiment, the material of the metal material layer 160 is AlSi.

[0146] Since the alignment mark is located above the substrate, the signal strength of the second feedback signal of the alignment mark obtained from the surface of the metal material layer 160 is 70% to 80%, thereby meeting the alignment requirement of the lithography machine.

[0147] The second feedback signal is used to indicate the ratio of the reflection signal and the detection signal obtained by detecting the alignment mark from the surface of the metal material layer 160 through the metal material layer 160 and the silicate glass material layer 150 .

[0148] In other words, the detection signal corresponding to the detection light has a preset intensity value. When the detection light passes through the silicate glass material layer 150 and the metal material layer 160 in sequence and is incident on the alignment mark, and is reflected by the alignment mark, the reflected light passes through the metal material layer 160 and the silicate glass material layer 150 in sequence and is received by the receiving end, and the reflected signal has a detection intensity value. The ratio of the detection intensity value of the reflected signal to the preset intensity value is used as the signal strength of the second feedback signal.

[0149] In this embodiment, when the semiconductor structure includes both the silicate glass material layer 150 and the metal material layer 160 , the signal strength of the second feedback signal may be greater than the signal strength of the first feedback signal.

[0150] It should be noted that the semiconductor structure described in this embodiment can be formed by the formation method described in the previous embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.

[0151] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a device area and a marking area adjacent to the device area; forming a pad oxide layer on the substrate; forming an active region on the substrate in the device region, wherein the active region includes the substrate where the pad oxide layer in the device region is exposed; In the step of forming an active area on the substrate in the device area, a groove is formed in the pad oxide layer in the mark area, the groove exposes the surface of the substrate, and the groove is used as an alignment mark.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming an active area on the substrate of the device area, the step of forming a groove in the pad oxide layer of the mark area includes: Forming a first initial trench and a second initial trench in the pad oxide layer, the first initial trench and the second initial trench serving as the trenches, the first initial trench and the second initial trench interpenetrating each other in a direction perpendicular to the surface of the substrate, and the second initial trench being located in the pad oxide layer below the first initial trench and exposing the surface of the substrate; The angle between the sidewall of the first initial groove and the top surface of the second initial groove is greater than the angle between the sidewall of the second initial groove and the top of the substrate, and the top opening size of the first initial groove is greater than the top opening size of the second initial groove.

3. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming a first initial trench and a second initial trench in the pad oxide layer comprises: Removing a portion of the pad oxide layer to form a first initial trench, wherein the first initial trench is located in the pad oxide layer; The remaining portion of the pad oxide layer exposed by the first initial trench is removed to form a second initial trench, wherein the second initial trench is located in the pad oxide layer below the first initial trench and exposes the surface of the substrate.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: A wet etching process is adopted to remove a portion of the pad oxide layer to form the first initial trench.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: The parameters of the wet etching process include: the etching solution includes HF and NH4F, the time is 600s to 900s, and the temperature is 19 degrees Celsius to 25 degrees Celsius.

6. The method for forming a semiconductor structure according to claim 3, wherein: A dry etching process is adopted to remove the remaining portion of the pad oxide layer exposed by the first initial trench to form the second initial trench.

7. The method for forming a semiconductor structure according to claim 6, wherein: The parameters of the dry etching process include: etching gas includes CH3F and CF4, pressure is 500mtorr to 1000mtorr, and time is 15s to 30s.

8. The method for forming a semiconductor structure according to claim 2, wherein: The angle between the sidewall of the second initial trench and the top of the substrate is determined according to the thickness of the pad oxide layer; The greater the thickness of the pad oxide layer, the further the angle between the sidewall of the second initial trench and the top of the substrate is from 90°, and the angle between the sidewall of the second initial trench and the top of the substrate is 80° to 90°.

9. The method for forming a semiconductor structure according to claim 2, wherein: An included angle between a sidewall of the first initial trench and a top of the second initial trench is 90° to 150°.

10. The method for forming a semiconductor structure according to claim 2, wherein: The greater the thickness of the pad oxide layer, the greater the proportion of the thickness of the first initial trench.

11. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the pad oxide layer is 1200 angstroms to 15000 angstroms.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the pad oxide layer includes one or more of silicon oxide, silicon nitride, aluminum oxide or zirconium oxide.

13. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a device area and a marking area adjacent to the device area; A pad oxide layer is located on the substrate, and the pad oxide layer located on the substrate in the marking area has a groove, the groove exposes the surface of the substrate, and the groove is used as an alignment mark; The active area is located in the device area, and the active area includes a substrate where the pad oxide layer of the device area is exposed.

14. The semiconductor structure according to claim 13, characterized in that: The grooves include: a second initial groove and a first initial groove which penetrate each other in a direction perpendicular to the surface of the substrate, the second initial groove exposes the surface of the substrate, and the first initial groove is located above the second initial groove; The angle between the sidewall of the first initial groove and the top surface of the second initial groove is greater than the angle between the sidewall of the second initial groove and the top of the substrate, and the top opening size of the first initial groove is greater than the top opening size of the second initial groove.

15. The semiconductor structure according to claim 14, characterized in that: The angle between the sidewall of the second initial trench and the top of the substrate is determined according to the thickness of the pad oxide layer; The greater the thickness of the pad oxide layer, the further the angle between the sidewall of the second initial trench and the top of the substrate is from 90°, and the angle between the sidewall of the second initial trench and the top of the substrate is 80° to 90°.

16. The semiconductor structure according to claim 14, characterized in that An included angle between a sidewall of the first initial trench and a top of the second initial trench is 90° to 150°.

17. The semiconductor structure according to claim 13, characterized in that The thickness of the pad oxide layer is 1200 angstroms to 15000 angstroms.

18. The semiconductor structure according to claim 13, characterized in that The material of the pad oxide layer includes one or more of silicon oxide, silicon nitride, aluminum oxide or zirconium oxide.

19. The semiconductor structure according to claim 13, characterized in that Also includes: a silicate glass material layer, wherein the silicate glass material layer is located on the pad oxide layer; Among them, the signal strength of the first feedback signal of the alignment mark obtained from the surface of the silicate glass material layer is 75% to 85%, and the first feedback signal is used to represent the ratio of the reflection signal and the detection signal obtained from the surface of the silicate glass material layer through the silicate glass material layer to detect the alignment mark.

20. The semiconductor structure according to claim 19, characterized in that Also includes: A metal material layer, wherein the metal material layer is located on the silicate glass material layer; Wherein, the signal strength of the second feedback signal of the alignment mark obtained from the surface of the metal material layer is 70% to 80%; The second feedback signal is used to indicate the ratio of the reflection signal and the detection signal obtained by detecting the alignment mark from the surface of the metal material layer through the metal material layer and the silicate glass material layer.

21. The semiconductor structure according to claim 19, characterized in that The material of the silicate glass material layer includes one or more of USG, PSG or BPSG.

22. The semiconductor structure according to claim 13, characterized in that The alignment mark is an alignment mark of an ASML lithography machine.

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