Substrate for semiconductor package and semiconductor package including same

Abstract

The invention provides a substrate for a semiconductor package and a semiconductor package including the same, wherein high-frequency communication can be realized, and a direct electroless gold plating (DEG) plating layer without a fine pitch corresponding nickel plating layer is formed on the substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor package substrate capable of realizing high frequency communication and having a direct chemical gold (DEG) plating layer formed thereon without a nickel plating layer corresponding to a fine pitch, and a semiconductor package including the substrate. Background Art

[0002] In the manufacture of electronic components, the step of forming a circuit on a semiconductor wafer is called a front-end process, and the step of assembling the wafer into a state that can be used in an actual product is called a back-end process, or a packaging process.

[0003] In the field of semiconductor packaging, new packaging technologies that are thinner, lighter and shorter have been developed and replaced by wire bonding technology or flip chip bonding technology.

[0004] Among them, wire bonding technology is a method of bonding thin metal wires to pads. That is, it is a technology for connecting the internal chip and the outside. Structurally, the wire acts as a bridge connecting the bonding pads of the chip (primary bonding) and the pads of the carrier (secondary bonding). Currently, the substrate used as the carrier is mainly a printed circuit board (PCB).

[0005] Moreover, there are three ways to connect the lead to the pad, namely, a thermal compression method that uses heat to heat and press to connect the bonding pad and a capillary (capillary, a capillary-shaped lead moving tool), a method of applying ultrasound to the capillary for bonding without using heat, and a composite method that uses both heat and ultrasound.

[0006] First, the thermal compression method is as follows, that is, the temperature of the chip bonding pad is raised to about 200°C in advance, and the temperature of the tip (Tip, end) of the splitter is also raised to make the lead into a ball shape, so that the splitter applies pressure to the bonding pad to attach the lead.

[0007] The ultrasonic method is a method in which the lead is punched onto the pad and ultrasonic waves are applied to a wedge (a lead moving tool similar to a wedge, which does not form a ball) to attach the lead to the pad. It has the advantage of low cost in terms of process and material. However, since ultrasonic waves are used instead of heat and pressure, it has the disadvantage of being easy to operate but poor in tensile strength after bonding (the force that the lead can withstand when it is pulled after wiring).

[0008] The most commonly used method in semiconductor processes is the thermosonic method, which combines the advantages of the thermocompression method and the ultrasonic method. Heat, pressure, and ultrasonic waves are applied to the splitter to perform bonding under optimal conditions. Compared with cost, the semiconductor back-end process attaches more importance to the bonding strength, so even though it is expensive, the thermosonic method using gold wire is mainly used.

[0009] In addition, the flip chip bonding technology is a form in which the semiconductor chip is facing downward and the metal protrusions that carry electricity are connected to the pads. Since the flip chip bonding is directed to the substrate without leads, it has the following characteristics, namely, reduced volume, reduced power consumption, reduced peripheral noise influence, fast speed due to the small signal movement distance, and high fixing strength.

[0010] Among them, the materials of metal protrusions mainly use solder (Solder) and gold (Au). Metal protrusions refer to conductive metal protrusions used to connect chips to circuit substrates through tape automated bonding (TAB) and flip chip (FC) methods, or conductive metal protrusions used to directly connect ball grid arrays (BGA) and chip scale packages (CSP) to circuit substrates.

[0011] The solder bumps are formed into spherical shapes by surface tension after the reflow process, and the gold bumps, which are one type of metal bumps, are formed into rectangular shapes with length, width, and height by gold electroplating.

[0012] The wafers with gold bumps will be used for TCP (tape carrier package), COG (Chip on Glass) packaging, and COF (chip on Film) packaging, and will be used in products such as televisions (TV), monitors, networks, mobile devices, tablets, and automotive DIC (Digital Image Correlation).

[0013] Since gold plating is excellent in physical and chemical properties such as conductivity, oxidation resistance, and chemical resistance, it is used for a variety of purposes in microelectronics and optoelectronics fields such as RDL (redistribution layer), pattern plating, conformal via coating, X-ray mask, MEMS (micro-electromechanical system), and gold bumping.

[0014] Currently, although nickel plating is formed on the semiconductor package substrate as described above, nickel plating is difficult to use for fine pitches due to its high plating thickness, cracks may occur due to the poor flexibility of nickel metal, and there is a lot of signal loss at high frequencies due to its magnetic nature.

[0015] Therefore, after hard work and multiple studies, the applicant has obtained a semiconductor package substrate that can achieve high-frequency communication and is formed with a direct chemical gold (DEG) plating layer without a fine pitch corresponding nickel plating layer, and a semiconductor package including the same, thereby completing the present invention.

[0016] Prior art literature

[0017] Patent Literature

[0018] Korean Patent No. 10-2433203 (Patent Announcement Date: August 16, 2022) Summary of the invention

[0019] Therefore, an object of the present invention is to provide a semiconductor package substrate having a direct chemical gold plating film formed thereon without a fine pitch-compatible nickel plating layer.

[0020] Another object of the present invention is to provide a semiconductor package including a semiconductor package substrate formed with a direct chemical gold plating film without a fine pitch compatible nickel plating layer.

[0021] The purpose of the present invention is not limited to the above-mentioned purpose, and other purposes not mentioned can be clearly understood by those skilled in the art through the following description.

[0022] In order to achieve the above-mentioned purpose, according to one embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; and a gold plating film formed on the above-mentioned strike gold plating film. In the above-mentioned semiconductor packaging substrate, the spacing is the sum of the circuit width and the spacing width. When used for fine circuits with a spacing level of 4 to 50 μm, the diffusion of the gold plating film of the above-mentioned semiconductor packaging substrate is 0.001 to 10 volume percent.

[0023] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; and a gold plating film formed on the above-mentioned strike gold plating film. When the above-mentioned semiconductor packaging substrate is measured by the high-speed ball shear strength evaluation condition of the following evaluation condition 1, the average high-speed ball shear strength is 1000~1600gf.

[0024] [Evaluation Condition 1]

[0025] High-speed shearing equipment: Dage 4000HS

[0026] Shear speed: 1m / s

[0027] Shear height: 50μm

[0028] Ball grid array (BGA) pad diameter: 350μm

[0029] Solder Ball Diameter: 450μm

[0030] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent of tin (Sn), 3 weight percent of silver (Ag) and 0.5 weight percent of copper (Cu))

[0031] Measurement points: n=25.

[0032] In addition, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; and a gold plating film formed on the above-mentioned strike gold plating film, and the void area of ​​the above-mentioned semiconductor packaging substrate is 0.005 to 10 volume percent.

[0033] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; and a gold plating film formed on the above-mentioned strike gold plating film. When the above-mentioned semiconductor packaging substrate is measured by the lead pull strength evaluation condition of the following evaluation condition 2, the lead pull strength is 6 to 14 gf.

[0034] [Evaluation Condition 2]

[0035] Wire Bonder: Wire Bonder-HB16

[0036] Pull Tester: Dage 4000

[0037] Au wire: 1mil

[0038] Bonding conditions:

[0039] 1st Bond – 300Hz (US), 250ms (time

[0040] (Time)), pressure (force) 250mN;

[0041] 2nd Bond – 400Hz (US), 350mls (time),

[0042] Pressure: 250mN

[0043] Heat treatment conditions: 175°C, 6 hours.

[0044] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above copper substrate; and a gold plating film formed on the above strike gold plating film, and the thickness of the above gold plating film is 2 to 1000 nm.

[0045] According to another embodiment of the present invention, there is provided a semiconductor package substrate, characterized in that it includes: a copper substrate; a strike gold plating film formed on the copper substrate; and a gold plating film formed on the strike gold plating film.

[0046] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above copper substrate; and a gold plating film formed on the above strike gold plating film, and the thickness of the above strike gold plating film is 2 to 30 nm.

[0047] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; and a gold plating film formed on the above-mentioned strike gold plating film. When the above-mentioned semiconductor packaging substrate is evaluated under the solder diffusion evaluation condition of the following evaluation condition 3, the solder ball diffusion is the solder ball diffusion diameter / solder ball diameter (N), and the diffusion multiple N is 1.2 to 6.

[0048] [Evaluation Condition 3]

[0049] Evaluation by reflowing the solder balls

[0050] Solder ball diameter: 300μm

[0051] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0052] Reflow conditions: preheat at 130 to 200°C for 80 to 120 seconds, then perform bonding (soldering) at 240 to 260°C for 20 to 60 seconds.

[0053] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; and a gold plating film formed on the above-mentioned strike gold plating film, and when the above-mentioned semiconductor packaging substrate is evaluated by the following anisotropic conductive film (ACF) bonding condition of evaluation condition 4 and the following tensile force measurement condition of evaluation condition 5, the bonding tensile force is 1000~1600g / cm.

[0054] [Evaluation Condition 4]

[0055] Temperature: 170℃

[0056] Pressure: 12.30kgf

[0057] Time: 7 seconds,

[0058] [Evaluation Condition 5]

[0059] Angle: 90°

[0060] Speed: 833μm / sec (seconds)

[0061] Tape: Low temperature tape AC-3614KS-25 (1.0×100mm)

[0062] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; and a gold plating film formed on the above-mentioned strike gold plating film. When the bendability of the above-mentioned semiconductor packaging substrate is evaluated by the crack (MIT) evaluation condition of the following evaluation condition 6, the bendability reaches 50 to 220 times after reflow soldering 2 to 5 times.

[0063] [Evaluation Condition 6]

[0064] Bendability testing equipment: MIT-DA / TOYOSEIKI

[0065] Loading: 500g

[0066] Bending speed: 175 times / min

[0067] Bending angle: 135°

[0068] Reflow conditions: preheating at 130-200°C for 80-120 seconds, followed by irreversible heating (heat aging) at 240-260°C for 20-60 seconds.

[0069] Furthermore, according to another embodiment of the present invention, a semiconductor packaging substrate is provided, characterized in that it includes: a copper substrate; and a gold plating film formed on the above-mentioned copper substrate, in which the spacing in the above-mentioned semiconductor packaging substrate is the sum of the circuit width and the spacing width, and when used for fine circuits with a spacing level of 4μm to 50μm, the diffusion of the gold plating film of the above-mentioned semiconductor packaging substrate is 0.001 volume percent to 5 volume percent.

[0070] Furthermore, according to another embodiment of the present invention, a semiconductor packaging substrate is provided, characterized in that it includes: a copper substrate; and a gold plating film formed on the copper substrate, and the void area of ​​the semiconductor packaging substrate is 0.005 to 10 volume percent.

[0071] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; and a gold plating film formed on the above-mentioned copper substrate. When the above-mentioned semiconductor packaging substrate is measured by the high-speed ball shear strength evaluation condition of the following evaluation condition 1, the average high-speed ball shear strength is 1000~1600gf.

[0072] [Evaluation Condition 1]

[0073] High-speed shearing equipment: Dage 4000HS

[0074] Shear speed: 1m / s

[0075] Shear height: 50μm

[0076] Ball grid array pad diameter: 350μm

[0077] Solder ball diameter: 450μm

[0078] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0079] Measurement points: n=25.

[0080] Furthermore, according to another embodiment of the present invention, a semiconductor packaging substrate is provided, characterized in that it includes: a copper substrate; and a gold plating film formed on the above-mentioned copper substrate, in which the spacing in the above-mentioned semiconductor packaging substrate is the sum of the circuit width and the spacing width, and the above-mentioned semiconductor packaging substrate is used for fine circuits with a spacing level of 4μm to 50μm.

[0081] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; and a gold plating film formed on the above-mentioned copper substrate. When the above-mentioned semiconductor packaging substrate is measured by the lead pull strength evaluation condition of the following evaluation condition 2, the lead pull strength is 6 to 14 gf.

[0082] [Evaluation Condition 2]

[0083] Wire Bonder: Wire Bonder-HB16

[0084] Tensile tester: Dage 4000

[0085] Gold wire: 1mil

[0086] Bonding conditions:

[0087] First bonding point – 300 Hz (US), 250 ms (time), pressure 250 mN;

[0088] Second bond point – 400Hz (US), 350mls (time), pressure 250mN

[0089] Heat treatment conditions: 175°C, 6 hours

[0090] According to another embodiment of the present invention, there is provided a semiconductor package substrate, which includes: a copper substrate; and a gold plating film formed on the copper substrate, wherein the thickness of the gold plating film is 2 nm to 1000 nm.

[0091] According to another embodiment of the present invention, there is provided a semiconductor package substrate, which includes: a copper substrate; and a gold plating film formed on the copper substrate.

[0092] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; and a gold plating film formed on the above-mentioned copper substrate. When the above-mentioned semiconductor packaging substrate is evaluated by the solder diffusion evaluation condition of the following evaluation condition 3, the solder ball diffusion is the solder ball diffusion diameter / solder ball diameter (N), and the diffusion multiple N is 1.2 to 6.

[0093] [Evaluation Condition 3]

[0094] Evaluation by reflowing the solder balls

[0095] Solder ball diameter: 300μm

[0096] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0097] Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform bonding (soldering) at 240-260°C for 20-60 seconds

[0098] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; and a gold-plated film formed on the above-mentioned copper substrate, and when the above-mentioned semiconductor packaging substrate is evaluated by the following anisotropic conductive film (ACF) bonding condition of evaluation condition 4 and the following tensile force measurement condition of evaluation condition 5, the bonding tensile force is 1000 to 1600 g / cm.

[0099] [Evaluation Condition 4]

[0100] Temperature: 170℃

[0101] Pressure: 12.30kgf

[0102] Time: 7 seconds,

[0103] [Evaluation Condition 5]

[0104] Angle: 90°

[0105] Speed: 833μm / sec

[0106] Tape: Low temperature tape AC-3614KS-25 (1.0×100mm).

[0107] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; and a gold plating film formed on the above-mentioned copper substrate. When the bendability of the above-mentioned semiconductor packaging substrate is evaluated by the crack (MIT) evaluation condition of the following evaluation condition 6, the bendability reaches 50 to 220 times after reflow soldering 2 to 5 times.

[0108] [Evaluation Condition 6]

[0109] Bendability testing equipment: MIT-DA / TOYOSEIKI

[0110] Loading: 500g

[0111] Bending speed: 175 times / minute

[0112] Bending angle: 135°

[0113] Reflow conditions: preheating at 130-200°C for 80-120 seconds, followed by irreversible heating (heat aging) at 240-260°C for 20-60 seconds.

[0114] Furthermore, according to still another embodiment of the present invention, a semiconductor package including the semiconductor package substrate is provided.

[0115] According to the present invention, a semiconductor package substrate having a direct chemical gold plating film without a nickel plating layer corresponding to a fine pitch can be provided, so that fine circuits are less diffused, it is easy to cope with fine pitches, and cracks are not generated.

[0116] Furthermore, since the present invention provides a semiconductor package including a semiconductor package substrate formed with a direct chemical gold plating film without a fine pitch corresponding nickel plating layer, the semiconductor package has excellent physical properties and is economical.

[0117] The effects of the present invention are not limited to the above effects, and should be understood to include all effects that can be derived from the structure of the invention described in the detailed description of the present invention or the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0118] Figure 1 FIG. 4 is a cross-sectional view of a semiconductor package substrate according to an embodiment of the present invention.

[0119] Figure 2 FIG. 1 is a scanning electron microscope (SEM) image showing a cross section of a semiconductor package substrate according to an embodiment of the present invention.

[0120] Figure 3 The depth graph of X-ray photoelectron spectroscopy (XPS) is shown to show the cross-sectional analysis and composition analysis of the impact gold plating film of the semiconductor package substrate according to one embodiment of the present invention.

[0121] Figure 4 This is a scanning electron microscope image showing whether or not there is diffusion of the gold plating film when the semiconductor package substrate according to one embodiment of the present invention is used for a fine pitch.

[0122] Figure 5 A high-speed ball shear strength chart and analysis results of a semiconductor package substrate according to an embodiment of the present invention.

[0123] Figure 6 The scanning electron microscope image is used to show whether a semiconductor package substrate according to another embodiment of the present invention has voids (voids between plating layers).

[0124] Figure 7 This is a graph showing the lead pull strength of a semiconductor package substrate according to an embodiment of the present invention.

[0125] Figure 8 The figure shows the solder diffusivity of the semiconductor package substrate according to one embodiment of the present invention and the analysis results.

[0126] Fig. 9FIG. 1 is a tensile force diagram and analysis results of a semiconductor package substrate according to an embodiment of the present invention.

[0127] Fig.10 The diagram and scanning electron microscope image show the bendability of the semiconductor package substrate according to one embodiment of the present invention, showing whether there are cracks.

[0128] Fig.11 The figure is a cross-sectional view of a semiconductor package substrate according to another embodiment of the present invention. DETAILED DESCRIPTION

[0129] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0130] References and Attachments Figure 1 The advantages, features and methods of achieving the same will be apparent from the various embodiments described in detail below.

[0131] However, the present invention is not limited to the multiple embodiments disclosed below, and may form a variety of different implementation methods. These embodiments only make the disclosure of the present invention complete, and the purpose is to enable ordinary technicians in the technical field to which the present invention belongs to fully understand the scope of the present invention. The present invention is only defined by the scope of the invention protection claims.

[0132] Furthermore, if it is determined during the description of the present invention that a related known technology or the like may obscure the gist of the present invention, the detailed description thereof will be omitted.

[0133] Hereinafter, the present invention will be described in detail.

[0134] Semiconductor packaging substrates—I

[0135] The present invention provides a semiconductor packaging substrate formed with a direct chemical gold plating film without a fine pitch corresponding nickel plating layer.

[0136] The semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; and a gold plating film formed on the strike gold plating film. In the semiconductor packaging substrate, the spacing may be a value obtained by adding a circuit width and a spacing width. When used for fine circuits with a spacing level of 4 to 50 μm, the diffusion of the gold plating film of the semiconductor packaging substrate may be 0.001 to 10 volume percent.

[0137] Since the present invention provides a semiconductor package substrate formed with a direct chemical gold plating film without a nickel plating layer corresponding to a fine pitch, the fine circuit has less diffusion, is easy to cope with a fine pitch, and does not generate cracks.

[0138] In the manufacture of electronic components, the step of forming a circuit on a semiconductor wafer is called a front-end process, and the step of assembling the wafer into a state that can be used in an actual product is called a back-end process, or a packaging process.

[0139] In the field of semiconductor packaging, new packaging technologies that are thinner, lighter and shorter have been developed and replaced by wire bonding technology or flip chip bonding technology.

[0140] Among them, wire bonding technology is a method of bonding thin metal wires to pads. That is, it is a technology for connecting the internal chip and the outside. Structurally, the wire acts as a bridge connecting the bonding pads of the chip (primary bonding) and the pads of the carrier (secondary bonding). Currently, the substrate used as the carrier is mainly a printed circuit board.

[0141] Moreover, there are three ways to connect the lead to the pad, namely, a thermal compression method that uses heat to heat and press to connect the bonding pad and a capillary (capillary, a capillary-shaped lead moving tool), a method of applying ultrasound to the capillary for bonding without using heat, and a composite method that uses both heat and ultrasound.

[0142] First, the thermal compression method is as follows, that is, the temperature of the chip bonding pad is raised to about 200°C in advance, and the temperature of the tip (Tip, end) of the splitter is also raised to make the lead into a ball shape, so that the splitter applies pressure to the bonding pad to attach the lead.

[0143] The ultrasonic method is a method in which the lead is punched onto the pad and ultrasonic waves are applied to a wedge (a lead moving tool similar to a wedge, which does not form a ball) to attach the lead to the pad. It has the advantage of low cost in terms of process and material. However, since ultrasonic waves are used instead of heat and pressure, it has the disadvantage of being easy to operate but poor in tensile strength after bonding (the force that the lead can withstand when it is pulled after wiring).

[0144] The most commonly used method in semiconductor processes is the thermosonic method, which combines the advantages of the thermocompression method and the ultrasonic method. Heat, pressure, and ultrasonic waves are applied to the splitter to perform bonding under optimal conditions. Compared with cost, the semiconductor back-end process attaches more importance to the bonding strength, so even though it is expensive, the thermosonic method using gold wire is mainly used.

[0145] In addition, the flip chip bonding technology is a form in which the semiconductor chip is facing downward and the metal protrusions that carry electricity are connected to the pads. Since the flip chip bonding is directed to the substrate without leads, it has the following characteristics, namely, reduced volume, reduced power consumption, reduced peripheral noise influence, fast speed due to the small signal movement distance, and high fixing strength.

[0146] Among them, the materials of metal protrusions mainly use solder (Solder) and gold (Au). Metal protrusions refer to conductive metal protrusions used to connect chips to circuit substrates through tape automated bonding (TAB) and flip chip (FC) methods, or conductive metal protrusions used to directly connect ball grid arrays (BGA) and chip scale packages (CSP) to circuit substrates.

[0147] The solder bumps are formed into spherical shapes by surface tension after the reflow process, and the gold bumps, which are one type of metal bumps, are formed into rectangular shapes with length, width, and height by gold electroplating.

[0148] The wafers with gold bumps will be used for TCP (tape carrier package), COG (Chip on Glass) packaging, and COF (chip on Film) packaging, and will be used in products such as televisions (TV), monitors, networks, mobile devices, tablets, and automotive DIC (Digital Image Correlation).

[0149] Since gold plating is excellent in physical and chemical properties such as conductivity, oxidation resistance, and chemical resistance, it is used for a variety of purposes in microelectronics and optoelectronics fields such as RDL (redistribution layer), pattern plating, conformal via coating, X-ray mask, MEMS (micro-electromechanical system), and gold bumping.

[0150] Currently, although nickel plating is formed on the semiconductor package substrate as described above, nickel plating is difficult to use for fine pitches due to its high plating thickness, cracks may occur due to the poor flexibility of nickel metal, and there is a lot of signal loss at high frequencies due to its magnetic nature.

[0151] Therefore, after hard work and multiple studies, the applicant has obtained a semiconductor package substrate that can achieve high-frequency communication and has a direct chemical gold plating layer without a fine-pitch corresponding nickel plating layer, and a semiconductor package including the same, thereby completing the present invention.

[0152] In this case, the semiconductor package substrate of the present invention may be a semiconductor package substrate on which no nickel plating layer is formed.

[0153] Therefore, since the semiconductor package substrate does not form a nickel plating layer as a post-film, signal loss is small in high-frequency communication, fine circuit diffusion is small, and it is easy to cope with fine pitches without generating cracks.

[0154] Furthermore, the copper substrate may be a copper metal substrate selected on a printed circuit board.

[0155] In this case, the copper metal substrate selected on the above-mentioned printed circuit board may include copper circuits.

[0156] Furthermore, the oxide film on the surface of the copper substrate can be appropriately removed by a reducing agent.

[0157] Furthermore, the copper substrate may have a thickness of 2 to 30 μm.

[0158] Among them, if the thickness of the above-mentioned copper base material is within the above-mentioned range, it can facilitate the transmission of electrical signals of the above-mentioned semiconductor package substrate.

[0159] In this case, the thickness of the copper substrate may preferably be 5 to 25 μm, and more preferably 5 to 20 μm.

[0160] Furthermore, the thickness of the copper substrate may be the thickness of the copper metal substrate selected on the printed circuit board.

[0161] Furthermore, the thickness of the copper substrate may be the copper thickness of the copper circuit.

[0162] Furthermore, the strike gold plating film formed on the copper substrate may be formed from a strike gold plating composition.

[0163] The above-mentioned strike gold plating composition may be a chemical strike gold plating composition.

[0164] In this case, the above-mentioned electroless strike gold plating composition may include a cyanide gold compound or a non-cyanide gold compound and a purine or pyrimidine compound having a carbonyl oxygen group.

[0165] Furthermore, the strike gold plating film formed on the copper substrate can act as a catalyst for the subsequent formation of a gold plating film.

[0166] Furthermore, the strike gold plating film formed on the copper substrate can suppress corrosion or voids (microscopic pores between plating layers) of the copper substrate.

[0167] Furthermore, the thickness of the strike gold plating film formed on the copper substrate may be 2 to 30 nm.

[0168] However, if the thickness of the strike gold plating film formed on the copper substrate exceeds the above range, corrosion or voids (microscopic pores between plating layers) of the copper substrate of the semiconductor package substrate may occur.

[0169] In this case, the thickness of the strike gold plating film formed on the copper substrate may preferably be 2 to 28 nm, and more preferably 2 to 25 nm.

[0170] Also, the gold plating film formed on the strike gold plating film may be formed from a gold plating composition.

[0171] The gold plating composition may be a chemical gold plating composition.

[0172] In this case, the electroless gold plating composition may include a cyanide gold compound or a non-cyanide gold compound, a carbonyl amide compound, and a nitrogen-containing heterocarboxylic acid.

[0173] Furthermore, the gold plating film formed on the above-mentioned strike gold plating film can play a role in electrically connecting the semiconductor chip to the copper substrate through a wire bonding process or a flip chip bonding process.

[0174] Furthermore, the gold plating film formed on the strike gold plating film can suppress erosion or dissolution of the copper substrate, thereby suppressing corrosion.

[0175] Furthermore, the thickness of the gold plating film formed on the strike gold plating film may be 2 to 1000 nm.

[0176] However, if the thickness of the gold plating film formed on the strike gold plating film exceeds the above range, erosion or dissolution of the copper base material of the semiconductor package substrate may occur, and corrosion may occur.

[0177] In this case, the thickness of the gold plating formed on the above-mentioned impact gold plating may preferably be 2 to 950 nm, more preferably 2 to 900 nm, even more preferably 2 to 800 nm, further preferably 2 to 700 nm, further preferably 2 to 600 nm, further preferably 2 to 500 nm, further preferably 2 to 400 nm, further preferably 2 to 300 nm, further preferably 2 to 200 nm, further preferably 2 to 150 nm, and most preferably 2 to 100 nm.

[0178] Figure 1 FIG. 4 is a cross-sectional view of a semiconductor package substrate according to an embodiment of the present invention.

[0179] Reference Figure 1 The semiconductor package substrate 100 includes: a strike gold plating film 130 formed on a copper substrate 110 ; and a gold plating film 150 formed on the strike gold plating film 130 .

[0180] Figure 2 FIG. 1 is a scanning electron microscope image showing a cross section of a semiconductor package substrate according to an embodiment of the present invention.

[0181] Reference Figure 2 The semiconductor packaging substrate includes a strike gold plating film (marked as Au on the upper part of Cu; not separated from the gold plating film) formed on a copper substrate (marked as Cu) and a gold plating film (marked as Au) formed on the above strike gold plating film.

[0182] Figure 3 The depth curve diagram of X-ray photoelectron spectroscopy is shown for cross-sectional analysis and composition analysis of an impact gold plating film of a semiconductor package substrate according to an embodiment of the present invention.

[0183] Reference Figure 3 An example of the thickness of the strike gold plating film of the semiconductor package substrate may be 5 to 9 nm.

[0184] Furthermore, in the semiconductor package substrate, the pitch is the sum of the circuit width and the spacing width. When used for fine circuits of 4 to 50 μm pitch level, the diffusion of the gold plating film of the semiconductor package substrate can be 0.001 to 10 volume percent.

[0185] The above-mentioned diffusibility of the gold plating film can be obtained by measuring the diffusion volume in a scanning electron microscope measurement.

[0186] When the diffusibility of the gold plating film is within the above range, the semiconductor package substrate can be used for fine pitches.

[0187] In this case, the diffusivity of the gold plating film may preferably be 0.001 to 9.8 volume percent, and more preferably 0.001 to 9.5 volume percent.

[0188] Figure 4 This is a scanning electron microscope image showing whether or not there is diffusion of the gold plating film when the semiconductor package substrate according to one embodiment of the present invention is used for a fine pitch.

[0189] Reference Figure 4 The semiconductor package substrate having a gold plating film with a thickness of 0.05 μm formed on the above-mentioned impact gold plating film can completely avoid the diffusion of the gold plating film in a fine circuit of a pitch level of 4 to 50 μm.

[0190] Furthermore, in the semiconductor package substrate in which the thickness of the gold plating film formed on the strike gold plating film is 0.15 μm, the diffusion of the gold plating film can be reduced to less than 1 volume percent in a fine circuit of a 4 to 50 μm pitch order.

[0191] Furthermore, in the semiconductor package substrate in which the thickness of the gold plating film formed on the strike gold plating film is 0.3 μm, the diffusion of the gold plating film can be reduced to 3 volume percent or less in a fine circuit of a 4 to 50 μm pitch level.

[0192] On the other hand, a semiconductor package substrate formed with an electroless nickel gold (ENIG, Electroless Nickel / Immersion Gold, Ni 2.5μm / Au 0.05μm) nickel-plated layer can achieve a gold plating film diffusivity of 57 volume percent in a fine circuit of a 4 to 50μm pitch level.

[0193] Furthermore, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; and a gold plating film formed on the strike gold plating film. When the semiconductor packaging substrate is measured by the high-speed ball shear strength evaluation condition of the following evaluation condition 1, the average high-speed ball shear strength can be 1000 to 1600 gf.

[0194] [Evaluation Condition 1]

[0195] High-speed shearing equipment: Dage 4000HS

[0196] Shear speed: 1m / s

[0197] Shear height: 50μm

[0198] Ball grid array pad diameter: 350μm

[0199] Solder ball diameter: 450μm

[0200] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0201] Measurement points: n = 25

[0202] The high-speed ball shear strength is used in flip chip bonding technology to evaluate the bonding strength between a semiconductor package substrate and a solder bump.

[0203] Among them, when the above-mentioned semiconductor packaging substrate is measured by the high-speed ball shear strength evaluation condition of the above-mentioned evaluation condition 1, if the above-mentioned average high-speed ball shear strength is within the above-mentioned range, the bonding strength between the semiconductor packaging substrate and the solder bump is excellent, and thus a good packaging process can be carried out.

[0204] In this case, the average high-speed ball shear strength may be preferably 1000 to 1550 gf, more preferably 1000 to 1500 gf, even more preferably 1000 to 1400 gf, and even more preferably 1000 to 1350 gf.

[0205] Figure 5 A high-speed ball shear strength chart and analysis results of a semiconductor package substrate according to an embodiment of the present invention.

[0206] Reference Figure 5 In the above-mentioned evaluation condition 1, the thickness of the gold plating formed on the above-mentioned impact gold plating is 0.03 μm, and the bonding strength between the direct chemical gold plating (DEG, Direct Electroless Gold)-0.03 semiconductor packaging substrate and the solder protrusion of the present invention can be an average high-speed ball shear strength of 1277.9 g.

[0207] Furthermore, in the evaluation condition 1, the bonding strength between the direct chemical gold plating-0.05 semiconductor package substrate of the present invention having a gold plating film having a thickness of 0.05 μm formed on the impact gold plating film and the solder bump can be an average high-speed ball shear strength of 1311.1 g.

[0208] Furthermore, in the evaluation condition 1, the bonding strength between the direct chemical gold plating-0.1 semiconductor package substrate of the present invention having a gold plating film having a thickness of 0.1 μm and the solder bump can be an average high-speed ball shear strength of 1321.2 g.

[0209] On the other hand, in the above evaluation condition 1, the bonding strength between the common electroless nickel gold (ENIG, Electroless Nikel / Immersion Gold; Ni 2.5 μm / Au 0.05 μm) semiconductor package substrate and the solder bump can be an average high-speed ball shear strength of 1080.5 g.

[0210] Furthermore, in the evaluation condition 1, the bonding strength between the highly flexible electroless nickel gold (ENIG, Electroless Nikel / Immersion Gold; Ni 2-5 μm / Au 0.03-0.15 μm) semiconductor package substrate and the solder bump can be an average high-speed ball shear strength of 1109.1 g.

[0211] Furthermore, in the evaluation condition 1, the bonding strength between the thin film chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni 0.1-0.3 μm / Au 0.03-0.15 μm) semiconductor package substrate and the solder bump can be an average high-speed ball shear strength of 1355.8 g.

[0212] Furthermore, in the evaluation condition 1, the bonding strength between the organic solderability preservative (OSP, Organic Solderability Preservative; 0.1-0.5 μm) semiconductor package substrate and the solder bump can be an average high-speed ball shear strength of 1275.3 g.

[0213] Therefore, when the above-mentioned semiconductor packaging substrate of the present invention is measured by the high-speed ball shear strength evaluation condition of the following evaluation condition 1, the average high-speed ball shear strength is greater than the average high-speed ball shear strength of ordinary chemical nickel gold (ENIG, Electroless Nikel / Immersion Gold; Ni 2.5μm / Au 0.05μm) semiconductor packaging substrate, high-flexibility chemical nickel gold (ENIG, Electroless Nikel / Immersion Gold; Ni 2~5μm / Au0.03~0.15μm) semiconductor packaging substrate and organic solderability protective layer (OSP, Organic Solderability Preservative; 0.1~0.5μm) semiconductor packaging substrate, so the bonding strength between the solder bumps can be better.

[0214] Furthermore, the semiconductor package of the present invention comprises: a copper substrate; a strike gold plating film formed on the copper substrate; and a gold plating film formed on the strike gold plating film. The void area of ​​the semiconductor package substrate can be 0.005 to 10 volume percent.

[0215] Furthermore, the void area on the copper substrate surface (microscopic pores between plating layers) is used to evaluate the copper substrate corrosion or solder brittle failure rate and is measured using a scanning electron microscope image.

[0216] If the void area on the surface of the copper substrate is within the above range, the semiconductor chip and the semiconductor package substrate can form an excellent electrical connection.

[0217] In this case, the void area on the surface of the copper substrate may preferably be 0.005 to 9.8 volume percent, and more preferably 0.005 to 9.5 volume percent.

[0218] Figure 6The scanning electron microscope image is used to show whether a semiconductor package substrate according to another embodiment of the present invention has voids (voids between plating layers).

[0219] Reference Figure 6 The thickness of the gold plating formed on the above-mentioned impact gold plating is 0.05μm. The direct chemical gold plating-0.05 semiconductor packaging substrate of the present invention can also make the void area on the surface of the copper substrate be 0.005~10 volume percent after aging heat treatment at a temperature of 175°C for 24 hours.

[0220] Furthermore, the direct chemical gold plating-0.15 semiconductor packaging substrate of the present invention, in which the thickness of the gold plating formed on the above-mentioned impact gold plating is 0.15 μm, can also make the void area on the surface of the copper substrate be 0.005 to 10 volume percent after aging heat treatment at a temperature of 175°C for 24 hours.

[0221] Moreover, the direct chemical gold plating-0.25 semiconductor packaging substrate of the present invention, in which the thickness of the gold plating formed on the above-mentioned impact gold plating is 0.25μm, can also make the void area on the surface of the copper substrate be 0.005 to 10 volume percent after aging heat treatment at a temperature of 175°C for 24 hours.

[0222] Furthermore, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; and a gold plating film formed on the strike gold plating film. When the semiconductor packaging substrate is measured by the lead pull strength evaluation condition of the following evaluation condition 2, the lead pull strength can be 6 to 14 gf.

[0223] [Evaluation Condition 2]

[0224] Wire Bonder: Wire Bonder-HB16

[0225] Tensile tester: Dage 4000

[0226] Gold wire: 1mil

[0227] Bonding conditions: First bonding point – 300Hz (US), 250ms (time), pressure 250mN; second bonding point – 400Hz (US), 350mls (time), pressure 250mN

[0228] Heat treatment conditions: 175°C, 6 hours

[0229] The wire pull strength is used in wire bonding technology to evaluate the bonding strength between a semiconductor package substrate and a wire.

[0230] Among them, when the above-mentioned semiconductor packaging substrate is measured by the lead pull strength evaluation condition of the above-mentioned evaluation condition 2, after aging heat treatment at a temperature of 175°C for 6 hours, if the above-mentioned lead pull strength is within the above-mentioned range, the bonding strength between the semiconductor packaging substrate and the lead is excellent, and thus a good packaging process can be carried out.

[0231] In this case, the wire pulling strength may preferably be 6 to 13.8 gf, more preferably 6 to 13.5 gf, even more preferably 7 to 13 gf, and even more preferably 7 to 12 gf.

[0232] Figure 7 This is a graph showing the lead pull strength of a semiconductor package substrate according to an embodiment of the present invention.

[0233] Reference Figure 7 In the above evaluation condition 2, the thickness of the gold plating formed on the above impact gold plating is 0.3 μm, and the bonding strength between the direct chemical gold plating-0.3 semiconductor packaging substrate of the present invention and the lead can be a lead pulling strength of 6 to 14 gf.

[0234] Furthermore, in the evaluation condition 2, the bonding strength between the direct chemical gold-plated-0.4 semiconductor package substrate of the present invention and the lead wire can be 6 to 14 gf of lead pull strength when the thickness of the gold plating film formed on the impact gold plating film is 0.4 μm.

[0235] Moreover, in the above evaluation condition 2, the bonding strength between the substrate and the lead of a conventional electroless nickel palladium immersion gold (ENEPIG; Ni 2-5 μm / Pd 0.03-0.15 μm / Au 0.03-0.15 μm) semiconductor package can be 6-14 gf of lead pull strength.

[0236] Furthermore, in the above evaluation condition 2, the bonding strength between the thin film chemical nickel palladium gold (ENEPIG, Electroless Nickel Electroless Palladium Immersion Gold; Ni 0.1-0.3μm / Pd 0.03-0.15μm / Au0.03-0.15μm) semiconductor package substrate and the lead can be a lead pull strength of 6-14gf.

[0237] Therefore, the direct chemical gold plating-0.3 semiconductor packaging substrate and the direct chemical gold plating-0.4 semiconductor packaging substrate of the present invention can make the bonding strength between the semiconductor packaging substrate and the lead similar to that of ordinary chemical nickel palladium gold (ENEPIG, Electroless Nickel Electroless Palladium Immersion Gold) and thin film chemical nickel palladium gold (ENEPIG, Electroless Nickel Electroless Palladium Immersion Gold).

[0238] Furthermore, the semiconductor package substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; and a gold plating film formed on the strike gold plating film, and the thickness of the gold plating film may be 2 to 1000 nm.

[0239] Furthermore, the semiconductor package substrate of the present invention may include: a copper base; a strike gold plating film formed on the copper base; and a gold plating film formed on the strike gold plating film.

[0240] Furthermore, the semiconductor package substrate of the present invention may include: a copper substrate; a gold strike plating film formed on the copper substrate; and a gold plating film formed on the gold strike plating film, and the gold strike plating film may have a thickness of 2 to 30 nm.

[0241] The semiconductor package substrate of the present invention may be a semiconductor package substrate without a nickel plating layer.

[0242] Therefore, since the semiconductor package substrate does not form a nickel plating layer as a post-film, signal loss is small in high-frequency communication, fine circuit diffusion is small, and it is easy to cope with fine pitches without generating cracks.

[0243] Furthermore, the copper substrate may be a copper metal substrate selected on a printed circuit board.

[0244] In this case, the copper metal substrate selected on the above-mentioned printed circuit board may include copper circuits.

[0245] Furthermore, the oxide film on the surface of the copper substrate can be appropriately removed by a reducing agent.

[0246] Furthermore, the copper substrate may have a thickness of 2 to 30 μm.

[0247] Among them, if the thickness of the above-mentioned copper base material is within the above-mentioned range, it can facilitate the transmission of electrical signals of the above-mentioned semiconductor package substrate.

[0248] In this case, the thickness of the copper substrate may preferably be 5 to 25 μm, and more preferably 5 to 20 μm.

[0249] Furthermore, the thickness of the copper substrate may be the thickness of the copper metal substrate selected on the printed circuit board.

[0250] Furthermore, the thickness of the copper substrate may be the copper thickness of the copper circuit.

[0251] Furthermore, the strike gold plating film formed on the copper substrate may be formed from a strike gold plating composition.

[0252] The above-mentioned strike gold plating composition may be a chemical strike gold plating composition.

[0253] In this case, the above-mentioned electroless strike gold plating composition may include a cyanide gold compound or a non-cyanide gold compound and a purine or pyrimidine compound having a carbonyl oxygen group.

[0254] Furthermore, the strike gold plating film formed on the copper substrate can act as a catalyst for the subsequent formation of a gold plating film.

[0255] Furthermore, the strike gold plating film formed on the copper substrate can suppress corrosion or voids (microscopic pores between plating layers) of the copper substrate.

[0256] Furthermore, the thickness of the strike gold plating film formed on the copper substrate may be 2 to 30 nm.

[0257] However, if the thickness of the strike gold plating film formed on the copper substrate exceeds the above range, corrosion or voids (microscopic pores between plating layers) of the copper substrate of the semiconductor package substrate may occur.

[0258] In this case, the thickness of the strike gold plating film formed on the copper substrate may preferably be 2 to 28 nm, and more preferably 2 to 25 nm.

[0259] Also, the gold plating film formed on the strike gold plating film may be formed from a gold plating composition.

[0260] The gold plating composition may be a chemical gold plating composition.

[0261] In this case, the electroless gold plating composition may include a cyanide gold compound or a non-cyanide gold compound, a carbonyl amide compound, and a nitrogen-containing heterocarboxylic acid.

[0262] Furthermore, the gold plating film formed on the above-mentioned strike gold plating film can play a role in electrically connecting the semiconductor chip to the copper substrate through a wire bonding process or a flip chip bonding process.

[0263] Furthermore, the gold plating film formed on the strike gold plating film can suppress erosion or dissolution of the copper substrate, thereby suppressing corrosion.

[0264] Furthermore, the thickness of the gold plating film formed on the strike gold plating film may be 2 to 1000 nm.

[0265] However, if the thickness of the gold plating film formed on the strike gold plating film exceeds the above range, erosion or dissolution of the copper base material of the semiconductor package substrate may occur, and corrosion may occur.

[0266] In this case, the thickness of the gold plating formed on the above-mentioned impact gold plating may preferably be 2 to 950 nm, more preferably 2 to 900 nm, even more preferably 2 to 800 nm, further preferably 2 to 700 nm, further preferably 2 to 600 nm, further preferably 2 to 500 nm, further preferably 2 to 400 nm, further preferably 2 to 300 nm, further preferably 2 to 200 nm, further preferably 2 to 150 nm, and most preferably 2 to 100 nm.

[0267] Moreover, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; and a gold plating film formed on the above-mentioned strike gold plating film. When the above-mentioned semiconductor packaging substrate is evaluated under the solder diffusion evaluation conditions of the following evaluation condition 3, the solder ball diffusion is the solder ball diffusion diameter / solder ball diameter (N), and the diffusion multiple N is 1.2 to 6.

[0268] [Evaluation Condition 3]

[0269] Evaluation by reflowing the solder balls

[0270] Solder ball diameter: 300μm

[0271] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0272] Reflow conditions: preheat at 130 to 200°C for 80 to 120 seconds, then perform bonding (soldering) at 240 to 260°C for 20 to 60 seconds.

[0273] Furthermore, the above-mentioned solder ball diffusion is used in flip chip bonding technology to evaluate the degree of bonding between a semiconductor package substrate and a solder bump.

[0274] Among them, when the above-mentioned semiconductor packaging substrate is evaluated by the solder diffusion evaluation condition of the above-mentioned evaluation condition 3, the above-mentioned solder ball diffusion is the solder ball diffusion diameter / solder ball diameter (N). If it is within the above-mentioned range, the degree of bonding between the semiconductor packaging substrate and the solder protrusion is excellent, and thus a good packaging process can be carried out.

[0275] In this case, the above-mentioned solder ball diffusion is solder ball diffusion diameter / solder ball diameter (N), the diffusion factor N may preferably be 1.2 to 5.8, the diffusion factor N may more preferably be 1.2 to 5.5, the diffusion factor N may more preferably be 1.2 to 5.3, and the diffusion factor N may further preferably be 1.2 to 5.

[0276] Figure 8 The figure shows the solder diffusivity of the semiconductor package substrate according to one embodiment of the present invention and the analysis results.

[0277] Reference Figure 8 In the evaluation condition 3, the thickness of the gold plating film formed on the impact gold plating film is 0.03 μm, and the bonding degree between the direct chemical gold plating-0.03 semiconductor package substrate and the solder bump can be made to diffuse multiples after 3 reflows. is 3.02.

[0278] Furthermore, in the evaluation condition 3, the thickness of the gold plating film formed on the above-mentioned impact gold plating film is 0.06 μm, and the bonding degree between the direct chemical gold plating-0.06 semiconductor package substrate of the present invention and the solder bump can make the diffusion multiple 1000 μm after 3 reflows. It is 3.11.

[0279] Furthermore, in the evaluation condition 3, the thickness of the gold plating film formed on the above-mentioned impact gold plating film is 0.1 μm, and the degree of bonding between the semiconductor package substrate and the solder bump can be made to diffuse multiples after 3 reflows. It is 3.29.

[0280] Furthermore, before and after reflow, the diffusion factor N of the semiconductor package substrate of the present invention can be set to All showed excellent results of more than 2 times the diameter of the diffusion solder ball.

[0281] On the other hand, in the above evaluation condition 3, the degree of bonding between the organic solderability protective layer (OSP, Organic Solderability Preservative; 0.1-0.5 μm) semiconductor package substrate and the solder bump can make the diffusion multiples after 3 reflows. It is 2.09.

[0282] Furthermore, in the evaluation condition 3, the bonding degree between the conventional chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni 2.5μm / Au 0.05μm) semiconductor package substrate and the solder bump can be made to diffuse multiples after three reflows. It is 3.68.

[0283] Therefore, when the semiconductor package substrate of the present invention is evaluated under the solder diffusion evaluation condition of the evaluation condition 3, the diffusion factor after three reflows is Greater than the diffusion multiple of the organic solderability protective layer (OSP, Organic Solderability Preservative; 0.1 ~ 0.5μm) semiconductor packaging substrate after 3 reflows The bonding degree with the solder bump can be improved.

[0284] Furthermore, when the semiconductor package substrate of the present invention is evaluated under the solder diffusion evaluation condition of the evaluation condition 3, the diffusion factor after three reflows is Diffusion multiples after 3 reflows of semiconductor packaging substrates made of ENIG (Electroless Nikel Immersion Gold; Ni 2.5μm / Au 0.05μm) and ordinary chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni 2.5μm / Au 0.05μm) quite.

[0285] Moreover, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; and a gold plating film formed on the above-mentioned strike gold plating film. When the above-mentioned semiconductor packaging substrate is evaluated by the anisotropic conductive film (ACF) bonding condition of the following evaluation condition 4 and the tensile force measurement condition of the following evaluation condition 5, the bonding tensile force can be 1000~1600g / cm.

[0286] [Evaluation Condition 4]

[0287] Temperature: 170℃

[0288] Pressure: 12.30kgf

[0289] Time: 7 seconds

[0290] [Evaluation Condition 5]

[0291] Angle: 90°

[0292] Speed: 833μm / sec

[0293] Tape: Low temperature tape AC-3614KS-25 (1.0×100mm).

[0294] Furthermore, the anisotropic conductive film bonding may be a bonding method using anisotropic conductive film (ACF) to form a bonding layer in a manner that allows vertical conduction and horizontal insulation.

[0295] Among them, when the above-mentioned semiconductor packaging substrate is evaluated by the anisotropic conductive film (ACF) bonding condition of the above-mentioned evaluation condition 4 and the tensile force measurement condition of the above-mentioned evaluation condition 5, if the above-mentioned bonding tensile force is within the above-mentioned range, the degree of bonding between the semiconductor packaging substrate, the solder bump and the anisotropic conductive film (ACF) is excellent, and thus a good packaging process can be carried out.

[0296] In this case, the bonding tensile force may preferably be 1000 to 1580 g / cm, more preferably 1000 to 1550 g / cm, even more preferably 1000 to 1530 g / cm, and even more preferably 1000 to 1500 g / cm.

[0297] Fig. 9 FIG. 1 is a tensile force diagram and analysis results of a semiconductor package substrate according to an embodiment of the present invention.

[0298] Reference Fig. 9 In the above-mentioned evaluation conditions 4 and 5, the direct chemical gold plating-0.05 semiconductor packaging substrate of the present invention, in which the thickness of the gold plating film formed on the above-mentioned impact gold plating film is 0.05 μm, enables the degree of bonding between the semiconductor packaging substrate, the solder bump and the anisotropic conductive film (ACF) to be an average bonding tensile force of 1299.8 g / cm.

[0299] Furthermore, in the above-mentioned evaluation conditions 4 and the above-mentioned evaluation conditions 5, the direct chemical gold plating-0.15 semiconductor packaging substrate of the present invention, in which the thickness of the gold plating film formed on the above-mentioned impact gold plating film is 0.15 μm, enables the degree of bonding between the semiconductor packaging substrate, the solder bump and the anisotropic conductive film (ACF) to be an average bonding tensile force of 1255.9 g / cm.

[0300] Moreover, in the above-mentioned evaluation conditions 4 and the above-mentioned evaluation conditions 5, the direct chemical gold plating-0.25 semiconductor packaging substrate of the present invention, in which the thickness of the gold plating film formed on the above-mentioned impact gold plating film is 0.25μm, enables the degree of bonding between the semiconductor packaging substrate, the solder bump and the anisotropic conductive film (ACF) to be an average bonding tensile force of 1083.6g / cm.

[0301] Therefore, the bonding tensile force of the semiconductor package substrate of the present invention can show an excellent result exceeding the standard of 750 g / cm.

[0302] On the other hand, in the above-mentioned evaluation conditions 4 and 5, the ordinary chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni 2.5μm / Au 0.05μm) semiconductor packaging substrate allows the degree of bonding between the semiconductor packaging substrate, solder bumps and anisotropic conductive film (ACF) to be 800 to 1000 g / cm of bonding tension.

[0303] Therefore, when the bonding tension of the semiconductor packaging substrate of the present invention is evaluated by the above-mentioned evaluation conditions 4 and the above-mentioned evaluation conditions 5, it is greater than that of the ordinary chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni2.5μm / Au 0.05μm) semiconductor packaging substrate, and the degree of bonding between the semiconductor packaging substrate, the solder bump and the anisotropic conductive film (ACF) can be better.

[0304] Furthermore, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; and a gold plating film formed on the strike gold plating film. When the semiconductor packaging substrate is evaluated by the crack (MIT) evaluation condition of the following evaluation condition 6, the bendability can reach 50 to 220 times after reflow soldering 2 to 5 times.

[0305] [Evaluation Condition 6]

[0306] Bendability testing equipment: MIT-DA / TOYOSEIKI

[0307] Loading: 500g

[0308] Bending speed: 175 times / minute

[0309] Bending angle: 135°

[0310] Reflow conditions: preheating at 130-200°C for 80-120 seconds, followed by irreversible heating (heat aging) at 240-260°C for 20-60 seconds.

[0311] Furthermore, the above-mentioned bendability may be a method of evaluating the presence or absence of cracks by repeatedly bending the semiconductor package substrate.

[0312] When the bendability of the semiconductor package substrate is evaluated by the crack (MIT) evaluation condition of the evaluation condition 6, if the bendability is within the above range after the reflow process 2 to 5 times, the occurrence of cracks in the semiconductor package substrate can be suppressed.

[0313] In this case, the bendability after the reflow process 2 to 5 times may be preferably 50 to 220 times, more preferably 60 to 220 times, even more preferably 70 to 220 times, and even more preferably 80 to 220 times.

[0314] Fig.10 The diagram and scanning electron microscope image show the bendability of the semiconductor package substrate according to one embodiment of the present invention, showing whether there are cracks.

[0315] Reference Fig.10 , under the above evaluation condition 6, the copper substrate can exhibit 154 times of bendability.

[0316] Moreover, in the above-mentioned evaluation condition 6, the direct chemical gold-plated-0.1 semiconductor packaging substrate of the present invention, in which the thickness of the gold plating film formed on the above-mentioned impact gold plating film is 0.1 μm, can exhibit 199 times of bendability before reflow soldering and 210 times of bendability after reflow soldering.

[0317] Furthermore, in the scanning electron microscope image of the 180° folding evaluation, the direct chemical gold plating-0.1 semiconductor packaging substrate of the present invention, in which the thickness of the gold plating film formed on the above-mentioned impact gold plating film is 0.1 μm, does not produce cracks after reflow soldering 5 times and reflow soldering 10 times.

[0318] Therefore, the semiconductor package substrate of the present invention can exhibit extremely soft and crack-free properties.

[0319] On the other hand, in the above-mentioned evaluation condition 6, the ordinary chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni 3μm / Au 0.05μm) semiconductor package substrate can show 145 times of bendability before reflow soldering and 78 times of bendability after reflow soldering, and the bendability decreases sharply.

[0320] Furthermore, in the scanning electron microscope images of the 180° folding evaluation, a common electroless nickel-gold (ENIG, Electroless Nikel Immersion Gold; Ni 3μm / Au 0.05μm) semiconductor package substrate may generate a lot of cracks after reflowing 5 times and reflowing 10 times.

[0321] Therefore, when the bendability of the semiconductor packaging substrate of the present invention is evaluated by the crack (MIT) evaluation condition of the above-mentioned evaluation condition 6, the bendability is greater than that of the ordinary chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni 3μm / Au 0.05μm) semiconductor packaging substrate, and thus the physical properties of the semiconductor packaging substrate of the present invention can be better.

[0322] Semiconductor packaging substrate—II

[0323] The present invention provides a semiconductor package substrate formed with a direct chemical gold plating film without a fine pitch corresponding nickel plating layer.

[0324] The semiconductor packaging substrate of the present invention may include: a copper substrate; and a gold plating film formed on the above copper substrate. In the above semiconductor packaging substrate, the spacing is the sum of the circuit width and the spacing width. When used for fine circuits with a spacing level of 10μm to 50μm, the diffusion of the gold plating film of the above semiconductor packaging substrate can be 0.001 volume percent to 5 volume percent.

[0325] According to the present invention, a semiconductor package substrate having a direct chemical gold plating film without a nickel plating layer corresponding to a fine pitch is provided, so that fine circuits are less diffused, it is easy to cope with fine pitches, and cracks are not generated.

[0326] In this case, the semiconductor package substrate of the present invention may be a semiconductor package substrate on which no nickel plating layer is formed.

[0327] Therefore, since the semiconductor package substrate does not form a nickel plating layer as a post-film, signal loss is small in high-frequency communication, fine circuit diffusion is small, and it is easy to cope with fine pitches without generating cracks.

[0328] Furthermore, the copper substrate may be a copper metal substrate selected on a printed circuit board.

[0329] In this case, the copper metal substrate selected on the above-mentioned printed circuit board may include copper circuits.

[0330] Furthermore, the oxide film on the surface of the copper substrate can be appropriately removed by a reducing agent.

[0331] Furthermore, the copper substrate may have a thickness of 2 to 30 μm.

[0332] Among them, if the thickness of the above-mentioned copper base material is within the above-mentioned range, it can facilitate the transmission of electrical signals of the above-mentioned semiconductor package substrate.

[0333] In this case, the thickness of the copper substrate may preferably be 5 to 25 μm, and more preferably 5 to 20 μm.

[0334] Furthermore, the thickness of the copper substrate may be the thickness of the copper metal substrate selected on the printed circuit board.

[0335] Furthermore, the thickness of the copper substrate may be the copper thickness of the copper circuit.

[0336] Furthermore, the gold plating film formed on the copper substrate may be formed from a gold plating composition.

[0337] The gold plating composition may be a chemical gold plating composition.

[0338] In this case, the electroless gold plating composition may include a cyanide gold compound or a non-cyanide gold compound, a carbonyl amide compound, and a nitrogen-containing heterocarboxylic acid.

[0339] Furthermore, the gold plating film formed on the copper substrate can play a role in electrically connecting the semiconductor chip to the copper substrate by a wire bonding process or a flip chip bonding process.

[0340] Furthermore, the thickness of the gold plating film formed on the copper substrate may be 2 to 1000 nm.

[0341] However, if the thickness of the gold plating film formed on the copper base material exceeds the above range, erosion or dissolution of the copper base material of the semiconductor package substrate may occur, and corrosion may occur.

[0342] In this case, the thickness of the gold-plated film formed on the copper substrate may preferably be 2 to 950 nm, more preferably 2 to 900 nm, even more preferably 2 to 800 nm, further preferably 2 to 700 nm, further preferably 2 to 600 nm, further preferably 2 to 500 nm, further preferably 2 to 400 nm, further preferably 2 to 300 nm, further preferably 2 to 200 nm, further preferably 2 to 150 nm, and most preferably 2 to 100 nm.

[0343] Fig.11 FIG. 4 is a cross-sectional view of a semiconductor package substrate according to an embodiment of the present invention.

[0344] Reference Fig.11 , the semiconductor package substrate 200 includes a gold plating film 240 formed on a copper base material 220 .

[0345] Furthermore, in the semiconductor packaging substrate, the pitch may be a sum of the circuit width and the spacing width, and when used for fine circuits of a pitch level of 4 to 50 μm, the diffusion of the gold plating film of the semiconductor packaging substrate may be 0.001 to 10 volume percent.

[0346] The above-mentioned diffusibility of the gold plating film can be obtained by measuring the diffusion volume in a scanning electron microscope measurement.

[0347] When the diffusibility of the gold plating film is within the above range, the semiconductor package substrate can be used for fine pitches.

[0348] In this case, the diffusivity of the gold plating film may preferably be 0.001 to 9.8 volume percent, and more preferably 0.001 to 9.5 volume percent.

[0349] Furthermore, the semiconductor packaging substrate of the present invention may include: a copper substrate; and a gold plating film formed on the copper substrate. When the semiconductor packaging substrate is measured by the high-speed ball shear strength evaluation condition 1 below, the average high-speed ball shear strength can be 1000 to 1600 gf.

[0350] [Evaluation Condition 1]

[0351] High-speed shearing equipment: Dage 4000HS

[0352] Shear speed: 1m / s

[0353] Shear height: 50μm

[0354] Ball grid array pad diameter: 350μm

[0355] Solder ball diameter: 450μm

[0356] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0357] Measurement points: n=25.

[0358] The high-speed ball shear strength is used in flip chip bonding technology to evaluate the bonding strength between a semiconductor package substrate and a solder bump.

[0359] Among them, when the above-mentioned semiconductor packaging substrate is measured by the high-speed ball shear strength evaluation condition of the above-mentioned evaluation condition 1, if the above-mentioned average high-speed ball shear strength is within the above-mentioned range, the bonding strength between the semiconductor packaging substrate and the solder bump is excellent, and thus a good packaging process can be carried out.

[0360] In this case, the average high-speed ball shear strength may be preferably 1000 to 1550 gf, more preferably 1000 to 1500 gf, even more preferably 1000 to 1400 gf, and even more preferably 1000 to 1350 gf.

[0361] Furthermore, the semiconductor package of the present invention may include: a copper substrate; and a gold plating film formed on the copper substrate. The void area of ​​the semiconductor package substrate may be 0.005 to 10 volume percent.

[0362] Furthermore, the void area on the copper substrate surface (microscopic pores between plating layers) is used to evaluate the copper substrate corrosion or solder brittle failure rate and is measured using a scanning electron microscope image.

[0363] If the void area on the surface of the copper substrate is within the above range, the semiconductor chip and the semiconductor package substrate can form an excellent electrical connection.

[0364] In this case, the void area on the surface of the copper substrate may preferably be 0.005 to 9.8 volume percent, and more preferably 0.005 to 9.5 volume percent.

[0365] Furthermore, the semiconductor package substrate of the present invention comprises: a copper substrate; and a gold plating film formed on the copper substrate. When the semiconductor package substrate is measured by the lead pull strength evaluation condition of the following evaluation condition 2, the lead pull strength can be 6 to 14 gf.

[0366] [Evaluation Condition 2]

[0367] Wire Bonder: Wire Bonder-HB16

[0368] Tensile tester: Dage 4000

[0369] Gold wire: 1mil

[0370] Bonding conditions: First bonding point – 300Hz (US), 250ms (time), pressure 250mN; second bonding point – 400Hz (US), 350mls (time), pressure 250mN

[0371] Heat treatment conditions: 175°C, 6 hours

[0372] The wire pull strength is used in wire bonding technology to evaluate the bonding strength between a semiconductor package substrate and a wire.

[0373] Among them, when the above-mentioned semiconductor packaging substrate is measured by the lead pull strength evaluation condition of the above-mentioned evaluation condition 2, after aging heat treatment at a temperature of 175°C for 6 hours, if the above-mentioned lead pull strength is within the above-mentioned range, the bonding strength between the semiconductor packaging substrate and the lead is excellent, and thus a good packaging process can be carried out.

[0374] In this case, the wire pulling strength may preferably be 6 to 13.8 gf, more preferably 6 to 13.5 gf, even more preferably 7 to 13 gf, and even more preferably 7 to 12 gf.

[0375] Furthermore, the semiconductor package substrate of the present invention may include: a copper substrate; and a gold plating film formed on the copper substrate, and the thickness of the gold plating film may be 2 to 1000 nm.

[0376] The semiconductor package substrate of the present invention may be a semiconductor package substrate without a nickel plating layer.

[0377] Therefore, since the semiconductor package substrate does not form a nickel plating layer as a post-film, signal loss is small in high-frequency communication, fine circuit diffusion is small, and it is easy to cope with fine pitches without generating cracks.

[0378] Furthermore, the copper substrate may be a copper metal substrate selected on a printed circuit board.

[0379] In this case, the copper metal substrate selected on the above-mentioned printed circuit board may include copper circuits.

[0380] Furthermore, the oxide film on the surface of the copper substrate can be appropriately removed by a reducing agent.

[0381] Furthermore, the copper substrate may have a thickness of 2 to 30 μm.

[0382] Among them, if the thickness of the above-mentioned copper base material is within the above-mentioned range, it can facilitate the transmission of electrical signals of the above-mentioned semiconductor package substrate.

[0383] In this case, the thickness of the copper substrate may preferably be 5 to 25 μm, and more preferably 5 to 20 μm.

[0384] Furthermore, the thickness of the copper substrate may be the thickness of the copper metal substrate selected on the printed circuit board.

[0385] Furthermore, the thickness of the copper substrate may be the copper thickness of the copper circuit.

[0386] Furthermore, the gold plating film formed on the copper substrate may be formed from a gold plating composition.

[0387] The gold plating composition may be a chemical gold plating composition.

[0388] In this case, the electroless gold plating composition may include a cyanide gold compound or a non-cyanide gold compound, a carbonyl amide compound, and a nitrogen-containing heterocarboxylic acid.

[0389] Furthermore, the gold plating film formed on the above-mentioned strike gold plating film can play a role in electrically connecting the semiconductor chip to the copper substrate through a wire bonding process or a flip chip bonding process.

[0390] Furthermore, the gold plating film formed on the strike gold plating film can suppress erosion or dissolution of the copper substrate, thereby suppressing corrosion.

[0391] Furthermore, the thickness of the gold plating film formed on the copper substrate may be 2 to 1000 nm.

[0392] However, if the thickness of the gold plating film formed on the copper base material exceeds the above range, erosion or dissolution of the copper base material of the semiconductor package substrate may occur, and corrosion may occur.

[0393] In this case, the thickness of the gold-plated film formed on the copper substrate may preferably be 2 to 950 nm, more preferably 2 to 900 nm, even more preferably 2 to 800 nm, further preferably 2 to 700 nm, further preferably 2 to 600 nm, further preferably 2 to 500 nm, further preferably 2 to 400 nm, further preferably 2 to 300 nm, further preferably 2 to 200 nm, further preferably 2 to 150 nm, and most preferably 2 to 100 nm.

[0394] Moreover, the semiconductor packaging substrate of the present invention may include: a copper substrate; and a gold plating film formed on the above-mentioned copper substrate. When the above-mentioned semiconductor packaging substrate is evaluated under the solder diffusion evaluation condition of the following evaluation condition 3, the solder ball diffusion is the solder ball diffusion diameter / solder ball diameter (N), and the diffusion multiple N can be 1.2 to 6.

[0395] [Evaluation Condition 3]

[0396] Evaluation by reflowing the solder balls

[0397] Solder ball diameter: 300μm

[0398] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0399] Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform bonding (soldering) at 240-260°C for 20-60 seconds

[0400] Furthermore, the above-mentioned solder ball diffusion is used in flip chip bonding technology to evaluate the degree of bonding between a semiconductor package substrate and a solder bump.

[0401] Among them, when the above-mentioned semiconductor packaging substrate is evaluated by the solder diffusion evaluation condition of the above-mentioned evaluation condition 3, the above-mentioned solder ball diffusion is the solder ball diffusion diameter / solder ball diameter (N). If it is within the above-mentioned range, the degree of bonding between the semiconductor packaging substrate and the solder protrusion is excellent, and thus a good packaging process can be carried out.

[0402] In this case, the above-mentioned solder ball diffusion is solder ball diffusion diameter / solder ball diameter (N), the diffusion factor N may preferably be 1.2 to 5.8, the diffusion factor N may more preferably be 1.2 to 5.5, the diffusion factor N may more preferably be 1.2 to 5.3, and the diffusion factor N may further preferably be 1.2 to 5.

[0403] Moreover, the semiconductor packaging substrate of the present invention may include: a copper substrate; and a gold-plated film formed on the above-mentioned copper substrate. When the above-mentioned semiconductor packaging substrate is evaluated by the anisotropic conductive film (ACF) bonding condition of the following evaluation condition 4 and the tensile force measurement condition of the following evaluation condition 5, the bonding tensile force can be 1000~1600g / cm.

[0404] [Evaluation Condition 4]

[0405] Temperature: 170℃

[0406] Pressure: 12.30kgf

[0407] Time: 7 seconds,

[0408] [Evaluation Condition 5]

[0409] Angle: 90°

[0410] Speed: 833μm / sec

[0411] Tape: Low temperature tape AC-3614KS-25 (1.0×100mm).

[0412] Furthermore, the anisotropic conductive film bonding may be a bonding method using anisotropic conductive film (ACF) to form a bonding layer in a manner that allows vertical conduction and horizontal insulation.

[0413] Among them, when the above-mentioned semiconductor packaging substrate is evaluated by the anisotropic conductive film (ACF) bonding condition of the above-mentioned evaluation condition 4 and the tensile force measurement condition of the above-mentioned evaluation condition 5, if the above-mentioned bonding tensile force is within the above-mentioned range, the degree of bonding between the semiconductor packaging substrate, the solder bump and the anisotropic conductive film (ACF) is excellent, and thus a good packaging process can be carried out.

[0414] In this case, the bonding tensile force may preferably be 1000 to 1580 g / cm, more preferably 1000 to 1550 g / cm, even more preferably 1000 to 1530 g / cm, and even more preferably 1000 to 1500 g / cm.

[0415] Furthermore, the semiconductor packaging substrate of the present invention may include: a copper substrate; and a gold plating film formed on the copper substrate. When the bendability of the semiconductor packaging substrate is evaluated by the crack (MIT) evaluation condition of the following evaluation condition 6, the bendability reaches 50 to 220 times after reflow soldering 2 to 5 times.

[0416] [Evaluation Condition 6]

[0417] Bendability testing equipment: MIT-DA / TOYOSEIKI

[0418] Loading: 500g

[0419] Bending speed: 175 times / minute

[0420] Bending angle: 135°

[0421] Reflow conditions: preheating at 130-200°C for 80-120 seconds, followed by irreversible heating (heat aging) at 240-260°C for 20-60 seconds.

[0422] Furthermore, the above-mentioned bendability may be a method of evaluating the presence or absence of cracks by repeatedly bending the semiconductor package substrate.

[0423] When the bendability of the semiconductor package substrate is evaluated by the crack (MIT) evaluation condition of the evaluation condition 6, if the bendability is within the above range after the reflow process 2 to 5 times, the occurrence of cracks in the semiconductor package substrate can be suppressed.

[0424] In this case, the bendability after the reflow process 2 to 5 times may be preferably 50 to 220 times, more preferably 60 to 220 times, even more preferably 70 to 220 times, and even more preferably 80 to 220 times.

[0425] Semiconductor package including semiconductor package substrate

[0426] The present invention provides a semiconductor package having a substrate for semiconductor packaging formed with a direct chemical gold plating film without a fine pitch corresponding nickel plating layer.

[0427] The present invention provides a semiconductor package including the semiconductor package substrate.

[0428] Since the present invention provides a semiconductor package including a semiconductor package substrate formed with a direct chemical gold plating film without a fine pitch corresponding nickel plating layer, the semiconductor package has excellent physical properties and is economical.

[0429] Hereinafter, the present invention will be described in detail by way of examples. However, the following examples are used to more specifically describe the present invention, and the scope of the present invention is not limited to the following examples. The following examples can be appropriately modified and changed by those skilled in the art within the scope of the present invention.

[0430] Example

[0431] Example 1: Manufacturing a semiconductor packaging substrate having a direct chemical gold plating film

[0432] After degreasing a copper substrate having a thickness of 10 μm (circuit spacing of 25 μm) at a temperature of 45°C for 5 minutes using ACIDCLEAN 620 of MK Chem&Tech as a degreasing liquid, the degreased copper substrate was etched at a temperature of 27°C for 2 minutes using MKS-3000 of MK Chem&Tech as an etching liquid.

[0433] Then, the etched copper substrate was plated with 6 nm thick chemical strike gold at 80° C. for 3 minutes using a strike gold plating composition containing a cyanide gold compound and a purine compound having carbonyl oxygen (NEOZEN SG from MK Chem&Tech).

[0434] Next, the strike gold plating film was electrolessly plated with gold using a gold plating composition for semiconductor package substrates containing a cyanide gold compound, a carbonylamide compound, and a nitrogen-containing heterocarboxylic acid (NEOZEN TG from MK Chem & Tech) to produce a semiconductor package substrate having a 0.10 μm thick gold plating film.

[0435] Example 2-Example 10 Manufacturing a semiconductor packaging substrate having a direct chemical gold plating film

[0436] As shown in Table 1, a semiconductor package substrate having a direct chemical gold plating film formed thereon was manufactured in the same manner as in Example 1 except for the thickness of the gold plating film.

[0437] Table 1

[0438]

[0439] Example 11: Manufacturing a semiconductor packaging substrate having a direct chemical gold plating film

[0440] After degreasing a copper substrate having a thickness of 10 μm (circuit spacing of 25 μm) at a temperature of 45°C for 5 minutes using ACIDCLEAN 620 of MK Chem&Tech as a degreasing liquid, the degreased copper substrate was etched at a temperature of 27°C for 2 minutes using MKS-1200 of MK Chem&Tech as an etching liquid.

[0441] Thereafter, the etched copper substrate was electrolessly plated with gold using a gold plating composition for semiconductor package substrates containing a cyanide gold compound, a carboxylic acid, and a heterocyclic nitrogen compound and containing no cyanide in other compositions (NEOZEN CFG from MK Chem&Tech), thereby producing a semiconductor package substrate having a gold plating film with a thickness of 0.10 μm.

[0442] Example 12-Example 20 Manufacturing a semiconductor packaging substrate having a direct chemical gold plating film

[0443] As shown in Table 2, a semiconductor package substrate having a direct chemical gold plating film formed thereon was manufactured in the same manner as in Example 11 except for the thickness of the gold plating film.

[0444] Table 2

[0445]

[0446] Comparative Example

[0447] Comparative Example 1: Manufacturing of a Conventional Electroless Nickel-Gold (ENIG) Semiconductor Packaging Substrate

[0448] A copper substrate having a thickness of 10 μm was degreased at 45° C. for 5 minutes using ACIDCLEAN 620 of MK CHEM&TECH as a degreasing liquid, and then the degreased copper substrate was etched at 27° C. for 2 minutes using MKS-3000 of MK CHEM&TECH as an etching liquid.

[0449] In order to remove the surface residue of the copper substrate after etching, an acid treatment was performed using a 10 wt % sulfuric acid aqueous solution at a temperature of 25° C. for 1 minute.

[0450] Thereafter, palladium catalysis was performed at 27° C. for 2 minutes using CATA-NC20 catalyst produced by MK CHEM&TECH, and post-treatment was performed at 27° C. for 2 minutes using POST-DIP PR produced by MK CHEM&TECH.

[0451] Next, NEOZEN MP-K, a rigid chemical nickel plating chemical of MK CHEM&TECH, was used to perform a treatment at 83°C for 20 minutes to increase the Ni thickness to 2 to 4 μm, and IG-10, a flash gold alternative gold plating chemical of MK CHEM&TECH, was used to perform a treatment at 80°C for 7 minutes to manufacture a conventional chemical nickel-gold semiconductor packaging substrate with an Au (gold) thickness of 0.03 to 0.05 μm.

[0452] Comparative Example 2: Manufacturing Highly Flexible Chemical Nickel-Au Semiconductor Packaging Substrate

[0453] A copper substrate having a thickness of 10 μm was degreased at 45° C. for 5 minutes using ACIDCLEAN 620 of MK CHEM&TECH as a degreasing liquid, and then the degreased copper substrate was etched at 27° C. for 2 minutes using MKS-3000 of MK CHEM&TECH as an etching liquid.

[0454] In order to remove the surface residue of the etched copper substrate, an acid treatment was performed using a 10 wt % sulfuric acid aqueous solution at a temperature of 25° C. for 1 minute.

[0455] Thereafter, palladium catalysis was performed at 27° C. for 2 minutes using CATA-NC20 catalyst produced by MK CHEM&TECH, and post-treatment was performed at 27° C. for 2 minutes using POST-DIP PR produced by MK CHEM&TECH.

[0456] Next, NEOZEN SPF-K, a highly flexible chemical nickel plating chemical of MK CHEM&TECH, was used to perform a treatment at 83°C for 20 minutes to increase the Ni (nickel) thickness to 2 to 4 μm, and FLASH GOLD IG-10, an alternative gold plating chemical of MK CHEM&TECH, was used to perform a treatment at 80°C for 7 minutes to manufacture a highly flexible chemical nickel-gold semiconductor packaging substrate with an Au thickness of 0.03 to 0.05 μm.

[0457] Comparative Example 3: Manufacturing of Thin Film Chemical Nickel Palladium Gold (ENEPIG) Semiconductor Packaging Substrate

[0458] A copper substrate having a thickness of 10 μm was degreased at 45° C. for 5 minutes using ACIDCLEAN 620 of MK CHEM&TECH as a degreasing liquid, and then the degreased copper substrate was etched at 27° C. for 2 minutes using MKS-3000 of MK CHEM&TECH as an etching liquid.

[0459] In order to remove the surface residue of the etched copper substrate, an acid treatment was performed using a 10 wt % sulfuric acid aqueous solution at a temperature of 25° C. for 1 minute.

[0460] Thereafter, palladium catalysis was performed at 27° C. for 2 minutes using CATA-NC20 catalyst produced by MK CHEM&TECH, and post-treatment was performed at 27° C. for 2 minutes using POST-DIP PR produced by MK CHEM&TECH.

[0461] Next, NEOZEN MP-K, an electroless nickel plating chemical of MK CHEM&TECH, was used to perform a treatment at 83°C for 1 minute to increase the Ni thickness to 0.15 to 0.3 μm, and FLASH GOLD IG-10, an alternative gold plating chemical of MK CHEM&TECH, was used to perform a treatment at 80°C for 7 minutes to manufacture a thin film electroless nickel palladium gold (ENEPIG) semiconductor packaging substrate with an Au thickness of 0.03 to 0.05 μm.

[0462] Comparative Example 4: Manufacturing of an Organic Solderability Preservative (OSP) Semiconductor Packaging Substrate

[0463] A copper substrate having a thickness of 10 μm was degreased at 45° C. for 20 seconds using ACIDCLEAN LF-T from MK CHEM&TECH as a degreasing liquid, and then the degreased copper substrate was etched at 27° C. for 30 seconds using MKS-1200 from MK CHEM&TECH as an etching liquid.

[0464] In order to remove the surface residue of the etched copper substrate, an acid treatment was performed using a 5 wt % sulfuric acid aqueous solution at a temperature of 25° C. for 30 seconds.

[0465] Then, the substrate was treated at 40° C. for 2 minutes using Glicoat SMD F2 (LX) manufactured by Shikoku Chemical Co., Ltd., Japan, to manufacture an organic solderability resist (OSP) semiconductor package substrate having a thickness of 0.1 to 0.4 μm.

[0466] Experimental example

[0467] Experimental Example 1: Cross-sectional analysis of a semiconductor package substrate having a direct chemical gold plating film

[0468] like Figure 2 As shown, the cross section of the semiconductor package substrate on which the direct chemical gold plating film of Example 7 was formed was measured by a scanning electron microscope.

[0469] The thickness of the gold plating film was measured to be 0.25 to 0.30 μm.

[0470] Furthermore, it is shown that no nickel plating is used.

[0471] Experimental Example 2 Measurement of the Thickness of the Impact Plating Film on a Semiconductor Package Substrate with Direct Chemical Gold Plating Film

[0472] like Figure 3 As shown, in the semiconductor package substrates having the direct chemical gold plating films formed thereon in Examples 1 to 10, the thickness of the impact gold plating films was measured by X-ray photoelectron spectroscopy (XPS).

[0473] The thickness of the strike gold plating film was measured to be 0.003 to 0.014 μm.

[0474] Experimental Example 3: Diffusion Measurement

[0475] In order to determine the diffusion properties of the gold coating, Figure 4 As shown, the surfaces of the semiconductor package substrates on which the direct chemical gold plating films of Examples 3, 5 and 7 were formed were measured by a scanning electron microscope.

[0476] Among them, the above-mentioned embodiment 3 has no diffusivity at all, the above-mentioned embodiment 5 has a diffusivity of less than 1 volume percent, and the above-mentioned embodiment 7 has a diffusivity of less than 3 volume percent.

[0477] And, if Figure 4 As shown, the surface of the conventional chemical nickel-gold semiconductor package substrate of the above-mentioned comparative example 1 was measured by a scanning electron microscope.

[0478] Among them, the comparative example 1 exhibits a diffusivity of 57 volume percent.

[0479] Therefore, unlike the common chemical nickel-gold semiconductor packaging substrate of Comparative Example 1, the semiconductor packaging substrate formed with a direct chemical gold plating film of the above-mentioned Examples 3, 5 and 7 of the present invention shows almost no diffusion.

[0480] Experimental Example 4 High-speed ball shear strength measurement

[0481] In order to determine the high-speed ball shear strength of semiconductor packaging substrates, such as Figure 5 As shown, the semiconductor package substrates having the direct chemical gold plating films formed thereon in Examples 1 to 3 were measured under the high-speed ball shear strength evaluation condition of the following evaluation condition 1.

[0482] [Evaluation Condition 1]

[0483] High-speed shearing equipment: Dage 4000HS

[0484] Shear speed: 1m / s

[0485] Shear height: 50μm

[0486] Ball grid array (BGA) pad diameter: 350μm

[0487] Solder Ball Diameter: 450μm

[0488] Solder Ball Type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0489] Measurement points: n=25.

[0490] The average high-speed ball shear strength of the semiconductor package substrates formed with the direct chemical gold plating films of Examples 1 to 3 is 1277.9 to 1312.2 gf.

[0491] On the other hand, when measured under the same high-speed ball shear strength evaluation conditions of the above-mentioned evaluation condition 1, the average high-speed ball shear strength of the conventional chemical nickel-gold semiconductor package substrate of the above-mentioned comparative example 1 was reduced to 1080.5 gf.

[0492] Furthermore, when measured under the same high-speed ball shear strength evaluation condition of the above-mentioned evaluation condition 1, the average high-speed ball shear strength of the high-flexibility chemical nickel-gold semiconductor package substrate of the above-mentioned comparative example 2 was reduced to 1109.1 gf.

[0493] Furthermore, when measured under the same high-speed ball shear strength evaluation condition of the above-mentioned evaluation condition 1, the average high-speed ball shear strength of the thin film chemical nickel palladium gold (ENEPIG) semiconductor package substrate of the above-mentioned comparative example 3 slightly increased to 1355.8 gf.

[0494] Furthermore, when measured under the same high-speed ball shear strength evaluation condition of the above-mentioned evaluation condition 1, the average high-speed ball shear strength of the organic solderability resist (OSP) semiconductor package substrate of the above-mentioned comparative example 4 was reduced to 1275.3 gf.

[0495] Experimental Example 5 Hole Measurement

[0496] To determine the porosity of copper substrates, Figure 6 As shown, the cross sections of the semiconductor package substrates on which the direct chemical gold plating films of Examples 3, 5, and 6 were formed were measured by scanning electron microscopy.

[0497] Among them, even after heat treatment, no voids were generated in the above-mentioned Embodiment 3, Embodiment 5 and Embodiment 6.

[0498] Furthermore, the semiconductor package substrates on which the direct chemical gold plating film is formed in the above-mentioned Examples 3, 5 and 6 of the present invention also do not cause corrosion of the copper base material.

[0499] Experimental Example 6 Lead Pull Strength Measurement

[0500] In order to determine the lead pull strength of semiconductor packaging substrates, such as Figure 7 As shown, the semiconductor package substrates having the direct chemical gold plating films formed thereon in Examples 7 and 9 described above were measured under the following evaluation condition 2 for lead pull strength evaluation.

[0501] [Evaluation Condition 2]

[0502] Wire Bonder: Wire Bonder-HB16

[0503] Tensile tester: Dage 4000

[0504] Gold wire: 1mil

[0505] Bonding conditions: first bonding point – 300 Hz (US), 250 ms (time), pressure 250 mN;

[0506] Second bond point – 400Hz (US), 350mls (time), pressure 250mN

[0507] Heat treatment conditions: 175°C, 6 hours.

[0508] The lead pull strength of the semiconductor package substrates formed with direct chemical gold plating films in Examples 7 and 9 was 8 to 13 gf after 5 reflows and 6 to 12 gf after aging at 150° C. for 12 hours.

[0509] On the other hand, when measured by the same lead pull strength evaluation condition of the above-mentioned evaluation condition 2, the lead pull strength of the ordinary chemical nickel-gold semiconductor packaging substrate of the above-mentioned comparison example 1 was 8 to 12 gf after 5 reflow soldering times, and decreased to 7 to 11.5 gf after aging at a temperature of 150°C for 12 hours.

[0510] Moreover, when measured by the same lead pull strength evaluation condition of the above-mentioned evaluation condition 2, the lead pull strength of the thin film chemical nickel palladium gold (ENEPIG) semiconductor packaging substrate of the above-mentioned comparison example 3 was 7 to 11.5 gf after 5 reflow soldering times, and decreased to 6 to 11 gf after aging at a temperature of 150°C for 12 hours.

[0511] Experimental Example 7: Measurement of solder diffusion

[0512] In order to determine the solder diffusion properties of semiconductor packaging substrates, such as Figure 8 As shown, the semiconductor package substrates having direct chemical gold plating films formed thereon in Examples 1, 2, and 4 (0.06 μm) were evaluated under the solder diffusibility evaluation condition of the following evaluation condition 3.

[0513] [Evaluation Condition 3]

[0514] Evaluation by reflowing the solder balls

[0515] Solder ball diameter: 300μm

[0516] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0517] Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform bonding (soldering) at 240-260°C for 20-60 seconds

[0518] The solder diffusion property of the semiconductor package substrate formed with a direct chemical gold plating film in the above-mentioned embodiment 1 is solder ball diffusion diameter / solder ball diameter (N). Before reflow soldering, the diffusion factor N is 3.23, and after reflow soldering 3 times, the diffusion factor N is 3.29.

[0519] Moreover, the solder diffusivity of the semiconductor package substrate formed with the direct chemical gold plating film in the above-mentioned Example 2 is solder ball diffusion diameter / solder ball diameter (N). Before reflow soldering, the diffusion factor N is 2.92, and after reflow soldering 3 times, the diffusion factor N is 3.02.

[0520] Furthermore, the solder diffusivity of the semiconductor package substrate formed with a direct chemical gold plating film in the above-mentioned Example 4 is solder ball diffusion diameter / solder ball diameter (N). Before reflow soldering, the diffusion factor N is 3.08, and after reflow soldering 3 times, the diffusion factor N is 3.11.

[0521] That is, the semiconductor package substrates on which the direct chemical gold plating films of Examples 1, 2, and 4 are formed have excellent solder diffusivity.

[0522] On the other hand, when evaluated under the same solder diffusion evaluation conditions of the above-mentioned evaluation condition 3, the solder diffusion of the ordinary chemical nickel-gold semiconductor packaging substrate of the above-mentioned comparison example 1 is the solder ball diffusion diameter / solder ball diameter (N). Before reflow soldering, the diffusion factor N is 3.72, and after reflow soldering 3 times, the diffusion factor N is 3.68.

[0523] Moreover, when evaluated under the same solder diffusion evaluation conditions of the above-mentioned evaluation condition 3, the solder diffusion of the organic solderability protective layer (OSP) semiconductor packaging substrate of the above-mentioned comparison example 4 is the solder ball diffusion diameter / solder ball diameter (N). Before reflow soldering, the diffusion factor N is 2.12. After reflow soldering 3 times, the diffusion factor N is greatly reduced to 2.09.

[0524] Experimental Example 8 Tensile force measurement

[0525] In order to determine the solder diffusion properties of semiconductor packaging substrates, such as Fig. 9As shown, the semiconductor package substrates formed with direct chemical gold plating films of Examples 13, 15 and 16 were evaluated under the following evaluation condition 4 for anisotropic conductive film (ACF) bonding and the following evaluation condition 5 for tensile force measurement.

[0526] [Evaluation Condition 4]

[0527] Temperature: 170℃

[0528] Pressure: 12.30kgf

[0529] Time: 7 seconds,

[0530] [Evaluation Condition 5]

[0531] Angle: 90°

[0532] Speed: 833μm / sec

[0533] Tape: Low temperature tape AC-3614KS-25 (1.0×100mm).

[0534] The average bonding tensile force of the semiconductor package substrate formed with the direct chemical gold plating film of Example 13 is 1299.8 g / cm.

[0535] Furthermore, the average bonding tensile force of the semiconductor package substrate on which the direct chemical gold plating film was formed in the above-mentioned Example 15 was 1255.9 g / cm.

[0536] Furthermore, the average bonding tensile force of the semiconductor package substrate on which the direct chemical gold plating film was formed in Example 16 was 1083.6 g / cm.

[0537] The quality evaluation standard (specification) of the average bonding tension of the semiconductor package substrate is 750 g / cm or more, and all of the semiconductor package substrates formed with direct chemical gold plating films of Examples 13, 15 and 16 satisfy the quality standard of bonding tension.

[0538] Experimental Example 9: Bendability Measurement

[0539] In order to determine the solder diffusion properties of semiconductor packaging substrates, such as Fig.10 As shown, the bendability of the semiconductor package substrate having the direct chemical gold plating film formed thereon in Example 11 was evaluated under the following evaluation condition 6 for crack (MIT) evaluation.

[0540] [Evaluation Condition 6]

[0541] Bendability testing equipment: MIT-DA / TOYOSEIKI

[0542] Loading: 500g

[0543] Bending speed: 175 times / minute

[0544] Bending angle: 135°

[0545] Reflow conditions: preheating at 130-200°C for 80-120 seconds, followed by irreversible heating (heat aging) at 240-260°C for 20-60 seconds.

[0546] Among them, the bendability of the semiconductor package substrate formed with the direct chemical gold plating film of the above-mentioned Example 11 reached 199 times before reflow soldering, but increased to 210 times after reflow soldering.

[0547] Therefore, the semiconductor package substrate on which the direct chemical gold plating film is formed in the above-mentioned Example 11 has extremely excellent flexibility.

[0548] On the other hand, the bendability of the highly flexible chemical nickel-gold semiconductor package substrate of the above-mentioned comparative example 2 reached 145 times before reflow soldering, and sharply decreased to 78 times after reflow soldering.

[0549] Moreover, in the scanning electron microscope image, the semiconductor packaging substrate formed with a direct chemical gold plating film of the above-mentioned Example 11 showed almost no change after 5 bendings and almost no damage after 10 bendings, but the high-flexibility chemical nickel-gold semiconductor packaging substrate of the above-mentioned Comparative Example 2 showed severe cracking and separation after 5 bendings and broke after 10 bendings.

[0550] Although specific embodiments of the semiconductor package substrate and the semiconductor package including the same according to the present invention have been described above, it is needless to say that various modifications may be made without departing from the scope of the present invention.

[0551] Therefore, the scope of the present invention is not limited to the described embodiments, but should be determined by the appended claims and the scope equivalent to the claims.

[0552] That is, the described embodiments are illustrative at all levels and should be understood as non-restrictive. The scope of the present invention is presented by the attached invention protection scope rather than detailed description, and should be interpreted as all changes or modified embodiments derived from the meaning, scope and equivalent concepts of the invention protection scope are included in the scope of the present invention.

Claims

1. A semiconductor packaging substrate, characterized in that: include: Copper substrate; impact gold plating, formed on the copper substrate; as well as The gold plating film is formed on the above-mentioned impact gold plating film.

2. The semiconductor package substrate according to claim 1, wherein: In the above semiconductor package substrate, the pitch is the sum of the circuit width and the spacing width. When used for fine circuits at a pitch level of 4 to 50 μm, the gold plating film diffusivity of the semiconductor packaging substrate is 0.001 to 10 volume percent.

3. The semiconductor package substrate according to claim 1, wherein: When the semiconductor package substrate is measured under the high-speed ball shear strength evaluation condition of the following evaluation condition 1, the average high-speed ball shear strength is 1000 to 1600 gf. Evaluation Condition 1: High-speed shearing equipment: Dage 4000HS Shear speed: 1m / s Shear height: 50μm Ball grid array pad diameter: 350μm Solder ball diameter: 450μm Solder ball type: SAC 305, a solder ball containing 96.5 weight percent tin, 3 weight percent silver, and 0.5 weight percent copper Measurement points: n=25.

4. The semiconductor package substrate according to claim 1, wherein: The hole area of ​​the semiconductor packaging substrate is 0.005 to 10 volume percent.

5. The semiconductor package substrate according to claim 1, wherein: When the semiconductor package substrate is measured under the following evaluation condition 2 for lead pull strength, the lead pull strength is 6 to 14 gf. Evaluation condition 2: Wire Bonder: Wire Bonder-HB16 Tensile tester: Dage 4000 Gold wire: 1mil Bonding conditions: First bonding point – frequency 300Hz, time 250ms, pressure 250mN; second bonding point – frequency 400Hz, time 350mls, pressure 250mN Heat treatment conditions: 175°C, 6 hours.

6. The semiconductor package substrate according to claim 1, wherein: The thickness of the gold plating film is 2 to 1000 nm.

7. The semiconductor package substrate according to claim 1, wherein: The thickness of the above-mentioned impact gold plating film is 2 to 30 nm.

8. The semiconductor package substrate according to claim 1, wherein: When the semiconductor package substrate is evaluated under the solder diffusion evaluation condition of the following evaluation condition 3, the solder ball diffusion is solder ball diffusion diameter / solder ball diameter (N), and the diffusion factor N is 1.2 to 6. Evaluation Condition 3: Evaluation by reflowing the solder balls Solder ball diameter: 300μm Solder ball type: SAC 305, a solder ball containing 96.5 weight percent tin, 3 weight percent silver, and 0.5 weight percent copper Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform bonding, i.e. soldering, at 240-260°C for 20-60 seconds.

9. The semiconductor package substrate according to claim 1, wherein: When the semiconductor package substrate is evaluated by the following evaluation condition 4 for anisotropic conductive film bonding and the following evaluation condition 5 for tensile force measurement, the bonding tensile force is 1000 to 1600 g / cm, Evaluation Condition 4: Temperature: 170℃ Pressure: 12.30kgf Time: 7 seconds, Evaluation criteria 5: Angle: 90° Speed: 833 μm / sec Tape: Low temperature tape AC-3614KS-25, specification is 1.0×100mm.

10. The semiconductor package substrate according to claim 1, wherein: When the bendability of the semiconductor package substrate is evaluated by the crack evaluation condition of the following evaluation condition 6, the bendability reaches 50 to 220 times after 2 to 5 reflows. Evaluation Condition 6: Bendability testing equipment: MIT-DA / Toyo Seiki Loading: 500g Bending speed: 175 times / minute Bending angle: 135° Reflow conditions: preheat at 130-200°C for 80-120 seconds, followed by irreversible thermal aging at 240-260°C for 20-60 seconds.

11. A semiconductor packaging substrate, characterized in that: include: Copper substrate; as well as A gold plating film is formed on the copper substrate.

12. The semiconductor package substrate according to claim 11, wherein: In the above semiconductor package substrate, the pitch is the sum of the circuit width and the spacing width. When used for fine circuits at a pitch level of 4 μm to 50 μm, the gold plating film of the semiconductor package substrate has a diffusivity of 0.001 volume percent to 5 volume percent.

13. The semiconductor package substrate according to claim 11, wherein: The hole area of ​​the semiconductor packaging substrate is 0.005 to 10 volume percent.

14. The semiconductor package substrate according to claim 11, wherein: When the semiconductor package substrate is measured under the high-speed ball shear strength evaluation condition of the following evaluation condition 1, the average high-speed ball shear strength is 1000 to 1600 gf. Evaluation Condition 1: High-speed shearing equipment: Dage 4000HS Shear speed: 1m / s Shear height: 50μm Ball grid array pad diameter: 350μm Solder ball diameter: 450μm Solder ball type: SAC 305, a solder ball containing 96.5 weight percent tin, 3 weight percent silver, and 0.5 weight percent copper Measurement points: n=25.

15. The semiconductor package substrate according to claim 11, wherein: In the above semiconductor package substrate, the pitch is the sum of the circuit width and the spacing width. The semiconductor package substrate is used for fine circuits at a pitch level of 4 μm to 50 μm.

16. The semiconductor package substrate according to claim 11, wherein: When the semiconductor package substrate is measured under the following evaluation condition 2 for lead pull strength, the lead pull strength is 6 to 14 gf. Evaluation condition 2: Wire Bonder: Wire Bonder-HB16 Tensile tester: Dage 4000 Gold wire: 1mil Bonding conditions: First bonding point – frequency 300Hz, time 250ms, pressure 250mN; second bonding point – frequency 400Hz, time 350mls, pressure 250mN Heat treatment conditions: 175°C, 6 hours.

17. The semiconductor package substrate according to claim 11, wherein: The thickness of the gold plating film is 2nm to 1000nm.

18. The semiconductor package substrate according to claim 11, wherein: When the semiconductor package substrate is evaluated under the solder diffusion evaluation condition of the following evaluation condition 3, the solder ball diffusion is solder ball diffusion diameter / solder ball diameter (N), and the diffusion factor N is 1.2 to 6. Evaluation Condition 3: Evaluation by reflowing the solder balls Solder ball diameter: 300μm Solder ball type: SAC 305, a solder ball containing 96.5 weight percent tin, 3 weight percent silver, and 0.5 weight percent copper Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform bonding, i.e. soldering, at 240-260°C for 20-60 seconds.

19. The semiconductor package substrate according to claim 11, wherein: When the semiconductor package substrate is evaluated by the following evaluation condition 4 for anisotropic conductive film bonding and the following evaluation condition 5 for tensile force measurement, the bonding tensile force is 1000 to 1600 g / cm, Evaluation Condition 4: Temperature: 170℃ Pressure: 12.30kgf Time: 7 seconds, Evaluation criteria 5: Angle: 90° Speed: 833 μm / sec Tape: Low temperature tape AC-3614KS-25, specification is 1.0×100mm.

20. The semiconductor package substrate according to claim 11, wherein: When the bendability of the semiconductor package substrate is evaluated by the crack evaluation condition of the following evaluation condition 6, the bendability reaches 50 to 220 times after 2 to 5 reflows. Evaluation Condition 6: Bendability testing equipment: MIT-DA / Toyo Seiki Loading: 500g Bending speed: 175 times / minute Bending angle: 135° Reflow conditions: preheat at 130-200°C for 80-120 seconds, followed by irreversible thermal aging at 240-260°C for 20-60 seconds.

21. A semiconductor package, characterized in that: A semiconductor package substrate according to any one of claims 1 to 20 is included.

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