Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the packaging structure comprises a substrate which comprises a bonding surface; the interconnection chip is bonded on the bonding surface of the substrate and is electrically connected with the substrate; the device chip comprises a first surface and a second surface which are opposite to each other, the first surface and the second surface are electrically connected with each other, and the first surface is bonded on the interconnection chip and is electrically connected with the interconnection chip; and the substrate layer is bonded on the second surface of the device chip. According to the invention, the first surface and the second surface, which are opposite to each other, of the device chip can be electrically connected with the substrate, and correspondingly, a scheme that the device chip supplies power through any one or two surfaces of the first surface and the second surface can be realized through the substrate.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a packaging structure and a packaging method. Background Art

[0002] Conventional chip manufacturing technologies are being pushed to their limits in terms of the size of a single chip. However, applications are eager to use the latest technology to achieve the capabilities of large-scale integrated circuits, and achieving high-speed and small-volume interconnections between chips is a major challenge.

[0003] One current solution is to use a smaller integrated circuit of a silicon bridge (Si Bridge) chip embedded in a silicon substrate to interconnect chips through the silicon bridge chip, thereby providing a heterogeneous chip package.

[0004] However, the current packaging structure is relatively complex, and the integration level between chips still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method to realize a solution in which a device chip is powered through either a first surface or a second surface or both surfaces.

[0006] To solve the above problems, the present invention provides a packaging structure, including: a substrate, including a bonding surface; an interconnection chip, bonded to the bonding surface of the substrate and electrically connected to the substrate; a device chip, including a first surface and a second surface opposite to each other, the first surface and the second surface are electrically connected to each other, the first surface is bonded to the interconnection chip and is electrically connected to the interconnection chip; a base layer, bonded to the second surface of the device chip.

[0007] Optionally, the first side is the front side of the chip, and the second side is the back side of the chip.

[0008] Optionally, the device chip includes a backside interconnection layer located on one side of the second surface, the backside interconnection layer is electrically connected to the interconnection chip, and the backside interconnection layer is also electrically connected to the device of the device chip.

[0009] Optionally, the device chip further includes a substrate and a device layer located on the substrate, wherein the device layer is located on a side of the substrate facing the interconnection chip; and the backside interconnection layer is located on a side of the substrate facing the substrate layer.

[0010] Optionally, a first interconnection structure located on one side of the first surface is formed in the device chip, and the backside interconnection layer of the device chip is electrically connected to the interconnection chip through the first interconnection structure.

[0011] Optionally, a second interconnection structure penetrating the interconnection chip is formed in the interconnection chip, the second interconnection structure is electrically connected to the first interconnection structure, and the second interconnection structure is also electrically connected to the substrate.

[0012] Optionally, the first interconnect structure includes a first bonding pad exposed by the first surface, and the second interconnect structure includes a second bonding pad located on a side facing away from the bonding surface and exposed by the interconnect chip, and the first bonding pad and the second bonding pad are bonded to each other.

[0013] Optionally, the packaging structure further includes: a bonding dielectric layer, located between the device chip and the base layer, and the device chip and the base layer are bonded via the bonding dielectric layer.

[0014] Optionally, the packaging structure further includes: a conductive bump, which is located between the interconnection chip and the substrate and electrically connects the interconnection chip and the substrate.

[0015] Optionally, the packaging structure further includes: a sealing layer filling the gaps between adjacent conductive bumps and covering the conductive bumps

[0016] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing an interconnection chip; providing a device chip, including a first surface and a second surface opposite to each other; bonding the first surface of the device chip to the interconnection chip, electrically connecting the first surface to the interconnection chip, and electrically connecting the first surface and the second surface to each other; providing a base layer; bonding the base layer to the second surface of the device chip; providing a substrate, including a bonding surface; after bonding the base layer to the second surface of the device chip, bonding the interconnection chip to the bonding surface of the substrate, and electrically connecting it to the substrate.

[0017] Optionally, in the step of providing a device chip, the first side is the front side of the chip, and the second side is the back side of the chip.

[0018] Optionally, the step of bonding the first side of the device chip to the interconnection chip includes: providing a carrier substrate; bonding the interconnection chip to the carrier substrate; after bonding the interconnection chip to the carrier substrate, bonding the device chip to the interconnection chip; after bonding the base layer to the second side of the device chip, before bonding the interconnection chip to the bonding surface of the substrate, the packaging method also includes: removing the carrier substrate.

[0019] Optionally, the step of bonding the device chip to the interconnect chip also includes: bonding the device chip to the interconnect chip with the first side facing the interconnect chip; performing back side thinning on the device chip through the second side; after the back side thinning, forming a back side interconnect layer on the second side, the back side interconnect layer is electrically connected to the device of the device chip, and the back side interconnect layer is also electrically connected to the interconnect chip.

[0020] Optionally, in the step of providing a device chip, the device chip includes a substrate, and a device layer located on the substrate, and the device layer is located on the surface of the substrate facing the first surface; in the step of performing back thinning on the device chip through the second surface, a portion of the thickness of the substrate is removed; in the step of forming a back interconnection layer on the second surface, a back interconnection layer is formed on the substrate, and the back interconnection layer is located on the surface of the substrate facing the second surface.

[0021] Optionally, in the step of providing a device chip, a first interconnection structure located on one side of the first surface is formed in the device chip; in the step of forming a back interconnection layer on the second surface, the back interconnection layer of the device chip is electrically connected to the interconnection chip through the first interconnection structure.

[0022] Optionally, in the step of providing an interconnection chip, a sub-interconnection structure is formed in the interconnection chip; after the interconnection chip is bonded to the carrier substrate and before the device chip is bonded to the interconnection chip, it also includes: forming a second bonding pad electrically connected to the sub-interconnection structure on the exposed side of the interconnection chip, the second bonding pad and the sub-interconnection structure forming a second interconnection structure that runs through the interconnection chip; in the step of bonding the device chip to the interconnection chip, the second interconnection structure is electrically connected to the first interconnection structure; in the step of bonding the interconnection chip to the bonding surface of the substrate, the second interconnection structure is electrically connected to the substrate.

[0023] Optionally, in the step of providing the device chip, the first interconnect structure includes a first bonding pad exposed by the first surface; and in the step of bonding the device chip to the interconnect chip, the first bonding pad is bonded to the second bonding pad.

[0024] Optionally, the step of bonding the interconnect chip to the bonding surface of the substrate includes: forming a conductive bump on the surface of the interconnect chip facing the substrate, or on the surface of the bonding surface; using the conductive bump to achieve bonding between the interconnect chip and the substrate, and the conductive bump electrically connects the interconnect chip and the substrate.

[0025] Optionally, after the interconnection chip is bonded to the bonding surface of the substrate, the packaging method further includes: filling a sealing layer in the gaps between adjacent conductive bumps, wherein the sealing layer covers the conductive bumps.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] An embodiment of the present invention provides a packaging structure, wherein an interconnection chip is bonded to a bonding surface of a substrate and electrically connected to the substrate, and a device chip includes a first surface and a second surface opposite to each other, the first surface and the second surface are electrically connected to each other, the first surface is bonded to the interconnection chip and electrically connected to the interconnection chip, and a base layer is bonded to the second surface of the device chip; in the embodiment of the present invention, the interconnection chip is bonded to the substrate to realize the electrical connection between the interconnection chip and the substrate, the first surface of the device chip is bonded to the interconnection chip to realize the electrical connection between the first surface of the device chip and the interconnection chip, and the electrical connection between the first surface of the device chip and the substrate is realized accordingly, the first surface and the second surface are electrically connected to each other, and the electrical connection between the second surface of the device chip and the substrate is realized accordingly, so that the first surface and the second surface opposite to the device chip can be electrically connected to the substrate, and the device chip can be powered through any one of the first surface and the second surface or both surfaces through the substrate, thereby improving the integration of the packaging structure, and the base layer is bonded to the second surface of the device chip, which is beneficial to reinforcing the device chip, improving the mechanical strength, making the device chip easy to bond, thereby easily realizing the solution of powering the device chip through any one of the first surface and the second surface or both surfaces through the substrate.

[0028] An embodiment of the present invention provides a packaging method, providing an interconnection chip, providing a device chip, including a first surface and a second surface opposite to each other, bonding the first surface of the device chip to the interconnection chip, electrically connecting the first surface to the interconnection chip, and electrically connecting the first surface and the second surface to each other, providing a base layer, bonding the base layer to the second surface of the device chip, providing a substrate, including a bonding surface, bonding the base layer to the second surface of the device chip, bonding the interconnection chip to the bonding surface of the substrate, and electrically connecting the substrate; in an embodiment of the present invention, the interconnection chip is bonded to the substrate to realize the electrical connection between the interconnection chip and the substrate, the first surface of the device chip is bonded to the interconnection chip, and the first surface of the device chip is electrically connected to the interconnection chip. The electrical connection of the chip is connected, and the electrical connection between the first side of the device chip and the substrate is realized accordingly. The first side and the second side are electrically connected to each other, and the electrical connection between the second side of the device chip and the substrate is realized accordingly, so that the first side and the second side opposite to each other of the device chip are both electrically connected to the substrate, and the device chip can be powered through any one of the first side and the second side or both sides through the substrate, thereby improving the integration of the packaging structure. Moreover, a base layer is bonded to the second side of the device chip, which is beneficial to strengthening the device chip and improving the mechanical strength, making the device chip easy to bond, thereby making it easy to realize the device chip powered through any one of the first side and the second side or both sides through the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;

[0030] Figures 2 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION

[0031] As can be seen from the background technology, usually only the front side of the chip is electrically connected to the outside of the two back sides of the chip. At present, the back side power delivery network (BSPDN) technology is developed, that is, an interconnection pad will also be formed on the back side of the chip for electrical connection with the outside, for example, as described in document 10.1109 / TED.2019.2954301. However, there is currently no method to electrically lead out the back side of the chip to achieve electrical connection between the front and back sides of the chip, making it difficult to improve the packaging integration.

[0032] In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, including: a substrate, including a bonding surface; an interconnection chip, bonded to the bonding surface of the substrate and electrically connected to the substrate; a device chip, including a first surface and a second surface opposite to each other, the first surface and the second surface are electrically connected to each other, the first surface is bonded to the interconnection chip and is electrically connected to the interconnection chip; a base layer, bonded to the second surface of the device chip.

[0033] In an embodiment of the present invention, an interconnection chip is bonded to a substrate to realize electrical connection between the interconnection chip and the substrate, and a first side of a device chip is bonded to an interconnection chip to realize electrical connection between the first side of the device chip and the interconnection chip, thereby realizing electrical connection between the first side of the device chip and the substrate, and the first side and the second side are electrically connected to each other, thereby realizing electrical connection between the second side of the device chip and the substrate, thereby realizing that the first side and the second side opposite to each other are both electrically connected to the substrate, thereby realizing a scheme in which the device chip is powered through either the first side or the second side or both sides through the substrate, thereby improving the integration of the packaging structure, and a base layer is bonded to the second side of the device chip, thereby helping to reinforce the device chip, improving the mechanical strength, and making it easy to bond the device chip, thereby easily realizing a scheme in which the device chip is powered through either the first side or the second side or both sides through the substrate.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention.

[0036] The packaging structure includes: a substrate 100, including a bonding surface 100a; an interconnection chip 300, bonded to the bonding surface 100a of the substrate 100 and electrically connected to the substrate 100; a device chip 200, including a first surface 200a and a second surface 200b opposite to each other, the first surface 200a and the second surface 200b are electrically connected to each other, the first surface 200a is bonded to the interconnection chip 300 and is electrically connected to the interconnection chip 300; a base layer 500, bonded to the second surface 200b of the device chip 200.

[0037] The substrate 100 is used to provide a process operation basis for bonding the interconnected chip 300 . Specifically, the bonding surface 100 a of the substrate 100 is a process operation platform.

[0038] In this embodiment, the substrate 100 includes an interconnection structure layer, and the exposed surface of the interconnection structure layer is a bonding surface 100a.

[0039] The interconnection structure layer is used to achieve bonding with the interconnection chip 300, thereby achieving electrical connection with the interconnection chip 300. The interconnection structure layer is also used to achieve electrical connection between the interconnection chip 300 and the outside.

[0040] In this embodiment, the interconnection structure layer is a redistribution structure. Specifically, the redistribution structure may include one or more redistribution layers. In this embodiment, the redistribution structure includes multiple redistribution layers as an example for description.

[0041] Specifically, in this embodiment, the substrate 100 is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0042] The device chip 200 is used to be electrically connected to the substrate 100 through the interconnection chip 300, so as to form a corresponding packaging structure to achieve corresponding functions.

[0043] In this embodiment, the first surface 200 a is bonded to the interconnection chip 300 and electrically connected to the interconnection chip 300 , thereby achieving electrical connection between the first surface 200 a and the interconnection chip 300 , and correspondingly achieving electrical connection between the first surface 200 a and the substrate 100 .

[0044] In this embodiment, the interconnection chip 300 is bonded to the substrate 100 to realize the electrical connection between the interconnection chip 300 and the substrate 100, and the first surface 200a of the device chip 200 is bonded to the interconnection chip 300 to realize the electrical connection between the first surface 200a of the device chip 200 and the interconnection chip 300, and accordingly realize the electrical connection between the first surface 200a of the device chip 200 and the substrate 100, and the first surface 200a and the second surface 200b are electrically connected to each other, and accordingly realize the electrical connection between the second surface 200b of the device chip 200 and the substrate 100, so that the first surface 200a and the second surface 200b of the device chip 200, which are opposite to each other, are both electrically connected to the substrate 100, and accordingly, the device chip 200 can be powered through any one or both sides of the first surface 200a and the second surface 200b through the substrate 100, thereby improving the integration of the packaging structure.

[0045] In this embodiment, the first surface 200a is the front side of the chip, and the second surface 200b is the back side of the chip.

[0046] Specifically, in this embodiment, the devices of the device chip 200 are powered through the second surface 200 b.

[0047] In this embodiment, the device chip 200 is bonded to the interconnection chip 300 , and the power supply to the devices of the device chip 200 is realized through the second surface 200 b , which is beneficial to simplify the circuit and improve the integration of the packaging structure.

[0048] Specifically, in the present embodiment, power is supplied to the devices of the device chip 200 through the second surface 200b, and signal electrical connections are made to the devices of the device chip 200 through the first surface 200a. Compared with a scheme in which both the power supply line and the signal line are electrically connected from the first surface of the first device chip, the present scheme is conducive to reducing mutual interference between the power supply line and the signal line, and is conducive to making the power supply line electrically connected through the second surface 200b have a higher degree of freedom in design and a larger formation space, which is conducive to reducing the resistance of the power supply line, thereby reducing the probability of the voltage drop affecting the working performance of the device due to excessive resistance of the power supply line, thereby improving the working performance of the device. At the same time, the signal line electrically connected through the first surface 200a also has a larger formation space, so that the device of the device chip 200 achieves better working performance.

[0049] In this embodiment, the device chip 200 includes a backside interconnection layer 220 located on one side of the second surface 200 b . The backside interconnection layer 220 is electrically connected to the interconnection chip 300 . The backside interconnection layer 220 is also electrically connected to the devices of the device chip 200 .

[0050] The backside interconnection layer 220 is used to realize electrical connection between the devices in the device chip 200 and the outside through the second surface 200 b . The backside interconnection layer 220 is also used to realize electrical connection between the interconnection chip 300 and the outside.

[0051] It should be noted that, in this embodiment, a through-silicon-via (TSV) structure is used to electrically connect the backside interconnect layer 220 to the device of the device chip 200 , which is beneficial for making electrical transmission more direct and rapid.

[0052] In this embodiment, the device chip 200 further includes a substrate 210 and a device layer 230 located on the substrate 210 . The device layer 230 is located on a side of the substrate 210 facing the interconnection chip 300 .

[0053] The device layer 230 is used to form the devices of the device chip 200. The device layer 230 is located on the side of the substrate 210 facing the interconnection chip 300 (i.e., the surface facing the first surface 200a), leaving space for forming the back interconnection layer 220 on the surface on the other side of the substrate 210, so that the back interconnection layer 220 formed on the surface on the other side of the substrate 210 can face the second surface 200b, thereby realizing the back power supply of the devices in the device layer 230.

[0054] Specifically, in this embodiment, in the process of packaging structure, the device chip 200 includes a substrate 210 and a device layer 230 located on the substrate 210, the substrate 210 is located on the second surface 200b side, and the device layer 210 is located on the first surface 200a side, then the substrate 210 can provide a process platform for the formation of the device layer 230, the substrate 210 also provides a process platform for forming a back interconnection layer 220, the substrate 210 is subjected to back thinning treatment, a portion of the thickness of the substrate 210 is removed through the second surface 200b, and after the back thinning is performed, the back interconnection layer 220 is formed on the remaining substrate 210.

[0055] Accordingly, in this embodiment, the backside interconnection layer 220 is located on the side of the substrate 210 facing the substrate layer 500 (ie, the side facing the second surface 200 b ).

[0056] In this embodiment, a first interconnection structure located on one side of the first surface 200 a is formed in the device chip 200 , and the backside interconnection layer 220 of the device chip 200 is electrically connected to the interconnection chip 300 through the first interconnection structure.

[0057] The first interconnect structure is used to penetrate the substrate 210 and electrically connect with the back interconnect layer 220 to realize electrical connection between the back interconnect layer 220 and the outside. The first interconnect structure is located on one side of the first surface 200a, and the first interconnect structure can be electrically connected to the interconnect chip 300 through the first surface 200a, and accordingly the back interconnect layer 220 is electrically connected to the interconnect chip 300 through the first interconnect structure.

[0058] In this embodiment, the backside interconnect layer 220 is electrically connected to the first side 200a of the device chip 200 through the first interconnect structure wiring, and then electrically connected to the substrate 100 through the first side 200a. The wiring of the first interconnect structure is conducive to more accurate electrical transmission.

[0059] It should be noted that, in this embodiment, the first interconnection structure includes a through-silicon-via (TSV) structure, which is conducive to making electrical transmission more direct and rapid.

[0060] In this embodiment, the material of the first interconnect structure is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0061] The interconnection chip 300 is used to electrically connect with the device chip 200 to realize the basic circuit structure between the interconnection chip 300 and the device chip 200. The interconnection chip 300 is also used to electrically connect with the substrate 100 to realize the electrical connection between the interconnection chip 300 and the outside, and correspondingly realize the electrical connection between the device chip 200 and the outside.

[0062] In the present embodiment, in the semiconductor manufacturing process, after the device chip 200 is bonded to the interconnection chip 300, the interconnection chip 300 is then bonded to the substrate 100, which increases the total thickness of the structure when the device chip 200 is bonded to the substrate 100, and is beneficial to increasing the bonding strength of the device chip 200, thereby facilitating the implementation of a solution for bonding the device chip 200 to the substrate 100 for back-side power supply, while achieving electrical connection between the device chip 200 and the interconnection chip 300, which is beneficial to increasing the diversity of the circuit structure and improving the applicability of the packaging structure.

[0063] It should be noted that, in this embodiment, the front side of the interconnection chip 300 faces the substrate 100 , and the back side of the chip faces the device chip 200 . The front side of the chip usually has more interconnection pads, which is beneficial to improving the electrical connection performance between the interconnection chip 300 and the substrate 100 .

[0064] In this embodiment, a second interconnection structure penetrating the interconnection chip 300 is formed in the interconnection chip 300 . The second interconnection structure is electrically connected to the first interconnection structure, and the second interconnection structure is also electrically connected to the substrate 100 .

[0065] The second interconnect structure serves as an electrical connection structure, and the second interconnect structure is electrically connected to the first interconnect structure to realize electrical connection between the second interconnect structure and the back interconnect layer 220. The second interconnect structure is also electrically connected to the substrate 100 to realize electrical connection between the back interconnect layer 220 and the substrate 100, thereby realizing a solution of back-side power supply to the device chip 200 through the back interconnect layer 220.

[0066] In this embodiment, the material of the second interconnect structure is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0067] In this embodiment, the interconnection chip 300 may further include devices, and the devices are electrically connected to the substrate 100, and the devices may also be electrically connected to the devices of the device chip 200, thereby realizing electrical connection between the devices of the interconnection chip 300 and the outside, realizing the basic circuit functions in the interconnection chip 300, and correspondingly realizing the substrate circuit between the devices of the interconnection chip 300 and the devices of the device chip 200.

[0068] In this embodiment, the first interconnect structure includes a first bonding pad exposed by the first surface 200a, and the second interconnect structure includes a second bonding pad located on the side facing away from the bonding surface 100a and exposed by the interconnect chip 300. The first bonding pad and the second bonding pad are bonded to each other.

[0069] The first bonding pad and the second bonding pad are used to realize the bonding between the device chip 200 and the interconnection chip 300, and realize the electrical connection between the first interconnection structure and the second interconnection structure.

[0070] The base layer 500 is used to protect the second surface 200 b of the device chip 200 , and is also used to reinforce the device chip 200 , so as to facilitate bonding the device chip 200 and the interconnection chip 300 to the substrate 100 .

[0071] In this embodiment, a base layer 500 is bonded to the second surface 200b of the device chip 200, which is beneficial to reinforcing the device chip and improving the mechanical strength, making the device chip 200 easy to bond, thereby facilitating the device chip 200 to be powered through either or both of the first surface 200a and the second surface 200b through the substrate 100.

[0072] In this embodiment, the base layer 500 is a light sheet wafer.

[0073] In this embodiment, the packaging structure further includes: a bonding dielectric layer 510 , which is located between the device chip 200 and the base layer 500 , and the device chip 200 and the base layer 500 are bonded via the bonding dielectric layer 510 .

[0074] The bonding medium layer 510 is used to achieve bonding between the device chip 200 and the base layer 500 , which is beneficial to enhancing the bonding effect.

[0075] In this embodiment, the packaging structure further includes: a conductive bump 110 , which is located between the interconnection chip 300 and the substrate 100 and electrically connects the interconnection chip 300 and the substrate 100 .

[0076] The conductive bumps 110 are used to realize electrical connection between the substrate 100 and the interconnection chip 300 .

[0077] In this embodiment, the material of the conductive bump 110 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the conductive bump 110 is tin.

[0078] For example, the conductive bump 110 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the same first conductive bump spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0079] In other embodiments, the conductive bump may also be a micro bump (uBump).

[0080] In this embodiment, the packaging structure further includes: a sealing layer 130 filling the gaps between adjacent conductive bumps 110 and covering the conductive bumps 110 .

[0081] The sealing layer 130 is used to achieve sealing between the device chip 200 and the substrate 100 , and to achieve sealing between the interconnection chip 300 and the substrate 100 , and is also used to achieve sealing of the conductive bumps 110 .

[0082] It should be noted that in the actual process, when a buried power rail (BPR) structure and a power delivery network (PDN) structure are used, higher requirements are placed on chip size and integration, and this embodiment is particularly applicable.

[0083] In this embodiment, the aforementioned conductive bump 110 is a first conductive bump 110, and the packaging structure further includes: a second conductive bump 120, located on the surface of the substrate 100 facing away from the bonding surface 100a, and the second conductive bump 120 is used to realize the electrical connection between the packaging structure and the external circuit.

[0084] The second conductive bumps 120 are used to realize electrical connection between the package structure and the external circuit, thereby realizing electrical connection between the device chip 200 and the interconnection chip 300 and the external circuit.

[0085] In this embodiment, the material of the second conductive bump 120 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 120 is tin.

[0086] For example, the second conductive bump 120 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same second conductive bump 120 spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces the size and weight.

[0087] In other embodiments, the second conductive bump may also be a ball grid array (BGA) structure.

[0088] Figures 2 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention.

[0089] refer to Figure 2 , providing a device chip 200, including a first surface 200a and a second surface 200b opposite to each other.

[0090] The device chip 200 is used to be electrically connected to the substrate later, so as to form a corresponding packaging structure to achieve corresponding functions, wherein the first surface 200a and the second surface 200b are both used to achieve electrical connection with the outside later.

[0091] In this embodiment, in the step of providing the device chip 200 , the first surface 200 a is the front surface of the chip, and the second surface 200 b is the back surface of the chip.

[0092] Subsequently, the devices of the device chip 200 are powered through the second surface 200 b , ie, the back surface of the chip.

[0093] In this embodiment, in the step of providing the device chip 200 , the device chip 200 includes a substrate 210 and a device layer 220 located on the substrate 210 . The substrate 210 is located on the second surface 200 b , and the device layer 220 is located on the first surface 200 a .

[0094] The substrate 210 is used to provide a process platform for forming the device layer 220 , and is also used to provide a process platform for subsequently forming a backside interconnection layer.

[0095] In this embodiment, the substrate 210 is located on the side of the second surface 200b, and the device layer 220 is located on the side of the first surface 200a. The substrate 210 is located on the side of the second surface 200b and there is a space for forming a back interconnection layer, so that the subsequently formed back interconnection layer is located on the surface of the substrate 210 facing the second surface 200b.

[0096] In this embodiment, in the step of providing the device chip 200 , a first interconnection structure located on one side of the first surface 200 a is formed in the device chip 200 .

[0097] The backside interconnection layer of the subsequent device chip 200 is electrically connected to the interconnection chip 300 through the first interconnection structure.

[0098] The first interconnect structure is used to subsequently electrically connect with the back interconnect layer to realize electrical connection between the back interconnect layer and the outside. The first interconnect structure is located on one side of the first surface 200a, and the first interconnect structure can subsequently be electrically connected to the substrate through the first surface 200a, and accordingly the back interconnect layer is electrically connected to the substrate through the first interconnect structure.

[0099] It should be noted that, in this embodiment, the first interconnection structure includes a through-silicon-via (TSV) structure, which is conducive to making electrical transmission more direct and rapid.

[0100] In this embodiment, the material of the first interconnect structure is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0101] In this embodiment, in the step of providing the device chip 200 , the first interconnect structure includes a first bonding pad exposed by the first surface 200 a .

[0102] The first bonding pad is used to subsequently bond the device chip 200 and the interconnection chip 300 with the second bonding pad, and is also used to subsequently electrically connect the first interconnection structure with the second interconnection structure.

[0103] refer to Figure 3 , providing an interconnection chip 300.

[0104] The interconnection chip 300 is used to be subsequently bonded with the device chip 200 to achieve electrical connection with the device chip 200 , and correspondingly achieve electrical connection with the substrate through the device chip 200 .

[0105] In this embodiment, in the step of providing the interconnection chip 300 , a sub-interconnection structure is formed in the interconnection chip 300 .

[0106] The sub-interconnection structure is used as an electrical connection structure to subsequently form a second interconnection structure, and the second interconnection structure is used to achieve electrical connection between the device chip 200 and the substrate.

[0107] In this embodiment, the material of the second interconnect structure is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0108] Combined with reference Figures 4 to 7 , the first surface 200a of the device chip 200 is bonded to the interconnection chip 300, the first surface 200a is electrically connected to the interconnection chip 300, and the first surface 200a and the second surface 200b are electrically connected to each other.

[0109] The interconnection chip 300 is electrically connected to the device chip 200 to realize the basic circuit structure between the interconnection chip 300 and the device chip 200. Subsequently, the interconnection chip 300 is also used to be electrically connected to the substrate to realize the electrical connection between the interconnection chip 300 and the outside.

[0110] In the present embodiment, the interconnection chip 300 is bonded to the device chip 200, which increases the total thickness of the structure when the interconnection chip 300 is subsequently bonded to the substrate, which is beneficial to increase the bonding strength of the device chip 200, thereby facilitating the subsequent implementation of a solution for bonding the device chip 200 to the substrate for back-side power supply, while achieving electrical connection between the device chip 200 and the interconnection chip 300, which is beneficial to increasing the diversity of the circuit structure and improving the applicability of the packaging structure.

[0111] It should be noted that, in the present embodiment, the back side of the interconnection chip 300 faces the device chip 200. When the interconnection chip 300 is subsequently bonded to the substrate, the front side of the interconnection chip 300 faces the substrate. The front side of the chip usually has more interconnection pads, which is beneficial to improving the electrical connection performance between the interconnection chip 300 and the substrate.

[0112] refer to Figure 4 The step of bonding the first surface 200 a of the device chip 200 to the interconnection chip 300 includes: providing a carrier substrate 400 .

[0113] The carrier substrate 400 is used to provide support for the subsequent formation of the second bonding pad.

[0114] In this embodiment, the carrier substrate 400 includes a carrier wafer or a glass substrate.

[0115] Continue to refer Figure 4 , bonding the interconnection chip 300 to the carrier substrate 400 .

[0116] The interconnection chip 300 is bonded to the carrier substrate 400 to expose the side where the second bonding pad is to be formed, in preparation for the subsequent formation of the second bonding pad.

[0117] refer to Figure 5 After bonding the interconnection chip 300 to the carrier substrate 400 and before bonding the device chip 200 to the interconnection chip 300, it also includes: forming a second bonding pad electrically connected to the sub-interconnection structure on the exposed side of the interconnection chip 300, and the second bonding pad and the sub-interconnection structure constitute a second interconnection structure that runs through the interconnection chip 300.

[0118] The second interconnection structure is used as an electrical connection structure to subsequently realize electrical connection between the device chip 200 and the substrate.

[0119] In this embodiment, the material of the second interconnect structure is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0120] refer to Figure 6 and Figure 7 After the interconnection chip 300 is bonded to the carrier substrate 400 , the device chip 200 is bonded to the interconnection chip 300 .

[0121] In this embodiment, in the step of bonding the device chip 200 to the interconnection chip 300 , the second interconnection structure is electrically connected to the first interconnection structure.

[0122] The second interconnect structure is electrically connected to the first interconnect structure, and is used to subsequently realize the electrical connection between the back interconnect layer and the second interconnect structure through the first interconnect structure, and correspondingly realize the electrical connection between the back interconnect layer and the substrate, thereby realizing the solution of back-side power supply to the device of the device chip 200 through the back interconnect layer.

[0123] In this embodiment, in the step of bonding the device chip 200 to the interconnection chip 300 , the first bonding pad is bonded to the second bonding pad.

[0124] The first bonding pad and the second bonding pad are used to realize the bonding between the device chip 200 and the interconnection chip 300, and are also used to realize the electrical connection between the first interconnection structure and the second interconnection structure.

[0125] Specifically, refer to Figure 6 The step of bonding the device chip 200 to the interconnection chip 300 includes: bonding the device chip 200 to the interconnection chip 300 with the first surface 200 a of the device chip 200 facing the interconnection chip 300 .

[0126] The device chip 200 is bonded to the interconnection chip 300 with the first surface 200 a facing the interconnection chip 300 , exposing the second surface 200 b , in preparation for subsequent backside thinning.

[0127] The carrier substrate 400 and the interconnection chip 300 are used to provide support for the subsequent backside thinning of the device chip 200 .

[0128] refer to Figure 7 , the device chip 200 is subjected to backside thinning processing through the second surface 200b.

[0129] The device chip 200 is subjected to backside thinning through the second surface 200 b to remove excess material of the substrate 210 .

[0130] In this embodiment, the device chip 200 is subjected to backside thinning treatment, and the carrier substrate 400 and the interconnection chip 300 are used to provide support during the backside thinning treatment process, and the carrier substrate 400 is located at the bottom of the interconnection chip 300, which is beneficial to protect the circuit structure of the interconnection chip 300 from being contaminated during the backside thinning treatment process.

[0131] In this embodiment, in the step of performing backside thinning on the device chip 200 through the second surface 200 b , a portion of the thickness of the substrate 210 is removed.

[0132] A portion of the thickness of the substrate 210 is removed, and the remaining portion of the thickness of the substrate 210 is retained to serve as a process platform for subsequently forming a backside interconnection layer.

[0133] Continue to refer Figure 7 After the back side thinning process is performed, a back side interconnection layer 230 is formed on the second side 200 b , and the back side interconnection layer 230 is electrically connected to the device of the device chip 200 , and the back side interconnection layer 230 is also electrically connected to the interconnection chip 300 .

[0134] The backside interconnection layer 220 is used to realize electrical connection between the devices in the device chip 200 and the outside through the second surface 200 b.

[0135] It should be noted that, in this embodiment, a through-silicon-via (TSV) structure is used to electrically connect the backside interconnect layer 220 to the device of the device chip 200 , which is beneficial for making electrical transmission more direct and rapid.

[0136] In this embodiment, in the step of forming the backside interconnection layer 230 on the second surface 200 b , the backside interconnection layer 230 is formed on the substrate 210 , and the backside interconnection layer 230 is located on the surface of the substrate 210 facing the second surface 200 b .

[0137] The back surface interconnection layer 230 is located on the surface of the substrate 210 facing the second surface 200 b , so that the back surface interconnection layer 230 is used to subsequently realize a solution of back-side power supply to the devices of the device chip 200 .

[0138] In this embodiment, in the step of forming the backside interconnection layer 230 on the second surface 200 b , the backside interconnection layer 230 of the device chip 200 is electrically connected to the interconnection chip 300 through the first interconnection structure.

[0139] The backside interconnection layer 230 is electrically connected to the first interconnection structure, so that the backside interconnection layer 230 is electrically connected to the substrate through the first interconnection structure.

[0140] In this embodiment, the backside interconnection layer 220 is electrically connected to the interconnection chip 300 through the first interconnection structure wiring, and then electrically connected to the substrate through the interconnection chip 300. The wiring of the first interconnection structure is conducive to more accurate electrical transmission.

[0141] refer to Figure 8 , providing a base layer 500.

[0142] The base layer 500 is used to provide support when forming conductive bumps on the interconnection chip 300 , protect the second surface 200 b of the device chip 200 , and reinforce the device chip 200 to facilitate bonding the device chip 200 and the interconnection chip 300 to the substrate 100 .

[0143] In this embodiment, the base layer 500 is a light sheet wafer.

[0144] refer to Fig. 9 , bonding the base layer 500 to the second surface 200 b of the device chip 200 .

[0145] In this embodiment, a base layer 500 is bonded to the second surface 200b of the device chip 200, which is beneficial to strengthening the device chip and improving the mechanical strength, making the device chip 200 easy to bond, thereby facilitating the subsequent power supply of the device chip 200 through the substrate through either or both of the first surface 200a and the second surface 200b.

[0146] In this embodiment, in the step of bonding the base layer 500 to the second surface 200 b of the device chip 200 , a bonding dielectric layer 510 is formed on the second surface 200 b of the device chip 200 , and the bonding between the device chip 200 and the base layer 500 is achieved using the bonding dielectric layer 510 .

[0147] The bonding medium layer 510 is used to achieve bonding between the device chip 200 and the base layer 500 , which is beneficial to enhancing the bonding effect.

[0148] refer to Fig.10 After bonding the base layer 500 to the second surface 200 b of the device chip 200 and before subsequently bonding the interconnection chip 300 to the bonding surface of the substrate, the packaging method further includes: removing the carrier substrate 400 .

[0149] After the base layer 500 is bonded to the device chip 200 , the carrier substrate 400 is removed to prepare for the subsequent bonding of the interconnection chip 300 to the substrate and to prepare for forming conductive bumps on the interconnection chip 300 .

[0150] refer to Fig.11 , providing a substrate 100 including a bonding surface 100a.

[0151] The substrate 100 is used to provide a process operation basis for realizing the bonding of the device chip 200 . Specifically, the bonding surface 100 a of the substrate 100 is a process operation platform.

[0152] In this embodiment, the substrate 100 includes an interconnection structure layer, and the exposed surface of the interconnection structure layer is a bonding surface 100a.

[0153] The interconnection structure layer is used to subsequently achieve bonding with the device chip 200 , thereby achieving electrical connection with the device chip 200 . The interconnection structure layer is also used to achieve electrical connection between the device chip 200 and the outside.

[0154] In this embodiment, the interconnection structure layer is a redistribution structure. Specifically, the redistribution structure may include one or more redistribution layers. In this embodiment, the redistribution structure includes multiple redistribution layers as an example for description.

[0155] Specifically, in this embodiment, the substrate 100 is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0156] Combined with reference Fig.12 and Fig.13 After the base layer 500 is bonded to the second surface 200 b of the device chip 200 , the interconnection chip 300 is bonded to the bonding surface 100 a of the substrate 100 and electrically connected to the substrate 100 .

[0157] After the device chip 200 is bonded to the interconnection chip 300 , the interconnection chip 300 is bonded to the substrate 100 to form a corresponding packaging structure to achieve corresponding functions.

[0158] In this embodiment, the interconnection chip 300 is bonded to the substrate 100 to realize the electrical connection between the interconnection chip 300 and the substrate 100, and the first surface 200a of the device chip 200 is bonded to the interconnection chip 300 to realize the electrical connection between the first surface 200a of the device chip 200 and the interconnection chip 300, and accordingly realize the electrical connection between the first surface 200a of the device chip 200 and the substrate 100, and the first surface 200a and the second surface 200b are electrically connected to each other, and accordingly realize the electrical connection between the second surface 200b of the device chip 200 and the substrate 100, so that the first surface 200a and the second surface 200b of the device chip 200, which are opposite to each other, are both electrically connected to the substrate 100, and accordingly, the device chip 200 can be powered through any one or both sides of the first surface 200a and the second surface 200b through the substrate 100, thereby improving the integration of the packaging structure.

[0159] Specifically, in this embodiment, the devices of the device chip 200 are powered through the second surface 200 b.

[0160] In this embodiment, the device chip 200 is bonded to the interconnection chip 300 , and the power supply to the devices of the device chip 200 is realized through the second surface 200 b , which is beneficial to simplify the circuit and improve the integration of the packaging structure.

[0161] Specifically, in the present embodiment, power is supplied to the devices of the device chip 200 through the second surface 200b, and signal electrical connections are made to the devices of the device chip 200 through the first surface 200a. Compared with a scheme in which both the power supply line and the signal line are electrically connected from the first surface of the first device chip, the present scheme is conducive to reducing mutual interference between the power supply line and the signal line, and is conducive to making the power supply line electrically connected through the second surface 200b have a higher degree of freedom in design and a larger formation space, which is conducive to reducing the resistance of the power supply line, thereby reducing the probability of the voltage drop affecting the working performance of the device due to excessive resistance of the power supply line, thereby improving the working performance of the device. At the same time, the signal line electrically connected through the first surface 200a also has a larger formation space, so that the device of the device chip 200 achieves better working performance.

[0162] In this embodiment, in the step of bonding the interconnection chip 300 to the substrate 100 , the second interconnection structure is electrically connected to the substrate 100 .

[0163] The second interconnect structure is electrically connected to the substrate 100 , thereby achieving electrical connection between the first interconnect structure and the substrate 100 , and correspondingly achieving electrical connection between the backside interconnect layer 230 and the substrate 100 .

[0164] In this embodiment, the step of bonding the device chip 200 to the substrate 100 includes: forming a conductive bump 110 on the first surface 200 a of the device chip 200 , or on the bonding surface 100 a .

[0165] The conductive bumps 110 are used to realize electrical connection between the substrate 100 and the device chip 200 .

[0166] In this embodiment, the material of the conductive bump 110 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the conductive bump 110 is tin.

[0167] For example, the conductive bump 110 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the same first conductive bump spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0168] In other embodiments, the conductive bump may also be a micro bump (uBump).

[0169] Specifically, refer to Fig.12 As an example, in this embodiment, a conductive bump 110 is formed on the first surface 200 a of the device chip 200 .

[0170] refer to Fig.13 The device chip 200 and the substrate 100 are bonded together using the conductive bumps 110 , and the conductive bumps 110 electrically connect the device chip 200 and the substrate 100 .

[0171] Continue to refer Fig.11 After the device chip 200 is bonded to the substrate 100 , the packaging method further includes: filling a sealing layer 130 in the gaps between adjacent conductive bumps 110 , wherein the sealing layer 130 covers the conductive bumps 110 .

[0172] The sealing layer 130 is used to achieve sealing between the device chip 200 and the substrate 100 , and to achieve sealing between the interconnection chip 300 and the substrate 100 , and is also used to achieve sealing of the conductive bumps 110 .

[0173] It should be noted that in the actual process, when a buried power rail (BPR) structure and a power delivery network (PDN) structure are used, higher requirements are placed on chip size and integration, and this embodiment is particularly applicable.

[0174] In this embodiment, the aforementioned conductive bump 110 is used as the first conductive bump 110, and the packaging method further includes: forming a second conductive bump 120 on the surface of the substrate 100 facing away from the bonding surface 100a, and the second conductive bump 120 is used to realize the electrical connection between the packaging structure and the external circuit.

[0175] The second conductive bumps 120 are used to realize electrical connection between the package structure and the external circuit, thereby realizing electrical connection between the device chip 200 and the interconnection chip 300 and the external circuit.

[0176] In this embodiment, the material of the second conductive bump 120 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 120 is tin.

[0177] For example, the second conductive bump 120 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same second conductive bump 120 spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces the size and weight.

[0178] In other embodiments, the second conductive bump may also be a ball grid array (BGA) structure.

[0179] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: a substrate, including a bonding surface; An interconnect chip, bonded to the bonding surface of the substrate and electrically connected to the substrate; A device chip, comprising a first surface and a second surface opposite to each other, the first surface and the second surface being electrically connected to each other, the first surface being bonded to the interconnection chip and electrically connected to the interconnection chip; The base layer is bonded to the second surface of the device chip.

2. The packaging structure according to claim 1, characterized in that: The first surface is the front side of the chip, and the second surface is the back side of the chip.

3. The packaging structure according to claim 1, characterized in that: The device chip comprises a backside interconnection layer located on one side of the second surface, the backside interconnection layer is electrically connected to the interconnection chip, and the backside interconnection layer is also electrically connected to the device of the device chip.

4. The packaging structure according to claim 3, characterized in that: The device chip further comprises a substrate, and a device layer located on the substrate, wherein the device layer is located on a side of the substrate facing the interconnection chip; The backside interconnection layer is located on a side of the substrate facing the substrate layer.

5. The packaging structure according to claim 3, characterized in that: A first interconnection structure located on one side of the first surface is formed in the device chip, and a backside interconnection layer of the device chip is electrically connected to the interconnection chip through the first interconnection structure.

6. The packaging structure according to any one of claims 5, characterized in that: A second interconnection structure penetrating the interconnection chip is formed in the interconnection chip, the second interconnection structure is electrically connected to the first interconnection structure, and the second interconnection structure is also electrically connected to the substrate.

7. The packaging structure according to claim 6, characterized in that: The first interconnect structure includes a first bonding pad exposed by the first surface, and the second interconnect structure includes a second bonding pad located on a side facing away from the bonding surface and exposed by the interconnect chip, wherein the first bonding pad and the second bonding pad are bonded to each other.

8. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a bonding medium layer, which is located between the device chip and the base layer, and the device chip and the base layer are bonded via the bonding medium layer.

9. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a conductive bump located between the interconnection chip and the substrate and electrically connecting the interconnection chip and the substrate.

10. The packaging structure according to claim 9, characterized in that: The packaging structure further includes a sealing layer, which fills the gaps between adjacent conductive bumps and covers the conductive bumps.

11. A packaging method, characterized in that: include: Providing interconnect chips; Providing a device chip, comprising a first surface and a second surface opposite to each other; Bonding the first surface of the device chip to the interconnection chip, the first surface being electrically connected to the interconnection chip, and the first surface and the second surface being electrically connected to each other; Provides a base layer; bonding the base layer to the second surface of the device chip; providing a substrate, including a bonding surface; After the base layer is bonded to the second surface of the device chip, the interconnection chip is bonded to the bonding surface of the substrate and electrically connected to the substrate.

12. The packaging method according to claim 11, characterized in that: In the step of providing the device chip, the first surface is the front side of the chip, and the second surface is the back side of the chip.

13. The packaging method according to claim 11, characterized in that: The step of bonding the first side of the device chip to the interconnect chip includes: providing a carrier substrate; bonding the interconnection chip to the carrier substrate; After bonding the interconnection chip to the carrier substrate, bonding the device chip to the interconnection chip; After bonding the base layer to the second surface of the device chip and before bonding the interconnection chip to the bonding surface of the substrate, the packaging method further includes: removing the carrier substrate.

14. The packaging method according to claim 13, characterized in that: The step of bonding the device chip to the interconnect chip further includes: bonding the first surface of the device chip to the interconnect chip with the first surface facing the interconnect chip; Performing a backside thinning process on the device chip through the second surface; After the backside thinning process is performed, a backside interconnection layer is formed on the second side, the backside interconnection layer is electrically connected to the device of the device chip, and the backside interconnection layer is also electrically connected to the interconnection chip.

15. The packaging method according to claim 14, characterized in that: In the step of providing the device chip, the device chip comprises a substrate and a device layer located on the substrate, wherein the device layer is located on a surface of the substrate facing the first surface; In the step of performing backside thinning on the device chip through the second surface, a portion of the thickness of the substrate is removed; In the step of forming a backside interconnection layer on the second surface, the backside interconnection layer is formed on the substrate, and the backside interconnection layer is located on a surface of the substrate facing the second surface.

16. The packaging method according to claim 15, characterized in that: In the step of providing the device chip, a first interconnect structure located on one side of the first surface is formed in the device chip; In the step of forming a backside interconnection layer on the second surface, the backside interconnection layer of the device chip is electrically connected to the interconnection chip through the first interconnection structure.

17. The packaging method according to claim 15, characterized in that: In the step of providing the interconnection chip, a sub-interconnection structure is formed in the interconnection chip; After bonding the interconnection chip to the carrier substrate and before bonding the device chip to the interconnection chip, the method further includes: forming a second bonding pad electrically connected to the sub-interconnection structure on an exposed surface of the interconnection chip, wherein the second bonding pad and the sub-interconnection structure constitute a second interconnection structure penetrating the interconnection chip; In the step of bonding the device chip to the interconnect chip, the second interconnect structure is electrically connected to the first interconnect structure; In the step of bonding the interconnect chip to the bonding surface of the substrate, the second interconnect structure is electrically connected to the substrate.

18. The packaging method according to claim 17, characterized in that: In the step of providing the device chip, the first interconnect structure includes a first bonding pad exposed by the first surface; In the step of bonding the device chip to the interconnect chip, the first bonding pad is bonded to the second bonding pad.

19. The packaging method according to claim 11, characterized in that: The step of bonding the interconnection chip to the bonding surface of the substrate includes: forming conductive bumps on the surface of the interconnection chip facing the substrate, or on the surface of the bonding surface; The interconnection chip and the substrate are bonded by using the conductive bumps, and the conductive bumps electrically connect the interconnection chip and the substrate.

20. The packaging method according to claim 19, characterized in that: After bonding the interconnection chip to the bonding surface of the substrate, the packaging method further comprises: filling a sealing layer in the gaps between adjacent conductive bumps, wherein the sealing layer covers the conductive bumps.

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