Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the packaging structure comprises a substrate which comprises a bonding surface; the interconnection chip is bonded on the bonding surface of the substrate, the interconnection chip comprises a first chip front surface and a first chip back surface which are opposite to each other, and the first chip back surface faces the substrate and is electrically connected with the substrate; and the device chip is bonded on the interconnection chip, the device chip comprises a second chip front surface and a second chip back surface which are opposite to each other, the second chip front surface faces the interconnection chip and is electrically connected with the interconnection chip, and the second chip back surface is electrically connected with the interconnection chip through the second chip front surface. According to the invention, the second chip front surface and the second chip back surface, which are opposite to each other, of the device chip can be electrically connected with the substrate, and correspondingly, a scheme that the device chip supplies power through any one surface or two surfaces of the second chip front surface and the second chip back surface can be realized through the substrate.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a packaging structure and a packaging method. Background Art

[0002] Conventional chip manufacturing technologies are being pushed to their limits in terms of the size of a single chip. However, applications are eager to use the latest technology to achieve the capabilities of large-scale integrated circuits, and achieving high-speed and small-volume interconnections between chips is a major challenge.

[0003] One current solution is to use a smaller integrated circuit of a silicon bridge (Si Bridge) chip embedded in a silicon substrate to interconnect chips through the silicon bridge chip, thereby providing a heterogeneous chip package.

[0004] However, the current packaging structure is relatively complex, and the integration level between chips still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, so as to realize a solution that a device chip is powered through any one or both sides of the front side of a second chip and the back side of the second chip.

[0006] To solve the above problems, the present invention provides a packaging structure, including: a substrate, including a bonding surface; an interconnection chip bonded to the bonding surface of the substrate, the interconnection chip including a first chip front side and a first chip back side opposite to each other, the back side of the first chip faces the substrate and is electrically connected to the substrate; a device chip bonded to the interconnection chip, the device chip including a second chip front side and a second chip back side opposite to each other, the second chip front side faces the interconnection chip and is electrically connected to the interconnection chip, and the back side of the second chip is electrically connected to the interconnection chip via the second chip front side.

[0007] Optionally, the device of the device chip is electrically connected to the back side of the second chip so as to supply power through the back side of the second chip.

[0008] Optionally, the device chip includes a backside interconnection layer located on the back side of the second chip, the backside interconnection layer is electrically connected to the interconnection chip, and the backside interconnection layer is also electrically connected to the device of the device chip.

[0009] Optionally, a first interconnection structure located on the front side of the second chip is formed in the device chip, and the backside interconnection layer of the device chip is electrically connected to the interconnection chip through the first interconnection structure.

[0010] Optionally, a first interconnection structure located on the front side of the second chip is formed in the device chip, a second interconnection structure penetrating the interconnection chip is formed in the interconnection chip, the second interconnection structure is electrically connected to the first interconnection structure, and the second interconnection structure is also electrically connected to the substrate.

[0011] Optionally, the packaging structure further includes: an interconnect pad, located on the back side of the first chip and electrically connected to the second interconnect structure.

[0012] Optionally, a first interconnection structure located on the front side of the second chip is formed in the device chip, the first interconnection structure includes a first bonding pad exposed by the front side of the second chip, a second interconnection structure penetrating the interconnection chip is formed in the interconnection chip, the second interconnection structure includes a second bonding pad exposed by the front side of the first chip, and the first bonding pad and the second bonding pad are bonded to each other.

[0013] Optionally, the packaging structure further includes: a carrier plate bonded to the back side of the second chip of the device chip

[0014] Optionally, the packaging structure further includes: a bonding dielectric layer, located between the device chip and the carrier board, and the device chip and the carrier board are bonded via the bonding dielectric layer.

[0015] Optionally, the packaging structure further includes: a conductive bump, which is located between the interconnection chip and the substrate and electrically connects the interconnection chip and the substrate.

[0016] Optionally, the packaging structure further includes: a sealing layer filling the gaps between adjacent conductive bumps and covering the conductive bumps.

[0017] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing an interconnection chip, including a first chip front side and a first chip back side opposite to each other; providing a device chip, including a second chip front side and a second chip back side opposite to each other; bonding the device chip to the interconnection chip, with the second chip front side facing the first chip front side and electrically connected to each other, and the second chip back side electrically connected to the interconnection chip via the second chip front side; providing a substrate, including a bonding surface; bonding the interconnection chip to the bonding surface of the substrate, with the first chip back side facing the substrate and electrically connected to the substrate.

[0018] Optionally, in the step of electrically connecting the back side of the second chip to the interconnection chip via the front side of the second chip, the devices of the device chip are electrically connected to the back side of the second chip for supplying power to the devices of the device chip via the back side of the second chip.

[0019] Optionally, the step of electrically connecting the back side of the second chip to the interconnection chip via the front side of the second chip includes: after bonding the front side of the second chip of the device chip to the front side of the first chip of the interconnection chip, performing back thinning on the device chip through the back side of the second chip; after the back thinning, forming a back interconnection layer on the back side of the second chip, the back interconnection layer being electrically connected to the device of the device chip, and the back interconnection layer being also electrically connected to the interconnection chip.

[0020] Optionally, in the step of providing a device chip, a first interconnection structure located on the front side of the second chip is formed in the device chip; in the step of bonding the front side of the second chip of the device chip to the front side of the first chip of the interconnection chip, the first interconnection structure is electrically connected to the interconnection chip; in the step of forming a back interconnection layer on the back side of the second chip, the back interconnection layer is electrically connected to the first interconnection structure.

[0021] Optionally, in the step of providing an interconnection chip, a second interconnection structure is formed in the interconnection chip, and the second interconnection structure extends from the front side of the first chip to the back side of the first chip; in the step of providing a device chip, a first interconnection structure located on the front side of the second chip is formed in the device chip; in the step of bonding the front side of the second chip of the device chip to the front side of the first chip of the interconnection chip, the second interconnection structure is electrically connected to the first interconnection structure; in the step of bonding the interconnection chip to the bonding surface of the substrate, the second interconnection structure is electrically connected to the substrate.

[0022] Optionally, before bonding the interconnection chip to the bonding surface of the substrate, the packaging method further includes: forming an interconnection pad electrically connected to the second interconnection structure on the back side of the first chip.

[0023] Optionally, the step of forming an interconnect pad electrically connected to the internal interconnect structure on the back side of the first chip includes: performing back side thinning on the back side of the first chip to expose the second interconnect structure; and forming an interconnect pad on the surface of the exposed second interconnect structure.

[0024] Optionally, after the device chip is bonded to the interconnection chip and the back side of the second chip is electrically connected to the interconnection chip via the front side of the second chip, and before an interconnection pad electrically connected to the internal interconnection structure is formed on the back side of the first chip, the packaging method further includes: providing a carrier board; and bonding the carrier board to the back side of the second chip of the device chip.

[0025] Optionally, in the step of providing a device chip, a first interconnection structure located on the front side of the second chip is formed in the device chip, and the first interconnection structure includes a first bonding pad exposed by the front side of the second chip; in the step of providing an interconnection chip, a second interconnection structure is formed in the interconnection chip, and the internal interconnection structure extends from the front side of the first chip to the back side of the first chip, and the second interconnection structure includes a second bonding pad exposed by the front side of the first chip; in the step of bonding the front side of the second chip of the device chip to the front side of the first chip of the interconnection chip, the first bonding pad and the second bonding pad are bonded to each other.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] An embodiment of the present invention provides a packaging structure, wherein an interconnection chip is bonded to a bonding surface of a substrate, the interconnection chip comprises a first chip front side and a first chip back side opposite to each other, the back side of the first chip faces the substrate and is electrically connected to the substrate, a device chip is bonded to the interconnection chip, the device chip comprises a second chip front side and a second chip back side opposite to each other, the second chip front side faces the interconnection chip and is electrically connected to the interconnection chip, and the back side of the second chip is electrically connected to the interconnection chip via the second chip front side; in an embodiment of the present invention, the interconnection chip is bonded to the substrate to realize electrical connection between the interconnection chip and the substrate, the second chip front side of the device chip is bonded to the interconnection chip to realize electrical connection between the second chip front side of the device chip and the interconnection chip The electrical connection of the second chip of the device chip and the substrate is realized accordingly, and the back side of the second chip is electrically connected to the interconnection chip via the front side of the second chip, and the electrical connection of the back side of the second chip of the device chip and the substrate is realized accordingly, so that the front side of the second chip and the back side of the second chip opposite to each other of the device chip are both electrically connected to the substrate, and the device chip can be powered by either or both sides of the front side of the second chip and the back side of the second chip through the substrate, thereby improving the integration of the packaging structure. At the same time, the front side of the second chip and the front side of the first chip are relatively electrically connected to the device chip and the interconnection chip, so that the bonding of the device chip and the interconnection chip is easy to realize and the electrical connection line is simple.

[0028] An embodiment of the present invention provides a packaging method, providing an interconnection chip, including a first chip front side and a first chip back side opposite to each other; providing a device chip, including a second chip front side and a second chip back side opposite to each other, bonding the device chip to the interconnection chip, with the second chip front side facing the first chip front side and electrically connected to each other, and the second chip back side electrically connected to the interconnection chip via the second chip front side, providing a substrate, including a bonding surface, bonding the interconnection chip to the bonding surface of the substrate, with the back side of the first chip facing the substrate and electrically connected to the substrate; in an embodiment of the present invention, the interconnection chip is bonded to the substrate to realize the electrical connection between the interconnection chip and the substrate, and the second chip front side of the device chip is bonded to the interconnection chip to realize the device chip The front side of the second chip is electrically connected to the interconnection chip, thereby realizing the electrical connection between the front side of the second chip of the device chip and the substrate. The back side of the second chip is electrically connected to the interconnection chip via the front side of the second chip, thereby realizing the electrical connection between the back side of the second chip of the device chip and the substrate. Thus, the front side of the second chip and the back side of the second chip opposite to each other are both electrically connected to the substrate, thereby realizing the solution of powering the device chip through either or both sides of the front side of the second chip and the back side of the second chip through the substrate, thereby improving the integration of the packaging structure. At the same time, the front side of the second chip and the front side of the first chip relatively realize the electrical connection between the device chip and the interconnection chip, thereby making it easy to realize the bonding between the device chip and the interconnection chip and the electrical connection line is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;

[0030] Figures 2 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION

[0031] As can be seen from the background technology, usually only the front side of the chip is electrically connected to the outside of the two back sides of the chip. At present, the back side power delivery network (BSPDN) technology is developed, that is, an interconnection pad will also be formed on the back side of the chip for electrical connection with the outside, for example, as described in document 10.1109 / TED.2019.2954301. However, there is currently no method to electrically lead out the back side of the chip to achieve electrical connection between the front and back sides of the chip, making it difficult to improve the packaging integration.

[0032] In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, including: a substrate, including a bonding surface; an interconnection chip bonded to the bonding surface of the substrate, the interconnection chip including a first chip front side and a first chip back side opposite to each other, the first chip back side faces the substrate and is electrically connected to the substrate; a device chip bonded to the interconnection chip, the device chip including a second chip front side and a second chip back side opposite to each other, the second chip front side faces the interconnection chip and is electrically connected to the interconnection chip, and the second chip back side is electrically connected to the interconnection chip via the second chip front side.

[0033] In the embodiment of the present invention, the interconnection chip is bonded to the substrate to realize the electrical connection between the interconnection chip and the substrate, the front side of the second chip of the device chip is bonded to the interconnection chip to realize the electrical connection between the front side of the second chip of the device chip and the interconnection chip, and accordingly realize the electrical connection between the front side of the second chip of the device chip and the substrate, the back side of the second chip is electrically connected to the interconnection chip via the front side of the second chip, and accordingly realize the electrical connection between the back side of the second chip of the device chip and the substrate, so that the front side of the second chip and the back side of the second chip opposite to each other can be electrically connected to the substrate, and accordingly the device chip can be powered by any one side or both sides of the front side of the second chip and the back side of the second chip through the substrate, thereby improving the integration of the packaging structure, and at the same time, the front side of the second chip and the front side of the first chip relatively realize the electrical connection between the device chip and the interconnection chip, so that the bonding between the device chip and the interconnection chip is easy to realize and the electrical connection line is simple.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention.

[0036] The packaging structure includes: a substrate 100, including a bonding surface 100a; an interconnection chip 300, bonded to the bonding surface 100a of the substrate 100, the interconnection chip 300 includes a first chip front side 300a and a first chip back side 300b opposite to each other, the first chip back side 300b faces the substrate 100 and is electrically connected to the substrate 100; a device chip 200, bonded to the interconnection chip 300, the device chip 200 includes a second chip front side 200a and a second chip back side 200b opposite to each other, the second chip front side 200a faces the interconnection chip 300 and is electrically connected to the interconnection chip 300, and the second chip back side 200b is electrically connected to the interconnection chip 300 via the second chip front side 200a.

[0037] The substrate 100 is used to provide a process operation basis for bonding the interconnected chip 300 . Specifically, the bonding surface 100 a of the substrate 100 is a process operation platform.

[0038] In this embodiment, the substrate 100 includes an interconnection structure layer, and the exposed surface of the interconnection structure layer is a bonding surface 100a.

[0039] The interconnection structure layer is used to achieve bonding with the interconnection chip 300, thereby achieving electrical connection with the interconnection chip 300. The interconnection structure layer is also used to achieve electrical connection between the interconnection chip 300 and the outside.

[0040] In this embodiment, the interconnection structure layer is a redistribution structure. Specifically, the redistribution structure may include one or more redistribution layers. In this embodiment, the redistribution structure includes multiple redistribution layers as an example for description.

[0041] Specifically, in this embodiment, the substrate 100 is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0042] The device chip 200 is used to be electrically connected to the substrate 100 through the interconnection chip 300, so as to form a corresponding packaging structure to achieve corresponding functions.

[0043] In this embodiment, the second chip front side 200 a faces the interconnection chip 300 and is electrically connected to the interconnection chip 300 , and the second chip back side 200 b is electrically connected to the interconnection chip 300 via the second chip front side 200 a .

[0044] In this embodiment, the interconnection chip 300 is bonded to the substrate 100 to realize the electrical connection between the interconnection chip 300 and the substrate 100, the second chip front side 200a of the device chip 200 is bonded to the interconnection chip 300 to realize the electrical connection between the second chip front side 200a of the device chip 200 and the interconnection chip 300, and the electrical connection between the second chip front side 200a of the device chip 200 and the substrate 100 is realized accordingly, and the second chip back side 200b is electrically connected to the interconnection chip 300 via the second chip front side 200a, and the electrical connection between the second chip back side 200b of the device chip 200 and the substrate 100 is realized accordingly. The device chip 200 is electrically connected to the substrate 100, thereby enabling the front side 200a of the second chip and the back side 200b of the second chip opposite to the device chip 200 to be electrically connected to the substrate 100. Accordingly, the device chip 200 can be powered by either or both sides of the second chip front side 200a and the second chip back side 200b through the substrate 100, thereby improving the integration of the packaging structure. At the same time, the front side 200a of the second chip and the front side 300a of the first chip relatively realize the electrical connection between the device chip 200 and the interconnection chip 300, thereby making it easy to bond the device chip 200 to the interconnection chip 300 and the electrical connection line simple.

[0045] Specifically, in this embodiment, the devices of the device chip 200 are powered through the second chip back side 200 b.

[0046] In this embodiment, the device chip 200 is bonded to the interconnection chip 300, and the power supply to the devices of the device chip 200 is realized through the second chip back side 200b, which is beneficial to simplify the circuit and improve the integration of the packaging structure.

[0047] Specifically, in the present embodiment, power is supplied to the device of the device chip 200 through the back side 200b of the second chip, and signal electrical connections are made to the device of the device chip 200 through the front side 200a of the second chip. Compared with a scheme in which both the power supply line and the signal line are electrically connected from the front side of the second chip of the first device chip, the present scheme is conducive to reducing mutual interference between the power supply line and the signal line, and is conducive to making the power supply line electrically connected through the back side 200b of the second chip have a higher degree of freedom in design and a larger formation space, which is conducive to reducing the resistance of the power supply line, thereby reducing the probability of the voltage drop affecting the working performance of the device due to the excessive resistance of the power supply line, thereby improving the working performance of the device. At the same time, the signal line electrically connected through the front side 200a of the second chip also has a larger formation space, so that the device of the device chip 200 achieves better working performance.

[0048] In this embodiment, the devices of the device chip 200 are electrically connected to the second chip back side 200 b so as to be powered through the second chip back side 200 b.

[0049] Specifically, in the present embodiment, power is supplied to the devices of the device chip 200 through the back side 200b of the second chip, and signal electrical connections are made to the devices of the device chip 200 through the front side 200a of the second chip. Compared with a scheme in which both the power supply line and the signal line are electrically connected from the front side of the second chip of the device chip, the present scheme is conducive to reducing mutual interference between the power supply line and the signal line, and is conducive to making the power supply line electrically connected through the back side 200b of the second chip have a higher degree of freedom in design and a larger formation space, which is conducive to reducing the resistance of the power supply line, thereby reducing the probability of the voltage drop affecting the working performance of the device due to excessive resistance of the power supply line, thereby improving the working performance of the device. At the same time, the signal line electrically connected through the front side 200a of the second chip also has a larger formation space, so that the device of the device chip 200 achieves better working performance.

[0050] In this embodiment, the device chip 200 includes a backside interconnection layer 220 located on the back side 200 b of the second chip. The backside interconnection layer 220 is electrically connected to the interconnection chip 300 and is also electrically connected to the devices of the device chip 200 .

[0051] The backside interconnection layer 220 is used to realize electrical connection between the devices in the device chip 200 and the outside through the second chip backside 200 b . The backside interconnection layer 220 is also used to realize electrical connection between the interconnection chip 300 and the outside.

[0052] It should be noted that, in this embodiment, a through-silicon-via (TSV) structure is used to electrically connect the backside interconnect layer 220 to the device of the device chip 200 , which is beneficial for making electrical transmission more direct and rapid.

[0053] In this embodiment, the device chip 200 further includes a substrate 210 and a device layer 230 located on the substrate 210 . The device layer 230 is located on a side of the substrate 210 facing the interconnection chip 300 .

[0054] The device layer 230 is used to form the devices of the device chip 200. The device layer 230 is located on the side of the substrate 210 facing the interconnection chip 300 (i.e., the surface facing the side of the second chip front 200a), leaving space for forming the back interconnection layer 220 on the other side of the substrate 210, so that the back interconnection layer 220 formed on the other side of the substrate 210 can face the back side 200b of the second chip, thereby realizing back power supply to the devices in the device layer 230.

[0055] Specifically, in this embodiment, in the process of packaging structure, the device chip 200 includes a substrate 210 and a device layer 230 located on the substrate 210, the substrate 210 is located on the back side 200b of the second chip, and the device layer 210 is located on the front side 200a of the second chip, then the substrate 210 can provide a process platform for the formation of the device layer 230, the substrate 210 also provides a process platform for forming a back interconnection layer 220, the substrate 210 is subjected to back thinning treatment, a portion of the thickness of the substrate 210 is removed through the back side 200b of the second chip, and after back thinning, a back interconnection layer 220 is formed on the remaining substrate 210.

[0056] Accordingly, in this embodiment, the backside interconnection layer 220 is located on the side of the substrate 210 facing the carrier board 500 (ie, the side facing the back side 200 b of the second chip).

[0057] In this embodiment, a first interconnect structure 410 located on the second chip front side 200 a is formed in the device chip 200 , and the backside interconnect layer 220 of the device chip 200 is electrically connected to the interconnect chip 300 via the first interconnect structure 410 .

[0058] The first interconnect structure 410 is used to electrically connect with the back interconnect layer 220 to realize electrical connection between the back interconnect layer 220 and the outside. The first interconnect structure 410 is located on the side of the second chip front side 200a. Then, the first interconnect structure 410 can be electrically connected with the interconnect chip 300 through the second chip front side 200a, and accordingly, the back interconnect layer 220 is electrically connected with the interconnect chip 300 through the first interconnect structure 410.

[0059] In this embodiment, the back interconnection layer 220 is electrically connected to the second chip front side 200a of the device chip 200 through the first interconnection structure 410 wiring, and then electrically connected to the substrate 100 through the second chip front side 200a. The wiring through the first interconnection structure 410 is conducive to making the electrical transmission more accurate.

[0060] It should be noted that, in the present embodiment, the first interconnect structure 410 includes a through-silicon-via (TSV) structure, which is beneficial for making electrical transmission more direct and rapid.

[0061] In this embodiment, the material of the first interconnect structure 410 is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0062] The interconnection chip 300 is used to electrically connect with the device chip 200 to realize the basic circuit structure between the interconnection chip 300 and the device chip 200. The interconnection chip 300 is also used to electrically connect with the substrate 100 to realize the electrical connection between the interconnection chip 300 and the outside, and correspondingly realize the electrical connection between the device chip 200 and the outside.

[0063] In the present embodiment, the interconnection chip 300 is bonded to the device chip 200, which increases the total thickness of the structure when the device chip 200 is bonded to the substrate 100, which is beneficial to increase the bonding strength of the device chip 200, thereby facilitating the implementation of a solution for bonding the device chip 200 to the substrate 100 for back-side power supply. At the same time, in the present embodiment, a device is also formed in the interconnection chip 300 to implement electrical connection between the device chip 200 and the interconnection chip 300, which is beneficial to increase the diversity of the circuit structure and improve the applicability of the packaging structure.

[0064] It should be noted that the electrical connection between the device chip 200 and the interconnection chip 300 can form a more complex circuit structure and improve the performance of the packaging structure, such as increasing the data storage capacity of the packaging structure.

[0065] In this embodiment, a second interconnection structure 420 penetrating the interconnection chip 300 is formed in the interconnection chip 300 . The second interconnection structure 420 is electrically connected to the first interconnection structure 410 . The second interconnection structure 420 is also electrically connected to the substrate 100 .

[0066] The second interconnect structure 420 serves as an electrical connection structure. The second interconnect structure 420 is electrically connected to the first interconnect structure 410 to realize the electrical connection between the second interconnect structure 420 and the back interconnect layer 220. The second interconnect structure 420 is also electrically connected to the substrate 100 to realize the electrical connection between the back interconnect layer 220 and the substrate 100, thereby realizing the solution of back-side power supply to the device chip 200 through the back interconnect layer 220.

[0067] In this embodiment, the material of the second interconnect structure 420 is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0068] In this embodiment, the interconnection chip 300 may further include devices, and the devices are electrically connected to the substrate 100, and the devices may also be electrically connected to the devices of the device chip 200, thereby realizing electrical connection between the devices of the interconnection chip 300 and the outside, realizing the basic circuit functions in the interconnection chip 300, and correspondingly realizing the substrate circuit between the devices of the interconnection chip 300 and the devices of the device chip 200.

[0069] In this embodiment, the first interconnect structure 410 includes a first bonding pad 411 exposed by the second chip front side 200a, and the second interconnect structure 420 includes a second bonding pad 421 located on the side facing away from the bonding surface 100a and exposed by the interconnect chip 300, and the first bonding pad 411 and the second bonding pad 421 are bonded to each other.

[0070] The first bonding pad 411 and the second bonding pad 421 are used to realize the bonding between the device chip 200 and the interconnection chip 300 , and realize the electrical connection between the first interconnection structure 410 and the second interconnection structure 420 .

[0071] In this embodiment, the packaging structure further includes: an interconnection pad 430 , which is located on the back side 300 b of the first chip and is electrically connected to the second interconnection structure 420 .

[0072] The interconnection pad 430 is used to achieve bonding between the interconnection chip 300 and the substrate 100 , and to achieve electrical connection between the interconnection chip 300 and the substrate 100 .

[0073] In other embodiments, the second interconnect structure may penetrate the interconnect chip, and the second interconnect structure includes an interconnect pad exposed by the back side of the first chip.

[0074] In this embodiment, the mounting structure further includes: a carrier plate 500 bonded to the second chip back side 200 b of the device chip 200 .

[0075] The carrier plate 500 is used to protect the second chip back side 200 b of the device chip 200 , and is also used to reinforce the device chip 200 , so as to facilitate bonding the device chip 200 and the interconnection chip 300 to the substrate 100 .

[0076] In this embodiment, a carrier board 500 is bonded to the back side 200b of the second chip of the device chip 200, which is beneficial to reinforcing the device chip and improving the mechanical strength, making the device chip 200 easy to bond, thereby facilitating the device chip 200 to be powered through either or both sides of the second chip front side 200a and the second chip back side 200b through the substrate 100.

[0077] In this embodiment, the carrier plate 500 is a light sheet wafer.

[0078] In this embodiment, the packaging structure further includes: a bonding dielectric layer 510 , which is located between the device chip 200 and the carrier board 500 , and the device chip 200 and the carrier board 500 are bonded via the bonding dielectric layer 510 .

[0079] The bonding dielectric layer 510 is used to achieve bonding between the device chip 200 and the carrier board 500 , which is beneficial to enhancing the bonding effect.

[0080] In this embodiment, the packaging structure further includes: a conductive bump 110 , which is located between the interconnection chip 300 and the substrate 100 and electrically connects the interconnection chip 300 and the substrate 100 .

[0081] The conductive bumps 110 are used to realize electrical connection between the substrate 100 and the interconnection chip 300 .

[0082] In this embodiment, the material of the conductive bump 110 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the conductive bump 110 is tin.

[0083] For example, the conductive bump 110 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the same first conductive bump spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0084] In other embodiments, the conductive bump may also be a micro bump (uBump).

[0085] In this embodiment, the packaging structure further includes: a sealing layer 130 filling the gaps between adjacent conductive bumps 110 and covering the conductive bumps 110 .

[0086] The sealing layer 130 is used to achieve sealing between the device chip 200 and the substrate 100 , and to achieve sealing between the interconnection chip 300 and the substrate 100 , and is also used to achieve sealing of the conductive bumps 110 .

[0087] It should be noted that in the actual process, when a buried power rail (BPR) structure and a power delivery network (PDN) structure are used, higher requirements are placed on chip size and integration, and this embodiment is particularly applicable.

[0088] In this embodiment, the aforementioned conductive bump 110 is a first conductive bump 110, and the packaging structure further includes: a second conductive bump 120, located on the surface of the substrate 100 facing away from the bonding surface 100a, and the second conductive bump 120 is used to realize the electrical connection between the packaging structure and the external circuit.

[0089] The second conductive bumps 120 are used to realize electrical connection between the package structure and the external circuit, thereby realizing electrical connection between the device chip 200 and the interconnection chip 300 and the external circuit.

[0090] In this embodiment, the material of the second conductive bump 120 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 120 is tin.

[0091] For example, the second conductive bump 120 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same second conductive bump 120 spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces the size and weight.

[0092] In other embodiments, the second conductive bump may also be a ball grid array (BGA) structure.

[0093] Figures 2 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention.

[0094] refer to Figure 2 , providing a device chip 200, including a second chip front side 200a and a second chip back side 200b opposite to each other.

[0095] The device chip 200 is used for subsequent electrical connection with the substrate to form a corresponding packaging structure to achieve corresponding functions, wherein the second chip front side 200a and the second chip back side 200b are both used for subsequent electrical connection with the outside.

[0096] Subsequently, the devices of the device chip 200 are powered through the second chip back side 200 b , ie, the chip back side.

[0097] In this embodiment, in the step of providing the device chip 200, the device chip 200 includes a substrate 210 and a device layer 230 located on the substrate 210. The substrate 210 is located on the back side 200b of the second chip, and the device layer 230 is located on the front side 200a of the second chip.

[0098] The substrate 210 is used to provide a process platform for forming the device layer 230 , and is also used to provide a process platform for subsequently forming a backside interconnection layer.

[0099] In this embodiment, the substrate 210 is located on the back side 200b of the second chip, and the device layer 230 is located on the front side 200a of the second chip. The substrate 210 is located on the back side 200b of the second chip, leaving space for forming a back interconnection layer, so that the subsequently formed back interconnection layer is located on the surface of the substrate 210 facing the back side 200b of the second chip.

[0100] In this embodiment, in the step of providing the device chip 200 , a first interconnection structure 410 located on a side of the second chip front side 200 a is formed in the device chip 200 .

[0101] The backside interconnection layer of the subsequent device chip 200 is electrically connected to the interconnection chip 300 through the first interconnection structure 410 .

[0102] The first interconnect structure 410 is used to subsequently electrically connect with the back interconnect layer to realize electrical connection between the back interconnect layer and the outside. The first interconnect structure 410 is located on the side of the second chip front side 200a. Then, the first interconnect structure 410 can subsequently be electrically connected to the substrate through the second chip front side 200a, and accordingly, the back interconnect layer is electrically connected to the substrate through the first interconnect structure 410.

[0103] It should be noted that, in the present embodiment, the first interconnect structure 410 includes a through-silicon-via (TSV) structure, which is beneficial for making electrical transmission more direct and rapid.

[0104] In this embodiment, the material of the first interconnect structure 410 is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0105] In this embodiment, in the step of providing the device chip 200 , the first interconnect structure 410 includes a first bonding pad 411 exposed by the second chip front side 200 a .

[0106] The first bonding pad 411 is used to subsequently bond the device chip 200 to the interconnection chip 300 with the second bonding pad 421 , and is also used to subsequently electrically connect the first interconnection structure 410 to the second interconnection structure 420 .

[0107] refer to Figure 3 , an interconnection chip 300 is provided, including a first chip front side 300a and a first chip back side 300b facing each other.

[0108] The interconnection chip 300 is used to be subsequently bonded with the device chip 200 to achieve electrical connection with the device chip 200 , and correspondingly achieve electrical connection with the substrate through the device chip 200 .

[0109] In this embodiment, in the step of providing the interconnection chip 300 , a second interconnection structure 420 is formed in the interconnection chip 300 , and the second interconnection structure 420 extends from the first chip front side 300 a to the first chip back side 300 b .

[0110] The second interconnect structure 420 is used to subsequently realize electrical connection between the device chip 200 and the substrate.

[0111] In this embodiment, the material of the second interconnect structure 420 is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0112] In this embodiment, in the step of providing the interconnect chip 300 , the second interconnect structure 420 includes a second bonding pad 421 exposed by the first chip front side 300 a .

[0113] The second bonding pad 421 is used to subsequently bond the device chip 200 and the interconnection chip 300 with the first bonding pad 411 , and is also used to subsequently electrically connect the first interconnection structure 410 and the second interconnection structure 420 .

[0114] Combined with reference Figures 4 to 6 , the device chip 200 is bonded to the interconnection chip 300, the second chip front side 200a is opposite to the first chip front side 300a and is electrically connected to each other, and the second chip back side 200b is electrically connected to the interconnection chip 300 via the second chip front side 200a.

[0115] The interconnection chip 300 is electrically connected to the device chip 200 to realize the basic circuit structure between the interconnection chip 300 and the device chip 200. Subsequently, the interconnection chip 300 is also used to be electrically connected to the substrate to realize the electrical connection between the interconnection chip 300 and the outside.

[0116] In this embodiment, the subsequent interconnection chip 300 is bonded to the substrate to realize the electrical connection between the interconnection chip 300 and the substrate, the second chip front side 200a of the device chip 200 is bonded to the interconnection chip 300 to realize the electrical connection between the second chip front side 200a of the device chip 200 and the interconnection chip 300, and the electrical connection between the second chip front side 200a of the device chip 200 and the substrate is realized accordingly, and the second chip back side 200b is electrically connected to the interconnection chip 300 via the second chip front side 200a, and the electrical connection between the second chip back side 200b of the device chip 200 and the substrate is realized accordingly. The device chip 200 is connected by the second chip front side 200a and the second chip back side 200b opposite to each other, thereby being electrically connected to the substrate. Accordingly, the device chip 200 can be powered by either or both sides of the second chip front side 200a and the second chip back side 200b through the substrate, thereby improving the integration of the packaging structure. Meanwhile, the second chip front side 200a and the first chip front side 300a relatively realize the electrical connection between the device chip 200 and the interconnection chip 300, thereby making it easy to bond the device chip 200 to the interconnection chip 300 and the electrical connection line simple.

[0117] In this embodiment, in the step of electrically connecting the second chip back side 200b to the interconnection chip 300 via the second chip front side 200a, the devices of the device chip 200 are electrically connected to the second chip back side 200b to supply power through the second chip back side 200b.

[0118] In this embodiment, the device chip 200 is bonded to the interconnection chip 300, and the power supply to the devices of the device chip 200 is realized through the second chip back side 200b, which is beneficial to simplify the circuit and improve the integration of the packaging structure.

[0119] Specifically, in the present embodiment, power is supplied to the device of the device chip 200 through the back side 200b of the second chip, and signal electrical connections are made to the device of the device chip 200 through the front side 200a of the second chip. Compared with a scheme in which both the power supply line and the signal line are electrically connected from the front side of the second chip of the first device chip, the present scheme is conducive to reducing mutual interference between the power supply line and the signal line, and is conducive to making the power supply line electrically connected through the back side 200b of the second chip have a higher degree of freedom in design and a larger formation space, which is conducive to reducing the resistance of the power supply line, thereby reducing the probability of the voltage drop affecting the working performance of the device due to the excessive resistance of the power supply line, thereby improving the working performance of the device. At the same time, the signal line electrically connected through the front side 200a of the second chip also has a larger formation space, so that the device of the device chip 200 achieves better working performance.

[0120] refer to Figure 4 , the second chip front side 200 a of the device chip 200 is bonded to the first chip front side 300 a of the interconnect chip 300 .

[0121] In this embodiment, in the step of bonding the device chip 200 to the interconnection chip 300 , the first interconnection structure 410 is electrically connected to the interconnection chip 300 .

[0122] The first interconnection structure 410 is electrically connected to the interconnection chip 300 , and the first interconnection structure 410 is subsequently electrically connected to the device of the device chip 200 , so as to realize the electrical connection of the device with the outside through the electrical connection with the interconnection chip 300 .

[0123] In this embodiment, in the step of bonding the device chip 200 to the interconnection chip 300 , the second interconnection structure 420 is electrically connected to the first interconnection structure 410 .

[0124] The second interconnect structure 420 is electrically connected to the first interconnect structure 410, and is used to subsequently realize the electrical connection between the back interconnect layer and the second interconnect structure 420 through the first interconnect structure 410, and correspondingly realize the electrical connection between the back interconnect layer and the substrate, thereby realizing a solution of back-side power supply to the device of the device chip 200 through the back interconnect layer.

[0125] In this embodiment, in the step of bonding the device chip 200 to the interconnection chip 300 , the first bonding pad 411 and the second bonding pad 421 are bonded.

[0126] The first bonding pad 411 and the second bonding pad 421 are used to realize the bonding between the device chip 200 and the interconnection chip 300 , and are also used to realize the electrical connection between the first interconnection structure 410 and the second interconnection structure 420 .

[0127] refer to Figure 5 The step of electrically connecting the second chip back side 200b to the interconnection chip 300 via the second chip front side 200a includes: after bonding the second chip front side 200a of the device chip 200 to the first chip front side 300a of the interconnection chip 300, performing back side thinning on the device chip 200 via the second chip back side 200b.

[0128] The second chip front side 200 a of the device chip 200 is bonded to the interconnection chip 300 with the second chip front side 200 a facing the interconnection chip 300 , exposing the second chip back side 200 b , in preparation for subsequent back side thinning process.

[0129] The interconnection chip 300 is used to provide support for the backside thinning of the device chip 200 .

[0130] In this embodiment, the device chip 200 is subjected to backside thinning processing through the second chip backside 200 b to remove excess material of the substrate 210 .

[0131] A portion of the thickness of the substrate 210 is removed, and the remaining portion of the thickness of the substrate 210 is retained to serve as a process platform for subsequently forming a backside interconnection layer.

[0132] refer to Figure 6 After the back side thinning process is performed, a back side interconnection layer 220 is formed on the back side 200 b of the second chip. The back side interconnection layer 220 is electrically connected to the device of the device chip 200 , and the back side interconnection layer 220 is also electrically connected to the interconnection chip 300 .

[0133] The backside interconnection layer 220 is used to realize electrical connection between the devices in the device chip 200 and the outside through the second chip backside 200 b.

[0134] It should be noted that, in this embodiment, a through-silicon-via (TSV) structure is used to electrically connect the backside interconnect layer 220 to the device of the device chip 200 , which is beneficial for making electrical transmission more direct and rapid.

[0135] In this embodiment, in the step of forming the backside interconnection layer 220 on the backside 200 b of the second chip, the backside interconnection layer 220 is formed on the substrate 210 , and the backside interconnection layer 220 is located on the surface of the substrate 210 facing the backside 200 b of the second chip.

[0136] The backside interconnection layer 220 is located on the surface of the substrate 210 facing the backside 200 b of the second chip, so that the backside interconnection layer 220 is used to subsequently realize a solution of backside power supply to the devices of the device chip 200 .

[0137] In this embodiment, in the step of forming the backside interconnection layer 220 on the backside 200 b of the second chip, the backside interconnection layer 220 is electrically connected to the first interconnection structure 410 .

[0138] The backside interconnect layer 220 is electrically connected to the first interconnect structure 410 , so that the backside interconnect layer 220 is electrically connected to the substrate via the first interconnect structure 410 .

[0139] In this embodiment, the backside interconnection layer 220 is electrically connected to the interconnection chip 300 through the first interconnection structure 410 wiring, and is subsequently electrically connected to the substrate through the interconnection chip 300. The wiring of the first interconnection structure 410 is conducive to more accurate electrical transmission.

[0140] refer to Figure 7 , a bonding dielectric layer 510 is formed on the second chip back side 200 b of the device chip 200 .

[0141] The bonding dielectric layer 510 is used to subsequently bond the device chip 200 to the carrier board.

[0142] refer to Figure 8 After bonding the device chip 200 to the interconnection chip 300 and electrically connecting the second chip back side 200b to the interconnection chip 300 via the second chip front side 200a, and before subsequently forming an interconnection pad electrically connected to the internal interconnection structure on the first chip back side 300b, the packaging method further includes: providing a carrier board 500.

[0143] The carrier plate 500 is used to provide support when conductive bumps are subsequently formed on the interconnection chip 300 , protect the second chip back side 200 b of the device chip 200 , and reinforce the device chip 200 to facilitate bonding the device chip 200 and the interconnection chip 300 to the substrate 100 .

[0144] In this embodiment, the carrier plate 500 is a light sheet wafer.

[0145] refer to Fig. 9 , bonding the carrier plate 500 to the second chip back side 200 b of the device chip 200 .

[0146] In this embodiment, a carrier board 500 is bonded to the back side 200b of the second chip of the device chip 200, which is beneficial to reinforcing the device chip and improving the mechanical strength, making the device chip 200 easy to bond, thereby facilitating the subsequent power supply of the device chip 200 through the substrate through either or both sides of the second chip front side 200a and the second chip back side 200b.

[0147] In this embodiment, in the step of bonding the carrier board 500 to the second chip back side 200 b of the device chip 200 , the bonding medium layer 510 is used to achieve the bonding between the device chip 200 and the carrier board 500 .

[0148] The bonding dielectric layer 510 is used to achieve bonding between the device chip 200 and the carrier board 500 , which is beneficial to enhancing the bonding effect.

[0149] Combined with reference Fig.10 and Fig.11 Before bonding the interconnection chip 300 to the bonding surface of the substrate, the packaging method further includes: forming an interconnection pad 430 electrically connected to the second interconnection structure 420 on the back side 300 b of the first chip.

[0150] The interconnection pad 430 is used to subsequently realize the bonding between the interconnection chip 300 and the substrate, and realize the electrical connection between the interconnection chip 300 and the substrate.

[0151] refer to Fig.10 The step of forming an interconnect pad 430 electrically connected to the second interconnect structure 420 on the back side 300 b of the first chip includes: performing a back side thinning process on the back side 300 b of the first chip to expose the second interconnect structure 420 .

[0152] The back side thinning process is performed on the back side of the first chip 300 b to expose the second interconnection structure 420 , so as to prepare for forming an interconnection pad electrically connected to the second interconnection structure 420 .

[0153] refer to Fig.11 , an interconnect pad 430 is formed on the exposed surface of the second interconnect structure 420 .

[0154] An interconnect pad 430 is formed on the exposed surface of the second interconnect structure 420 to achieve electrical connection between the interconnect pad 430 and the second interconnect structure 420 .

[0155] In other embodiments, the second interconnect structure may penetrate the interconnect chip, and the second interconnect structure includes an interconnect pad exposed by the back side of the first chip.

[0156] refer to Fig.12 , providing a substrate 100 including a bonding surface 100a.

[0157] The substrate 100 is used to provide a process operation basis for realizing the bonding of the device chip 200 . Specifically, the bonding surface 100 a of the substrate 100 is a process operation platform.

[0158] In this embodiment, the substrate 100 includes an interconnection structure layer, and the exposed surface of the interconnection structure layer is a bonding surface 100a.

[0159] The interconnection structure layer is used to subsequently achieve bonding with the device chip 200 , thereby achieving electrical connection with the device chip 200 . The interconnection structure layer is also used to achieve electrical connection between the device chip 200 and the outside.

[0160] In this embodiment, the interconnection structure layer is a redistribution structure. Specifically, the redistribution structure may include one or more redistribution layers. In this embodiment, the redistribution structure includes multiple redistribution layers as an example for description.

[0161] Specifically, in this embodiment, the substrate 100 is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0162] Combined with reference Fig.13 and Fig.14 , the interconnection chip 300 is bonded to the bonding surface 100 a of the substrate 100 , and the back surface 300 b of the first chip faces the substrate 100 and is electrically connected to the substrate 100 .

[0163] After the device chip 200 is bonded to the interconnection chip 300 , the interconnection chip 300 is bonded to the substrate 100 to form a corresponding packaging structure to achieve corresponding functions.

[0164] In this embodiment, in the step of bonding the interconnection chip 300 to the substrate 100 , the second interconnection structure 420 is electrically connected to the substrate 100 .

[0165] The second interconnect structure 420 is electrically connected to the substrate 100 , thereby achieving electrical connection between the first interconnect structure 410 and the substrate 100 , and correspondingly achieving electrical connection between the backside interconnect layer 220 and the substrate 100 .

[0166] In this embodiment, the step of bonding the device chip 200 to the substrate 100 includes: forming a conductive bump 110 on the second chip front side 200 a of the device chip 200 , or on the bonding surface 100 a .

[0167] The conductive bumps 110 are used to realize electrical connection between the substrate 100 and the device chip 200 .

[0168] In this embodiment, the material of the conductive bump 110 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the conductive bump 110 is tin.

[0169] For example, the conductive bump 110 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the same first conductive bump spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0170] In other embodiments, the conductive bump may also be a micro bump (uBump).

[0171] Specifically, refer to Fig.13 As an example, in this embodiment, a conductive bump 110 is formed on the second chip front side 200 a of the device chip 200 .

[0172] refer to Fig.14 The device chip 200 and the substrate 100 are bonded together using the conductive bumps 110 , and the conductive bumps 110 electrically connect the device chip 200 and the substrate 100 .

[0173] Continue to refer Fig.14 After the device chip 200 is bonded to the substrate 100 , the packaging method further includes: filling a sealing layer 130 in the gaps between adjacent conductive bumps 110 , wherein the sealing layer 130 covers the conductive bumps 110 .

[0174] The sealing layer 130 is used to achieve sealing between the device chip 200 and the substrate 100 , and to achieve sealing between the interconnection chip 300 and the substrate 100 , and is also used to achieve sealing of the conductive bumps 110 .

[0175] It should be noted that in the actual process, when a buried power rail (BPR) structure and a power delivery network (PDN) structure are used, higher requirements are placed on chip size and integration, and this embodiment is particularly applicable.

[0176] In this embodiment, the aforementioned conductive bump 110 is used as the first conductive bump 110, and the packaging method further includes: forming a second conductive bump 120 on the surface of the substrate 100 facing away from the bonding surface 100a, and the second conductive bump 120 is used to realize the electrical connection between the packaging structure and the external circuit.

[0177] The second conductive bumps 120 are used to realize electrical connection between the package structure and the external circuit, thereby realizing electrical connection between the device chip 200 and the interconnection chip 300 and the external circuit.

[0178] In this embodiment, the material of the second conductive bump 120 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 120 is tin.

[0179] For example, the second conductive bump 120 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same second conductive bump 120 spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces the size and weight.

[0180] In other embodiments, the second conductive bump may also be a ball grid array (BGA) structure.

[0181] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: a substrate, including a bonding surface; An interconnection chip bonded to the bonding surface of the substrate, the interconnection chip comprising a first chip front side and a first chip back side opposite to each other, the first chip back side facing the substrate and electrically connected to the substrate; A device chip is bonded to the interconnection chip, wherein the device chip includes a second chip front side and a second chip back side opposite to each other, the second chip front side faces the interconnection chip and is electrically connected to the interconnection chip, and the second chip back side is electrically connected to the interconnection chip via the second chip front side.

2. The packaging structure according to claim 1, characterized in that: The devices of the device chip are electrically connected to the back side of the second chip so as to supply power through the back side of the second chip.

3. The packaging structure according to claim 1, characterized in that: The device chip comprises a backside interconnection layer located on the back side of the second chip, the backside interconnection layer is electrically connected to the interconnection chip, and the backside interconnection layer is also electrically connected to the device of the device chip.

4. The packaging structure according to claim 3, characterized in that: A first interconnection structure located on the front side of the second chip is formed in the device chip, and the backside interconnection layer of the device chip is electrically connected to the interconnection chip through the first interconnection structure.

5. The packaging structure according to claim 1, characterized in that: The device chip has a first interconnection structure located on the front side of the second chip, the interconnection chip has a second interconnection structure penetrating the interconnection chip, the second interconnection structure is electrically connected to the first interconnection structure, and the second interconnection structure is also electrically connected to the substrate.

6. The packaging structure according to claim 5, characterized in that: The packaging structure further includes: an interconnect pad, which is located on the back side of the first chip and is electrically connected to the second interconnect structure.

7. The packaging structure according to claim 1, characterized in that: A first interconnection structure located on the front side of the second chip is formed in the device chip, the first interconnection structure includes a first bonding pad exposed by the front side of the second chip, a second interconnection structure penetrating the interconnection chip is formed in the interconnection chip, the second interconnection structure includes a second bonding pad exposed by the front side of the first chip, and the first bonding pad is bonded to the second bonding pad.

8. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a carrier board bonded to the back side of the second chip of the device chip.

9. The packaging structure according to claim 8, characterized in that: The packaging structure further includes: a bonding medium layer, which is located between the device chip and the carrier board, and the device chip and the carrier board are bonded via the bonding medium layer.

10. The packaging structure according to claim 1, wherein: The packaging structure further includes: a conductive bump located between the interconnection chip and the substrate and electrically connecting the interconnection chip and the substrate.

11. The packaging structure according to claim 10, characterized in that: The packaging structure further includes a sealing layer, which fills the gaps between adjacent conductive bumps and covers the conductive bumps.

12. A packaging method, characterized in that: include: Providing an interconnection chip, including a first chip front side and a first chip back side facing each other; Providing a device chip, including a second chip front side and a second chip back side opposite to each other; Bonding the device chip to the interconnection chip, the front side of the second chip is opposite to the front side of the first chip and they are electrically connected to each other, and the back side of the second chip is electrically connected to the interconnection chip via the front side of the second chip; providing a substrate, including a bonding surface; The interconnection chip is bonded to the bonding surface of the substrate, and the back side of the first chip faces the substrate and is electrically connected to the substrate.

13. The packaging method according to claim 12, characterized in that: In the step of electrically connecting the second chip backside to the interconnection chip via the second chip frontside, the devices of the device chip are electrically connected to the second chip backside for supplying power to the devices of the device chip via the second chip backside.

14. The packaging method according to claim 12, characterized in that: The step of electrically connecting the back side of the second chip to the interconnection chip via the front side of the second chip comprises: after bonding the second chip front side of the device chip to the first chip front side of the interconnection chip, performing a back side thinning process on the device chip via the back side of the second chip; After the backside thinning process is performed, a backside interconnection layer is formed on the backside of the second chip, the backside interconnection layer is electrically connected to the devices of the device chip, and the backside interconnection layer is also electrically connected to the interconnection chip.

15. The packaging method according to claim 14, characterized in that: In the step of providing the device chip, a first interconnect structure located on a front side of the second chip is formed in the device chip; In the step of bonding the device chip to the interconnect chip, the first interconnect structure is electrically connected to the interconnect chip; In the step of forming a backside interconnection layer on the backside of the second chip, the backside interconnection layer is electrically connected to the first interconnection structure.

16. The packaging method according to claim 12, characterized in that: In the step of providing the interconnection chip, a second interconnection structure is formed in the interconnection chip, and the second interconnection structure extends from a front side of the first chip to a back side of the first chip; In the step of providing the device chip, a first interconnect structure located on a front side of the second chip is formed in the device chip; In the step of bonding the device chip to the interconnect chip, the second interconnect structure is electrically connected to the first interconnect structure; In the step of bonding the interconnect chip to the bonding surface of the substrate, the second interconnect structure is electrically connected to the substrate.

17. The packaging method according to claim 16, characterized in that: Before bonding the interconnection chip to the bonding surface of the substrate, the packaging method further includes: forming an interconnection pad electrically connected to the second interconnection structure on the back side of the first chip.

18. The packaging method according to claim 17, characterized in that: The step of forming an interconnect pad electrically connected to the internal interconnect structure on the back side of the first chip comprises: performing a back side thinning process on the back side of the first chip so that the second interconnect structure is exposed; An interconnect pad is formed on the exposed surface of the second interconnect structure.

19. The packaging method according to claim 16, characterized in that: After bonding the device chip to the interconnection chip and electrically connecting the back side of the second chip to the interconnection chip via the front side of the second chip, and before forming an interconnection pad electrically connected to the internal interconnection structure on the back side of the first chip, the packaging method further includes: providing a carrier board; bonding the carrier board to the back side of the second chip of the device chip.

20. The packaging method according to claim 12, characterized in that: In the step of providing the device chip, a first interconnect structure located on a front side of the second chip is formed in the device chip, and the first interconnect structure includes a first bonding pad exposed by the front side of the second chip; In the step of providing the interconnection chip, a second interconnection structure is formed in the interconnection chip, the internal interconnection structure extends from a front side of the first chip to a back side of the first chip, and the second interconnection structure includes a second bonding pad exposed by the front side of the first chip; In the step of bonding the device chip to the interconnect chip, the first bonding pad is bonded to the second bonding pad.

Images