Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The semiconductor device comprises at least one dielectric layer, a conductive structure and a first insulator. The at least one dielectric layer includes a stacked structure. The stack structure includes a low dielectric constant dielectric layer, an etch stop layer, and a conductive layer between the low dielectric constant dielectric layer and the etch stop layer. The conductive structure is disposed in the at least one dielectric layer, and the first insulator is disposed between the conductive layer and the conductive structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and in particular to a semiconductor device with a dielectric layer and a method for forming the same. Background Art

[0002] Integrated circuits (ICs) are constructed by forming various active components and the interconnection structure in a substrate or different film layers. Generally speaking, the manufacturing process of the interconnection structure first etches a through hole or a circuit pattern in a dielectric layer, then fills the through hole or the circuit pattern with a conductive material such as copper, and flattens it to complete the manufacturing of the interconnection structure. In the back-end processes of semiconductor devices, the frequent use of plasma makes it easy for excess charges to accumulate on the conductive material filled in the through hole or the circuit pattern. The accumulation of excess charges often forms a current and enters the circuit from the conductive material, penetrates the gate dielectric layer (gateoxide), or derives a threshold voltage shift, causing damage to the components of the front-end manufacturing process, which is a structural defect (plasma induced damage, PID) caused by the antenna effect.

[0003] However, in the advanced semiconductor industry, components are gradually miniaturized and the integration of components is continuously improved. The antenna effect has a significant impact on the operating performance of semiconductor devices. The layout of the circuit needs to take into account the appropriate antenna ratio (Antennaratio, AR), that is, the ratio between the area of ​​the metal wire and the area of ​​the gate dielectric layer. If the antenna ratio is smaller, the impact of the antenna effect is smaller, and the yield and reliability of the semiconductor device can be improved accordingly. However, the limitation of the antenna ratio causes the difficulty and complexity of circuit design and manufacturing process to continue to increase. Therefore, the improvement of the existing technology is a topic that the relevant technical personnel attach great importance to. Summary of the invention

[0004] The present invention aims to provide a semiconductor device and a method for forming the same, wherein a conductive layer is additionally disposed in the middle of a dielectric layer, and an insulator is additionally disposed between a conductive structure disposed in the dielectric layer and the conductive layer, and the unstable charges accumulated on the conductive structure are guided to the outside through the conductive layer. As a result, the semiconductor device and the method for forming the same of the present invention are not limited by the antenna ratio (AR2000) of the prior art, and the antenna effect is avoided while increasing the antenna ratio, thereby effectively improving the reliability and yield of the semiconductor device, and thus achieving better operating performance.

[0005] An embodiment of the present invention provides a semiconductor device, comprising at least one dielectric layer, a conductive structure and a first insulator. The at least one dielectric layer comprises a stacked structure. The stacked structure comprises a low-k dielectric layer, an etch stop layer and a conductive layer between the low-k dielectric layer and the etch stop layer. The conductive structure is disposed in the at least one dielectric layer, and the first insulator is disposed between the conductive layer and the conductive structure.

[0006] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising the following steps: forming at least one dielectric layer, the at least one dielectric layer comprising a stacked structure, the stacked structure comprising a low-k dielectric layer, an etch stop layer, and a conductive layer located between the low-k dielectric layer and the etch stop layer; forming a conductive structure in the at least one dielectric layer; and forming a first insulator between the conductive layer and the conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a semiconductor device in a first embodiment of the present invention;

[0008] Figures 2 to 4 Schematic diagram of a method for forming a semiconductor device in a first embodiment of the present invention, wherein:

[0009] Figure 2 is a schematic cross-sectional view of a semiconductor device after forming a stacked structure;

[0010] Figure 3 is a schematic cross-sectional view of a semiconductor device after a through hole is formed; and

[0011] Figure 4 is a schematic cross-sectional view of a semiconductor device after an insulator is formed;

[0012] Figure 5 is a cross-sectional schematic diagram of a semiconductor device in a second embodiment of the present invention;

[0013] Figure 6 is a cross-sectional schematic diagram of a semiconductor device in a third embodiment of the present invention;

[0014] Figure 7 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention;

[0015] Figure 8 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention;

[0016] Fig. 9 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device according to a sixth embodiment of the present invention.

[0017] Explanation of symbols

[0018] 10, 30, 40, 50, 60, 70: Semiconductor devices

[0019] 100: Base

[0020] 102: Shallow Trench Isolation

[0021] 110: Dielectric layer

[0022] 112: Plug

[0023] 120, 720: Dielectric layer

[0024] 122: Etch stop layer

[0025] 124: Conductive layer

[0026] 126: Low dielectric constant dielectric layer

[0027] 128: First Insulator

[0028] 130, 630, 730: Conductive structure

[0029] 140: Gate structure

[0030] 142: Gate dielectric layer

[0031] 144: Gate

[0032] 146: Source / Drain

[0033] 222: Etch stop material layer

[0034] 224: Conductive material layer

[0035] 226: Low dielectric constant dielectric material layer

[0036] 230: Perforation

[0037] 328: Second Insulator

[0038] 328a: Part I

[0039] 328b: Part 2

[0040] 428: First Insulator

[0041] 528: First Insulator

[0042] P1: Insulation processing technology

[0043] R31, R32, R33, R34, R35: Exposed area

[0044] R41, R42, R43, R44, R45: Exposed area

[0045] T1: Thickness DETAILED DESCRIPTION

[0046] In order to enable a person skilled in the art who is familiar with the technical field to which the present invention belongs to further understand the present invention, several preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings. Moreover, without departing from the spirit of the present invention, the technical features of the different embodiments described below can be replaced, reorganized, or mixed with each other to form other embodiments.

[0047] Please refer to Figure 1 , which is a cross-sectional schematic diagram of a semiconductor device 10 in a first embodiment of the present invention. The semiconductor device 10 includes at least one dielectric layer 120, a conductive structure 130, a conductive layer 124, and a first insulator 128. The dielectric layer 120 includes a stacked structure, which includes an etching stop layer 122 and a low-k dielectric layer 126. The conductive structure 130 is disposed in the dielectric layer 120, and includes, for example, various elements made of conductive materials, such as wires, plugs, metal layers or metal wiring layers (redistribution layers, RDL), etc. In this embodiment, the conductive structure 130 has, for example, a dual damascene structure, but is not limited thereto. It should be noted that the conductive layer 124 is disposed in the stacked structure, between the etching stop layer 122 and the low dielectric constant dielectric layer 126, and a first insulator 128 is further disposed between the conductive layer 124 and the conductive structure 130 to electrically isolate the conductive layer 124 and the conductive structure 130, so as to prevent the two from being directly connected and short-circuited. Therefore, by disposing the conductive layer 124 in the middle of the stacked structure of the dielectric layer 120, it is preferred that the conductive layer 124 is not directly disposed on the top surface or the bottom surface of the dielectric layer 120, so as to disperse or guide the unstable charges accumulated on the conductive structure 130 to the outside or to the ground through the conductive layer 124, thereby reducing the chance of structural damage to the semiconductor device 10 caused by plasma in the back-end manufacturing process, thereby avoiding the occurrence of an antenna effect.

[0048] In one embodiment, the conductive layer 124 includes, for example, various suitable conductive materials, such as metal materials such as titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), or tungsten (W), or semiconductor materials such as doped silicon, doped germanium, indium zinc oxide, or indium gallium zinc oxide, but not limited thereto; and the first insulator 128 includes, for example, the conductive material after insulation treatment, such as metal oxides such as titanium dioxide (TiO2), tantalum dioxide (TaO2), aluminum oxide (Al2O3), or copper oxide (CuO), metal nitrides such as aluminum nitride or copper nitride, semiconductor oxides or semiconductor nitrides such as silicon oxide, germanium oxide, silicon nitride, or germanium nitride, but not limited thereto. It should be noted that the thickness T1 of the first insulator 128 in the horizontal direction is preferably between 50 angstroms and 300 angstroms, so as to effectively electrically isolate the conductive layer 124 from the conductive structure 130 without excessively increasing the dielectric constant of the dielectric layer 120. In another embodiment, the low-k dielectric layer 126, for example, includes a dielectric material having a dielectric constant lower than 3, preferably a dielectric material having a dielectric constant between 2.5 and 2.9, such as fluorinated silica glass (FSG), carbon silicon oxide (SiCOH) or spin-on silicon glass (spin-on glass), etc.; and the etch stop layer 122, for example, includes a dielectric material having a dielectric constant greater than the dielectric constant of the low-k dielectric layer 126, such as nitrogen doped silicon carbide (SiCN), etc., but is not limited to this.

[0049] For example Figure 1 As shown, an etching stop layer 122, a conductive layer 124 and a low-k dielectric layer 126 are sequentially stacked on a substrate 100 from bottom to top. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate (such as silicon carbide or silicon germanium), or a silicon-on-insulator substrate, and at least one shallow trench isolation 102 is disposed in the substrate 100 to surround and define a plurality of active areas (not shown) in the substrate 100, but the present invention is not limited thereto. The semiconductor device 10 further includes a dielectric layer 110 and a gate structure 140 disposed between the dielectric layer 120 and the substrate 100. The gate structure 140 is disposed on the substrate 100, and further includes a gate dielectric layer 142 and a gate 144 sequentially stacked on the top surface of the substrate 100, and two source / drain electrodes 146 are disposed in the substrate 100 on both sides of the gate structure 140.

[0050] The dielectric layer 110 covers the gate structure 140 and the substrate 100, and a plug 112 is disposed in the dielectric layer 110 to electrically connect the gate structure 140 below and the conductive structure 130 above. In this configuration, the dielectric layer 110 serves as an interlayer dielectric layer (ILD) of the semiconductor device 10, and the plug 112 in the dielectric layer 110 serves as a contact plug or a zero-layer metal interconnect layer (metal 0, M0) of the semiconductor device 10. In addition, the dielectric layer 120 serves as an intermetal dielectric layer (IMD) of the semiconductor device 10, and the conductive structure 130 in the dielectric layer 120 serves as a first-layer metal interconnect layer (metal1, M1) of the semiconductor device 10. The aforementioned zeroth metal interconnect layer and the first metal interconnect layer are sequentially disposed on the gate structure 140 , so that the gate structure 140 can be electrically connected to other active components and / or passive components through other connecting components in subsequent manufacturing processes, thereby achieving the desired operating performance.

[0051] According to the semiconductor device 10 of the present embodiment, the conductive layer 124 is additionally disposed in the middle of the intermetallic dielectric layer (dielectric layer 120), and the conductive layer 124 is used to disperse or guide the unstable charges that may be accumulated on the metal interconnect layer (conductive structure 130) to the outside or to the ground, thereby reducing the chance of structural damage to the semiconductor device 10 caused by plasma in the semiconductor back-end manufacturing process. As a result, the semiconductor device 10 of the present embodiment can avoid the occurrence of antenna effect, and the antenna ratio of the semiconductor device 10 does not need to be limited by the antenna ratio of the prior art. Therefore, the semiconductor device 10 of the present embodiment has significantly improved component reliability and yield, thereby achieving better operating performance.

[0052] In order to enable a person skilled in the art to which the present invention pertains to easily understand the semiconductor device 10 of the present invention, a method for forming the semiconductor device 10 of the present invention will be further described below.

[0053] Please refer to Figures 2 to 4 FIG. 1 is a schematic diagram of a method for forming a semiconductor device in accordance with a first embodiment of the present invention. Figure 2 As shown, a substrate 100 is provided, a shallow trench isolation 102 is formed in the substrate 100, a gate dielectric layer 142 and a gate 144 are formed on the substrate 100 to form a gate structure 140, and two source / drain electrodes 146 are formed in the substrate 100, respectively located on both sides of the gate structure 140. Next, a dielectric layer 110 is covered on the substrate 100 and the gate structure 140, and a plug 112 is formed in the dielectric layer 110.

[0054] Then, Figure 2 As shown, an etching stop material layer 222, a conductive material layer 224, and a low-k dielectric material layer 226 are sequentially formed on the dielectric layer 110 and the plug 112. In one embodiment, the etching stop material layer 222, for example, includes a dielectric material having a dielectric constant greater than the dielectric constant of the low-k dielectric material layer 226, such as nitrogen-doped carbon, etc. The low-k dielectric material layer 226, for example, includes a dielectric material having a dielectric constant lower than 3, preferably including a dielectric material having a dielectric constant between 2.5 and 2.9, such as fluorinated silicon glass, carbon silicon oxide, or spin-on silicon glass, etc., but not limited thereto. In another embodiment, the conductive material layer 224, for example, includes various suitable conductive materials, such as metal materials such as titanium, tantalum, aluminum, copper, or tungsten, or semiconductor materials such as doped silicon, doped germanium, indium zinc oxide, or indium gallium zinc oxide, but not limited thereto.

[0055] like Figure 3 As shown, an etching process is performed through at least one mask layer (not shown), such as a dry etching process containing plasma. The etching process is performed, for example, by using the etching stop material layer 222 as an etching barrier layer to sequentially etch through the low-k dielectric material layer 226, the conductive material layer 224, and the etching stop material layer 222, and finally forming at least one through hole 230 in the low-k dielectric material layer 226, the conductive material layer 224, and the etching stop material layer 222. In this way, the bottom surface of the through hole 230 partially exposes the top surface of the plug 112, and the sidewall of the through hole 230 partially exposes the low-k dielectric material layer 226, the conductive material layer 224, and the etching stop material layer 222. Then, the mask layer is completely removed.

[0056] like Figure 4 As shown, an insulation processing manufacturing process P1 is performed to insulate the exposed portion of the conductive material layer 224 from the sidewall of the self-piercing hole 230 to form a first insulator 128. It should be particularly noted that the insulation processing manufacturing process P1 includes different steps according to the material selection of the conductive material layer 224. For example, when the conductive material layer 224 includes a metal material such as titanium, tantalum, aluminum, copper or tungsten, the insulation processing manufacturing process P1 includes, for example, an oxidation processing manufacturing process to form a first insulator 128 including a metal oxide such as titanium dioxide, tantalum dioxide, aluminum oxide or copper oxide; or, the insulation processing manufacturing process P1 may also include a nitridation processing process to form a first insulator 128 including a metal nitride such as aluminum nitride or copper nitride, but is not limited thereto. On the other hand, when the conductive material layer 224 includes semiconductor materials such as doped silicon, doped germanium, indium zinc oxide or indium gallium zinc oxide, the insulation processing process P1 includes an oxidation processing process and / or a nitridation processing process to form a first insulator 128 including semiconductor oxides or semiconductor nitrides such as silicon oxide, germanium oxide, silicon nitride, germanium nitride, etc., but is not limited to this.

[0057] Then, at least one deposition process is continued to be performed to fill the through hole 230 with a conductive material (not shown) and further cover the top surface of the low-k dielectric material layer 226. Then, a planarization process is performed to remove the conductive material formed outside the through hole 230, so as to form a Figure 1 The conductive structure 130 shown in FIG. Figure 1 The low-k dielectric layer 126 and the etch stop layer 122 together form the dielectric layer 120 and form the Figure 1 The conductive layer 124 is shown. In one embodiment, the conductive material preferably includes a barrier layer (not shown) conformally covering the surface of the through hole 230 and a metal layer (not shown) filling the through hole 230, but the present invention is not limited thereto.

[0058] Those skilled in the art should be able to easily understand that in order to meet actual needs, the semiconductor device and the method for forming the semiconductor device of the present invention may also have other aspects, not limited to the above. The following will further describe other embodiments or variations of the semiconductor device and the method for forming the semiconductor device of the present invention. In order to simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the same aspects. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0059] Please refer to Figure 5 , which is a cross-sectional schematic diagram of a semiconductor device 30 in a second embodiment of the present invention. The structure of the semiconductor device 30 is substantially the same as the semiconductor device 10 in the first embodiment, and the similarities are not repeated. The main difference between the semiconductor device 30 of this embodiment and the semiconductor device 10 in the first embodiment is that a second insulator 328 is additionally provided.

[0060] Specifically, the second insulator 328 is disposed on the sidewall of the conductive structure 130 and covers the first insulator 128. Figure 5 As shown, the second insulator 328 includes, for example, a first portion 328a disposed on the plug sidewall of the dual damascene structure and a second portion 328b disposed on the conductive line sidewall of the dual damascene structure, and the whole has a discontinuous structure. The second portion 328b of the second insulator 328 directly contacts the first insulator 128 and is disposed between the conductive structure 130 and the first insulator 128, so as to further effectively electrically isolate the conductive layer 124 from the conductive structure 130 without excessively increasing the dielectric constant of the dielectric layer 120.

[0061] In one embodiment, the second insulator 328 includes insulating materials such as silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, and preferably includes insulating materials different from the first insulator, but not limited thereto. The second insulator 328 is formed, for example, by performing a deposition process and an etching back process, but not limited thereto. For example, in forming Figure 4 After the structure shown, an insulating material is uniformly deposited on the surface of the through-hole 230, and then the insulating material covering the horizontal surface of the through-hole 230 is removed by a back-etching process, while the insulating material covering the vertical sidewall of the through-hole 230 is retained to form a second insulator 328 with a discontinuous film layer.

[0062] Under this configuration, the semiconductor device 30 of the present embodiment can also disperse or guide the unstable charges that may be accumulated on the metal interconnect layer (conductive structure 130) to the outside or to the ground through the conductive layer 124 disposed in the middle of the intermetallic dielectric layer (dielectric layer 120), thereby reducing the chance of structural damage to the semiconductor device 30 caused by plasma in the semiconductor back-end manufacturing process. In addition, the semiconductor device 30 of the present embodiment is additionally provided with a second insulator 328. By simultaneously disposing the first insulator 128 and the second insulator 328 between the conductive layer 124 and the conductive structure 130, the conductive layer 124 and the conductive structure 130 are more effectively electrically isolated to avoid direct conduction between the two and a short circuit. As a result, the semiconductor device 30 of the present embodiment can also avoid the occurrence of an antenna effect, and the antenna ratio of the semiconductor device 30 does not need to be limited by the antenna ratio of the prior art, and has significantly improved component reliability and yield.

[0063] Please refer to Figure 6 , which is a cross-sectional schematic diagram of a semiconductor device 40 in a third embodiment of the present invention. The structure of the semiconductor device 40 is substantially the same as that of the semiconductor device 30 in the second embodiment, and the similarities are not repeated. The main difference between the semiconductor device 40 of this embodiment and the semiconductor device 30 in the second embodiment is that the first insulator 428 includes an air gap layer.

[0064] Specifically, the first insulator 428 is formed by, for example, partially removing Figure 3The metal material layer 224 shown forms an air gap (not shown) that shrinks inward from the vertical sidewalls of the through hole 230. Then, a deposition process and an etching back process are performed to form the second insulator 328. At the same time, the second portion 328b of the second insulator 328 is closed but not filled in the air gap, so that the air gap layer is formed to constitute the first insulator 428. In this way, the first insulator 428 including the air gap layer and the second insulator 328 including the insulating material can more effectively electrically isolate the conductive layer 124 and the conductive structure 130 without increasing the dielectric constant of the dielectric layer 120.

[0065] Under this configuration, the semiconductor device 40 of the present embodiment can also disperse or guide the unstable charges that may be accumulated on the metal interconnect layer (conductive structure 130) to the outside or to the ground through the conductive layer 124 disposed in the middle of the intermetallic dielectric layer (dielectric layer 120), thereby reducing the chance of structural damage to the semiconductor device 40 caused by plasma in the semiconductor back-end manufacturing process. In addition, the semiconductor device 40 of the present embodiment is provided with a first insulator 428 including the air gap layer and a second insulator 328 including the insulating material between the conductive layer 124 and the conductive structure 130, so as to more effectively electrically isolate the conductive layer 124 and the conductive structure 130, and avoid the two being directly connected and short-circuited. Therefore, the semiconductor device 40 of the present embodiment can also avoid the occurrence of antenna effect, and the antenna ratio of the semiconductor device 40 does not need to be limited by the antenna ratio of the prior art, and has significantly improved component reliability and yield.

[0066] Please refer to Figure 7 , which is a cross-sectional schematic diagram of a semiconductor device 50 in a fourth embodiment of the present invention. The structure of the semiconductor device 50 is substantially the same as that of the semiconductor device 30 in the second embodiment, and the similarities are not repeated. The main difference between the semiconductor device 50 of this embodiment and the semiconductor device 30 in the second embodiment is that the first insulator 528 and the second insulator 328 include the same insulating material.

[0067] In detail, the first insulator 528 is also formed by partially removing the Figure 3The metal material layer 224 shown forms an air gap (not shown) that shrinks inward from the through hole 230 on both sides. Then, a deposition process and a back-etching process are performed to simultaneously form the first insulator 528 and the second insulator 328. It should be noted that the deposition process of this embodiment is to specially adjust its deposition conditions so that the insulating material fills the air gap to form the first insulator 528, and then further covers the surface of the through hole 320. The second insulator 328 including the first part 328a and the second part 328b is formed through a subsequent back-etching process. Among them, the second part 328b of the second insulator 328 directly contacts the first insulator 528, and the two are integrally formed, such as Figure 7 As shown, the first insulator 528 and the second insulator 328 formed by the same manufacturing process include the same insulating material and can also effectively electrically isolate the conductive layer 124 from the conductive structure 130 without increasing the dielectric constant of the dielectric layer 120 .

[0068] Under this configuration, the semiconductor device 50 of the present embodiment can also disperse or guide the unstable charges that may be accumulated on the metal interconnect layer (conductive structure 130) to the outside or to the ground through the conductive layer 124 disposed in the middle of the intermetallic dielectric layer (dielectric layer 120), thereby reducing the chance of structural damage to the semiconductor device 50 caused by plasma in the semiconductor back-end manufacturing process. In addition, the semiconductor device 50 of the present embodiment is to set a first insulator 528 and a second insulator 328 of the same material between the conductive layer 124 and the conductive structure 130 to electrically isolate the conductive layer 124 and the conductive structure 130, thereby preventing the two from being directly connected and short-circuited. Therefore, the semiconductor device 50 of the present embodiment can also avoid the occurrence of an antenna effect, and the antenna ratio of the semiconductor device 50 does not need to be limited by the antenna ratio of the prior art, and has significantly improved component reliability and yield.

[0069] Please refer to Figure 8 , which is a cross-sectional schematic diagram of a semiconductor device 60 in a fifth embodiment of the present invention. The structure of the semiconductor device 60 is substantially the same as that of the semiconductor device 10 in the first embodiment, and the similarities are not repeated. The main difference between the semiconductor device 60 of this embodiment and the semiconductor device 10 in the first embodiment is that a plurality of dielectric layers 120 are sequentially stacked on the dielectric layer 110, and a conductive structure 630 is respectively disposed in each dielectric layer 120.

[0070] In detail, Figure 8As shown, each dielectric layer 120 includes an etch stop layer 122 and a low dielectric constant dielectric layer 126 stacked in sequence, and each conductive structure 630 includes, for example, various elements made of conductive materials, such as wires, plugs, metal layers or metal wiring layers, but is not limited thereto. It should be noted that a conductive layer 124 is disposed in the middle of each dielectric layer 120, located between the low dielectric constant dielectric layer 126 and the etch stop layer 122, and a first insulator 128 is disposed between the conductive layer 124 in each dielectric layer 120 and each conductive structure 630. Those skilled in the art should easily understand that the specific number of dielectric layers 120 and / or the specific pattern or exposure area of ​​the conductive structure 630 of each layer in this embodiment are only examples, and can be adjusted according to actual component requirements, and are not limited to the above. Figure 8 For example, in another embodiment, one, two or N dielectric layers 120 may be selectively disposed on the first dielectric layer 110, and the exposed areas R31, R32, R33, R34, and R35 of the conductive structures 630 disposed in the one, two or N (N is a positive integer greater than 2) dielectric layers 120 may be different from each other or have various desired patterns. In addition, in another embodiment, each dielectric layer 120 may also be further disposed as follows: Figure 5 The second insulator 328 shown, or Figure 6 The first insulator 428 and the second insulator 328 shown, or Figure 7 The first insulator 528 and the second insulator 328 are shown, but are not limited thereto.

[0071] Under this configuration, the dielectric layer 110 also serves as an interlayer dielectric layer of the semiconductor device 60, and the plug 112 in the dielectric layer 110 serves as a contact plug or a zero-th metal interconnect layer of the semiconductor device 60. The first dielectric layer 120 of each layer serves as an intermetallic dielectric layer of the semiconductor device 60, and the conductive structure 630 in the first dielectric layer 120 of each layer serves as a first metal interconnect layer, a second metal interconnect layer (metal 2, M2), a third metal interconnect layer (metal 3, M3) to an n-th (n is a positive integer greater than 3) metal interconnect layer of the semiconductor device 60. Thus, the semiconductor device 60 of this embodiment can not only neutralize the unstable charges accumulated on the metal interconnect layers (conductive structures 630) of each layer by disposing the conductive layer 124 inside each intermetallic dielectric layer, but also increase the tolerance of the semiconductor device 60 to the antenna effect, thereby more effectively reducing the chance of structural damage to the semiconductor device 60 caused by plasma in the back-end manufacturing process.

[0072] Therefore, the semiconductor device 60 of the present embodiment also has significantly improved component reliability and yield, and is not subject to the limitation of the antenna ratio in the prior art.

[0073] Please refer to Fig. 9 , which is a cross-sectional schematic diagram of a semiconductor device 70 in a sixth embodiment of the present invention. The structure of the semiconductor device 70 is substantially the same as the semiconductor device 10 in the first embodiment, and the similarities are not repeated. The main difference between the semiconductor device 70 of this embodiment and the semiconductor device 10 in the first embodiment is that multiple dielectric layers 120, 720 are disposed on the dielectric layer 110, and conductive structures 630, 730 are disposed in each dielectric layer 120.

[0074] In detail, each dielectric layer 120, 720 includes an etching stop layer 122 and a low dielectric constant dielectric layer 126 stacked in sequence. It should be particularly noted that a conductive layer 124 is additionally provided in at least one dielectric layer 720, preferably in the dielectric layer 720 above the conductive structure 630 having a relatively large exposed area R41. The conductive structures 630, 730 include, for example, various components made of conductive materials, such as wires, plugs, metal layers or metal wiring layers, etc., but are not limited thereto. Among them, the exposed area R41 of the conductive structure 630 is, for example, greater than the exposed areas R42, R43, R44, R45 of other conductive structures 730, but is not limited thereto. Those skilled in the art should be able to easily understand that the specific patterns of the conductive structures 630, 730 in this embodiment or their exposed areas R41, R42, R43, R44, R45, etc. are also only examples, and can be adjusted according to actual component requirements, and are not limited to. Fig. 9 Furthermore, the specific number and / or location of the conductive layers 124 may also be adjusted according to actual device requirements, or, alternatively, the conductive layers 124 and the conductive structures 630 and 730 may be arranged as follows: Figure 5 The second insulator 328 shown in FIG. Figure 6 The first insulator 428 and the second insulator 328 shown, or Figure 7 The first insulator 528 and the second insulator 328 are shown, but are not limited thereto.

[0075] Under this configuration, the dielectric layer 110 also serves as an interlayer dielectric layer of the semiconductor device 70, and the plug 112 in the dielectric layer 110 serves as a contact plug or a zero-th metal interconnect layer of the semiconductor device 70, and each dielectric layer 120, 720 serves as an intermetallic dielectric layer of the semiconductor device 70, so that the conductive structures 630, 730 in each dielectric layer 120, 720 serve as the first metal interconnect layer, the second metal interconnect layer, the third metal interconnect layer to the Nth metal interconnect layer, etc. of the semiconductor device 70 in sequence. In this way, the semiconductor device 70 of the present embodiment can also achieve the effect of dispersing or guiding the unstable charges accumulated on each layer of the metal interconnect layer (conductive structures 630, 730) to the outside or to the ground by setting a conductive layer 124 inside at least one intermetallic dielectric layer (dielectric layer 720), especially setting it inside the intermetallic dielectric layer above the metal interconnect layer with a relatively large exposed area, thereby reducing the chance of structural damage to the semiconductor device 70 caused by plasma in the later stage manufacturing process.

[0076] Therefore, the semiconductor device 70 of the present embodiment also has significantly improved component reliability and yield, and is not subject to the limitation of the antenna ratio in the prior art.

[0077] In general, the semiconductor device and the method for forming the same of the present invention are to set a conductive layer inside at least one intermetallic dielectric layer, and to set at least a first insulator between the conductive layer and the metal interconnect layer, so as to effectively electrically isolate the conductive layer from the metal interconnect layer without increasing the dielectric constant of the intermetallic dielectric layer. In this way, the unstable charges accumulated on the metal interconnect layer can be dispersed or guided to the outside or to the ground through the conductive layer, effectively reducing the chance of structural damage to the semiconductor device caused by plasma in the back-end manufacturing process. Preferably, the conductive layer and the first insulator are arranged in the middle of the intermetallic dielectric layer above the metal interconnect layer with a relatively large exposed area, or are arranged in each intermetallic dielectric layer, thereby achieving the effect of effectively dispersing or guiding the unstable charges accumulated on each metal interconnect layer to the outside or to the ground. Therefore, the semiconductor device of the present invention is not subject to the limitation of the antenna ratio of the prior art, and the antenna effect is avoided while increasing the antenna ratio, effectively improving the reliability and yield of the semiconductor device, and thus achieving better operating performance.

[0078] It should be additionally explained that, although the aforementioned embodiments are described using a semiconductor device having a metal interconnect layer as an implementation example, those skilled in the art should be able to easily understand that the present invention's method of using additional conductive layers and insulators to guide unstable charges can also be applied to the dielectric layers of other semiconductor devices having conductive structures to improve the structural reliability and yield of these semiconductor devices.

[0079] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: at least one dielectric layer, comprising a stacked structure, the stacked structure comprising a low-k dielectric layer and an etch stop layer; A conductive structure disposed in the at least one dielectric layer; A conductive layer, disposed in the stacked structure and between the low-k dielectric layer and the etch stop layer; as well as The first insulator is arranged between the conductive layer and the conductive structure.

2. The semiconductor device according to claim 1, further comprising: The second insulator is disposed on the side wall of the conductive structure and covers the first insulator.

3. The semiconductor device according to claim 2, wherein: The second insulator includes a discontinuous structure.

4. The semiconductor device according to claim 2, wherein: The first insulator and the second insulator include different insulating materials.

5. The semiconductor device according to claim 4, wherein: The first insulator includes an air gap layer.

6. The semiconductor device according to claim 2, wherein: The first insulator and the second insulator include the same insulating material.

7. The semiconductor device according to claim 1, wherein: The dielectric constant of the low-k dielectric layer is smaller than the dielectric constant of the etch stop layer.

8. The semiconductor device according to claim 1, wherein: The thickness of the first insulator is between 50 angstroms and 300 angstroms.

9. The semiconductor device according to claim 1, wherein: The conductive layer includes a semiconductor material or a metal material.

10. The semiconductor device according to claim 1, further comprising: The plurality of dielectric layers are stacked in sequence; as well as The plurality of conductive structures are respectively disposed in the dielectric layers, wherein each of the dielectric layers further comprises the conductive layer disposed in each of the dielectric layers, and the first insulator disposed between each of the conductive layers and each of the conductive structures.

11. The semiconductor device according to claim 1, further comprising: The plurality of dielectric layers are stacked in sequence; as well as The plurality of conductive structures are respectively disposed in the dielectric layers, wherein one of the dielectric layers comprises the conductive layer and the first insulator disposed between the conductive layer and the conductive structure in the dielectric layer.

12. The semiconductor device according to claim 1, further comprising: substrate; A gate is disposed on the substrate; as well as The plug is disposed in the interlayer dielectric layer on the substrate and is located below the at least one dielectric layer, wherein the plug directly contacts the conductive structure.

13. A method for forming a semiconductor device, comprising: forming at least one dielectric layer, the at least one dielectric layer comprising a stacked structure, the stacked structure comprising a low-k dielectric layer and an etch stop layer; forming a conductive structure within the at least one dielectric layer; forming a conductive layer in the stacked structure between the low-k dielectric layer and the etch stop layer; and A first insulator is formed between the conductive layer and the conductive structure.

14. The method for forming a semiconductor device according to claim 13, further comprising: sequentially forming an etching stop material layer, a conductive material layer, and a low dielectric constant dielectric material layer; forming through holes in the low-k dielectric material layer, the conductive material layer, and the etch stop material layer; forming the first insulator through the through hole; as well as The conductive structure is formed in the through hole.

15. The method for forming a semiconductor device according to claim 14, wherein: Forming the first insulator also includes: An oxidation process is performed to oxidize a portion of the conductive material layer to form the first insulator, wherein the conductive material layer includes a metal material.

16. The method for forming a semiconductor device according to claim 14, wherein: Forming the first insulator also includes: A nitridation process is performed to nitridate a portion of the conductive material layer to form the first insulator, wherein the conductive material layer includes a semiconductor material.

17. The method for forming a semiconductor device according to claim 14, further comprising: A second insulator is formed on the first insulator, wherein the second insulator is between the conductive structure and the first insulator.

18. The method for forming a semiconductor device according to claim 17, wherein forming the second insulator further comprises: Partially removing the metal material layer to form an air gap; as well as A deposition process is performed to form the second insulator on the sidewall of the through hole and the first insulator in the air gap.

19. The method for forming a semiconductor device according to claim 17, wherein forming the second insulator further comprises: Partially removing the metal material layer to form an air gap; as well as A deposition process is performed to form the second insulator on the sidewall of the through hole and to form the first insulator including an air gap layer.

20. The method for forming a semiconductor device according to claim 13, further comprising: providing a substrate; forming a gate structure on the substrate; as well as A plug and an interlayer dielectric layer surrounding the plug are formed on the substrate and are located below the at least one dielectric layer, wherein the plug directly contacts the conductive structure.

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