Class AB amplifier, chip and electronic equipment

Abstract

The invention discloses an AB-class amplifier, a chip and electronic equipment, and belongs to the technical field of electronic circuits. Differential input signals are converted into high-side driving signals and low-side driving signals through an input circuit; the capacitor assembly detects an alternating current component in the output signal so as to output a feedback current; the capacitance multiplication circuit is used for adjusting the feedback current so as to output positive electrode amplification current and negative electrode amplification current; the positive amplification current is a preset multiple of the sum of the first bias current and the feedback current, and the negative amplification current is a preset multiple of the difference of the first bias current and the feedback current; the rail-to-rail output circuit outputs an output signal according to the high-side driving signal and the low-side driving signal under the feedback action of the positive electrode amplification current and the negative electrode amplification current; therefore, when the large capacitive load is driven, the layout area and / or power consumption are / is reduced.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuit technology, and in particular, relates to a class AB amplifier, chip, and electronic equipment. Background Art

[0002] Electronic circuits often use negative feedback to ensure stability, which often requires frequency compensation. The Class AB amplifier is one such circuit that needs to drive resistive and / or capacitive loads. Miller compensation is a well-established method that is widely used in class AB amplifier compensation. The core component of Miller compensation is an internal capacitor commonly referred to as the Miller capacitor. When using traditional Miller compensation for amplifiers driving large capacitive loads, there are usually two options: 1) use a large Miller capacitor; 2) bias the output stage with a large current to obtain a large transconductance. Both options are limited by the area and power requirements of the electronic chip.

[0003] In the related Class AB amplifier architecture, traditional Miller compensation is achieved by feeding the output back through two symmetrical paths, where two equal Miller capacitors are deployed. However, the feedback is not multiplied in this Class AB amplifier to reduce the layout area and / or power in applications that need to drive large capacitive loads.

[0004] Therefore, the related class AB amplifier cannot reduce the layout area and / or power while driving large capacitive loads. Summary of the invention

[0005] The purpose of the present application is to provide a class AB amplifier, chip, and electronic device, aiming to solve the problems of small adjustment range, poor precision, and large layout area of ​​related class AB amplifiers.

[0006] The embodiment of the present application provides a class AB amplifier, characterized by comprising:

[0007] An input circuit, used for receiving a differential input signal and converting the differential input signal into a high-side drive signal and a low-side drive signal;

[0008] A rail-to-rail output circuit, connected to the input circuit, and configured to output an output signal according to the high-side drive signal and the low-side drive signal;

[0009] A capacitor component connected to the rail-to-rail output circuit and used to detect an AC component in the output signal to output a feedback current;

[0010] a capacitance multiplier circuit connected to the capacitance component, the input circuit and the rail-to-rail output circuit, and configured to adjust the feedback current to output a positive amplified current and a negative amplified current; the positive amplified current is a preset multiple of the sum of the first bias current and the feedback current, and the negative amplified current is a preset multiple of the difference between the first bias current and the feedback current;

[0011] The rail-to-rail output circuit is also used to output an output signal according to the high-side drive signal and the low-side drive signal under the feedback effect of the positive amplified current and the negative amplified current.

[0012] In one embodiment, the capacitance multiplication circuit comprises:

[0013] a current synthesis circuit connected to the capacitor component, and configured to output a positive electrode synthesis current and a negative electrode synthesis current according to the feedback current; the positive electrode synthesis current is the sum of the first bias current and the feedback current, and the negative electrode synthesis current is the difference between the first bias current and the feedback current;

[0014] a first current mirror connected to the current synthesis circuit, the input circuit and the rail-to-rail output circuit, and configured to amplify the positive electrode synthesis current by a preset multiple to output the positive electrode amplified current;

[0015] The second current mirror is connected to the current synthesis circuit, the input circuit and the rail-to-rail output circuit, and is used to amplify the negative electrode synthesis current by a preset multiple to output the negative electrode amplified current.

[0016] In one embodiment, the first current mirror includes a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube;

[0017] The source of the first PMOS tube and the source of the second PMOS tube are connected to a positive power supply, the drain of the first PMOS tube is connected to the source of the third PMOS tube, and the drain of the second PMOS tube is connected to the source of the fourth PMOS tube;

[0018] The gate of the first PMOS tube, the gate of the second PMOS tube and the drain of the third PMOS tube are used together as the positive electrode synthesis current input terminal of the first current mirror, and are connected to the current synthesis circuit to access the positive electrode synthesis current;

[0019] The gate of the third PMOS tube and the gate of the fourth PMOS tube serve together as the first voltage input terminal of the first current mirror, and are connected to the first voltage source V1 to access the first voltage;

[0020] The drain of the fourth PMOS tube serves as the positive amplified current output terminal of the first current mirror, and is connected to the input circuit and the rail-to-rail output circuit to output the positive amplified current.

[0021] In one embodiment, the second current mirror includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;

[0022] The source of the first NMOS tube and the source of the second NMOS tube are connected to a negative power supply, the drain of the first NMOS tube is connected to the source of the third NMOS tube, and the drain of the second NMOS tube is connected to the source of the fourth NMOS tube;

[0023] The gate of the first NMOS tube, the gate of the second NMOS tube and the drain of the third NMOS tube are used together as the negative electrode synthesis current input terminal of the second current mirror, and are connected to the current synthesis circuit to access the negative electrode synthesis current;

[0024] The gate of the third NMOS tube and the gate of the fourth NMOS tube serve together as the second voltage input terminal of the second current mirror, and are connected to the second voltage source to access the second voltage;

[0025] The drain of the fourth NMOS tube serves as the negative amplified current output terminal of the first current mirror, and is connected to the input circuit and the rail-to-rail output circuit to output the negative amplified current.

[0026] In one embodiment, the current synthesis circuit includes a first current source, a second current source, a third current source, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor and a sixth field effect transistor;

[0027] The positive electrode of the first current source, the positive electrode of the second current source and the positive electrode of the third current source are connected to a positive power supply;

[0028] The negative electrode of the first current source, the drain of the fourth field effect transistor, the gate of the first field effect transistor, the gate of the second field effect transistor and the gate of the third field effect transistor are used together as the feedback current input terminal of the current synthesis circuit, and are connected to the capacitor component to access the feedback current;

[0029] The negative electrode of the second current source and the drain of the fifth field effect transistor serve together as a negative electrode synthesis current output terminal of the current synthesis circuit, and are connected to the second current mirror to output the negative electrode synthesis current;

[0030] The cathode of the third current source and the drain of the sixth field effect transistor serve together as the positive electrode synthesis current output terminal of the current synthesis circuit, and are connected to the first current mirror to output the positive electrode synthesis current;

[0031] The gate of the fourth field effect transistor, the gate of the fifth field effect transistor and the gate of the sixth field effect transistor are used together as a second voltage input terminal, which is connected to a second voltage source to access a second voltage;

[0032] The source of the first field effect transistor, the source of the second field effect transistor and the source of the third field effect transistor are connected to a negative power supply;

[0033] Wherein, the first current output by the first current source is equal to the sum of the first bias current and the second bias current;

[0034] The second current output by the second current source is equal to the sum of twice the first bias current and the second bias current;

[0035] The third current output by the third current source is equal to the second bias current.

[0036] In one embodiment, the current synthesis circuit includes a fourth current source, a fifth current source, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor and a first resistor;

[0037] The positive electrode of the fourth current source and the positive electrode of the fifth current source are connected to a positive power supply;

[0038] The first end of the first resistor is used as a feedback current input end of the current synthesis circuit and is connected to the capacitor component to access the feedback current;

[0039] The second end of the first resistor is connected to the negative electrode of the fourth current source, the drain of the tenth field effect transistor, the gate of the seventh field effect transistor, the gate of the eighth field effect transistor and the gate of the ninth field effect transistor;

[0040] The cathode of the fifth current source and the drain of the eleventh field effect transistor serve together as a cathode synthesis current output terminal of the current synthesis circuit, and are connected to the second current mirror to output the cathode synthesis current;

[0041] The drain of the twelfth field effect transistor serves as the positive electrode synthesis current output terminal of the current synthesis circuit and is connected to the first current mirror to output the positive electrode synthesis current;

[0042] The gate of the tenth field effect transistor, the gate of the eleventh field effect transistor and the gate of the twelfth field effect transistor are used together as a second voltage input terminal, which is connected to a second voltage source V2 to access a second voltage;

[0043] The source of the seventh field effect transistor, the source of the eighth field effect transistor and the source of the ninth field effect transistor are connected to a negative power supply;

[0044] Wherein, the fourth current output by the fourth current source is equal to the first bias current;

[0045] The second current output by the second current source is equal to twice the first bias current.

[0046] In one embodiment, the input circuit comprises:

[0047] A conversion circuit, used for receiving a differential input signal and converting the differential input signal into a first differential current signal and a second differential current signal;

[0048] A folded common-source and common-gate circuit is connected to the conversion circuit, the rail-to-rail output circuit and the capacitance multiplication circuit, and is used to convert the first differential current signal and the second differential current signal into the high-side drive signal and the low-side drive signal.

[0049] In one embodiment, the folded cascode circuit comprises:

[0050] A reference current source, used for providing a reference current;

[0051] a third current mirror, connected to the conversion circuit, the reference current source, the rail-to-rail output circuit and the capacitance multiplication circuit, for mirroring the reference current to output a static current, and superimposing the first differential current signal to output a dynamic current;

[0052] a fourth current mirror, connected to the conversion circuit, the reference current source, the rail-to-rail output circuit and the capacitance multiplication circuit, for mirroring the reference current to output the static current, and superimposing the second differential current signal to output the dynamic current;

[0053] an adjustment circuit, connected to the third current mirror, the fourth current mirror, the rail-to-rail output circuit and the capacitance multiplication circuit, for accessing a synthetic current, outputting a common mode voltage of the high-side drive signal and a common mode voltage of the low-side drive signal according to the static current, and outputting a dynamic component of the high-side drive signal and a dynamic component of the low-side drive signal according to the dynamic current;

[0054] The synthetic current includes the static current and the dynamic current.

[0055] An embodiment of the present invention further provides a chip, wherein the chip includes the above-mentioned class AB amplifier.

[0056] An embodiment of the present invention further provides an electronic device, wherein the electronic device includes the above-mentioned class AB amplifier.

[0057] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the capacitance multiplication circuit adjusts the feedback current to output a positive amplified current and a negative amplified current; the positive amplified current is a preset multiple of the sum of the first bias current and the feedback current, and the negative amplified current is a preset multiple of the difference between the first bias current and the feedback current; the rail-to-rail output circuit outputs an output signal according to the high-side drive signal and the low-side drive signal under the feedback effect of the positive amplified current and the negative amplified current; therefore, the feedback current is multiplied by the capacitance multiplication circuit, and while driving a large capacitive load, the layout area and / or power consumption are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 A schematic diagram of the structure of a class AB amplifier provided in one embodiment of the present application;

[0060] Figure 2 A schematic diagram of a structure of a capacitance multiplication circuit in a class AB amplifier provided in an embodiment of the present application;

[0061] Figure 3 A schematic diagram of a structure of an input circuit in a class AB amplifier provided in an embodiment of the present application;

[0062] Figure 4 A schematic diagram of a structure of a folded cascode circuit in a class AB amplifier provided in an embodiment of the present application;

[0063] Figure 5 A partial exemplary circuit schematic diagram of a capacitance multiplication circuit in a class AB amplifier provided in an embodiment of the present application;

[0064] Figure 6 Another partial exemplary circuit schematic diagram of a capacitance multiplication circuit in a class AB amplifier provided in an embodiment of the present application;

[0065] Figure 7A partial exemplary circuit schematic diagram of a class AB amplifier provided in one embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0067] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0068] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0069] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0070] Figure 1 The structure diagram of the class AB amplifier provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0071] The above-mentioned class AB amplifier includes an input circuit 01 , a rail-to-rail output circuit 02 , a capacitor component 03 and a capacitor multiplication circuit 04 .

[0072] The input circuit 01 is used to receive a differential input signal and convert the differential input signal into a high-side drive signal and a low-side drive signal.

[0073] The rail-to-rail output circuit 02 is connected to the input circuit 01 and is used to output an output signal according to the high-side driving signal and the low-side driving signal.

[0074] The capacitor component 03 is connected to the rail-to-rail output circuit 02 and is used to detect the AC component in the output signal to output a feedback current.

[0075] The capacitance multiplier circuit 04 is connected to the capacitance component 03, the input circuit 01 and the rail-to-rail output circuit 02, and is used to adjust the feedback current to output a positive amplified current and a negative amplified current; the positive amplified current is a preset multiple of the sum of the first bias current and the feedback current, and the negative amplified current is a preset multiple of the difference between the first bias current and the feedback current.

[0076] The rail-to-rail output circuit 02 is also used to output an output signal according to a high-side drive signal and a low-side drive signal under the feedback effect of the positive amplified current and the negative amplified current.

[0077] It should be noted that the preset multiple is greater than 1.

[0078] like Figure 2 As shown, the capacitance multiplication circuit 04 includes a current synthesis circuit 041 , a first current mirror 042 and a second current mirror 043 .

[0079] The current synthesis circuit 041 is connected to the capacitor component 03 and is used to output a positive electrode synthesis current and a negative electrode synthesis current according to the feedback current; the positive electrode synthesis current is the sum of the first bias current and the feedback current, and the negative electrode synthesis current is the difference between the first bias current and the feedback current.

[0080] The first current mirror 042 is connected to the current synthesis circuit 041, the input circuit 01 and the rail-to-rail output circuit 02, and is used to amplify the positive electrode synthesis current by a preset multiple to output the positive electrode amplified current.

[0081] The second current mirror 043 is connected to the current synthesis circuit 041, the input circuit 01 and the rail-to-rail output circuit 02, and is used to amplify the negative electrode synthesis current by a preset multiple to output the negative electrode amplified current.

[0082] The positive electrode composite current and the negative electrode composite current are composited by the current composite circuit 041, and the positive electrode composite current and the negative electrode composite current are multiplied by the first current mirror 042 and the second current mirror 043. The hardware structure is simple and reliable.

[0083] like Figure 3 As shown, the input circuit 01 includes a conversion circuit 011 and a folded cascode circuit 012 .

[0084] The conversion circuit 011 is used to receive a differential input signal and convert the differential input signal into a first differential current signal and a second differential current signal.

[0085] The folded cascode circuit 012 is connected to the conversion circuit 011, the rail-to-rail output circuit 02 and the capacitance multiplication circuit 04, and is used to convert the first differential current signal and the second differential current signal into a high-side drive signal and a low-side drive signal.

[0086] The input circuit 01 has fewer amplification stages, and the circuit is simple and reliable.

[0087] like Figure 4 As shown, the folded cascode circuit 012 includes a reference current source I0 , a third current mirror 121 , a fourth current mirror 122 and an adjustment circuit 123 .

[0088] A reference current source I0, used for providing a reference current;

[0089] The third current mirror 121 is connected to the conversion circuit 011, the reference current source I0, the rail-to-rail output circuit 02 and the capacitance multiplication circuit 04, and is used to mirror the reference current to output a static current, and to superimpose the first differential current signal to output a dynamic current.

[0090] The fourth current mirror 122 is connected to the conversion circuit 011, the reference current source I0, the rail-to-rail output circuit 02 and the capacitance multiplication circuit 04, and is used to mirror the reference current to output a static current, and to superimpose the second differential current signal to output a dynamic current.

[0091] The adjustment circuit 123 is connected to the third current mirror 121, the fourth current mirror 122, the rail-to-rail output circuit 02 and the capacitance multiplication circuit 04, and is used to access the synthetic current, output the common mode voltage of the high-side drive signal and the common mode voltage of the low-side drive signal according to the static current, and output the dynamic component of the high-side drive signal and the dynamic component of the low-side drive signal according to the dynamic current.

[0092] The composite current includes static current and dynamic current.

[0093] The folded cascode circuit 012 has a symmetrical structure and improves the output characteristics of the class AB amplifier.

[0094] Figure 5 FIG. 1 shows a partial exemplary circuit structure of a capacitance multiplication circuit in a class AB amplifier provided by an embodiment of the present invention. Figure 6 Another partial exemplary circuit structure of a capacitance multiplication circuit in a class AB amplifier provided by an embodiment of the present invention is shown. Figure 7 A partial exemplary circuit structure of a class AB amplifier provided by an embodiment of the present invention is shown. For the sake of convenience, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0095] like Figure 5 and Figure 6As shown, the first current mirror 042 includes a first P-channel Metal Oxide Semiconductor (PMOS) tube P1, a second PMOS tube P2, a third PMOS tube P3 and a fourth PMOS tube P4.

[0096] The source of the first PMOS tube P1 and the source of the second PMOS tube P2 are connected to the positive power supply VDD, the drain of the first PMOS tube P1 is connected to the source of the third PMOS tube P3, and the drain of the second PMOS tube P2 is connected to the source of the fourth PMOS tube P4; the gate of the first PMOS tube P1, the gate of the second PMOS tube P2 and the drain of the third PMOS tube P3 are jointly used as the positive composite current input terminal of the first current mirror 042, connected to the current synthesis circuit 041 to access the positive composite current; the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube P4 are jointly used as the first voltage input terminal of the first current mirror 042, connected to the first voltage source V1 to access the first voltage; the drain of the fourth PMOS tube P4 is used as the positive amplified current output terminal of the first current mirror 042, connected to the input circuit 01 and the rail-to-rail output circuit 02 to output the positive amplified current; it can be understood that the first voltage is provided by the first voltage source V1.

[0097] like Figure 5 and Figure 6 As shown, the second current mirror 043 includes a first N-channel Metal Oxide Semiconductor (NMOS) tube N1, a second NMOS tube N2, a third NMOS tube N3 and a fourth NMOS tube N4.

[0098] The source of the first NMOS tube N1 and the source of the second NMOS tube N2 are connected to the negative power supply VSS, the drain of the first NMOS tube N1 is connected to the source of the third NMOS tube N3, and the drain of the second NMOS tube N2 is connected to the source of the fourth NMOS tube N4; the gate of the first NMOS tube N1, the gate of the second NMOS tube N2 and the drain of the third NMOS tube N3 are used together as the negative synthesis current input terminal of the second current mirror 043, connected to the current synthesis circuit 041 to access the negative synthesis current; the gate of the third NMOS tube N3 and the gate of the fourth NMOS tube N4 are used together as the second voltage input terminal of the second current mirror 043, connected to the second voltage source V2 to access the second voltage; the drain of the fourth NMOS tube N4 is used as the negative amplified current output terminal of the first current mirror 042, connected to the input circuit 01 and the rail-to-rail output circuit 02 to output the negative amplified current; it can be understood that the second voltage is provided by the second voltage source V2.

[0099] like Figure 5As shown, the current synthesis circuit 041 includes a first current source I1, a second current source I2, a third current source I3, a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5 and a sixth field effect transistor M6.

[0100] The positive electrode of the first current source I1, the positive electrode of the second current source I2 and the positive electrode of the third current source I3 are connected to the positive power supply VDD; the negative electrode of the first current source I1, the drain of the fourth field effect transistor M4, the gate of the first field effect transistor M1, the gate of the second field effect transistor M2 and the gate of the third field effect transistor M3 are used as the feedback current input terminal of the current synthesis circuit 041, and are connected to the capacitor component 03 to access the feedback current; the negative electrode of the second current source I2 and the drain of the fifth field effect transistor M5 are used as the negative electrode synthesis current output terminal of the current synthesis circuit 041, and are connected to the second current mirror 04 3 is connected to output a negative composite current; the negative electrode of the third current source I3 and the drain of the sixth field effect transistor M6 are commonly used as the positive composite current output terminal of the current synthesis circuit 041, and are connected to the first current mirror 042 to output the positive composite current; the gate of the fourth field effect transistor M4, the gate of the fifth field effect transistor M5 and the gate of the sixth field effect transistor M6 are commonly used as the second voltage input terminal, and are connected to the second voltage source V2 to access the second voltage; the source of the first field effect transistor M1, the source of the second field effect transistor M2 and the source of the third field effect transistor M3 are commonly connected to the negative power supply VSS.

[0101] Among them, the first current I1 output by the first current source is equal to the sum of the first bias current Ib0 and the second bias current Ib1; the second current I2 output by the second current source is equal to the sum of twice the first bias current Ib0 and the second bias current Ib1; the third current I3 output by the third current source is equal to the second bias current Ib1.

[0102] like Figure 6 As shown, the current synthesis circuit 041 includes a fourth current source I4, a fifth current source I5, a seventh field effect transistor M7, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, a twelfth field effect transistor M12 and a first resistor R1.

[0103] The positive electrode of the fourth current source I4 and the positive electrode of the fifth current source I5 are commonly connected to the positive power supply VDD;

[0104] The first end of the first resistor R1 is used as the feedback current input end of the current synthesis circuit 041, and is connected to the capacitor component 03 to receive the feedback current; the second end of the first resistor R1 is connected to the cathode of the fourth current source I4, the drain of the tenth field effect transistor M10, the gate of the seventh field effect transistor M7, the gate of the eighth field effect transistor M8 and the gate of the ninth field effect transistor M9; the cathode of the fifth current source I5 and the drain of the eleventh field effect transistor M11 are used together as the cathode synthesis current output end of the current synthesis circuit 041, and are connected to the second current mirror 043 to output the feedback current. The drain of the twelfth field effect transistor M12 serves as the positive composite current output terminal of the current synthesis circuit 041, and is connected to the first current mirror 042 to output the positive composite current; the gate of the tenth field effect transistor M10, the gate of the eleventh field effect transistor M11 and the gate of the twelfth field effect transistor M12 serve as the second voltage input terminal, and are connected to the second voltage source V2 to access the second voltage; the source of the seventh field effect transistor M7, the source of the eighth field effect transistor M8 and the source of the ninth field effect transistor M9 are connected to the negative power supply VSS.

[0105] The fourth current I4 output by the fourth current source is equal to the first bias current Ib0; and the second current I2 output by the second current source is equal to twice the first bias current Ib0.

[0106] It can be understood that the second voltage is provided by the second voltage source V2.

[0107] like Figure 7 As shown, the conversion circuit 011 includes a sixth current source I6, a seventh current source I7, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5 and a sixth NMOS transistor N6.

[0108] The positive electrode of the sixth current source I6 is connected to the positive power supply VDD, the negative electrode of the sixth current source I6 is connected to the source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6, the negative electrode of the seventh current source I7 is connected to the negative power supply VSS, and the positive electrode of the seventh current source I7 is connected to the source of the fifth NMOS tube N5 and the source of the sixth NMOS tube N6; the drain of the fifth NMOS tube N5 and the drain of the sixth NMOS tube N6 serve together as the first differential current signal output end of the conversion circuit 011, and the folded common source common gate circuit The fifth PMOS transistor P5 and the sixth PMOS transistor P6 are connected to the folded common-source and common-gate circuit 012 to output the first differential current signal; the drain of the fifth PMOS transistor P5 and the drain of the sixth PMOS transistor P6 are jointly used as the second differential current signal output terminal of the conversion circuit 011, and are connected to the folded common-source and common-gate circuit 012 to output the second differential current signal; the gate of the fifth PMOS transistor P5, the gate of the fifth NMOS transistor N5, the gate of the sixth PMOS transistor P6 and the gate of the sixth NMOS transistor N6 are jointly used as the differential input signal input terminal of the conversion circuit 011 to access the differential input signal.

[0109] The third current mirror 121 includes a seventh PMOS transistor P7 , an eighth PMOS transistor P8 , a ninth PMOS transistor P9 and a tenth PMOS transistor P10 .

[0110] The source of the seventh PMOS tube P7 and the source of the eighth PMOS tube P8 are connected to the positive power supply VDD.

[0111] The drain of the ninth PMOS tube P9, the gate of the seventh PMOS tube P7 and the gate of the eighth PMOS tube P8 are all connected to the positive electrode of the reference current source I0I0; the drain of the seventh PMOS tube P7, the drain of the eighth PMOS tube P8, the source of the ninth PMOS tube P9 and the source of the tenth PMOS tube P10 serve together as the first differential current signal input terminal of the third current mirror 121, and are connected to the conversion circuit 011 to access the first differential current signal; the drain of the tenth PMOS tube P10 serves as the synthetic current output terminal of the third current mirror 121, and is connected to the adjustment circuit 123, the capacitance multiplication circuit 04 and the rail-to-rail output circuit 02 to output the synthetic current; the gate of the ninth PMOS tube P9 and the gate of the tenth PMOS tube P10 serve as the third voltage input terminal of the third current mirror 121, and are connected to the third voltage source V3 to access the third voltage.

[0112] It can be understood that the third voltage is provided by a third voltage source V3.

[0113] The fourth current mirror 122 includes a seventh NMOS transistor N7 , an eighth NMOS transistor N8 , a ninth NMOS transistor N9 and a tenth NMOS transistor N10 .

[0114] The source of the seventh NMOS transistor N7 and the source of the eighth NMOS transistor N8 are connected to the negative power supply VSS.

[0115] The drain of the ninth NMOS tube N9, the gate of the seventh NMOS tube N7 and the gate of the eighth NMOS tube N8 are all connected to the negative electrode of the reference current source I0I0; the drain of the seventh NMOS tube N7, the drain of the eighth NMOS tube N8, the source of the ninth NMOS tube N9 and the source of the tenth NMOS tube N10 are used together as the second differential current signal input terminal of the fourth current mirror 122, connected to the conversion circuit 011 to access the second differential current signal; the drain of the tenth NMOS tube N10 is used as the synthetic current output terminal of the fourth current mirror 122, connected to the adjustment circuit 123, the capacitance multiplication circuit 04 and the rail-to-rail output circuit 02 to output the synthetic current; the gate of the ninth NMOS tube N9 and the gate of the tenth NMOS tube N10 are used as the fourth voltage input terminal of the third current mirror 121, connected to the fourth voltage source V4 to access the fourth voltage.

[0116] It can be understood that the fourth voltage is provided by a fourth voltage source V4.

[0117] The rail-to-rail output circuit 02 includes an eleventh PMOS transistor P11 and an eleventh NMOS transistor N11.

[0118] The source of the eleventh PMOS tube P11 is connected to the positive power supply VDD, and the source of the eleventh NMOS tube N11 is connected to the negative power supply VSS; the gate of the eleventh PMOS tube P11 is used as the high-side drive signal input terminal of the rail-to-rail output circuit 02 and the positive amplified current input terminal of the rail-to-rail output circuit 02, and is connected to the input circuit 01 and the capacitor multiplication circuit 04 to receive the high-side drive signal and the positive amplified current; the gate of the eleventh NMOS tube N11 is used as the low-side drive signal input terminal of the rail-to-rail output circuit 02 and the negative amplified current input terminal of the rail-to-rail output circuit 02, and is connected to the input circuit 01 and the capacitor multiplication circuit 04 to receive the low-side drive signal and the negative amplified current; the drain of the eleventh PMOS tube P11 and the drain of the eleventh NMOS tube N11 are used together as the output signal output terminal of the rail-to-rail output circuit 02, and are connected to the capacitor component 03 to output the output signal.

[0119] The capacitor component 03 may include a first capacitor C1.

[0120] The following is a combination of working principles Figures 5 to 7 As shown for further explanation:

[0121] like Figure 7 As shown, the sixth current source I6, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 convert the differential input signal into a first differential current signal; the seventh current source I7, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 convert the differential input signal into a second differential current signal.

[0122] The seventh PMOS tube P7 to the tenth PMOS tube P10 mirror the reference current to output a static current, and superimpose the first differential current signal to output a dynamic current; the seventh NMOS tube N7 to the tenth NMOS tube N10 mirror the reference current to output a static current, and superimpose the second differential current signal to output a dynamic current; the adjustment circuit 123 is connected to the synthetic current, outputs the common mode voltage of the high-side drive signal and the common mode voltage of the low-side drive signal according to the static current, and outputs the dynamic component of the high-side drive signal and the dynamic component of the low-side drive signal according to the dynamic current; wherein the synthetic current includes the static current and the dynamic current.

[0123] The gate of the eleventh PMOS tube P11 is connected to the high-side drive signal, and the eleventh NMOS tube N11 is connected to the low-side drive signal. Under the drive of the high-side drive signal and the low-side drive signal, the drain of the eleventh PMOS tube P11 and the drain of the eleventh NMOS tube N11 jointly output the output signal.

[0124] At the same time, the first capacitor C1 detects the AC component in the output signal to output a feedback current.

[0125] like Figure 5 As shown, due to the AC coupled feedback current Ifb flowing into the capacitance multiplication circuit 04, it is combined with the first current I1, and then mirrored from M1 / M4 to M2 / M5 and M3 / M6 at a mirror ratio of 1:1. The output current of the first current source I1 to the output current of the third current source I3 is set as follows:

[0126] I1=Ib0+Ib1;

[0127] I2=2*Ib0+Ib1;

[0128] I3=Ib1;

[0129] Wherein, Ib0 is a first bias current, which is a small DC current used to bias the current mirror, and Ib1 is a second bias current.

[0130] Therefore, the following conclusions can be drawn: the positive electrode composite current is equal to Ib0+Ifb, and the positive electrode composite current is equal to Ib0–Ifb.

[0131] Among them, Ib1 is a relatively large DC bias current, which makes the transconductance gm1 of the first field effect transistor M1 large enough to place the left half plane (left half plane pole) zero introduced by gm1 and the first capacitor C1 at a frequency far higher than the closed-loop bandwidth of the amplifier. The frequency of this zero point is determined by gm1 / C1. Therefore, the larger the gm1, the higher the zero point frequency. The positive amplified current output terminal Iop of the capacitor multiplier circuit 04 and the negative amplified current output terminal Ion of the capacitor multiplier circuit 04 are directly connected to Figure 7The gate of the eleventh PMOS tube P11 and the gate of the eleventh NMOS tube N11 in the capacitor multiplier circuit 04 are high impedance nodes of the class AB amplifier. The DC current from the positive amplified current output terminal Iop of the capacitor multiplier circuit 04 and the negative amplified current output terminal Ion of the capacitor multiplier circuit 04 need to be a relatively small value, otherwise the capacitor multiplier circuit 04 will affect the DC characteristics of the amplifier. Therefore, by properly setting I2 and I3, Ib1 is removed before entering the output current mirror. I2 has 2*Ib0 terms in its composition, so as to create a feedback current complementary to the feedback current through the positive amplified current output terminal Iop of the capacitor multiplier circuit 04 through the negative amplified current output terminal Ion of the capacitor multiplier circuit 04. In this way, the capacitance multiplier obtains an additional 2 times gain, plus the 1:K ratio of the first current mirror 042 (the first PMOS tube P1 to the fourth PMOS tube P4) and the second current mirror 043 (the first NMOS tube N1 to the fourth NMOS tube N4), that is: the positive amplified current is equal to K(Ib0+Ifb), the positive composite current is equal to K(Ib0-Ifb), and the total capacitance multiplication factor achieved is 2K.

[0132] like Figure 6 As shown, due to the AC coupling, the feedback current Ifb flows into the capacitance multiplication circuit 04, is combined with the first current I1, and then is mirrored from M7 / M10 to M8 / M11 and M9 / M12 at a mirror ratio of 1:1.

[0133] The output current of the fourth current source I4 to the output current of the fifth current source I5 are set as follows:

[0134] I4=Ib0;

[0135] I5=2*Ib0;

[0136] Wherein, Ib0 is a first bias current, which is a small DC current used to bias the current mirror.

[0137] Therefore, the following conclusion can be drawn: the positive electrode composite current is equal to Ib0+Ifb, and the positive electrode composite current is equal to Ib0–Ifb. Adding the 1:K ratio of the first current mirror 042 (the first PMOS tube P1 to the fourth PMOS tube P4) and the second current mirror 043 (the first NMOS tube N1 to the fourth NMOS tube N4), that is, the positive electrode amplified current is equal to K(Ib0+Ifb), the positive electrode composite current is equal to K(Ib0-Ifb), and the total capacitance multiplication factor is 2K.

[0138] It should be noted that the left half plane pole zero point is introduced by using the first capacitor C1 and the input resistance (first resistor R1) of the capacitance multiplier circuit 04. Here, a resistor (first resistor R1) is added to the feedback current input terminal of the capacitance multiplier. (First resistor R1) can be set much higher than 1 / gm1, so that gm1 can be ignored, and the position of the left half plane pole zero point is determined by 1 / (R1*C1). By selecting the appropriate value of R1, this zero point can be used to offset the influence of the non-dominant pole in the amplifier. Since gm1 does not need to be a large value in this use, compared with the previous implementation, the second bias current Ib1 of DC is removed, thereby also removing I3.

[0139] Thus, the rail-to-rail output circuit outputs an output signal according to the high-side drive signal and the low-side drive signal under the feedback effect of the positive amplified current and the negative amplified current.

[0140] An embodiment of the present invention further provides a chip, wherein the chip includes the above-mentioned class AB amplifier.

[0141] An embodiment of the present invention further provides an electronic device, wherein the electronic device includes the above-mentioned class AB amplifier.

[0142] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0143] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A class AB amplifier, characterized in that: include: An input circuit, used for receiving a differential input signal and converting the differential input signal into a high-side drive signal and a low-side drive signal; A rail-to-rail output circuit, connected to the input circuit, and configured to output an output signal according to the high-side drive signal and the low-side drive signal; A capacitor component connected to the rail-to-rail output circuit and used for detecting an AC component in the output signal to output a feedback current; a capacitance multiplier circuit connected to the capacitance component, the input circuit and the rail-to-rail output circuit, and configured to adjust the feedback current to output a positive amplified current and a negative amplified current; the positive amplified current is a preset multiple of the sum of the first bias current and the feedback current, and the negative amplified current is a preset multiple of the difference between the first bias current and the feedback current; The rail-to-rail output circuit is also used to output an output signal according to the high-side drive signal and the low-side drive signal under the feedback effect of the positive amplified current and the negative amplified current.

2. The class AB amplifier according to claim 1, wherein: The capacitance multiplication circuit comprises: a current synthesis circuit connected to the capacitor component, and configured to output a positive electrode synthesis current and a negative electrode synthesis current according to the feedback current; the positive electrode synthesis current is the sum of the first bias current and the feedback current, and the negative electrode synthesis current is the difference between the first bias current and the feedback current; a first current mirror connected to the current synthesis circuit, the input circuit and the rail-to-rail output circuit, and configured to amplify the positive electrode synthesis current by a preset multiple to output the positive electrode amplified current; The second current mirror is connected to the current synthesis circuit, the input circuit and the rail-to-rail output circuit, and is used to amplify the negative electrode synthesis current by a preset multiple to output the negative electrode amplified current.

3. The class AB amplifier according to claim 2, characterized in that: The first current mirror includes a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; The source of the first PMOS tube and the source of the second PMOS tube are connected to a positive power supply, the drain of the first PMOS tube is connected to the source of the third PMOS tube, and the drain of the second PMOS tube is connected to the source of the fourth PMOS tube; The gate of the first PMOS tube, the gate of the second PMOS tube and the drain of the third PMOS tube are used together as the positive electrode synthesis current input terminal of the first current mirror, and are connected to the current synthesis circuit to access the positive electrode synthesis current; The gate of the third PMOS tube and the gate of the fourth PMOS tube serve together as the first voltage input terminal of the first current mirror, and are connected to the first voltage source to access the first voltage; The drain of the fourth PMOS tube serves as the positive amplified current output terminal of the first current mirror, and is connected to the input circuit and the rail-to-rail output circuit to output the positive amplified current.

4. The class AB amplifier according to claim 2, wherein: The second current mirror includes a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; The source of the first NMOS tube and the source of the second NMOS tube are connected to a negative power supply, the drain of the first NMOS tube is connected to the source of the third NMOS tube, and the drain of the second NMOS tube is connected to the source of the fourth NMOS tube; The gate of the first NMOS tube, the gate of the second NMOS tube and the drain of the third NMOS tube are used together as the negative electrode synthesis current input terminal of the second current mirror, and are connected to the current synthesis circuit to access the negative electrode synthesis current; The gate of the third NMOS tube and the gate of the fourth NMOS tube serve together as the second voltage input terminal of the second current mirror, and are connected to the second voltage source to access the second voltage; The drain of the fourth NMOS tube serves as the negative amplified current output terminal of the first current mirror, and is connected to the input circuit and the rail-to-rail output circuit to output the negative amplified current.

5. The class AB amplifier according to claim 2, wherein: The current synthesis circuit includes a first current source, a second current source, a third current source, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor and a sixth field effect transistor; The positive electrode of the first current source, the positive electrode of the second current source and the positive electrode of the third current source are connected to a positive power supply; The negative electrode of the first current source, the drain of the fourth field effect transistor, the gate of the first field effect transistor, the gate of the second field effect transistor and the gate of the third field effect transistor are used together as the feedback current input terminal of the current synthesis circuit, and are connected to the capacitor component to access the feedback current; The negative electrode of the second current source and the drain of the fifth field effect transistor serve together as a negative electrode synthesis current output terminal of the current synthesis circuit, and are connected to the second current mirror to output the negative electrode synthesis current; The cathode of the third current source and the drain of the sixth field effect transistor serve together as the positive electrode synthesis current output terminal of the current synthesis circuit, and are connected to the first current mirror to output the positive electrode synthesis current; The gate of the fourth field effect transistor, the gate of the fifth field effect transistor and the gate of the sixth field effect transistor are used together as a second voltage input terminal, which is connected to a second voltage source to access a second voltage; The source of the first field effect transistor, the source of the second field effect transistor and the source of the third field effect transistor are connected to a negative power supply; Wherein, the first current output by the first current source is equal to the sum of the first bias current and the second bias current; The second current output by the second current source is equal to the sum of twice the first bias current and the second bias current; The third current output by the third current source is equal to the second bias current.

6. The class AB amplifier according to claim 2, wherein: The current synthesis circuit includes a fourth current source, a fifth current source, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor and a first resistor; The positive electrode of the fourth current source and the positive electrode of the fifth current source are connected to a positive power supply; The first end of the first resistor serves as a feedback current input end of the current synthesis circuit and is connected to the capacitor component to access the feedback current; The second end of the first resistor is connected to the negative electrode of the fourth current source, the drain of the tenth field effect transistor, the gate of the seventh field effect transistor, the gate of the eighth field effect transistor and the gate of the ninth field effect transistor; The cathode of the fifth current source and the drain of the eleventh field effect transistor serve together as a cathode synthesis current output terminal of the current synthesis circuit, and are connected to the second current mirror to output the cathode synthesis current; The drain of the twelfth field effect transistor serves as the positive electrode synthesis current output terminal of the current synthesis circuit and is connected to the first current mirror to output the positive electrode synthesis current; The gate of the tenth field effect transistor, the gate of the eleventh field effect transistor and the gate of the twelfth field effect transistor are used together as a second voltage input terminal, which is connected to a second voltage source V2 to access a second voltage; The source of the seventh field effect transistor, the source of the eighth field effect transistor and the source of the ninth field effect transistor are connected to a negative power supply; Wherein, the fourth current output by the fourth current source is equal to the first bias current; The second current output by the second current source is equal to twice the first bias current.

7. The class AB amplifier according to any one of claims 1 to 6, characterized in that: The input circuit comprises: A conversion circuit, used for receiving a differential input signal and converting the differential input signal into a first differential current signal and a second differential current signal; A folded common-source and common-gate circuit is connected to the conversion circuit, the rail-to-rail output circuit and the capacitance multiplication circuit, and is used to convert the first differential current signal and the second differential current signal into the high-side drive signal and the low-side drive signal.

8. The class AB amplifier according to claim 7, wherein: The folded cascode circuit comprises: A reference current source, used for providing a reference current; a third current mirror, connected to the conversion circuit, the reference current source, the rail-to-rail output circuit and the capacitance multiplication circuit, for mirroring the reference current to output a static current, and superimposing the first differential current signal to output a dynamic current; a fourth current mirror, connected to the conversion circuit, the reference current source, the rail-to-rail output circuit and the capacitance multiplication circuit, for mirroring the reference current to output the static current, and superimposing the second differential current signal to output the dynamic current; an adjustment circuit, connected to the third current mirror, the fourth current mirror, the rail-to-rail output circuit and the capacitance multiplication circuit, for accessing a synthetic current, outputting a common mode voltage of the high-side drive signal and a common mode voltage of the low-side drive signal according to the static current, and outputting a dynamic component of the high-side drive signal and a dynamic component of the low-side drive signal according to the dynamic current; The synthetic current includes the static current and the dynamic current.

9. A chip, characterized in that: The chip comprises the class AB amplifier as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the class AB amplifier according to any one of claims 1 to 8.

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