Multifunctional time relay realized by hardware
The multi-function time relay implemented through hardware uses reset circuits, oscillation frequency division circuits, etc. to form a delay circuit, which solves the problem that existing time relays cannot achieve multiple delay mode switching, realizes smooth switching and flexibility of delay modes, and reduces production and R&D costs.
Patent Information
- Application Number
- CN202411252777.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2025-02-28
AI Technical Summary
Existing time relays cannot achieve multiple delay modes of mutual switching, and the use of microprocessors is limited by occasions, resulting in extended production cycles, increased costs and complex software development.
The multi-function time relay is realized through hardware, and a reset circuit, an oscillation frequency division circuit, a data selector, an RS flip-flop and a logic output terminal are used to form a delay circuit, which realizes switching of multiple delay modes, avoids the software programming of the microprocessor.
It realizes smooth switching of various delay modes, saves production materials and reduces production cycles, and reduces software R&D costs and cycles, increasing the usage scenarios and flexibility of time relays.
Smart Images
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Abstract
Description
Technical Field
[0001] The invention relates to the technical field of time relays, and in particular to a multifunctional time relay realized by hardware. Background Art
[0002] Time relay is an important category of relay, usually composed of delay circuit and electromagnetic relay, and has a wide range of applications in the control field. Although the existing time relays are based on basic delay circuits, different delay modes are not interchangeable, resulting in the need for more printing tools, more materials and procurement inventory for the application party to adapt to different time relays, resulting in longer production cycles and increased production costs. Producing different types of delays through microprocessors is a technical approach to solve this problem, but microprocessors involve software programming. In special application scenarios, the complex software evaluation brought about by microprocessor software programming greatly increases the R&D cycle and cost. Summary of the invention
[0003] In view of the deficiencies in the prior art, the present invention provides a hardware-implemented multifunctional time relay, which solves the technical problem that the existing time relays cannot realize switching between multiple delay modes, and the microprocessor is limited by the occasion to solve the delay mode switching problem. The purpose of realizing switching between multiple delay modes through hardware without the need for microprocessor intervention and control is achieved.
[0004] In order to solve the above technical problems, the present invention provides the following technical solutions: a multifunctional time relay implemented by hardware, which is formed by combining a delay circuit and an electromagnetic relay, and the delay circuit includes:
[0005] A reset circuit, the reset circuit is used to convert a reset pulse signal of a high level of a power supply into a reset signal of a low level;
[0006] An oscillating frequency dividing circuit, which is used to generate a square wave signal of a fixed frequency as a timing signal after power-on, and divide the timing signal into a plurality of different divided frequency signals;
[0007] A data selector, to which external control signals A and B are connected, and the data selector selects one of the multiple frequency division signals output by the oscillation frequency division circuit according to the external control signals A and B to realize the data selection signal of programmable frequency division counting, and outputs a high level when a reset signal exists;
[0008] RS trigger, the RS trigger includes three input signals of mode selection, data selection output, and reset output, and according to the "0" or "1" of the mode selection, it serves as a delay circuit of a time relay for cycle delay, action delay, or time-limited timing, and outputs a trigger signal;
[0009] The logic output end of the delay circuit includes three input ends of trigger output, reset output and output selection, which are used to input trigger signal, reset signal and data selection signal respectively. When the reset signal exists, the logic output end is controlled by the data selector to output "0" or "1", and after the reset signal disappears, the RS trigger controls the output of "0" or "1";
[0010] The output drive circuit is used to drive the coil of the electromagnetic relay.
[0011] Preferably, the reset circuit is composed of a two-input NOR gate D1A, a resistor R1 and a capacitor C1, the capacitor C1 is connected in series between the power supply VDD and the two ends of the two-input NOR gate D1A, the resistor R1 is connected to the two ends of the two-input NOR gate D1A and grounded, and a low-level reset signal is generated when a high-level reset control signal is input to one end of the two-input NOR gate D1A.
[0012] Preferably, the oscillating frequency division circuit comprises two CMOS NOT gates, a current limiting resistor R2, a delay resistor R3, a capacitor Ct, a two-input NAND gate D2A and a frequency division counter D3;
[0013] Two CMOS NOT gates, a current limiting resistor R2, and a capacitor Ct are connected in series and then connected to the 2nd terminal of a two-input NAND gate D2A. A delay resistor R3 is connected between the two CMOS NOT gates and in parallel with the current limiting resistor R2. The 3rd terminal of the two-input NAND gate D2A is connected to the CK1 port of a frequency dividing counter D3. The Q4, Q7, Q10, and Q14 terminals of the frequency dividing counter D3 are used as data selection output terminals to output four different data selection signals.
[0014] Preferably, terminal 1 of the two-input NAND gate D2A serves as the input terminal of the reset signal. When the reset signal exists, the two-input NAND gate D2A outputs a low level, blocking the oscillation signal from being transmitted to the frequency division counter D3, and the output of the data selection output terminal is a high level.
[0015] Preferably, after the external control signals A and B connected to the data selector change, the extension time of the delay circuit can be changed, and the model of the data selector is 74LS151.
[0016] Preferably, the RS trigger includes a NAND gate D4 and a NAND gate D5;
[0017] The 8th terminal of the NAND gate D5 is used as the input terminal of the mode selection signal, the 2nd terminal of the NAND gate D5 is used as the input terminal of the reset signal, the 1st terminal of the NAND gate D4 is used as the input terminal of the data selection signal, the output terminal of the NAND gate D5 is connected to the 8th terminal of the NAND gate D4, and the output terminal of the NAND gate D4 is connected to the 1st terminal of the NAND gate D5.
[0018] Preferably, the logic output terminal includes a two-input NAND gate D6A and an XNOR gate D7A;
[0019] Terminal 1 of the two-input NAND gate D6A is used as the input terminal of the trigger signal, terminal 2 of the two-input NAND gate D6A is used as the input terminal of the reset signal, terminal 2 of the XNOR gate D7A is used as the access terminal of the output selection signal, and terminal 3 of the two-input NAND gate D6A is connected to terminal 1 of the XNOR gate D7A;
[0020] When the reset signal exists, the input of the output selection terminal is opposite to the output of the XOR gate D7A. When the reset signal disappears, the output signal of the XOR gate D7A jumps according to the change of the trigger signal.
[0021] Preferably, the output drive circuit includes a resistor R4, a resistor R5, a transistor and a MOS tube for amplifying the output signal of the logic output end, the base of the transistor is connected to the output end of the XOR gate D7A, the emitter of the transistor is grounded, resistors R4 and R5 are connected in series between the collector of the transistor and the external power supply, the gate of the MOS tube is connected between the resistors R4 and R5, and the source of the MOS tube is connected to the coil of the electromagnetic relay.
[0022] By means of the above technical solution, the present invention provides a multifunctional time relay implemented by hardware, which has at least the following beneficial effects:
[0023] 1. The present invention controls the MOS tube through a triode, so that the signal output by the logic output end of the delay circuit can be amplified by the MOS tube, and then drive the electromagnetic coil of the relay to move, avoiding the problem that the signal output by the logic output end cannot drive the electromagnetic coil, and then the coil cannot be moved, so that the time relay as a whole can work normally.
[0024] 2. The present invention can realize the mutual switching between multiple delay modes through the function of the delay circuit composed of a reset circuit, an oscillation frequency division circuit, a data selector, an RS trigger, and a logic output terminal. The smooth switching of the delay mode can be completed without the need for software programming of a microprocessor, which can save production materials and reduce the production cycle, and the software development cost and cycle are also greatly reduced.
[0025] 3. The present invention controls the overall frequency division coefficient of the delay circuit through a data selector in coordination with external control signals A and B, thereby adjusting the delay time of the delay circuit. The delay time can be changed at any time as needed, thereby increasing the use scenarios and flexibility of the time relay. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0027] Figure 1 A circuit structure block diagram of a multifunctional time relay realized by hardware of the present invention;
[0028] Figure 2 is a circuit diagram of a reset circuit of the present invention;
[0029] Figure 3 A circuit diagram of an oscillating frequency dividing circuit of the present invention;
[0030] Figure 4 A circuit diagram of an RS trigger of the present invention;
[0031] Figure 5 A circuit diagram of a logic output terminal of the present invention;
[0032] Figure 6 FIG. 4 is a circuit diagram of an output drive circuit of the present invention.
[0033] In the figure: 1. Reset circuit; 2. Oscillation frequency division circuit; 3. Data selector; 4. RS trigger; 5. Logic output terminal; 6. Output drive circuit. DETAILED DESCRIPTION
[0034] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods, so that the implementation process of how the present application uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.
[0035] Since the existing time relay cannot realize the switching between multiple delay modes, and the use of microprocessors is limited by occasions, please refer to Figure 1 - Figure 6The present embodiment provides a multifunctional time relay implemented by hardware, which can realize the switching between multiple delay modes through hardware and does not require the intervention of a microprocessor for control. The multifunctional time relay is formed by a delay circuit and an electromagnetic relay. The delay circuit includes: a reset circuit 1 for converting a high-level reset pulse signal of a power supply into a low-level reset signal. The reset circuit 1 is composed of a two-input NOR gate D1A and a resistor R1 and a capacitor C1. The capacitor C1 is connected in series between the power supply VDD and the two ends of the two-input NOR gate D1A. The resistor R1 is connected to the two ends of the two-input NOR gate D1A and is grounded. When a high-level reset control signal is input to terminal 1 of the two-input NOR gate D1A, a low-level reset signal is generated. When the power supply is powered on, a high-level reset pulse signal will appear at terminal 2 of D1A, causing a low-level reset pulse signal to appear in the NOR gate D1A. In particular, terminal 1 of the NOR gate D1A can be led out as a reset control signal. When a high-level signal is input to terminal 1, a low-level reset signal is generated through the reset circuit. The reset signal output by the reset circuit can control the oscillation frequency division circuit 2, the RS trigger 4 and the logic output terminal 5, thereby completing the switching of different delay functions under different input conditions.
[0036] Since the single frequency of the reset signal cannot be directly divided, to prevent problems such as the signal frequency being too high, please refer to Figure 3 , used for generating a square wave signal of a fixed frequency as a timing signal after power-on, and dividing the timing signal to form an oscillating frequency dividing circuit 2 with multiple different frequency dividing signals, the oscillating frequency dividing circuit 2 comprises two CMOS NOT gates, a current limiting resistor R2, a delay resistor R3, a capacitor Ct, a two-input NAND gate D2A and a frequency dividing counter D3, the two CMOS NOT gates, the current limiting resistor R2 and the capacitor Ct are connected in series and then connected to the 2nd end of the two-input NAND gate D2A, the delay resistor R3 is connected between the two CMOS NOT gates and in parallel with the current limiting resistor R2, the 3rd end of the two-input NAND gate D2A is connected to the CK1 port of the frequency dividing counter D3, and the Q4 end, Q7 end, Q10 end and Q14 end of the frequency dividing counter D3 are used as data selection. The output terminal outputs four different data selection signals. The 1 terminal of the two-input NAND gate D2A is used as the input terminal of the reset signal. When the reset signal exists, the two-input NAND gate D2A outputs a low level, blocking the oscillation signal from being transmitted to the frequency division counter D3. At the same time, the output of the data selection output terminal is a high level. When the circuit is powered on, the oscillation circuit starts to work and generates a square wave signal of a certain frequency as a timing signal, which is sent to the frequency division counter D3 for frequency division. The four frequency division signals of the frequency division counter D3 are sent to the data selection circuit. The four combinations of 00, 01, 10, and 11 enable the data selection circuit to select one of the four frequency division signals, thereby realizing programmable frequency division counting. As far as the present invention is concerned, the data selection output realizes 2 division of the oscillator signal. 4 , 2 7 , 210 , 2 14 Frequency division, data selection output initially outputs a high level, and generates an oscillation signal through the oscillation circuit in the oscillation frequency division circuit 2, which can enable the two-input NAND gate D2A to output an electrical signal and perform frequency division, thereby completing the frequency division of the original electrical signal and reducing the signal frequency.
[0037] After frequency division, you need to select one frequency output from multiple frequency division signals. To solve this problem, please refer to Figure 3 This embodiment provides a data selection signal for selecting one of the multiple frequency division signals output from the oscillation frequency division circuit 2 according to the external control signals A and B to realize programmable frequency division counting, and outputs a high level data selector 3 when the reset signal exists. The data selector 3 is connected to the external control signals A and B. When the external control signals A and B change, the extension time of the delay circuit can be changed. The model of the data selector 3 is 74LS151. Through the signal selection function of the data selector 3, one of the multiple frequency division signals can be selected as the output signal, thereby improving the quality of the signal output.
[0038] Since the existing time relay cannot realize the switching between multiple delay modes, and the use of microprocessors is limited by occasions, please refer to Figure 4 The present embodiment proposes a delay circuit for a time relay for cyclic delay, action delay, or time-limited timing according to "0" or "1" selected in mode, and outputs an RS trigger 4 for a trigger signal. The RS trigger 4 includes three input signals of mode selection, data selection output, and reset output. The RS trigger 4 includes a NAND gate D4 and a NAND gate D5. The 8th terminal of the NAND gate D5 is used as the input terminal of the mode selection signal, the 2nd terminal of the NAND gate D5 is used as the input terminal of the reset signal, the 1st terminal of the NAND gate D4 is used as the input terminal of the data selection signal, the output terminal of the NAND gate D5 is connected to the 8th terminal of the NAND gate D4, and the output terminal of the NAND gate D4 is connected to the 1st terminal of the NAND gate D5. If the mode selection is "0", when a low-level reset signal exists, the output of D5 is high, the data selection output is high, and the trigger output is low; after the reset signal disappears, the trigger output state is opposite to the data selection output; this structure can be used as a delay circuit for a time relay for cyclic delay. If the mode is selected as "1", after the trigger output state becomes high for the first time, the output of D5 changes from high level to low level, and then locks the trigger output state to maintain the high level unchanged after the first time it becomes high, and is not affected by the oscillation signal. This structure can be used as a delay circuit for a time relay with action delay and time limit timing. Through the delay circuit composed of the RS trigger, it can realize mutual switching between multiple delay modes, and can complete smooth switching of delay modes without software programming of the microprocessor, which can save production materials and reduce production cycle, and the software R&D cost and cycle are also greatly reduced.
[0039] Since the output signal needs to be combined with the reset signal, trigger signal and output selection signal and perform logic operation before output, please refer to Figure 5 The present embodiment proposes a logic output terminal 5 for controlling the data selector 3 to output "0" or "1" when the reset signal exists, and for controlling the RS trigger 4 to output "0" or "1" after the reset signal disappears. The logic output terminal 5 includes three input terminals of trigger output, reset output and output selection, which are respectively used for inputting the trigger signal, the reset signal and the data selection signal. The logic output terminal 5 includes a two-input NAND gate D6A and an XOR gate D7A. Terminal 1 of the two-input NAND gate D6A is used as the input terminal of the trigger signal, and terminal 2 of the two-input NAND gate D6A is used as the input terminal of the reset signal. The XOR gate D7A is used as the input terminal of the reset signal. Terminal 2 of NOT gate D7A is used as the access terminal of the output selection signal, and terminal 3 of the two-input NAND gate D6A is connected to terminal 1 of XNOR gate D7A. When the reset signal exists, the input of the output selection terminal is opposite to the output of XNOR gate D7A. When the reset signal disappears, the output signal of XNOR gate D7A jumps according to the change of the trigger signal. If the output selection terminal is "0", the output of NAND gate D6A after reset is "1", and the output of XNOR gate D7A is "0"; if the output selection terminal is "1", the output of NAND gate D6A after reset is "0", and the output of XNOR gate D7A is "1". After the reset signal disappears, the output state of XNOR gate D7A is determined by the output of the trigger. If the output of the trigger is "1", the output of NOT gate D6A is "0". At this time, no matter whether the output selection terminal is "0" or "1", the output of XNOR gate D7A will jump. The output of the trigger is "0", and the same conclusion applies. The reset signal, trigger signal, and output selection signal can be logically operated through the logic output terminal, so that the output signal meets subsequent needs.
[0040] Since the XOR output of the delay circuit cannot directly drive the coil of the electromagnetic relay, please refer to Figure 6 This embodiment provides an output drive circuit 6 for driving the coil of an electromagnetic relay. The output drive circuit 6 includes a resistor R4, a resistor R5, a transistor and a MOS tube for amplifying the output signal of the logic output terminal 5. The base of the transistor is connected to the output terminal of the XOR gate D7A, the emitter of the transistor is grounded, the resistors R4 and R5 are connected in series between the collector of the transistor and the external power supply, the gate of the MOS tube is connected between the resistors R4 and R5, the source of the MOS tube is connected to the coil of the electromagnetic relay, and the MOS tube is controlled by the transistor so that the signal output from the logic output terminal of the delay circuit can be amplified by the MOS tube, thereby driving the electromagnetic coil of the relay to move, thereby avoiding the problem that the signal output from the logic output terminal cannot drive the electromagnetic coil, thereby failing to move the coil, and enabling the time relay to work normally as a whole.
[0041] The above implementation methods have been described in detail. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A multifunctional time relay realized by hardware, which is formed by combining a delay circuit and an electromagnetic relay, characterized in that: The delay circuit includes: A reset circuit (1), the reset circuit (1) being used to convert a reset pulse signal of a high level of a power supply into a reset signal of a low level; An oscillating frequency dividing circuit (2), the oscillating frequency dividing circuit (2) being used to generate a square wave signal of a fixed frequency as a timing signal after power-on, and to divide the timing signal into a plurality of different divided frequency signals; A data selector (3), the data selector (3) is connected to external control signals A and B, and the data selector (3) selects one of the multiple frequency division signals output by the oscillation frequency division circuit (2) according to the external control signals A and B to realize the data selection signal of programmable frequency division counting, and outputs a high level when a reset signal exists; An RS trigger (4), the RS trigger (4) comprising three input signals of mode selection, data selection output and reset output, and serving as a delay circuit of a time relay for cycle delay, action delay or time-limit timing according to "0" or "1" selected by the mode, and outputting a trigger signal; A logic output terminal (5) of the delay circuit, the logic output terminal (5) comprising three input terminals of a trigger output, a reset output and an output selection, for inputting a trigger signal, a reset signal and a data selection signal respectively; when the reset signal is present, the logic output terminal (5) is controlled by the data selector (3) to output "0" or "1", and after the reset signal disappears, the logic output terminal (5) is controlled by the RS trigger (4) to output "0" or "1"; An output drive circuit (6), wherein the output drive circuit (6) is used to drive the coil of the electromagnetic relay.
2. A hardware-implemented multifunctional time relay according to claim 1, characterized in that: The reset circuit (1) is composed of a two-input NOR gate D1A, a resistor R1 and a capacitor C1. The capacitor C1 is connected in series between a power supply VDD and two ends of the two-input NOR gate D1A. The resistor R1 is connected to two ends of the two-input NOR gate D1A and is grounded. When a high-level reset control signal is input to one end of the two-input NOR gate D1A, a low-level reset signal is generated.
3. A hardware-implemented multifunctional time relay according to claim 1, characterized in that: The oscillating frequency division circuit (2) comprises two CMOS NOT gates, a current limiting resistor R2, a delay resistor R3, a capacitor Ct, a two-input NAND gate D2A and a frequency division counter D3; Two CMOS NOT gates, a current limiting resistor R2, and a capacitor Ct are connected in series and then connected to the 2nd terminal of a two-input NAND gate D2A. A delay resistor R3 is connected between the two CMOS NOT gates and in parallel with the current limiting resistor R2. The 3rd terminal of the two-input NAND gate D2A is connected to the CK1 port of a frequency dividing counter D3. The Q4, Q7, Q10, and Q14 terminals of the frequency dividing counter D3 are used as data selection output terminals to output four different data selection signals.
4. A hardware-implemented multifunctional time relay according to claim 3, characterized in that: Terminal 1 of the two-input NAND gate D2A serves as the input terminal of the reset signal. When the reset signal is present, the two-input NAND gate D2A outputs a low level, blocking the oscillation signal from being transmitted to the frequency division counter D3, and the output of the data selection output terminal is a high level.
5. A hardware-implemented multifunctional time relay according to claim 1, characterized in that: After the external control signals A and B connected to the data selector (3) change, the extension time of the delay circuit can be changed. The model of the data selector (3) is 74LS151.
6. A hardware-implemented multifunctional time relay according to claim 1, characterized in that: The RS trigger (4) comprises a NAND gate D4 and a NAND gate D5; The 8th terminal of the NAND gate D5 is used as the input terminal of the mode selection signal, the 2nd terminal of the NAND gate D5 is used as the input terminal of the reset signal, the 1st terminal of the NAND gate D4 is used as the input terminal of the data selection signal, the output terminal of the NAND gate D5 is connected to the 8th terminal of the NAND gate D4, and the output terminal of the NAND gate D4 is connected to the 1st terminal of the NAND gate D5.
7. A hardware-implemented multifunctional time relay according to claim 1, characterized in that: The logic output terminal (5) includes a two-input NAND gate D6A and an XNOR gate D7A; Terminal 1 of the two-input NAND gate D6A is used as the input terminal of the trigger signal, terminal 2 of the two-input NAND gate D6A is used as the input terminal of the reset signal, terminal 2 of the XNOR gate D7A is used as the access terminal of the output selection signal, and terminal 3 of the two-input NAND gate D6A is connected to terminal 1 of the XNOR gate D7A; When the reset signal exists, the input of the output selection terminal is opposite to the output of the XOR gate D7A. When the reset signal disappears, the output signal of the XOR gate D7A jumps according to the change of the trigger signal.
8. A hardware-implemented multifunctional time relay according to claim 1, characterized in that: The output drive circuit (6) comprises a resistor R4, a resistor R5, a transistor and a MOS transistor for amplifying an output signal of a logic output terminal (5), the base of the transistor being connected to the output terminal of an XOR gate D7A, the emitter of the transistor being grounded, resistors R4 and R5 being connected in series between the collector of the transistor and an external power supply, the gate of the MOS transistor being connected between the resistors R4 and R5, and the source of the MOS transistor being connected to the coil of an electromagnetic relay.