Circuit board and manufacturing method thereof

Abstract

The invention provides a circuit board comprising an embedded capacitor, a substrate and an insulating layer. The embedded capacitor comprises a dielectric layer, a first electrode and a second electrode, the first electrode and the second electrode are paired, the dielectric layer is provided with a first side surface, a second side surface adjacent to the first side surface, a third side surface opposite to the first side surface and a fourth side surface opposite to the second side surface, and the first electrode and the second electrode respectively cover the first side surface and the third side surface. The substrate surrounds the embedded capacitor, the substrate is physically connected to the second side face and the fourth side face of the dielectric layer, and the first electrode is located between the first side face and the side wall of the substrate. The insulating layer wraps the embedded capacitor and the substrate, wherein the insulating layer extends from the upper surface of the substrate to the lower surface of the substrate along the first electrode and the side wall of the substrate. The embedded capacitor is provided with a dielectric layer which is physically connected with the substrate, so that the position accuracy is improved, and the component integration degree of the circuit board is improved by reducing the size of the embedded capacitor through process combination.

Description

Technical Field

[0001] The present disclosure relates to circuit boards and methods of manufacturing the same, and more particularly to circuit boards including embedded capacitors. Background Art

[0002] The circuit board process usually uses embedded pressing to combine embedded capacitors into the circuit board. However, when the size of the embedded capacitor is very small, the embedded capacitor is easily impacted by the flowing material during the pressing process and deviates, resulting in abnormal function or failure of the circuit board. In addition, small-sized embedded capacitors often have small-sized pads, which makes it more difficult to electrically connect the circuit layer in the circuit board with the embedded capacitor. Summary of the invention

[0003] In order to solve the above problems, the present disclosure provides a circuit board including an embedded capacitor and a manufacturing method thereof, which can manufacture the embedded capacitor with precise position by a simplified process, thereby improving the reliability and component integration of the circuit board.

[0004] According to one embodiment of the present disclosure, a circuit board includes a first embedded capacitor, a substrate, and an insulating layer. The first embedded capacitor includes a dielectric layer and a pair of first and second electrodes, wherein the dielectric layer has a first side, a second side adjacent to the first side, a third side relative to the first side, and a fourth side relative to the second side, and the first electrode and the second electrode cover the first side and the third side, respectively. The substrate surrounds the first embedded capacitor, wherein the substrate is physically connected to the second side and the fourth side of the dielectric layer, and the first electrode is located between the first side and the side wall of the substrate. The insulating layer covers the first embedded capacitor and the substrate, wherein the insulating layer extends from the upper surface of the substrate to the lower surface of the substrate along the first electrode and the side wall.

[0005] In some embodiments, the substrate and the dielectric layer are integrally formed.

[0006] In some embodiments, the dielectric layer has an upper surface connecting the first side surface and the second side surface, and the upper surface of the substrate and the upper surface of the dielectric layer are coplanar.

[0007] In some embodiments, the first electrode includes a first pad on the dielectric layer, a second pad under the dielectric layer, and a plate physically connecting the first pad and the second pad.

[0008] In some embodiments, the first electrode includes a first pad on the dielectric layer, the second electrode includes a second pad on the dielectric layer, and the second pad and the first pad are separated from each other.

[0009] In some embodiments, the circuit board further includes a second embedded capacitor, wherein the second embedded capacitor includes a dielectric layer and a pair of third and fourth electrodes, and the length of the dielectric layer of the second embedded capacitor located between the third electrode and the fourth electrode is different from the length of the dielectric layer of the first embedded capacitor located between the first electrode and the second electrode.

[0010] According to one embodiment of the present disclosure, a method for manufacturing a circuit board includes the following steps. An initial substrate is provided. A first opening process is performed on the initial substrate to form a pair of openings, a dielectric layer located between the pair of openings, and a substrate physically connected to the dielectric layer, wherein the dielectric layer has a pair of side surfaces facing the pair of openings and opposite to each other. A conductive layer is formed on the substrate, on the dielectric layer, and in the pair of openings. A mask is formed on the conductive layer, wherein the mask at least shields the pair of openings. The conductive layer is etched using the mask to expose the dielectric layer and the substrate, and the conductive layer located in the pair of openings is retained. After etching the conductive layer using the mask, the mask is removed. After removing the mask, the conductive layer located on the pair of side surfaces of the dielectric layer is retained, and other conductive layers located outside the pair of side surfaces in the pair of openings are removed.

[0011] In some embodiments, the step of forming a mask on the conductive layer includes masking a conductive portion of the conductive layer located on the dielectric layer with the mask, and after removing the mask, further includes retaining the conductive portion located on the dielectric layer.

[0012] In some embodiments, the step of removing other conductive layers in the pair of openings located outside the pair of side surfaces includes performing a second opening process along the pair of openings to expand the pair of openings in a direction away from the pair of side surfaces, wherein the first opening process and the second opening process use the same process steps.

[0013] In some embodiments, forming a mask on the conductive layer includes masking a conductive portion of the conductive layer with the mask, wherein the conductive portion is located on a substrate portion of the substrate, and performing a second opening process includes removing the conductive portion and the substrate portion.

[0014] According to the above-mentioned embodiments, the circuit board disclosed herein includes an embedded capacitor and a substrate formed using an opening process and a mask etching process. The substrate is physically connected to the dielectric layer of the embedded capacitor, thereby improving the positional accuracy of the embedded capacitor and the reliability of the circuit board. Forming the dielectric layer of the embedded capacitor through the opening process can reduce the size of the embedded capacitor, thereby improving the component integration of the circuit board, and embedded capacitors of various sizes and arrangements can be manufactured at the same time. The electrodes of the embedded capacitor are formed through a mask etching process, so that the electrode pads can be manufactured independently to reduce the offset between the electrode pads and other components. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0016] Figure 1 A cross-sectional view of a circuit board is shown according to one embodiment of the present disclosure.

[0017] Figure 2A and Figure 2B Draw Figure 1 Top view and cross-sectional view of the embedded capacitor and substrate.

[0018] 3A to 3T Some embodiments according to the present disclosure illustrate multiple views of a circuit board at various intermediate stages of the manufacturing process.

[0019] Figure 4 A top view of a circuit board is shown according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] In order to realize the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc. are described below to simplify the disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

[0023] The present disclosure provides a circuit board including an embedded capacitor and a manufacturing method thereof, wherein the dielectric layer of the embedded capacitor is physically connected to the substrate, thereby improving the position accuracy of the embedded capacitor and the reliability of the circuit board. The dielectric layer of the embedded capacitor is formed by a hole opening process, and the electrode of the embedded capacitor is formed by a mask etching process, so that the size (e.g., volume) of the embedded capacitor can be reduced to improve the component integration of the circuit board, and the electrode pad can be independently manufactured according to design requirements to reduce the offset between components.

[0024] According to one embodiment of the present disclosure, Figure 1 A cross-sectional view of the circuit board 10 is shown. In order to clearly describe the components included in the circuit board 10, Figure 1 Only some components of the circuit board 10 are shown, but a circuit board including additional components (such as a seed layer under the conductive layer, a system board electrically connected to the circuit board, etc.) is also within the scope of the present disclosure.

[0025] refer to Figure 1 , the circuit board 10 includes an embedded capacitor 100, a substrate 200, an insulating layer 300 and a contact 400. The embedded capacitor 100 and the substrate 200 are located together in the insulating layer 300, so the embedded capacitor 100 and the substrate 200 can be regarded as components of the same level. For example, the embedded capacitor 100 and the substrate 200 can be located in the same plane. Further, the substrate 200 is physically connected to the embedded capacitor 100, so that the embedded capacitor 100 can be accurately fixed at a specified position in the insulating layer 300. Therefore, when the contact 400 extends into the insulating layer 300 and is electrically connected to the embedded capacitor 100, the risk of the contact 400 and the embedded capacitor 100 forming an offset conductive path can be reduced, thereby improving the reliability of the circuit board 10.

[0026] In order to more clearly describe the relationship between the embedded capacitor 100 and the substrate 200, Figure 2A Draw Figure 1 A top view of the embedded capacitor 100 and the substrate 200, Figure 2B Draw along Figure 2A Cross-section along the midline AA′. Figures 1 to 2BThe embedded capacitor 100 includes a dielectric layer 110 and a pair of a first electrode 120 and a second electrode 130. The dielectric layer 110 has a first side surface 110a, a second side surface 110b adjacent to the first side surface 110a, a third side surface 110c relative to the first side surface 110a, a fourth side surface 110d relative to the second side surface 110b, an upper surface 110t connecting the first side surface 110a to the fourth side surface 110d, and a lower surface 110u connecting the first side surface 110a to the fourth side surface 110d.

[0027] although Figures 1 to 2B The dielectric layer 110 is shown as a rectangular parallelepiped with straight edges, but in other embodiments, the dielectric layer 110 may have curved edges, a cube shape, a trapezoidal shape, or other shapes. When the dielectric layer 110 has a trapezoidal shape, the first side surface 110a and the third side surface 110c are both inclined surfaces.

[0028] The first electrode 120 covers the first side surface 110a, and the second electrode 130 covers the third side surface 110c, so after a voltage is applied to the first electrode 120 and the second electrode 130, the dielectric layer 110 between the first electrode 120 and the second electrode 130 can store electrical energy. More specifically, the first electrode 120 includes a plate 122 on the first side surface 110a, a first pad 124 on the upper surface 110t, and a second pad 126 on the lower surface 110u. The plate 122 physically connects the first pad 124 on the dielectric layer 110 and the second pad 126 under the dielectric layer 110, so that the first electrode 120 extends continuously from the upper surface 110t along the first side surface 110a to the lower surface 110u.

[0029] Similarly, the second electrode 130 includes a plate 132 on the third side surface 110c, a first pad 134 on the upper surface 110t, and a second pad 136 on the lower surface 110u. The first pads 124 and the first pads 134 are separated from each other, and the second pads 126 and the second pads 136 are separated from each other. In some embodiments, the separation distance D1 between the first pads 124 and the first pads 134 in the x-direction may be the same as the separation distance D2 between the second pads 126 and the second pads 136 in the x-direction.

[0030] The first pad 124 of the first electrode 120 may extend along the x-direction toward the second electrode 130 on the upper surface 110t. Figure 2ASimilarly, the first pad 134 of the second electrode 130 may extend toward the first electrode 120 and have a length W1 in the x-direction. In some embodiments, the embedded capacitor 100 may be composed of the dielectric layer 110, the first electrode 120, and the second electrode 130, such that the total length of the embedded capacitor 100 in the x-direction is the sum of twice the length W1 and the spacing D1.

[0031] The first electrode 120 may completely cover the first side surface 110a, so that the width of the first electrode 120 is close to the width of the dielectric layer 110. Figure 2A As shown, the opposite edges of the first electrode 120 can be aligned with the second side 110b and the fourth side 110d of the dielectric layer 110, respectively, so that the first electrode 120 and the dielectric layer 110 have a width W2 in the y direction. In some embodiments, the electrode plate 122, the first liner 124, and the second liner 126 can have the same width W2, so that the first electrode 120 has a uniform width as a whole. In such an embodiment, Figure 2A As shown, the area of ​​the first pad 124 on the upper surface 110 t may be length W1×width W2 , but the present disclosure is not limited thereto.

[0032] The substrate 200 surrounds the embedded capacitor 100 and is physically connected to the embedded capacitor 100, so that the embedded capacitor 100 can be fixed at a position on the same layer as the substrate 200. Specifically, the substrate 200 is physically connected to the second side surface 110b and the fourth side surface 110d of the dielectric layer 110, so that the dielectric layer 110 is fixed in the y direction by the substrate 200. Since the substrate 200 is directly connected to the two opposite sides of the dielectric layer 110, the dielectric layer 110 can form a stable structure with the substrate 200, that is, the dielectric layer 110 can be firmly fixed in the substrate 200 to reduce or inhibit the relative movement between the dielectric layer 110 and the substrate 200, thereby avoiding the position deviation of the embedded capacitor 100.

[0033] It is worth noting that the dielectric layer 110 is connected to the substrate 200 at the second side surface 110b and the fourth side surface 110d, but in fact there is no interface or seam between the dielectric layer 110 and the substrate 200. Specifically, the dielectric layer 110 and the substrate 200 are continuous dielectric material layers, wherein the dielectric material layer between the first electrode 120 and the second electrode 130 serves as the dielectric layer 110 of the embedded capacitor 100, and the dielectric material layer surrounding the embedded capacitor 100 serves as the substrate 200. In other words, the substrate 200 and the dielectric layer 110 can be integrally formed into one piece, so that the directly connected substrate 200 and the dielectric layer 110 have the same material composition.

[0034] In some embodiments, the upper surface 200t and the lower surface 200u of the substrate 200 may be coplanar with the upper surface 110t and the lower surface 110u of the dielectric layer 110, respectively, so that the substrate 200 is physically connected to the second side surface 110b and the fourth side surface 110d of the whole, thereby providing a stable connection between the substrate 200 and the dielectric layer 110. Figure 2B As shown, the dielectric layer 110 and the substrate 200 can be continuous dielectric material layers with uniform thickness, wherein the thickness T1 of the dielectric layer 110 in the z-direction is the same as the thickness T2 of the substrate 200 in the z-direction. For example, the thickness T1 of the dielectric layer 110 and the thickness T2 of the substrate 200 can be as small as 40 microns and still have a stable connection.

[0035] The substrate 200 may be separated from the first side surface 110a and the third side surface 110c of the dielectric layer 110, so that at least two accommodation spaces can be formed between the substrate 200 and the dielectric layer 110. Figure 2A and Figure 2B As shown, there may be a pair of openings 210 a and 210 b between the substrate 200 and the dielectric layer 110 , and the first electrode 120 and the second electrode 130 may be located in the openings 210 a and 210 b respectively, so that the first electrode 120 and the second electrode 130 may be located between the substrate 200 and the dielectric layer 110 .

[0036] The opening 210a extends from the upper surface 200t of the substrate 200 to the lower surface 200u of the substrate 200, so that the first side surface 110a of the dielectric layer 110 and the side wall 200a of the substrate 200 are located on opposite sides of the opening 210a. Similarly, the opening 210b extends the substrate 200 and separates the third side surface 110c of the dielectric layer 110 and the side wall 200c of the substrate 200 on opposite sides of the opening 210b.

[0037] The first electrode 120 extends along the opening 210a and covers the first side surface 110a of the dielectric layer 110, so that the electrode plate 122 is located between the first side surface 110a and the side wall 200a, and the electrode plate 122 and the side wall 200a are separated from each other in the x-direction. Similarly, the electrode plate 132 of the second electrode 130 is located between the third side surface 110c and the side wall 200c, and the electrode plate 132 and the side wall 200c are separated from each other. In some embodiments, the separation distance between the electrode plate 132 and the side wall 200c in the x-direction can be the same as the separation distance D3 between the electrode plate 122 and the side wall 200a. Although FIG. 2A to FIG. 2B The openings 210a and 210b are shown as rectangular shapes with straight sidewalls, but in other embodiments, the openings 210a and 210b may have curved sidewalls, tapered sidewalls, cubic shapes, cylindrical shapes, or other shapes.

[0038] Reference Figure 1 , the insulating layer 300 covers the embedded capacitor 100 and the substrate 200, so that the embedded capacitor 100 and the substrate 200 are located together in the insulating layer 300. Specifically, the insulating layer 300 covers the upper surface 110t and the lower surface 110u of the dielectric layer 110, the first electrode 120, the second electrode 130, and the upper surface 200t and the lower surface 200u of the substrate 200. Further, the insulating layer 300 extends from the upper surface 200t of the substrate 200 to the lower surface 200u of the substrate 200 along the electrode plate 122 of the first electrode 120 and the side wall 200a of the substrate 200, and the insulating layer 300 extends from the upper surface 200t of the substrate 200 to the lower surface 200u of the substrate 200 along the electrode plate 132 of the second electrode 130 and the side wall 200c of the substrate 200. In other words, the insulating layer 300 fills Figure 2B The illustrated opening 210 a is between the first electrode 120 and the side wall 200 a and the opening 210 b is between the second electrode 130 and the side wall 200 c .

[0039] The contact 400 is disposed in the insulating layer 300, wherein the contact 400 extends toward the embedded capacitor 100 and is electrically connected to the first electrode 120 and the second electrode 130. For example, a plurality of contacts 400 may extend from the outer surface of the insulating layer 300 and contact the first pad 124, the second pad 126, the first pad 134, and the second pad 136. In some embodiments, the contact 400 may directly contact the first pad 124, the second pad 126, the first pad 134, and the second pad 136, wherein the contact 400 is aligned with the above-mentioned individual pads, thereby forming a conductive path in which the contact 400 is aligned with the first electrode 120 or the second electrode 130.

[0040] According to some embodiments of the present disclosure, 3A to 3T Multiple views of a circuit board at various intermediate stages of the manufacturing process are shown. Figure 3A , Figure 3C , Figure 3E , Figure 3H , Figure 3K , Figure 3N and Figure 3Q Drawings showing top views of the PCB at various intermediate stages of the manufacturing process. Figure 3B , Figure 3D , Figure 3F , Fig. 3I , Figure 3L , Fig.3O , Figure 3R and Figure 3T A cross-sectional view of the circuit board along line AA′ in the top view of the manufacturing process is shown. Figure 3G , Figure 3J , Figure 3M , Figure 3P and Figure 3S A cross-sectional view of the circuit board along line BB′ in the top view of the manufacturing process is shown. 3A to 3T The fabrication method depicted can be used to form, for example, Figures 1 to 2B The circuit board 10 described above, however, those skilled in the art should understand that the circuit board manufacturing method disclosed herein can also be used to form other circuit boards within the scope of the disclosure including embedded capacitors.

[0041] It is worth noting that unless otherwise stated, 3A to 3T When a series of steps are depicted or described as an embodiment, the order in which the steps are described should not be limiting. For example, some steps may be performed in a different order than the embodiment described, some steps may occur simultaneously, some steps may not be required, and / or some steps may be repeated. In addition, additional steps may be performed before, during, or after the depicted steps to fully form the circuit board.

[0042] refer to FIG. 3A to FIG. 3B , providing an initial substrate 20. Specifically, the initial substrate 20 includes at least one dielectric material layer, wherein the dielectric material layer is used to form a dielectric layer of an embedded capacitor and a substrate connected to the embedded capacitor in subsequent steps. For example, the dielectric material layer may include silicon, ceramic, glass, epoxy resin glass, graphene oxide or other dielectric materials suitable for capacitors, wherein the ceramic may include BaTiO 3 、CaTiO 3 、SrTiO 3 or CaZrO 3 .

[0043] In some embodiments, the initial substrate 20 may further include a conductive film (not specifically shown) on the dielectric material layer. Figures 3E to 3G When a conductive layer 500 is subsequently formed on the conductive film, the conductive film can improve the integrity and stability of the conductive layer. The conductive film can be a metal film, and the metal type contained in the conductive film can be the same or similar to the metal type contained in the subsequent conductive layer. For example, when the subsequent conductive layer includes copper metal, titanium / copper can be used as the material of the conductive film. In some examples, the conductive film can also be used as a seed layer for electroplating.

[0044] refer to FIG. 3C to FIG. 3D, a first opening process is performed on the initial substrate 20 to form a pair of openings 210a and openings 210b, a dielectric layer 110 located between the openings 210a and the openings 210b, and a substrate 200 physically connected to the dielectric layer 110. Specifically, the first opening process forms the openings 210a and the openings 210b extending from the upper surface of the initial substrate 20 to the lower surface of the initial substrate 20, wherein the openings 210a and the openings 210b are aligned with each other in the x-direction, so that the initial substrate 20 can be divided into the dielectric layer 110 between the openings 210a and the openings 210b and the substrate 200 surrounding the dielectric layer 110 along the edges of the openings 210a and the openings 210b.

[0045] After the opening 210a and the opening 210b are formed, the dielectric layer 110 has a first side surface 110a and a third side surface 110c opposite to each other, wherein the first side surface 110a faces the opening 210a and the side wall 200a of the substrate 200, and the third side surface 110c faces the opening 210b and the side wall 200c of the substrate 200. The dielectric layer 110 also has a second side surface 110b and a fourth side surface 110d opposite to each other, wherein the second side surface 110b and the fourth side surface 110d are physically connected to the substrate 200. Since the dielectric layer 110 and the substrate 200 are two elements divided by the opening 210a and the opening 210b, there is substantially no interface or seam at the connection between the dielectric layer 110 and the substrate 200.

[0046] The opening 210a and the opening 210b divide the area between the two openings into the dielectric layer 110 of the embedded capacitor. The distance between the opening 210a and the opening 210b in the x direction can define the length of the dielectric layer 110 in the x direction, and the distance between the opening 210a and the opening 210b in the y direction can define the width of the dielectric layer 110 in the y direction. In other words, the opening 210a and the opening 210b can define the size (e.g., volume) of the dielectric layer 110 of the embedded capacitor. Therefore, if a high-precision opening process is used to form the opening 210a and the opening 210b of small size (e.g., width in the x direction or y direction), the dielectric layer 110 and the subsequently formed embedded capacitor can have a small volume accordingly. For example, the first opening process can be laser drilling, routing, punching, or other suitable opening processes.

[0047] refer to Figures 3E to 3G , a conductive layer 500 is formed on the substrate 200, on the dielectric layer 110, in the opening 210a and in the opening 210b. Specifically, the conductive layer 500 is formed on FIG. 3C to FIG. 3D1 , the conductive layer 500 is formed on the structure shown in the figure, thereby covering the upper surface 200t of the substrate 200, the lower surface 200u of the substrate 200, the upper surface 110t of the dielectric layer 110, and the lower surface 110u of the dielectric layer 110. The conductive layer 500 is also formed in the openings 210a and 210b to cover the exposed surfaces in the openings, such as the sidewall 200a, sidewall 200b, and sidewall 200d of the substrate 200 in the opening 210a, and the first side surface 110a of the dielectric layer 110 in the opening 210a. Similarly, the conductive layer 500 also covers the exposed surface of the opening 210b including the sidewall 200c and the third side surface 110c.

[0048] In some embodiments, the formation of the conductive layer 500 may be conformal, so that the horizontal portion (e.g., the conductive layer 500 on the upper surface 110t) and the vertical portion (e.g., the conductive layer 500 on the first side 110a) of the conductive layer 500 have similar thicknesses. For example, the conductive layer 500 may be formed by evaporation, sputtering, electroplating, electroless plating, or other suitable deposition techniques to form a conductive material including, for example, copper metal. In some examples, the conductive layer 500 in the openings 210a and 210b may be formed by a through-hole plating (PTH) technique of a circuit board manufacturing process.

[0049] In some embodiments, after the conductive layer 500 is formed in the openings 210a and 210b, the conductive layer 500 does not fill the openings 210a and 210b, so that gaps remain in the openings 210a and 210b, respectively. Figure 3F As shown, the thickness of the conductive layer 500 may be smaller than the width of the openings 210a and 210b in the x-direction, so the remaining opening 210a separates the conductive layer 500 covering the first side surface 110a from the conductive layer 500 covering the sidewall 200a.

[0050] refer to Figures 3H to 3J , a mask 600 is formed on the conductive layer 500 to shield the conductive layer 500 in the opening 210a and the opening 210b. Specifically, the mask 600 is formed on the conductive layer 500 on the upper surface 110t and the upper surface 200t, and the mask 600 is formed on the conductive layer 500 on the lower surface 110u and the lower surface 200u, so that both ends of the opening 210a and the opening 210b are shielded by the mask 600. For example, forming the mask 600 may include forming a photoresist material (e.g., a dry film) on the conductive layer 500, and patterning the photoresist material through steps such as exposure and development, thereby forming a mask 600 that completely shields the opening 210a and the opening 210b.

[0051] Since the mask 600 shields the openings 210a and 210b, in the subsequent etching process, the portion of the conductive layer 500 located in the openings 210a and 210b may remain unetched. In the embodiment where the conductive layer 500 does not fill the openings 210a and 210b, the surface of the mask 600 contacting the conductive layer 500 may be parallel to the upper surface 110t of the dielectric layer 110, so that the mask 600 does not fill the openings 210a and 210b and the gaps in the openings 210a and 210b are retained.

[0052] In addition to shielding the openings 210a and 210b, the mask 600 can also shield a portion of the conductive layer 500 located on the upper surface 110t and the lower surface 110u of the dielectric layer 110. In subsequent processes, the shielded portions of the conductive layer 500 on the dielectric layer 110 will form electrode portions of the embedded capacitor, and the relevant details will be described in detail below. In addition, the mask 600 can also shield a portion of the conductive layer 500 located on the upper surface 200t and the lower surface 200u of the substrate 200. In some embodiments, the shielded portions of the conductive layer 500 on the substrate 200 will be removed later, such as Figure 3Q to Figure 3S As shown, in some other embodiments, the shielded portion of the conductive layer 500 on the substrate 200 can be used as an electrode portion of other embedded capacitors.

[0053] refer to Figures 3K to 3M , an etching process is performed on the conductive layer 500 using the mask 600 to remove a portion of the conductive layer 500 and expose the dielectric layer 110 and the substrate 200. Specifically, an etching process such as wet etching can be performed on the conductive layer 500, and the etching process is stopped at the surface of the dielectric layer 110 and the substrate 200, thereby retaining a portion of the conductive layer 500 shielded by the mask 600. In some other embodiments, the etching process can be an etching process that is selective to metal materials, so that the conductive layer 500 that is not shielded by the mask 600 can be etched.

[0054] Since the mask 600 shields the openings 210a and 210b, the portion of the conductive layer 500 located in the openings 210a and 210b may remain after the etching process. In the embodiment where the mask 600 shields the conductive layer 500 on the dielectric layer 110, the portion of the conductive layer 500 on the dielectric layer 110 may also remain after the etching process. Figure 3LAs shown, the conductive layer 500 retained in the opening 210a and on the first side surface 110a will serve as the plate 122 of the first electrode 120, the conductive layer 500 retained on the upper surface 110t will serve as the first pad 124 of the first electrode 120, and the conductive layer 500 retained on the lower surface 110u will serve as the second pad 126 of the first electrode 120. Similarly, the conductive layer 500 retained in the opening 210b, on the upper surface 110t and on the lower surface 110u will serve as the plate 132, the first pad 134 and the second pad 136 of the second electrode 130. In other words, etching the conductive layer 500 using the mask 600 can define the pattern and size (e.g., length and width) of the first electrode 120 and the second electrode 130 of the embedded capacitor.

[0055] In the embodiment where the mask 600 shields the conductive layer 500 on the substrate 200, a portion of the conductive layer 500 on the substrate 200 may remain after the etching process. Figure 3L As shown, the conductive layer 500 on the side wall 200a of the substrate 200 in the opening 210a can be retained as a conductive portion 510, the conductive layer 500 on the upper surface 200t can be retained as a conductive portion 512, and the conductive layer 500 on the lower surface 200u can be retained as a conductive portion 514. Figure 3Q to Figure 3S In the embodiment shown, the conductive portion 510, the conductive portion 512 and the conductive portion 514 will be removed, but in some other embodiments, these conductive portions can be used as electrode portions of other embedded capacitors. The conductive layer 500 on the sidewalls 200b and 200d of the substrate 200 in the opening 210a can also be retained as the conductive portion 516 and the conductive portion 518, which will be removed in subsequent processes.

[0056] refer to Figure 3N to Figure 3P After etching the conductive layer 500 using the mask 600, the mask 600 is removed. After removing the mask 600, the openings 210a and 210b are exposed again, and the dielectric layer 110, the substrate 200, and the conductive patterns on both are retained. In an embodiment where the mask 600 includes a photoresist material, a photoresist stripper can be used, for example, to strip the photoresist.

[0057] refer to Figure 3Q to Figure 3S, retaining the conductive patterns on the first side 110a and the third side 110c of the dielectric layer 110, and removing other conductive patterns in the openings 210a and 210b other than the first side 110a and the third side 110c. Specifically, the second opening process can be performed along the openings 210a and 210b, wherein the opening positions avoid the conductive patterns on the first side 110a, thereby retaining the electrode plate 122 of the first electrode 120. In an embodiment in which the dielectric layer 110 includes the first liner 124 and the second liner 126, the second opening process further retains the first liner 124 and the second liner 126 to form the first electrode 120 including the electrode plate 122, the first liner 124 and the second liner 126. Similarly, the second opening process also retains the electrode plate 132, the first liner 134 and the second liner 136 of the second electrode 130. Therefore, after the second opening process, the embedded capacitor 100 including the dielectric layer 110 , the first electrode 120 and the second electrode 130 is formed.

[0058] The second opening process removes part of the conductive pattern in the opening 210a and the opening 210b, so that the first electrode 120 and the second electrode 130 are independent of other conductive patterns, and thus can be used as a pair of electrodes of the embedded capacitor 100. For example, Figure 3S As shown, the second opening process can remove the conductive pattern (ie, the conductive pattern on the sidewall 200b and the sidewall 200d) in the opening 210a. Figure 3P The conductive portion 516 and the conductive portion 518 in the second hole are formed to make the first electrode 120 and the second electrode 130 independent conductive patterns. In such an example, the second hole opening process and the first hole opening process may use the same process steps (such as drilling or profile cutting), but the hole size or hole position of the second hole opening process is different from that of the first hole opening process.

[0059] In some embodiments where the conductive pattern remains on the substrate 200, the second opening process may further expand the opening 210a in a direction away from the first side 110a and expand the opening 210b in a direction away from the third side 110c, thereby removing the conductive pattern on the substrate 200. For example, the second opening process may remove Fig.3O The conductive portion 510, the conductive portion 512, the conductive portion 514, and the portion of the substrate 200 located between the conductive portion 512 and the conductive portion 514 make the opening 210a expand toward the substrate 200 along the x direction. In such an example, the sidewall 200a will retreat toward the substrate 200, so that Figure 3R The width of the opening 210a is greater than Fig.3O The width of the opening 210a in.

[0060] It is worth mentioning that Figure 3Q to Figure 3SThe illustrated embodiment forms a single embedded capacitor 100 surrounded by the substrate 200, so only the plate 122 in the opening 210a and the plate 132 in the opening 210b remain. However, in other embodiments where the substrate 200 surrounds the embedded capacitor 100 and additional embedded capacitors are adjacent to the embedded capacitor 100, the embedded capacitor 100 may be retained. Fig.3O The conductive portion 510, the conductive portion 512 and the conductive portion 514 are used as electrodes of an additional embedded capacitor, but the present disclosure is not limited thereto.

[0061] refer to Figure 3T , an insulating layer 300 is formed on the dielectric layer 110 and the substrate 200, so that the insulating layer 300 covers the embedded capacitor 100 and the substrate 200. Specifically, the insulating layer 300 can be directly formed on Figure 3Q to Figure 3S In the structure shown, the insulating layer 300 is physically in contact with the upper surface 110t and the lower surface 110u of the dielectric layer 110, the upper surface 200t and the lower surface 200u of the substrate 200, the first electrode 120, and the second electrode 130. The insulating layer 300 further extends into the openings 210a and 210b, thereby physically contacting the electrode plate 122 on the first side 110a and the electrode plate 132 on the third side 110c. Since the insulating layer 300 extends from the upper surface 110t and the upper surface 200t to the lower surface 110u and the lower surface 200u along the openings 210a and 210b, the embedded capacitor 100 and the substrate 200 can form a stably connected element in the same layer.

[0062] The method of manufacturing a circuit board including an embedded capacitor according to the present disclosure can bring various advantages. The method of the present disclosure uses a hole-opening process combined with the formation and etching of a conductive layer to manufacture an embedded capacitor connected to a substrate, thereby simplifying the manufacturing process and omitting the embedded pressing process, thereby improving the position accuracy of the embedded capacitor and the reliability of the circuit board. Since the dielectric layer of the substrate and the embedded capacitor is formed using the same material layer, a high-strength connection is provided between the substrate and the embedded capacitor, thereby reducing the thickness of the embedded capacitor while maintaining the stability of the circuit board structure.

[0063] The method disclosed herein defines the length and width of the dielectric layer of the embedded capacitor by a hole-opening process, and directly forms electrodes on the dielectric layer by a mask etching process. Therefore, the method disclosed herein can manufacture embedded capacitors of small size and precise position, thereby improving the component integration of the circuit board. The mask etching process also helps to reduce the spacing between the paired pads of the embedded capacitor, thereby reducing the size of the embedded capacitor. For example, the spacing between the paired pads (e.g., Figure 2BThe spacing D1) shown can be as small as 20 microns while still accurately forming the embedded capacitor at a designated location in the circuit board. In the above example, the volume of the embedded capacitor can be as small as 270×120×40 cubic microns.

[0064] Since the length and width of the embedded capacitor mainly depend on the size and spacing of the paired openings formed by the opening process, embedded capacitors of various sizes can be manufactured in the same substrate at the same time, or embedded capacitors of non-standard sizes can be manufactured according to the capacitance value requirements, and multiple arrangements of embedded capacitors can be provided according to design requirements. In addition, the position of the embedded capacitor also depends on the paired openings formed by the opening process, so that the position of the embedded capacitor is highly accurate and it is not easy to cause problems such as short circuits between different embedded capacitors. Therefore, the spacing between multiple embedded capacitors can be shortened to improve the component integration of the circuit board.

[0065] To illustrate the above advantages, Figure 4 According to some embodiments of the present disclosure, a top view of a circuit board 30 is shown. The circuit board 30 includes a plurality of embedded capacitors 100a to 100d, wherein each of the embedded capacitors 100a to 100d has a structure similar to Figure 3T The structure of the embedded capacitor 100 is shown. In other words, each of the embedded capacitors 100 a to 100 d includes a pair of a first electrode 120 and a second electrode 130 and a dielectric layer 110 between the first electrode 120 and the second electrode 130 .

[0066] like Figure 4 As shown, since the hole-forming process can simultaneously form pairs of holes of different sizes and spacings, the length W3 of the dielectric layer 110 of the embedded capacitor 100a in the y direction can be different from the length W4 of the dielectric layer 110 of the embedded capacitor 100b in the y direction. Further, the pad sizes of the embedded capacitor 100a and the embedded capacitor 100b correspond to their respective holes, so the pad area of ​​the first electrode 120 of the embedded capacitor 100a located on the dielectric layer 110 can be different from the pad area of ​​the first electrode 120 of the embedded capacitor 100b located on the dielectric layer 110.

[0067] Figure 4The embedded capacitor 100c and the embedded capacitor 100d are adjacent capacitors, wherein there is a spacing D4 between the embedded capacitor 100c and the embedded capacitor 100d. Since the hole opening process can accurately form the paired through holes of the embedded capacitor 100c and the embedded capacitor 100d, it is not necessary to reserve a wide spacing D4 and the short circuit between the embedded capacitor 100c and the embedded capacitor 100d can be avoided. For example, the spacing D4 between the embedded capacitor 100c and the embedded capacitor 100d can be as small as 20 microns without causing the failure of the embedded capacitor 100c and the embedded capacitor 100d. In some embodiments, the first electrode 120 of the embedded capacitor 100c and the second electrode 130 of the embedded capacitor 100d can share the same opening, that is, the spacing D4 between the embedded capacitor 100c and the embedded capacitor 100d is the width of an opening.

[0068] In addition to defining the size of the embedded capacitor, the disclosed method uses a mask etching process to define the pad size of the embedded capacitor, so that the electrode pad can be independently manufactured corresponding to the contact, reducing the offset between the contact and the pad. For example, in an embodiment where a laser drilling process is used to form the contact opening, the area of ​​the electrode pad formed by the opening process and the mask etching process (e.g., Figure 2A The length W1×width W2 shown can be as small as 120×120 square microns while still aligning and matching subsequently formed contacts.

[0069] In addition, the mask etching process can form the wiring on the same layer as the electrode pad while forming the pad of the embedded capacitor. Figure 4 As shown, the circuit board 30 may include a trace 700 located on a substrate, wherein the trace 700 and the first electrode 120 / the second electrode 130 undergo the same conductive layer formation and etching steps, so the trace 700 and the first electrode 120 / the second electrode 130 are located in the same layer. In an embodiment in which the trace 700 and the first electrode 120 / the second electrode 130 are formed from a uniform conductive layer, the trace 700 and the pads of the first electrode 120 / the second electrode 130 may have the same thickness, but in other embodiments, the trace 700 may also be reprocessed to have a different thickness from the first electrode 120 / the second electrode 130.

[0070] According to the above-mentioned embodiments of the present disclosure, the present disclosure manufactures a circuit board including an embedded capacitor through a hole opening process and a mask etching process, so a simplified process can be used to manufacture a small-sized and precisely positioned embedded capacitor, thereby improving the reliability and component integration of the circuit board. The dielectric layer of the embedded capacitor is physically connected to the same layer substrate in the circuit board, and the electrode pad design of the embedded capacitor can be independent of the dielectric layer, thereby reducing the risk of displacement between the embedded capacitor and other components in the circuit board.

[0071] The features of some embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

[0072]

Explanation of symbols

[0073] 10,30: Circuit board

[0074] 20: Initial substrate

[0075] 100,100a,100b,100c,100d:Built-in capacitors

[0076] 110: Dielectric layer

[0077] 110a: First side

[0078] 110b: Second side

[0079] 110c: third side

[0080] 110d: The fourth side

[0081] 110t: Upper surface

[0082] 110u: bottom surface

[0083] 120: first electrode

[0084] 122: Plate

[0085] 124: First liner

[0086] 126: Second liner

[0087] 130: Second electrode

[0088] 132: Plate

[0089] 134: First liner

[0090] 136: Second liner

[0091] 200:Substrate

[0092] 200a, 200b, 200c, 200d: side wall

[0093] 200t: Upper surface

[0094] 200u: bottom surface

[0095] 210a, 210b: opening

[0096] 300: Insulation layer

[0097] 400: Contact

[0098] 500: Conductive layer

[0099] 510,512,514,516,518: conductive part

[0100] 600: Mask

[0101] 700: Routing

[0102] AA′,BB′: line

[0103] D1,D2,D3,D4: Spacing

[0104] T1, T2: thickness

[0105] W1, W3, W4: Length

[0106] W2: Width

[0107] x,y,z: direction.

Claims

1. A circuit board, characterized in that: include: A first embedded capacitor, comprising a dielectric layer and a first electrode and a second electrode in a pair, wherein the dielectric layer has a first side surface, a second side surface adjacent to the first side surface, a third side surface opposite to the first side surface, and a fourth side surface opposite to the second side surface, and the first electrode and the second electrode cover the first side surface and the third side surface respectively; a substrate surrounding the first embedded capacitor, wherein the substrate is physically connected to the second side and the fourth side of the dielectric layer, and the first electrode is located between the first side and a sidewall of the substrate; as well as An insulating layer covers the first embedded capacitor and the substrate, wherein the insulating layer extends from the upper surface of the substrate to the lower surface of the substrate along the first electrode and the side wall.

2. The circuit board according to claim 1, characterized in that: The substrate and the dielectric layer are integrally formed.

3. The circuit board according to claim 1, characterized in that: The dielectric layer has an upper surface connecting the first side surface and the second side surface, and the upper surface of the substrate and the upper surface of the dielectric layer are coplanar.

4. The circuit board according to claim 1, characterized in that: The first electrode includes a first pad located on the dielectric layer, a second pad under the dielectric layer, and a plate physically connecting the first pad and the second pad.

5. The circuit board according to claim 1, characterized in that: The first electrode includes a first pad located on the dielectric layer, and the second electrode includes a second pad located on the dielectric layer, wherein the second pad and the first pad are separated from each other.

6. The circuit board according to claim 1, characterized in that: Further includes a second embedded capacitor, wherein the second embedded capacitor includes a dielectric layer and a paired third electrode and fourth electrode, and the length of the dielectric layer of the second embedded capacitor located between the third electrode and the fourth electrode is different from the length of the dielectric layer of the first embedded capacitor located between the first electrode and the second electrode.

7. A method for manufacturing a circuit board, characterized in that: include: providing an initial substrate; Performing a first opening process on the initial substrate to form a pair of openings, a dielectric layer located between the pair of openings, and a substrate physically connected to the dielectric layer, wherein the dielectric layer has a pair of side surfaces facing the pair of openings and opposite to each other; forming a conductive layer on the substrate, on the dielectric layer, and in the pair of openings; forming a mask on the conductive layer, wherein the mask at least covers the pair of openings; etching the conductive layer using the mask to expose the dielectric layer and the substrate and retain the conductive layer in the pair of openings; After etching the conductive layer using the mask, removing the mask; as well as After removing the mask, the conductive layer located on the pair of side surfaces of the dielectric layer is retained, and other conductive layers located outside the pair of side surfaces in the pair of openings are removed.

8. The method according to claim 7, characterized in that The step of forming the mask on the conductive layer includes shielding the conductive portion of the conductive layer located on the dielectric layer with the mask; as well as After removing the mask, the method further includes retaining the conductive portion on the dielectric layer.

9. The method according to claim 7, characterized in that: The step of removing the other conductive layers in the pair of openings located outside the pair of side surfaces includes performing a second opening process along the pair of openings to expand the pair of openings in a direction away from the pair of side surfaces, wherein the first opening process and the second opening process use the same process steps.

10. The method according to claim 9, characterized in that The step of forming the mask on the conductive layer includes shielding a conductive portion of the conductive layer with the mask, the conductive portion being located on a substrate portion of the substrate; as well as The step of performing the second opening process includes removing the conductive portion and the substrate portion.

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