Chip packaging structure, storage system and electronic equipment

Abstract

The invention provides a chip packaging structure, a storage system and electronic equipment, relates to the technical field of chip packaging, and aims to improve the strain capacity of the chip packaging structure and reduce the stress borne by the chip packaging structure when the chip packaging structure deforms. The chip packaging structure comprises a packaging substrate, a first chip and a semiconductor chip set. The first chip is disposed on the first surface of the package substrate. The semiconductor chip set is arranged on the first surface of the packaging substrate, and the semiconductor chip set and the first chip are arranged at intervals in the first direction. The semiconductor chip set comprises a plurality of second chips which are arranged in a stacked mode in the direction perpendicular to the first surface, every two adjacent second chips are arranged in a staggered mode in the first direction, and in at least one pair of two adjacent second chips, the second chip on the upper layer deviates towards the side away from the first chip compared with the second chip on the lower layer. Wherein the geometric center line of each second chip in the first direction is positioned on one side, far away from the first chip, of the reference surface. The chip packaging structure is applied to chip packaging.

Description

Technical Field

[0001] The present disclosure relates to the field of chip packaging technology, and in particular to a chip packaging structure, a storage system and an electronic device. Background Art

[0002] As the feature size of the memory cell approaches the process limit, planar processes and manufacturing technologies become challenging and costly, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND).

[0003] Chip packaging is an important step in the manufacturing process of 3D NAND memory. The chip packaging structure usually connects a chipset consisting of multiple 3D NAND memories to a packaging substrate through wiring, and fixes the chipset through a packaging shell (also called a packaging layer). How to improve the deformation capacity (strain capacity) of the chip packaging structure under stress and reduce the stress on the chipset is a problem that needs to be solved urgently in current chip packaging. Summary of the invention

[0004] Embodiments of the present disclosure provide a chip packaging structure, a storage system, and an electronic device, which are intended to improve the strain capacity of the chip packaging structure and reduce the stress on the second chip when the chip packaging structure is deformed.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, an embodiment of the present disclosure provides a chip packaging structure. The chip packaging structure includes a packaging substrate, a first chip and a semiconductor chip group. The packaging substrate includes a first surface. The first chip is arranged on the first surface of the packaging substrate. The semiconductor chip group is arranged on the first surface of the packaging substrate and is spaced apart from the first chip along a first direction. The semiconductor chip group includes a plurality of second chips stacked in a direction perpendicular to the first surface, any two adjacent second chips are staggered in the first direction, and in at least one pair of two adjacent second chips, the second chip on the upper layer is offset to a side away from the first chip compared to the second chip on the lower layer. Wherein, the geometric center line of each second chip in the first direction is located on a side of a reference plane away from the first chip. The first direction is parallel to the first surface; the reference plane is perpendicular to the first direction and passes through the center line of the packaging substrate in the first direction.

[0007] In the chip packaging structure provided by the above-mentioned embodiment of the present disclosure, the first chip and the semiconductor chip group are arranged along the first direction on the first surface of the packaging substrate. A surface perpendicular to the first direction and passing through the center line of the packaging substrate in the first direction is set as a reference surface. Among the multiple second chips included in the semiconductor chip group, the geometric center line of each second chip in the first direction is located on the side of the reference surface away from the first chip; in this way, when the chip packaging structure is subjected to bending stress, the geometric center of the semiconductor chip group along the first direction does not coincide with the stress concentration area of ​​the chip packaging structure, which can reduce the stress on the semiconductor chip group, and can reduce the volume of the second chip on the side of the reference surface close to the first chip, thereby improving the deformation ability of the side of the reference surface close to the first chip, and improving the overall strain capacity of the chip packaging structure. Moreover, setting the geometric center line of the second chip in the first direction on the side of the reference surface away from the first chip is conducive to reducing the size of the chip packaging structure in the first direction and reducing the volume of the chip packaging structure. When the chip packaging structure is subjected to bending stress, the upper second chip is subjected to greater stress than the lower second chip, and at least one second chip is offset to the side away from the first chip compared to its adjacent lower second chip, which is beneficial for the upper second chip (such as the topmost layer) to be away from the stress concentration area of ​​the chip packaging structure, reducing the stress borne by the upper second chip and thereby reducing the risk of damage to the upper second chip.

[0008] In some embodiments, along a direction away from the packaging substrate, among two adjacent second chips, an odd-numbered second chip is offset toward a side away from the first chip compared to an even-numbered second chip.

[0009] In some embodiments, along a direction away from the packaging substrate, among two adjacent second chips, an odd-numbered second chip is offset toward a side closer to the first chip than an even-numbered second chip.

[0010] In some embodiments, odd-numbered second chips are connected in sequence and connected to the packaging substrate; even-numbered second chips are connected in sequence and connected to the packaging substrate.

[0011] In some embodiments, along the direction away from the packaging substrate, end surfaces of odd-numbered second chips located on the same side in the first direction are flush, and / or end surfaces of even-numbered second chips located on the same side in the first direction are flush.

[0012] In some embodiments, at least a portion of each of the second chips is located on a side of the reference plane close to the first chip.

[0013] In some embodiments, along a direction away from the packaging substrate, the uppermost second chip is located on a side of the reference plane away from the first chip.

[0014] In some embodiments, each of the second chips is located on a side of the reference plane away from the first chip.

[0015] In some embodiments, among any two adjacent second chips, the second chip on an upper layer is offset to a side away from the first chip compared to the second chip on a lower layer.

[0016] In some embodiments, along a direction away from the packaging substrate, at least a portion of the first second chip is located on a side of the reference plane close to the first chip, and the top second chip is located on a side of the reference plane away from the first chip.

[0017] In some embodiments, the chip packaging structure further includes a packaging layer. The packaging layer is disposed on a side of the first chip and the semiconductor chipset away from the packaging substrate, and covers the first chip and the semiconductor chipset. The chip packaging structure has a first cross section, the first cross section is parallel to the first direction and perpendicular to the first surface; the first cross section is located in a region on one side of the reference plane close to the first chip, and the area of ​​the packaging layer accounts for greater than or equal to 80%.

[0018] In another aspect, a storage system is provided, which includes the chip packaging structure described in any one of the above embodiments.

[0019] In another aspect, an electronic device is provided, wherein the electronic device comprises the above storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 A chip packaging structure diagram provided for related technologies;

[0022] Figure 2 is a planar structural diagram of a chip packaging structure according to some embodiments;

[0023] Figure 3 is a cross-sectional structural diagram of a chip packaging structure according to some embodiments;

[0024] Figure 4 A schematic diagram of the force of a chip packaging structure according to some embodiments;

[0025] Figure 5 is another cross-sectional structural diagram of a chip packaging structure according to some embodiments;

[0026] Figure 6 is a strain bar graph of the chip packaging structure 1000;

[0027] Figure 7A to Figure 7C is a stress distribution diagram of the chip packaging structure 1000;

[0028] Figure 8 is another cross-sectional structural diagram of a chip packaging structure according to some embodiments;

[0029] Fig. 9 is another cross-sectional structural diagram of a chip packaging structure according to some embodiments;

[0030] Fig.10 is another cross-sectional structural diagram of a chip packaging structure according to some embodiments;

[0031] Fig.11 is a structural diagram of a storage system according to some embodiments. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0033] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0034] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0035] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0036] When describing some embodiments, the term "connection" and its derivative expressions may be used. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0037] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0038] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0039] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0040] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0041] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0042] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0043] like Figure 1 As shown, Figure 1 A chip packaging structure 2000 is provided for related technology. The chip packaging structure 2000 includes a packaging substrate 10, and a first chip 20 (such as a control chip) and a plurality of second chips 30 (such as memory chips) arranged on the packaging substrate 10 and spaced apart in the horizontal direction. The plurality of second chips 30 are stacked in the vertical direction, and in each two adjacent second chips 30, the second chip 30 located in the upper layer is offset to the side closer to the first chip 20 compared to the second chip 30 located in the lower layer. Among them, the "second chip 30 in the upper layer" refers to the second chip 30 in the two adjacent second chips 30, which is far away from the packaging substrate 10; the "second chip 30 in the lower layer" refers to the second chip 30 in the two adjacent second chips 30, which is close to the packaging substrate 10. The center plane of the chip packaging structure 2000 in the horizontal direction (i.e., the plane where the midpoint of the chip packaging structure 2000 in the horizontal direction is located) is M. In the chip packaging structure 2000 provided by the related technology, the second chip 30 that is farther away from the packaging substrate 10 is closer to the center plane M of the chip packaging structure 2000 in the horizontal direction. In this way, when the chip packaging structure 2000 is subjected to bending stress, the second chip 30 that is farther away from the packaging substrate 10 is subjected to greater stress, which is not conducive to improving the safety of the second chip 30.

[0044] In order to solve the above problems, some embodiments of the present disclosure provide a chip packaging structure 1000. Figure 2 and Figure 3 , Figure 3 for Figure 2The chip package structure 1000 includes a package substrate 100 , a first chip 200 and a semiconductor chip set 300 .

[0045] The package substrate 100 has a certain rigidity to provide rigid support for the first chip 200 and the semiconductor chipset 300; the package substrate 100 also has a certain elasticity to produce elastic deformation and reduce the stress when the package structure 1000 is bent or twisted. Exemplarily, the material of the package substrate 100 may include an insulating material. For example, the package substrate 100 may be an epoxy resin-based substrate, a resin-based bismaleimide triazine (BT) substrate, etc.

[0046] The package substrate 100 may include one or more conductive layers, which may be used, for example, to lay metal traces and circuits, thereby providing electrical support for the first chip 200 and the semiconductor chipset 300. In the case where the package substrate 100 includes multiple conductive layers, an insulating layer may be included between adjacent conductive layers, and different conductive layers may be connected through vias. The material of the conductive layer includes, but is not limited to, metals such as gold, silver, copper, and aluminum.

[0047] The package substrate 100 includes a first surface 110, and the first surface 110 is configured to be provided with a first chip 200 and a semiconductor chip group 300. Figure 3 As shown, the upper surface of the packaging substrate 100 is the first surface 110 , and other descriptions of the relative positional relationship of “upper” and “lower” are based on the first surface 110 as the upper surface as a reference.

[0048] The first chip 200 is disposed on the first surface 110 of the package substrate 100. The first chip 200 can be bonded and fixed to the first surface 110 of the package substrate 100, for example, by an adhesive layer, and the first chip 200 can be electrically connected to the conductive layer of the package substrate 100 by a first connecting wire (not shown in the figure). Exemplarily, the adhesive layer can be DAF (full name: Die Attach Film) glue; the material of the first connecting wire includes but is not limited to copper, aluminum, silver, gold, tin, etc.

[0049] Exemplarily, the chip package structure 1000 may be a flash memory package product, such as a universal flash storage (Universal Flash Storage; referred to as: UFS) or an embedded multimedia card (Embedded Multi Media Card; referred to as: eMMC). In this case, the first chip 200 may be, for example, a control chip, and the plurality of second chips 310 included in the semiconductor chipset 300 may be chips such as 3D NAND or DRAM. Of course, in some other chip package products, the semiconductor chipset 300 may also include but is not limited to a controller chip, a FR radio frequency chip, a positioning chip, a Bluetooth chip, a sensor chip, or any combination thereof, as long as the same technical idea as that of the present application is adopted.

[0050] The semiconductor chip group 300 is disposed on the first surface 110 of the package substrate 100 and is spaced apart from the first chip 200 along the first direction X. The semiconductor chip group 300 includes a plurality of second chips 310 stacked along a direction Z perpendicular to the first surface 110. An adhesive layer may be included between two adjacent second chips 310 and between the bottom second chip 310 and the package substrate 100, and the adhesive layer is used to bond the adjacent second chips into a whole. The first direction X may be any direction parallel to the first surface 110.

[0051] For example, the semiconductor chipset 300 may include 2, 4, 5, 8 or any other number of second chips 310, and the embodiments of the present disclosure are not listed one by one. In the following embodiments, the semiconductor chipset 300 includes 8 second chips 310 as an example for schematic description. It can be understood that the embodiments of the present disclosure are not limited to this, as long as the same technical concept is adopted. In addition, the second chip 310 can be, for example, 3D NAND.

[0052] like Figure 3 As shown, the chip packaging structure 1000 further includes a second connection line 420, and the second connection line 420 is used to connect the second chip 310 to the packaging substrate 100. Any two adjacent second chips 310 among the plurality of second chips 310 are staggered in the first direction X. In other words, any two adjacent second chips 310 have a gap at both ends along the first direction X. For example, the left end and the right end of the two adjacent second chips 310 along the first direction X are respectively spaced. In this way, among the two adjacent second chips 310, the upper second chip 310 (the second chip 310 farther from the packaging substrate 100) can expose the connection area of ​​the lower second chip 310 (the second chip 310 closer to the packaging substrate 100), which is conducive to the electrical connection of the lower second chip 310 with the packaging substrate 100 through the second connection line 420.

[0053] like Figure 2 and Figure 3 As shown, the chip packaging structure 1000 has a reference plane P, which is perpendicular to the first direction X and passes through the center line L2 of the packaging substrate 100 in the first direction X. Figure 2 and Figure 3 In the embodiment, the reference plane P coincides with the center line L2 of the packaging substrate 100 in the first direction X.

[0054] The geometric center line L1 of each second chip 310 included in the semiconductor chip group 300 in the first direction X is located on the side of the reference plane P away from the first chip 200. Since the elastic modulus of the encapsulation layer 500 is generally smaller than the elastic modulus of the second chip 310, when the encapsulation layer 500 and the second chip are subjected to the same stress, the deformation of the second chip 310 is smaller, and the deformation of the encapsulation layer 500 is larger. When the chip packaging structure 1000 is subjected to bending stress, the deformation area is mainly concentrated on the side of the semiconductor chip group 300 close to the first chip 200. Based on this, the geometric center line L1 of the second chip 310 in the first direction X is set on the side of the reference plane P away from the first chip 200, which can reduce the volume proportion of the semiconductor chip group 300 on the side of the reference plane P close to the first chip 200, thereby increasing the deformation amount on the side of the reference plane P close to the first chip 200, that is, to improve the overall PKG deformation of the chip packaging structure 1000 and reduce the overall stress of the chip packaging structure 1000. Meanwhile, the geometric center line L1 of the second chip 310 in the first direction X does not coincide with the stress concentration area of ​​the chip package structure 1000 , which can reduce the stress on the semiconductor chipset 300 and the risk of bending failure of the second chip 310 .

[0055] Understandably, see Figure 4 , Figure 4 Schematic diagram of bending stress on the chip packaging structure 1000. When the chip packaging structure 1000 is subjected to stress formed by forces F1, F2 and F3, F3 acts near the reference plane P. The deformation near the reference plane P is small, and the area of ​​the chip packaging structure 1000 close to the reference plane P is the area where the stress on the chip packaging structure 1000 is concentrated.

[0056] Continue reading Figure 3 and Figure 4 The geometric center line L1 of the second chip 310 in the first direction X is arranged on the side of the reference plane P away from the first chip 200, so as to avoid the geometric center line L1 of the second chip 310 in the first direction X from coinciding with the reference plane P, and to make the second chip 310 avoid the stress concentration area as much as possible, thereby reducing the stress on the second chip 310, thereby reducing the risk of damage to the second chip 310 and improving the reliability of the chip packaging structure 1000.

[0057] Moreover, compared with setting the geometric center line L1 of the second chip 310 in the first direction X on the side of the reference plane P close to the first chip 200, in the embodiment of the present disclosure, the geometric center line L1 of the second chip 310 in the first direction X is set on the side of the reference plane P away from the first chip 200, which is beneficial to reducing the size of the chip packaging structure 1000 in the first direction X, reducing the volume of the chip packaging structure 1000, and facilitating a compact design of the product.

[0058] When the chip package structure 1000 is subjected to bending stress, the upper second chip 310 will be subjected to greater stress. Figure 3 As shown, in at least one pair of two adjacent second chips 310, the upper second chip 310 is offset to the side away from the first chip 200 compared to the lower second chip 310. For example, in the direction away from the package substrate 100, in any two adjacent second chips 310, the odd-numbered second chip 311 is offset to the side away from the first chip 200 compared to the even-numbered second chip 312. In this way, the upper second chip 310 (for example, the uppermost layer) is away from the stress concentration area of ​​the chip package structure 1000, reducing the stress on the upper second chip 310, thereby reducing the risk of damage to the upper second chip 310.

[0059] In some embodiments, Figure 3 As shown, along the direction away from the package substrate 100 ( Figure 3 In any two adjacent second chips 310, the odd-numbered second chip 311 is offset to the side away from the first chip 200 compared to the even-numbered second chip 312. In other words, the plurality of second chips 310 included in the semiconductor chip group 300 are arranged in a "Z-shape" along the direction Z away from the package substrate 100, and the odd-numbered second chips 311 protrude to the side away from the first chip 200, and the even-numbered second chips 312 protrude to the side close to the first chip 200. In this way, the size of the semiconductor chip group 300 along the first direction X can be reduced, which is conducive to reducing the volume of the chip packaging structure 1000.

[0060] In other embodiments, Figure 5 As shown, along the direction away from the package substrate 100 ( Figure 5In the direction from bottom to top in the semiconductor chip group 300, the odd-numbered second chip 311 of any two adjacent second chips 310 is offset to the side close to the first chip 200 compared to the even-numbered second chip 312. The plurality of second chips 310 included in the semiconductor chip group 300 are arranged in a "Z-shape" along the direction Z away from the package substrate 100, and the odd-numbered second chips 311 protrude to the side close to the first chip 200, and the even-numbered second chips 312 protrude to the side away from the first chip 200. Figure 3 Similar to the chip packaging structure shown, the size of the semiconductor chipset 300 along the first direction X can be reduced, which is beneficial to reducing the volume of the chip packaging structure 1000 .

[0061] In some embodiments, Figure 3 and Figure 5 As shown, when the plurality of second chips 310 included in the semiconductor chip set 300 are arranged in a "Z-shape", the odd-numbered second chips 311 are sequentially connected and connected to the package substrate 100. The even-numbered second chips 312 are sequentially connected and connected to the package substrate 100.

[0062] For example, Figure 3 and Figure 5 As shown, the chip package structure 1000 includes a plurality of second connection lines 420. Every adjacent two odd-numbered second chips 311 among the odd-numbered second chips 311 are connected through the second connection line 420, and the odd-numbered second chips 311 located at the bottom layer (i.e., the odd-numbered second chips 311 closest to the package substrate 100) are connected to the package substrate 100 through the second connection line 420. Every adjacent two second chips 310 among the even-numbered second chips 312 are connected through the second connection line 420, and the even-numbered second chips 312 located at the bottom layer (i.e., the even-numbered second chips 312 closest to the package substrate 100) are connected to the package substrate 100 through the second connection line 420. Compared with multiple second chips 310 connected in sequence in a direction away from the packaging substrate 100, the odd-numbered second chips 311 and the even-numbered second chips 312 are respectively connected to the packaging substrate 100, and the second connecting wire 420 does not need to pass between two adjacent second chips 310. This is beneficial to simplify the connection structure of the multiple second chips 310, reduce the wiring difficulty of the second connecting wire 420, and improve the connection reliability of the multiple second chips 310.

[0063] In some embodiments, continue to refer to Figure 3 and Figure 5, along the direction away from the packaging substrate 100, the end faces of the odd-numbered second chips 311 on the same side in the first direction X are flush. And / or, the end faces of the even-numbered second chips 312 on the same side in the first direction X are flush. Exemplarily, the sizes of the multiple second chips 310 in the first direction X are the same, in which case the multiple left end faces of the multiple odd-numbered second chips 311 are flush, and the multiple right end faces of the multiple odd-numbered second chips 311 are flush. The multiple left end faces of the multiple even-numbered second chips 312 are flush, and the multiple right end faces of the multiple even-numbered second chips 312 are flush. In this way, the size of the semiconductor chip group 300 in the first direction X can be greatly reduced, which is conducive to reducing the size of the chip packaging structure 1000.

[0064] In some embodiments, Figure 3 and Figure 5 As shown, part of each second chip 310 is located on the side of the reference plane P close to the first chip 200. On the one hand, the second chip 310 has a certain rigidity, and part of the second chip 310 is located on the side of the reference plane P close to the first chip 200, which is conducive to improving the rigidity of the stress concentration area (both sides of the reference plane P) and reducing the risk of the chip packaging structure 1000 being bent and broken. On the other hand, it is conducive to reducing the interval between the semiconductor chip group 300 and the first chip 200 in the first direction X, which is conducive to reducing the size of the semiconductor chip group 300 in the first direction X, and making the chip packaging structure 1000 more compact.

[0065] See also Figure 6 , Figure 6 is the maximum strain of the chip packaging structure 1000 under different packaging arrangements of multiple second chips. Figure 1 The packaging arrangement of the second chip shown is Opt 2. Figure 3 The packaging arrangement of the second chip shown is Opt3. Figure 5 The packaging arrangement of the second chip is shown.

[0066] like Figure 6 As shown, by comparing Opt1, Opt2 and Opt3, when other conditions are the same (such as the type, size and position of the first chip, the type, size and number of the second chips, and the relative position of the first chip and the bottom second chip, etc.), only by arranging the multiple second chips 310 in a "Z-shape" arrangement in the direction away from the packaging substrate 10, the maximum strain of the chip packaging structure 1000 can be increased from 3204ue to 3615ue and 3471ue, which can significantly increase the maximum strain of the chip packaging structure 1000 (about 10%) and improve the strain capacity of the chip packaging structure 1000.

[0067] like Figure 7A to Figure 7C As shown, Fig. 7A For multiple second chips Figure 1 Stress distribution diagram of the chip packaging structure 1000 under the packaging arrangement shown; Figure 7B For multiple second chips Figure 3 Stress distribution diagram of the chip packaging structure 1000 under the packaging arrangement shown; Figure 7C The second chips 310 are Figure 5 The stress distribution diagram of the chip packaging structure 1000 under the packaging arrangement shown. Figure 7A to Figure 7C In the example, the stress decreases from the center to both sides.

[0068] contrast Figure 7A to Figure 7C , when other conditions are the same, by simply arranging the plurality of second chips 310 in a "Z-shaped" arrangement, the stress concentration area of ​​the chip package structure 1000 can be shifted to the left side (the side close to the first chip). Figure 1 As shown in the figure, along the direction away from the package substrate 10, the plurality of second chips 30 are offset in sequence toward the side close to the first chip 20; Figure 3 and Figure 5 As shown, multiple second chips 310 are arranged in a "Z-shape" in a direction away from the packaging substrate 10, so that the topmost second chip 310 is farther away from the reference plane P, thereby making the topmost second chip 310 away from the stress concentration area of ​​the chip packaging structure 1000, thereby improving the safety of the topmost second chip 310 and reducing the risk of the topmost second chip 310 being damaged due to stress.

[0069] In some embodiments, see Figure 8 , along the direction Z away from the package substrate 100, the top second chip 310 is located on the side of the reference plane P away from the first chip 200. When the chip package structure 1000 is subjected to bending stress, along the reference plane and in the direction away from the package substrate 100 (along the reference plane from bottom to top), the stress on the chip package structure 1000 becomes greater and greater. The top second chip 310 is located on the side of the reference plane P away from the first chip 200, which can keep the top second chip 310 away from the stress concentration area and protect the top second chip 310 from being damaged by stress.

[0070] In some embodiments, Fig. 9 As shown, each second chip 310 is located on a side of the reference plane P away from the first chip 200. In this way, all second chips 310 can be kept away from the stress center, reducing the risk of the second chips 310 being damaged by stress and improving the safety of the semiconductor chipset 300.

[0071] In some embodiments, Fig.10As shown, among any two adjacent second chips 310, the upper second chip 310 is offset to the side away from the first chip 200 compared to the lower second chip 310; in other words, along the direction away from the package substrate 100, the second chips 310 are offset to the side away from the first chip 200 in sequence. As described above, along the reference plane and in the direction away from the package substrate 100, the stress on the chip package structure 1000 is getting greater and greater, and along the direction away from the package substrate 100, the second chip 310 is farther and farther away from the stress concentration area, which can make one or more second chips 310 in the upper layer away from the stress concentration area, and reduce the stress on one or more second chips 310 in the upper layer.

[0072] In some embodiments, Fig.10 As shown, along the direction away from the package substrate 100, at least part of the first second chip 310 is located on the side of the reference plane P close to the first chip 200, and the uppermost second chip 310 is located on the side of the reference plane P away from the first chip 200. In this way, on the one hand, it is helpful to reduce the size of the chip package structure 1000 in the first direction X, and on the other hand, the one or more second chips 310 below can provide a certain strength support for the chip package structure 1000, reducing the risk of the chip package structure 1000 being bent and broken.

[0073] In some embodiments, Figure 3 and Figure 5 as well as Figure 8 to Figure 10 As shown, the chip packaging structure further includes a packaging layer 500 . The packaging layer 500 is disposed on a side of the first chip 200 and the semiconductor chipset 300 away from the packaging substrate 100 , and covers the first chip 200 , the semiconductor chipset 300 and the first surface of the packaging substrate 100 .

[0074] The encapsulation layer 500 has a certain elasticity so that when the chip encapsulation structure 1000 is squeezed by an external force, it can produce a certain deformation and absorb part of the external force. Exemplarily, the material of the encapsulation layer 500 may include but is not limited to epoxy molding compound (English: Epoxy Molding Compound; abbreviated: EMC).

[0075] See also Figure 2 , the chip packaging structure 1000 has a first cross section AA, the first cross section AA is parallel to the first direction X, and is perpendicular to the first surface 110. In the embodiment of the present disclosure, Figure 3 to Figure 5 as well as Figure 8-Figure 9The figures are all first cross sections AA of the chip packaging structure 1000. The first cross section AA is located in the area on one side of the reference plane P close to the first chip 200, and the area of ​​the packaging layer 500 accounts for greater than or equal to 80%; in other words, the area of ​​the packaging layer 500 in the left area of ​​the reference plane P accounts for greater than or equal to 80%. By adopting the stacking arrangement scheme of the second chip described in any of the above embodiments, the area of ​​the packaging layer 500 can be increased, and the deformation capacity of the left area of ​​the reference plane P can be increased, thereby reducing the stress on the first chip 200 and the semiconductor chip group 300.

[0076] like Fig.11 As shown, some embodiments of the present disclosure further provide a storage system 3000. The storage system includes the chip packaging structure 1000 and the controller 3100 in any of the above embodiments.

[0077] The storage system can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage package UFS or an embedded multimedia card package eMMC. That is, the storage system can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0078] In some embodiments, the storage system may be integrated into a memory card, wherein the memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0079] In other embodiments, the storage system may also be integrated into a solid state drive (SSD).

[0080] In the storage system 3000, in some embodiments, the controller 3100 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0081] In other embodiments, the controller 3100 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0082] In some embodiments, the controller 3100 may be configured to manage data stored in the chip package structure 1000 and communicate with an external device (e.g., a host). In some embodiments, the controller 3100 may also be configured to control operations of the chip package structure 1000, such as read, erase, and program operations. In some embodiments, the controller 3100 may also be configured to manage various functions regarding data stored or to be stored in the chip package structure 1000, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 3100 is also configured to process error correction codes for data read from or written to the chip package structure 1000.

[0083] Of course, the controller 3100 may also perform any other suitable functions, such as formatting the chip package structure 1000; for example, the controller 3100 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0084] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0085] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0086] The electronic device may include the storage system described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0087] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: A packaging substrate including a first surface; A first chip is disposed on a first surface of the packaging substrate; A semiconductor chipset is disposed on the first surface of the package substrate and is spaced apart from the first chip along a first direction; the semiconductor chipset comprises a plurality of second chips stacked in a direction perpendicular to the first surface, any two adjacent second chips are staggered in the first direction, and in at least one pair of two adjacent second chips, the upper second chip is offset to a side away from the first chip compared to the lower second chip; the first direction is parallel to the first surface; The geometric center line of each second chip in the first direction is located on a side of a reference plane away from the first chip; the reference plane is perpendicular to the first direction and passes through the center line of the packaging substrate in the first direction.

2. The chip packaging structure according to claim 1, characterized in that: Along the direction away from the packaging substrate, among two adjacent second chips, the odd-numbered second chips are offset to a side away from the first chip compared to the even-numbered second chips.

3. The chip packaging structure according to claim 1, characterized in that: Along the direction away from the packaging substrate, among two adjacent second chips, the odd-numbered second chips are offset to a side closer to the first chip than the even-numbered second chips.

4. The chip packaging structure according to claim 2 or 3, characterized in that: The odd-numbered second chips are connected in sequence and connected to the packaging substrate; the even-numbered second chips are connected in sequence and connected to the packaging substrate.

5. The chip packaging structure according to claim 2 or 3, characterized in that: Along the direction away from the packaging substrate, end surfaces of the odd-numbered second chips located on the same side in the first direction are flush, and / or end surfaces of the even-numbered second chips located on the same side in the first direction are flush.

6. The chip packaging structure according to claim 2 or 3, characterized in that: A portion of each of the second chips is located on a side of the reference surface close to the first chip.

7. The chip packaging structure according to claim 2 or 3, characterized in that: Along the direction away from the packaging substrate, the uppermost second chip is located on a side of the reference surface away from the first chip.

8. The chip packaging structure according to claim 7, characterized in that: Each of the second chips is located on a side of the reference surface away from the first chip.

9. The chip packaging structure according to claim 1, characterized in that: Among any two adjacent second chips, the second chip on the upper layer is offset to a side away from the first chip compared to the second chip on the lower layer.

10. The chip packaging structure according to claim 9, characterized in that: Along the direction away from the packaging substrate, a portion of the first second chip is located on a side of the reference surface close to the first chip, and the uppermost second chip is located on a side of the reference surface away from the first chip.

11. The chip packaging structure according to any one of claims 1 to 10, characterized in that: It also includes a packaging layer, which is arranged on a side of the first chip and the semiconductor chipset away from the packaging substrate and covers the first chip and the semiconductor chipset; The chip packaging structure has a first cross-section, which is parallel to the first direction and perpendicular to the first surface; the first cross-section is located in a region on one side of the reference plane close to the first chip, and the area of ​​the packaging layer accounts for greater than or equal to 80%.

12. A storage system, characterized in that: The invention comprises a chip packaging structure as claimed in any one of claims 1 to 11.

13. An electronic device, characterized in that: Comprising the storage system as claimed in claim 12.

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