P-type GaN HEMT device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and particularly discloses a P-type GaN HEMT device and a preparation method thereof. The P-type GaN HEMT device comprises an intrinsic silicon carbide substrate, a GaN buffer layer and an n-type GaN layer which are sequentially arranged from bottom to top in the longitudinal direction. The intrinsic GaN layer, the AlGaN layer and the drain metal are transversely and horizontally arranged on the n-type GaN layer, and the intrinsic GaN layer and the AlGaN layer are the same in thickness; the insulating medium extends inwards from the upper end of the AlGaN layer; the P-type GaN layer and the gate metal are transversely and horizontally arranged in the insulating medium; the P-type GaN HEMT device further comprises source electrode metal which is flush with the top of the grid electrode metal and is arranged on the upper portion of the AlGaN layer. Through the combination of the longitudinal HEMT structure withstand voltage and the transverse n-type GaN withstand voltage which are arranged at the same time, the withstand voltage capability of the device is improved, and the switching speed and stability of the device are effectively ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a P-type GaN HEMT device and a preparation method thereof. Background Art

[0002] As one of the representatives of wide bandgap semiconductor devices, GaN and its high electron mobility transistor (HEMT) use materials such as gallium nitride (GaN) or gallium arsenide (GaAs), which have higher electron mobility than traditional silicon materials and have the characteristics of low drive loss, low on-resistance and high operating frequency. In practical applications, since the voltage resistance of lateral devices is determined by the device volume, the device power density is low, and the threshold voltage of p-type GaN as a switching device is low, it is easy to be triggered by mistake.

[0003] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0004] The main purpose of the present invention is to provide a P-type GaN HEMT device and a preparation method thereof, aiming to solve the technical problem of low power density of lateral switching devices in the prior art.

[0005] To achieve the above object, the present invention provides a P-type GaN HEMT device, the P-type GaN HEMT device comprising: an intrinsic silicon carbide substrate, a GaN buffer layer and an n-type GaN layer arranged in sequence from bottom to top vertically;

[0006] The P-type GaN HEMT device further comprises: an intrinsic GaN layer, an AlGaN layer and a drain metal arranged horizontally on the n-type GaN layer, wherein the intrinsic GaN layer has the same thickness as the AlGaN layer;

[0007] The P-type GaN HEMT device further includes: an insulating medium extending inwardly from the upper end of the AlGaN layer;

[0008] The P-type GaN HEMT device further includes: a P-type GaN layer and a gate metal arranged laterally and horizontally inside the insulating medium;

[0009] The P-type GaN HEMT device further includes a source metal that is flush with the top of the gate metal and is disposed on the upper portion of the AlGaN layer.

[0010] Optionally, a first preset doping concentration of the GaN buffer layer is set according to the thickness of the GaN buffer layer;

[0011] A second preset doping concentration of the P-type GaN layer is set according to the width of the P-type GaN layer.

[0012] Optionally, the insulating medium is a concave structure, and the insulating medium includes: a first insulating part and a second insulating part;

[0013] The first insulating portion is disposed longitudinally between the AlGaN layer and the gate metal;

[0014] The second insulating portion is laterally disposed between the AlGaN layer and the P-type GaN layer.

[0015] Optionally, the ratio of Al to GaN in the AlGaN layer is set to a first preset ratio according to a gate turn-on voltage of the P-type GaN HEMT device.

[0016] In addition, to achieve the above object, the present invention also provides a method for preparing a P-type GaN HEMT device, which is applied to the preparation of the above-mentioned P-type GaN HEMT device, and the method comprises the following steps:

[0017] Epitaxially growing a GaN buffer layer on an intrinsic silicon carbide substrate;

[0018] epitaxially growing an n-type GaN layer on the GaN buffer layer;

[0019] Depositing a drain metal on the n-type GaN layer, and epitaxially preparing an intrinsic GaN layer and an AlGaN layer;

[0020] An insulating dielectric, a P-type GaN layer and a gate metal are deposited in the AlGaN layer, and a source metal is deposited on the AlGaN layer.

[0021] Optionally, the step of depositing a drain metal on the n-type GaN layer and epitaxially preparing an intrinsic GaN layer and an AlGaN layer comprises:

[0022] Depositing a barrier layer on the n-type GaN layer;

[0023] Etching a drain metal through hole on the barrier layer to deposit the drain metal in the drain metal through hole;

[0024] epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer having the same thickness on the n-type GaN layer;

[0025] epitaxially preparing a second intrinsic GaN layer having the same lateral position on the first intrinsic GaN layer;

[0026] epitaxially preparing a second AlGaN layer having the same lateral position on the first AlGaN layer;

[0027] The top of the first intrinsic GaN layer and the bottom of the second intrinsic GaN layer are flush with the bottom of the insulating metal.

[0028] Optionally, the step of epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer with the same thickness on the n-type GaN layer comprises:

[0029] Depositing a barrier layer on the n-type GaN layer;

[0030] Etching a first intrinsic GaN layer through hole on the barrier layer to deposit a first intrinsic GaN layer in the first intrinsic GaN layer through hole;

[0031] removing the barrier layer, and depositing a barrier layer on the first intrinsic GaN layer;

[0032] A first AlGaN layer through hole is etched on the barrier layer to deposit a first AlGaN layer in the first AlGaN layer through hole.

[0033] Optionally, the step of epitaxially preparing a second intrinsic GaN layer with the same lateral position on the first intrinsic GaN layer includes:

[0034] Depositing a barrier layer on the first intrinsic GaN layer;

[0035] Etching a second intrinsic GaN layer through hole on the barrier layer to deposit a second intrinsic GaN layer in the second intrinsic GaN layer through hole;

[0036] The step of epitaxially preparing a second AlGaN layer in the same lateral position on the first AlGaN layer comprises:

[0037] removing the barrier layer, and depositing a barrier layer on the first AlGaN layer;

[0038] A second AlGaN layer through hole is etched on the barrier layer to deposit a second AlGaN layer in the second AlGaN layer through hole.

[0039] Optionally, the step of depositing an insulating medium, a P-type GaN layer and a gate metal in the AlGaN layer, and depositing a source metal on the AlGaN layer comprises:

[0040] depositing a barrier layer on the second AlGaN layer;

[0041] Etching an insulating medium through hole on the barrier layer to deposit the insulating medium in the insulating medium through hole;

[0042] removing the barrier layer and depositing a barrier layer on the insulating medium;

[0043] Etching a p-type GaN through hole on the barrier layer to deposit p-type GaN in the p-type GaN through hole;

[0044] removing the barrier layer and depositing a barrier layer on the insulating medium;

[0045] etching a gate metal through hole on the barrier layer to deposit a gate metal in the gate metal through hole;

[0046] A source metal is deposited on the AlGaN layer.

[0047] Optionally, the step of depositing a source metal on the AlGaN layer includes:

[0048] Depositing a barrier layer on the AlGaN layer;

[0049] A source metal via is etched on the barrier layer to deposit the source metal in the source metal via.

[0050] The technical solution of the present invention proposes a P-type GaN HEMT device and a preparation method thereof. The P-type GaN HEMT device comprises: an intrinsic silicon carbide substrate, a GaN buffer layer and an n-type GaN layer arranged in sequence from bottom to top vertically; the P-type GaN HEMT device also comprises: an intrinsic GaN layer, an AlGaN layer and a drain metal arranged horizontally on the n-type GaN layer, and the thickness of the intrinsic GaN layer is the same as that of the AlGaN layer; the P-type GaN HEMT device also comprises: an insulating medium extending inward from the upper end of the AlGaN layer; the P-type GaN HEMT device also comprises: a P-type GaN layer and a gate metal arranged horizontally inside the insulating medium; the P-type GaN HEMT device also comprises: a source metal flush with the top of the gate metal and arranged on the upper part of the AlGaN layer. The traditional lateral HEMT device is transformed from a simple lateral withstand voltage structure into a combination of a longitudinal HEMT structure withstand voltage and a lateral n-type GaN withstand voltage, thereby ensuring low on-resistance and high switching speed of the device, while achieving high withstand voltage and high power density of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A schematic structural diagram of a first embodiment of a P-type GaN HEMT device proposed by the present invention;

[0052] Figure 2 A schematic diagram of a process of an embodiment of a method for preparing a P-type GaN HEMT device according to the present invention;

[0053] Figure 3 A first structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device proposed by the present invention;

[0054] Figure 4 A second structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device provided by the present invention;

[0055] Figure 5 A third structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device provided by the present invention;

[0056] Figure 6 A fourth structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device provided by the present invention;

[0057] Figure 7 A fifth structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device provided by the present invention;

[0058] Figure 8 A sixth structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device provided by the present invention;

[0059] Fig. 9 It is a seventh structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device provided by the present invention;

[0060] Fig.10 The eighth structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device provided by the present invention;

[0061] Fig.11 It is a ninth structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device provided by the present invention;

[0062] Fig.12 The tenth structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device provided by the present invention;

[0063] Fig.13 It is an eleventh structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device proposed by the present invention.

[0064] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0065] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0066] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0068] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0069] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the P-type GaN HEMT device proposed by the present invention. Figure 1 A first embodiment of a P-type GaN HEMT device of the present invention is provided.

[0070] In this embodiment, the P-type GaN HEMT device includes: an intrinsic silicon carbide substrate 10, a GaN buffer layer 20 and an n-type GaN layer 30 arranged in sequence from bottom to top. The P-type GaN HEMT device also includes: an intrinsic GaN layer 40, an AlGaN layer 50 and a drain metal 60 arranged horizontally on the n-type GaN layer 30, wherein the thickness of the intrinsic GaN layer 40 is the same as that of the AlGaN layer 50. The P-type GaN HEMT device also includes: an insulating medium 70 extending inward from the upper end of the AlGaN layer 50; the P-type GaN HEMT device also includes: a P-type GaN layer 80 and a gate metal 90 arranged horizontally inside the insulating medium 70; the P-type GaN HEMT device also includes: a source metal 100 flush with the top of the gate metal 90 and arranged on the upper part of the AlGaN layer 50.

[0071] It should be noted that the P-type GaN HEMT device adopts a horizontal and vertical combination structure, which changes the traditional horizontal HEMT device's simple horizontal withstand voltage structure into a combination of vertical HEMT structure withstand voltage and horizontal n-type GaN withstand voltage, which can effectively improve the device's withstand voltage capability. The device realizes the enhanced implementation of the HEMT device through the p-type GaN layer, which can effectively ensure the low gate charge of the device and the switching speed of the device; at the same time, an insulating medium is constructed just below the gate metal of the device and on the contact surface between the p-type GaN layer and the AlGaN layer, which can increase the threshold voltage of the device and avoid the device threshold voltage being too low (the threshold voltage may be only 1V when there is only a p-type GaN layer but no insulating medium), which is easy to be triggered by mistake, and effectively suppresses gate leakage and improves the gate reliability of the device.

[0072] It should be understood that when the gate voltage is zero, the p-type GaN layer affects the energy bands of the AlGaN layer and the intrinsic GaN layer, causing the two-dimensional electron gas originally formed by the p-type GaN layer and the AlGaN layer to disappear in this region, causing the device to be turned off under zero gate voltage conditions. At this time, the positive voltage is increased in the drain part, and the electric field distribution diffuses from the drain to the source laterally, and diffuses upward after reaching the electric field in the two-dimensional electron gas region, and turns off in the gate-controlled region. When a positive voltage is applied to the device gate, the two-dimensional electron gas is re-formed in the gate-controlled region, causing the device to conduct. Since the gate is only used to change the energy band and re-form the two-dimensional electron gas, this region only needs to provide potential but not charge, so the gate charge is small, so the high switching speed of the device can be achieved.

[0073] In a possible implementation, the thickness of the intrinsic silicon carbide substrate can be set to 800nm ​​to ensure the support of the substrate for subsequent processes. The thickness of the GaN buffer layer can be set to 100nm. This thickness is due to the low defect density generated by SiC and GaN. At a thickness of 100nm, good defect suppression can be achieved to ensure the quality of GaN on the GaN buffer layer. The thickness of the n-type GaN layer can be set to 300nm. It is a lateral conductive material of the device. The thickness is the guarantee for effective conduction. The drain metal thickness can be set to 200nm. The maximum thickness of the intrinsic GaN layer and the AlGaN layer can be set to 5μm. The insulating medium material can be Al2O3. The insulating medium is a concave structure. The insulating medium includes: a first insulating part and a second insulating part; the first insulating part is longitudinally arranged between the AlGaN layer and the gate metal; the second insulating part is transversely arranged between the AlGaN layer and the P-type GaN layer. The bottom thickness of the insulating medium can be set to 50nm, the side wall width can be set to 20nm, the width of the p-type GaN layer can be set to 80nm, the gate metal thickness can be set to 100nm, and the width can be set to 100nm, where the thickness is to ensure the gate's control ability over the device, and the width is to reduce the difficulty of the etching process.

[0074] It should be understood that the first preset doping concentration of the GaN buffer layer can be set according to the thickness of the GaN buffer layer, and the second preset doping concentration of the P-type GaN layer can be set according to the width of the P-type GaN layer. The GaN buffer layer is unintentionally doped due to the difference in the crystal structure of SiC and GaN. When the thickness of the GaN buffer layer is 100nm, the natural doping concentration is set at 1e13cm -3 to 2e14cm -3 When the width of p-type GaN is 80nm, the natural doping concentration is set at 2e16cm -3 .

[0075] Furthermore, the gate on-voltage and enhancement characteristics of the P-type GaN HEMT device can be set by the ratio of Al to GaN in the AlGaN layer, and the ratio is set to a first preset ratio according to the model of the device actually produced. For example, if the gate on-voltage of the device is required to be 2-3V, the ratio of Al to GaN in the AlGaN layer is between 3:7-5:5.

[0076] In this embodiment, the P-type GaN HEMT device includes: an intrinsic silicon carbide substrate, a GaN buffer layer, and an n-type GaN layer arranged in sequence from bottom to top vertically; the P-type GaN HEMT device also includes: an intrinsic GaN layer, an AlGaN layer, and a drain metal arranged horizontally on the n-type GaN layer, and the thickness of the intrinsic GaN layer is the same as that of the AlGaN layer; the P-type GaN HEMT device also includes: an insulating medium extending inward from the upper end of the AlGaN layer; the P-type GaN HEMT device also includes: a P-type GaN layer and a gate metal arranged horizontally inside the insulating medium; the P-type GaN HEMT device also includes: a source metal flush with the top of the gate metal and arranged on the upper part of the AlGaN layer. The traditional lateral HEMT device is transformed from a simple lateral withstand voltage structure into a combination of a longitudinal HEMT structure withstand voltage and a lateral n-type GaN withstand voltage, so as to ensure low on-resistance and high switching speed of the device, and realize high withstand voltage and high power density of the device.

[0077] In addition, the present invention also provides a method for preparing a P-type GaN HEMT device. Figure 2 , Figure 2 The figure is a schematic flow chart of an embodiment of a method for preparing a P-type GaN HEMT device proposed by the present invention.

[0078] In this embodiment, the method for preparing the P-type GaN HEMT device includes the following steps:

[0079] Step S10: epitaxially growing a GaN buffer layer on the intrinsic silicon carbide substrate.

[0080] Reference Figure 3 , Figure 3 This is a first structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device proposed by the present invention.

[0081] It should be noted that the intrinsic silicon carbide substrate thickness can be set to 800nm, which is to ensure the support of the substrate for subsequent processes. The GaN buffer layer thickness is 100nm. This thickness is due to the low defect density generated by SiC and GaN. At a thickness of 100nm, better defect suppression can be achieved to ensure the quality of GaN on the buffer layer. Among them, it can meet the support of subsequent processes and meet the final specifications of the switching elements within a certain range (for example, 500-1200nm), and the specific settings can be determined according to actual production needs.

[0082] Step S20: epitaxially growing an n-type GaN layer on the GaN buffer layer.

[0083] It should be noted that the n-type GaN layer can be the lateral conductive material of the device, that is, the lateral conductive dielectric material from the drain to the two-dimensional electron gas in the device. The thickness of the n-type GaN layer can be set to 300nm to ensure effective conduction. Figure 4 , Figure 4 This is a second structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device proposed by the present invention.

[0084] Step S30: depositing a drain metal on the n-type GaN layer, and epitaxially preparing an intrinsic GaN layer and an AlGaN layer.

[0085] It should be noted that the drain metal is arranged flush with the top of the intrinsic GaN layer and the AlGaN layer, and is arranged on the top of the n-type GaN layer.

[0086] Specifically, the step of depositing the drain metal on the n-type GaN layer may include: depositing a barrier layer on the n-type GaN layer; etching a drain metal through hole on the barrier layer to deposit the drain metal in the drain metal through hole. Figure 5 , Figure 5 This is a third structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device proposed in the present invention, in which a barrier layer is deposited on an n-type GaN layer, a metal via hole is etched, and a metal is deposited.

[0087] Furthermore, the step of epitaxially preparing an intrinsic GaN layer and an AlGaN layer may include: epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer with the same thickness on the n-type GaN layer, epitaxially preparing a second intrinsic GaN layer with the same lateral position on the first intrinsic GaN layer, and epitaxially preparing a second AlGaN layer with the same lateral position on the first AlGaN layer.

[0088] It should be understood that the intrinsic GaN layer includes a first intrinsic GaN layer and a second intrinsic GaN layer, and the AlGaN layer includes a first AlGaN layer and a second AlGaN layer. The top of the first intrinsic GaN layer and the bottom of the second intrinsic GaN layer are flush with the bottom of the insulating metal. The first AlGaN layer is horizontally arranged with the first intrinsic GaN layer, and the second AlGaN layer is horizontally arranged with the second intrinsic GaN layer.

[0089] Specifically, the step of epitaxially preparing the first intrinsic GaN layer and the first AlGaN layer with the same thickness on the n-type GaN layer can refer to Figure 6 , Figure 6 The fourth structural schematic diagram of an embodiment of the method for preparing a P-type GaN HEMT device proposed in the present invention is as follows: a barrier layer is deposited on the n-type GaN layer; a first intrinsic GaN layer through hole is etched on the barrier layer to deposit a first intrinsic GaN layer in the first intrinsic GaN layer through hole.

[0090] Reference Figure 7 , Figure 7 The fifth structural diagram of an embodiment of the method for preparing a P-type GaN HEMT device proposed in the present invention is as follows: the barrier layer is removed, and a barrier layer is deposited on the first intrinsic GaN layer; a first AlGaN layer through hole is etched on the barrier layer to deposit a first AlGaN layer in the first AlGaN layer through hole.

[0091] Reference Figure 8 , Figure 8 The sixth structural diagram of an embodiment of the method for preparing a P-type GaN HEMT device proposed in the present invention is as follows: a barrier layer is deposited on the first intrinsic GaN layer; a second intrinsic GaN layer through hole is etched on the barrier layer to deposit a second intrinsic GaN layer in the second intrinsic GaN layer through hole.

[0092] Reference Fig. 9 , Fig. 9 The seventh structural diagram of an embodiment of the method for preparing a P-type GaN HEMT device proposed in the present invention is as follows: the barrier layer is removed, and a barrier layer is deposited on the first AlGaN layer; a second AlGaN layer through hole is etched on the barrier layer to deposit a second AlGaN layer in the second AlGaN layer through hole.

[0093] Step S40: depositing an insulating dielectric, a P-type GaN layer and a gate metal in the AlGaN layer, and depositing a source metal on the AlGaN layer.

[0094] Specifically, the insulating medium may be a concave region extending inwardly and arranged inside the second AlGaN layer. Fig.10 , Fig.10 The eighth structural diagram of the first embodiment of the method for preparing a P-type GaN HEMT device proposed by the present invention is as follows: a barrier layer is deposited on the second AlGaN layer; an insulating medium through hole is etched on the barrier layer to deposit the insulating medium in the insulating medium through hole.

[0095] Reference Fig.11 , Fig.11 The ninth structural diagram of the first embodiment of the method for preparing a P-type GaN HEMT device proposed by the present invention is as follows: removing the barrier layer, depositing a barrier layer on the insulating medium; etching a p-type GaN through hole on the barrier layer, and depositing p-type GaN in the p-type GaN through hole.

[0096] Reference Fig.12 , Fig.12 The tenth structural diagram of the first embodiment of the method for preparing a P-type GaN HEMT device proposed by the present invention is as follows: removing the barrier layer, depositing a barrier layer on the insulating medium; etching a gate metal through hole on the barrier layer, and depositing a gate metal in the gate metal through hole.

[0097] Reference Fig.13 , Fig.13 The eleventh structural schematic diagram of an embodiment of a method for preparing a P-type GaN HEMT device proposed in the present invention. The step of depositing a source metal on the AlGaN layer may include: depositing a barrier layer on the AlGaN layer; etching a source metal through hole on the barrier layer to deposit the source metal in the source metal through hole.

[0098] In this embodiment, the preparation method of the P-type GaN HEMT device may include: epitaxially growing a GaN buffer layer on an intrinsic silicon carbide substrate. Epitaxially growing an n-type GaN layer on an intrinsic silicon carbide substrate with a GaN buffer layer. Depositing a barrier layer on the n-type GaN layer, etching a through hole for the metal, and depositing a through metal. Removing the barrier layer, depositing a barrier layer on the n-type GaN layer, etching a through hole for the intrinsic GaN layer, and depositing an intrinsic GaN layer. Removing the barrier layer, depositing a barrier layer on the n-type GaN layer, etching a through hole for the AlGaN layer, and depositing an AlGaN layer. Removing the barrier layer, depositing a barrier layer on the n-type GaN layer, etching a through hole for the intrinsic GaN layer for a second time, and depositing an intrinsic GaN layer for a second time. Removing the barrier layer, depositing a barrier layer on the n-type GaN layer, etching a through hole for the AlGaN layer for a second time, and depositing an AlGaN layer for a second time. Remove the barrier layer, deposit a barrier layer, etch the gate structure through hole, etch the gate structure groove along the through hole, and deposit the insulating dielectric. Remove the barrier layer, deposit a barrier layer, etch the p-type GaN through hole, and deposit the p-type GaN layer. Remove the barrier layer, deposit a barrier layer, etch the gate metal through hole, etch the gate metal groove along the through hole, and deposit the gate metal. Remove the barrier layer, deposit a barrier layer, etch the source metal through hole, and deposit the source metal. On the basis of ensuring the low on-resistance and high switching speed of the device, the high withstand voltage and high power density of the device are prioritized.

[0099] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0100] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A P-type GaN HEMT device, characterized in that: The P-type GaN HEMT device comprises: an intrinsic silicon carbide substrate, a GaN buffer layer and an n-type GaN layer which are arranged in sequence from bottom to top vertically; The P-type GaN HEMT device further comprises: an intrinsic GaN layer, an AlGaN layer and a drain metal arranged horizontally on the n-type GaN layer, wherein the intrinsic GaN layer has the same thickness as the AlGaN layer; The P-type GaN HEMT device further includes: an insulating medium extending inwardly from the upper end of the AlGaN layer; The P-type GaN HEMT device further includes: a P-type GaN layer and a gate metal arranged laterally and horizontally inside the insulating medium; The P-type GaN HEMT device further includes a source metal that is flush with the top of the gate metal and is disposed on the upper portion of the AlGaN layer.

2. The P-type GaN HEMT device according to claim 1, characterized in that: Setting a first preset doping concentration of the GaN buffer layer according to the thickness of the GaN buffer layer; A second preset doping concentration of the P-type GaN layer is set according to the width of the P-type GaN layer.

3. The P-type GaN HEMT device according to claim 2, characterized in that: The insulating medium is a concave structure, and the insulating medium comprises: a first insulating part and a second insulating part; The first insulating portion is disposed longitudinally between the AlGaN layer and the gate metal; The second insulating portion is laterally disposed between the AlGaN layer and the P-type GaN layer.

4. The P-type GaN HEMT device according to claim 3, characterized in that: The ratio of Al to GaN in the AlGaN layer is set to a first preset ratio according to a gate turn-on voltage of the P-type GaN HEMT device.

5. A method for preparing a P-type GaN HEMT device, applied to the preparation of the P-type GaN HEMT device according to any one of claims 1 to 4, characterized in that: The preparation method comprises the following steps: Epitaxially growing a GaN buffer layer on an intrinsic silicon carbide substrate; epitaxially growing an n-type GaN layer on the GaN buffer layer; Depositing a drain metal on the n-type GaN layer, and epitaxially preparing an intrinsic GaN layer and an AlGaN layer; An insulating dielectric, a P-type GaN layer and a gate metal are deposited in the AlGaN layer, and a source metal is deposited on the AlGaN layer.

6. The preparation method according to claim 5, characterized in that: The step of depositing a drain metal on the n-type GaN layer and epitaxially preparing an intrinsic GaN layer and an AlGaN layer comprises: Depositing a barrier layer on the n-type GaN layer; Etching a drain metal through hole on the barrier layer to deposit the drain metal in the drain metal through hole; epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer having the same thickness on the n-type GaN layer; epitaxially preparing a second intrinsic GaN layer having the same lateral position on the first intrinsic GaN layer; epitaxially preparing a second AlGaN layer having the same lateral position on the first AlGaN layer; The top of the first intrinsic GaN layer and the bottom of the second intrinsic GaN layer are flush with the bottom of the insulating metal.

7. The preparation method according to claim 6, characterized in that: The step of epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer with the same thickness on the n-type GaN layer comprises: Depositing a barrier layer on the n-type GaN layer; Etching a first intrinsic GaN layer through hole on the barrier layer to deposit a first intrinsic GaN layer in the first intrinsic GaN layer through hole; removing the barrier layer, and depositing a barrier layer on the first intrinsic GaN layer; A first AlGaN layer through hole is etched on the barrier layer to deposit a first AlGaN layer in the first AlGaN layer through hole.

8. The preparation method according to claim 6, characterized in that: The step of epitaxially preparing a second intrinsic GaN layer having the same lateral position on the first intrinsic GaN layer comprises: Depositing a barrier layer on the first intrinsic GaN layer; Etching a second intrinsic GaN layer through hole on the barrier layer to deposit a second intrinsic GaN layer in the second intrinsic GaN layer through hole; The step of epitaxially preparing a second AlGaN layer in the same lateral position on the first AlGaN layer comprises: removing the barrier layer, and depositing a barrier layer on the first AlGaN layer; A second AlGaN layer through hole is etched on the barrier layer to deposit a second AlGaN layer in the second AlGaN layer through hole.

9. The preparation method according to claim 6, characterized in that: The step of depositing an insulating medium, a P-type GaN layer and a gate metal in the AlGaN layer, and depositing a source metal on the AlGaN layer comprises: depositing a barrier layer on the second AlGaN layer; Etching an insulating medium through hole on the barrier layer to deposit the insulating medium in the insulating medium through hole; removing the barrier layer and depositing a barrier layer on the insulating medium; Etching a p-type GaN through hole on the barrier layer to deposit p-type GaN in the p-type GaN through hole; removing the barrier layer and depositing a barrier layer on the insulating medium; etching a gate metal through hole on the barrier layer to deposit a gate metal in the gate metal through hole; A source metal is deposited on the AlGaN layer.

10. The preparation method according to claim 9, characterized in that: The step of depositing a source metal on the AlGaN layer comprises: Depositing a barrier layer on the AlGaN layer; A source metal via is etched on the barrier layer to deposit the source metal in the source metal via.

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