Transistor structure
By designing well regions with different doping concentrations in the transistor structure, the challenge of preventing breakdown and reducing the Kirk effect in the prior art is solved, achieving higher electrical performance and reliability.
Patent Information
- Application Number
- CN202311067294.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-23
- Publication Date
- 2025-02-28
AI Technical Summary
Existing transistor structures have challenges in improving electrical performance and reliability, especially in preventing breakdown and reducing the Kirk effect.
A transistor structure is designed, including first and second well regions with different doping concentrations, gate structures, drift regions, doping regions and isolation structures. The higher doping concentration of the first well region prevents breakdown, and the lower doping concentration of the second well region avoids the doping compensation effect, thereby reducing the damage caused by the Kirk effect and hot carriers.
By optimizing the doping concentration of the well region, it effectively prevents breakdown and reduces the Kirk effect, and improves the electrical performance and reliability of the transistor structure.
Smart Images
Figure CN119545853A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure, and in particular to a transistor structure. Background Art
[0002] Currently, transistor structures are widely used in various electronic products. However, how to further improve the electrical performance and reliability of transistor structures is a goal that needs continuous efforts. Summary of the invention
[0003] The present invention provides a transistor structure which has better electrical performance and better reliability.
[0004] The present invention provides a transistor structure, including a substrate, a first well region, a second well region, a gate structure, a drift region, a first doping region, a second doping region and a first isolation structure. The first well region and the second well region are located in the substrate and are adjacent to each other. The gate structure is located on the substrate. The drift region is located in the second well region on one side of the gate structure. The first doping region and the second doping region are located in the substrate on both sides of the gate structure. The first doping region is located in the first well region. The second doping region is located in the drift region. The first isolation structure is located in the substrate between the gate structure and the second doping region. The first well region has a first portion that is lower than the bottom surface of the drift region. The second well region has a second portion that is lower than the bottom surface of the drift region. The doping concentration of the first portion of the first well region is greater than the doping concentration of the second portion of the second well region.
[0005] According to an embodiment of the present invention, in the above transistor structure, the first well region may have a third portion that is lower than the bottom surface of the first isolation structure. The second well region may have a fourth portion that is lower than the bottom surface of the first isolation structure. The doping concentration of the third portion of the first well region may be greater than the doping concentration of the fourth portion of the second well region.
[0006] According to an embodiment of the present invention, in the transistor structure, the first well region may have a top surface and a bottom surface opposite to each other. The top surface may be adjacent to the gate structure. The first well region may have a doping concentration that increases from the top surface to the bottom surface.
[0007] According to an embodiment of the present invention, in the transistor structure, the second well region may have a top surface and a bottom surface opposite to each other. The top surface may be adjacent to the gate structure. The second well region may have a doping concentration that decreases from the top surface to the bottom surface.
[0008] According to an embodiment of the present invention, in the above transistor structure, the bottom surface of the drift region may be lower than the bottom surface of the first isolation structure. The drift region may surround the first isolation structure.
[0009] According to an embodiment of the present invention, in the above transistor structure, the drift region may also be located in the first well region.
[0010] According to an embodiment of the present invention, in the transistor structure, a portion of the first well region may be located directly below the gate structure.
[0011] According to an embodiment of the present invention, in the transistor structure, a portion of the second well region may be located directly below the gate structure.
[0012] According to an embodiment of the present invention, in the above transistor structure, a portion of the drift region may be located directly below the gate structure.
[0013] According to an embodiment of the present invention, in the above transistor structure, a portion of the first isolation structure may be located directly below the gate structure.
[0014] According to an embodiment of the present invention, in the above transistor structure, the gate structure may include a gate and a gate dielectric layer. The gate is located on a substrate. The gate dielectric layer is located between the gate and the substrate.
[0015] According to an embodiment of the present invention, in the transistor structure, the first well region and the second well region may have a first conductivity type, and the drift region, the first doping region and the second doping region may have a second conductivity type.
[0016] According to an embodiment of the present invention, in the above transistor structure, the substrate may have a first conductivity type.
[0017] According to an embodiment of the present invention, the transistor structure may further include a third well region. The third well region is located in the substrate below the first well region and the second well region. The third well region may have the second conductivity type.
[0018] According to an embodiment of the present invention, in the transistor structure, the first well region and the second well region may be connected to the third well region.
[0019] According to an embodiment of the present invention, in the above transistor structure, a lightly doped drain (LDD) region may be further included. The lightly doped drain region is located in the first well region between the first doping region and the gate structure. The lightly doped drain region may have a second conductivity type.
[0020] According to an embodiment of the present invention, in the above transistor structure, the lightly doped drain region may be located directly below the gate structure.
[0021] According to an embodiment of the present invention, the transistor structure may further include a bulk region. The bulk region is located in the first well region. The first doped region may be located between the gate structure and the bulk region. The bulk region may have a first conductivity type.
[0022] According to an embodiment of the present invention, the transistor structure may further include a second isolation structure located in the substrate between the first doped region and the main region.
[0023] According to an embodiment of the present invention, in the above transistor structure, the bottom surface of the first well region may be lower than the bottom surface of the second isolation structure. The first well region may surround the second isolation structure.
[0024] Based on the above, in the transistor structure proposed by the present invention, the first well region has a first portion that is lower than the bottom surface of the drift region, the second well region has a second portion that is lower than the bottom surface of the drift region, and the doping concentration of the first portion of the first well region is greater than the doping concentration of the second portion of the second well region. Therefore, the higher doping concentration of the first portion of the first well region can prevent the occurrence of a punch through phenomenon between the first doping region and the drift region, and the lower doping concentration of the second portion of the second well region can avoid excessive doping compensation effect at the overlap of the second portion and the drift region, thereby reducing the Kirk effect of the drift region and reducing the damage caused by hot carriers generated by the local strong electric field, thereby improving the electrical performance and reliability of the transistor structure.
[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 2 is a cross-sectional view of a transistor structure according to some embodiments of the present invention.
[0027] Description of Figure Numbers:
[0028] 10: Semiconductor structure
[0029] 100: substrate
[0030] 102,104,120: Well region
[0031] 106: Gate structure
[0032] 108: Drift Zone
[0033] 110,112: doping area
[0034] 114,126: Isolation structure
[0035] 116: Gate
[0036] 118: Gate dielectric layer
[0037] 122: Lightly doped drain region
[0038] 124: Main area
[0039] P1: Part 1
[0040] P2: Part 2
[0041] P3: Part 3
[0042] P4: Part 4
[0043] S1, S2, S4, S6, S7: bottom
[0044] S3, S5: Top surface
[0045] T1: Transistor structure DETAILED DESCRIPTION
[0046] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.
[0047] Figure 1 is a cross-sectional view of a transistor structure according to some embodiments of the present invention.
[0048] Please refer to Figure 1 , the transistor structure T1 includes a substrate 100, a well region 102, a well region 104, a gate structure 106, a drift region 108, a doped region 110, a doped region 112 and an isolation structure 114. In some embodiments, the transistor structure T1 may be a laterally diffused metal oxide semiconductor (LDMOS) transistor structure. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 100 may have a first conductivity type (e.g., P type).
[0049] Hereinafter, the first conductivity type and the second conductivity type may be one and the other of the P-type conductivity type and the N-type conductivity type, respectively. That is, the first conductivity type and the second conductivity type are different conductivity types. In this embodiment, the first conductivity type may be the P-type conductivity type, and the second conductivity type may be the N-type conductivity type, but the present invention is not limited thereto. In other embodiments, the first conductivity type may be the N-type conductivity type, and the second conductivity type may be the P-type conductivity type.
[0050] Well region 102 and well region 104 are located in substrate 100 and are adjacent to each other. Figure 1 , the boundary of the portion of the well region 102 overlapping the drift region 108 is indicated by a bold dashed line, and the boundary of the portion of the well region 104 overlapping the drift region 108 is indicated by a bold dashed line. In some embodiments, the well region 102 may be connected to or overlap the well region 104. In some embodiments, a portion of the well region 102 may be located directly below the gate structure 106. In some embodiments, a portion of the well region 104 may be located directly below the gate structure 106. The well region 102 and the well region 104 may have the same conductivity type. In some embodiments, the well region 102 and the well region 104 may have a first conductivity type (e.g., P type).
[0051] The gate structure 106 is located on the substrate 100. In some embodiments, the gate structure 106 may include a gate 116 and a gate dielectric layer 118. The gate 116 is located on the substrate 100. In some embodiments, the gate 116 may be a doped polysilicon gate or a metal gate. The gate dielectric layer 118 is located between the gate 116 and the substrate 100. In some embodiments, the material of the gate dielectric layer 118 is, for example, silicon oxide.
[0052] The drift region 108 is located in the well region 104 at one side of the gate structure 106. In some embodiments, the drift region 108 may also be located in the well region 102. In some embodiments, a portion of the drift region 108 may be located directly below the gate structure 106. In some embodiments, the drift region 108 may have a second conductivity type (eg, N-type).
[0053] The doped region 110 and the doped region 112 are located in the substrate 100 on both sides of the gate structure 106. The doped region 110 is located in the well region 102. The doped region 112 is located in the drift region 108. In some embodiments, the doped region 110 can be used as a source region, and the doped region 112 can be used as a drain region. In some embodiments, the doped region 110 and the doped region 112 can have a second conductivity type (e.g., N-type).
[0054] The isolation structure 114 is located in the substrate 100 between the gate structure 106 and the doped region 112. In some embodiments, the bottom surface S1 of the drift region 108 may be lower than the bottom surface S2 of the isolation structure 114. In some embodiments, the drift region 108 may surround the isolation structure 114. In some embodiments, a portion of the isolation structure 114 may be located directly below the gate structure 106. In some embodiments, the isolation structure 114 may be a shallow trench isolation (STI) structure. In some embodiments, the material of the isolation structure 114 is, for example, silicon oxide.
[0055] The well region 102 has a first portion P1 that is lower than the bottom surface S1 of the drift region 108. The well region 104 has a second portion P2 that is lower than the bottom surface S1 of the drift region 108. The doping concentration of the first portion P1 of the well region 102 is greater than the doping concentration of the second portion P2 of the well region 104. Therefore, the higher doping concentration of the first portion P1 of the well region 102 can prevent the breakdown phenomenon between the doping region 110 and the drift region 108, while the lower doping concentration of the second portion P2 of the well region 104 can avoid excessive doping compensation effect at the overlap of the second portion P2 and the drift region 108, thereby reducing the Kirk effect of the drift region 108 and reducing the damage caused by hot carriers generated by the local strong electric field, thereby improving the electrical performance and reliability of the transistor structure T1. In some embodiments, the well region 102 and the well region 104 may have a first conductivity type (e.g., P type), and the doping concentration of the first conductivity type dopant (e.g., P type dopant) in the first portion P1 of the well region 102 may be greater than the doping concentration of the first conductivity type dopant (e.g., P type dopant) in the second portion P2 of the well region 104.
[0056] The well region 102 may have a third portion P3 that is lower than the bottom surface S2 of the isolation structure 114. The well region 104 may have a fourth portion P4 that is lower than the bottom surface S2 of the isolation structure 114. The doping concentration of the third portion P3 of the well region 102 may be greater than the doping concentration of the fourth portion P4 of the well region 104, wherein the higher doping concentration of the third portion P3 may prevent breakdown between the doping region 110 and the drift region 108, and the lower doping concentration of the fourth portion P4 may avoid excessive doping compensation effect at the overlap of the fourth portion P4 and the drift region 108, thereby reducing the Kirk effect of the drift region 108 and reducing the damage caused by hot carriers generated by the local strong electric field, thereby improving the electrical performance and reliability of the transistor structure T1. In some embodiments, the well region 102 and the well region 104 may have a first conductivity type (e.g., P type), and the doping concentration of the first conductivity type dopant (e.g., P type dopant) in the third portion P3 of the well region 102 may be greater than the doping concentration of the first conductivity type dopant (e.g., P type dopant) in the fourth portion P4 of the well region 104.
[0057] In some embodiments, the well region 102 may have a top surface S3 and a bottom surface S4 opposite to each other. The top surface S3 may be adjacent to the gate structure 106. In some embodiments, the well region 102 may have a doping concentration that increases from the top surface S3 to the bottom surface S4, thereby facilitating optimization of the threshold voltage (Vt) and the transistor gate control capability. In some embodiments, the well region 104 may have a top surface S5 and a bottom surface S6 opposite to each other. The top surface S5 may be adjacent to the gate structure 106. The well region 104 may have a doping concentration that decreases from the top surface S5 to the bottom surface S6.
[0058] In some embodiments, the transistor structure T1 may further include a well region 120. The well region 120 is located in the substrate 100 below the well region 102 and the well region 104. In some embodiments, the well region 102 and the well region 104 may be connected to the well region 120. The well region 120 may have a second conductivity type (e.g., N-type). In some embodiments, the well region 120 may be a deep well region (e.g., a deep N-type well, DNW) having a second conductivity type.
[0059] In some embodiments, the transistor structure T1 may further include a lightly doped drain region 122. The lightly doped drain region 122 is located in the well region 102 between the doped region 110 and the gate structure 106. In some embodiments, the lightly doped drain region 122 may be located directly below the gate structure 106. In some embodiments, the lightly doped drain region 122 may have a second conductivity type (e.g., N-type).
[0060] In some embodiments, the transistor structure T1 may further include a body region 124. The body region 124 is located in the well region 102. The doped region 110 may be located between the gate structure 106 and the body region 124. In some embodiments, the body region 124 may have a first conductivity type (eg, P type).
[0061] In some embodiments, the transistor structure T1 may further include an isolation structure 126. The isolation structure 126 is located in the substrate 100 between the doped region 110 and the body region 124. In some embodiments, the bottom surface S4 of the well region 102 may be lower than the bottom surface S7 of the isolation structure 126. In some embodiments, the well region 102 may surround the isolation structure 126. In some embodiments, the isolation structure 126 may be a shallow trench isolation structure. In some embodiments, the material of the isolation structure 126 is, for example, silicon oxide.
[0062] In some embodiments, the semiconductor structure 10 may include a plurality of transistor structures T1. In some embodiments, two adjacent transistor structures T1 are disposed on both sides of the doping region 112 in a mirror-symmetrical manner and may share the substrate 100, the well region 104, the drift region 108, and the doping region 112. In some embodiments, two adjacent transistor structures T1 may also share the well region 120.
[0063] Based on the above embodiments, it can be known that in the transistor structure T1, the well region 102 has a first portion P1 that is lower than the bottom surface S1 of the drift region 108, the well region 104 has a second portion P2 that is lower than the bottom surface S1 of the drift region 108, and the doping concentration of the first portion P1 of the well region 102 is greater than the doping concentration of the second portion P2 of the well region 104. Therefore, the higher doping concentration of the first portion P1 of the well region 102 can prevent the breakdown phenomenon between the doping region 110 and the drift region 108, and the lower doping concentration of the second portion P2 of the well region 104 can avoid excessive doping compensation effect at the overlap of the second portion P2 and the drift region 108, thereby reducing the Kirk effect of the drift region 108 and reducing the damage caused by hot carriers generated by the local strong electric field, thereby improving the electrical performance and reliability of the transistor structure T1.
[0064] In summary, in the transistor structure of the above embodiment, the first well region and the second well region are located in the substrate and are adjacent to each other. The gate structure is located on the substrate. The drift region is located in the second well region on one side of the gate structure. The first doping region and the second doping region are located in the substrate on both sides of the gate structure. The first doping region is located in the first well region. The second doping region is located in the drift region. The first isolation structure is located in the substrate between the gate structure and the second doping region. The first well region has a first portion that is lower than the bottom surface of the drift region. The second well region has a second portion that is lower than the bottom surface of the drift region. The doping concentration of the first portion of the first well region is greater than the doping concentration of the second portion of the second well region. Therefore, the higher doping concentration of the first portion of the first well region can prevent the phenomenon of breakdown between the first doping region and the drift region, and the lower doping concentration of the second portion of the second well region can avoid excessive doping compensation effect at the overlap of the second portion and the drift region, thereby reducing the Kirk effect of the drift region and reducing the damage caused by hot carriers generated by the local strong electric field, thereby improving the electrical performance and reliability of the transistor structure.
[0065] Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.
Claims
1. A transistor structure, characterized in that: include: substrate; A first well region and a second well region are located in the substrate and are adjacent to each other; A gate structure, located on the substrate; a drift region located in the second well region on one side of the gate structure; A first doping region and a second doping region are located in the substrate at two sides of the gate structure, wherein the first doping region is located in the first well region, and the second doping region is located in the drift region; as well as A first isolation structure is located in the substrate between the gate structure and the second doping region, wherein The first well region has a first portion that is lower than a bottom surface of the drift region, The second well region has a second portion that is lower than a bottom surface of the drift region, and A doping concentration of the first portion of the first well region is greater than a doping concentration of the second portion of the second well region.
2. The transistor structure according to claim 1, characterized in that: The first well region has a third portion that is lower than a bottom surface of the first isolation structure, The second well region has a fourth portion that is lower than a bottom surface of the first isolation structure, and A doping concentration of the third portion of the first well region is greater than a doping concentration of the fourth portion of the second well region.
3. The transistor structure according to claim 1, characterized in that: The first well region has a top surface and a bottom surface opposite to each other, The top surface is adjacent to the gate structure, and The first well region has a doping concentration that increases from the top surface to the bottom surface.
4. The transistor structure according to claim 1, characterized in that: The second well region has a top surface and a bottom surface opposite to each other, The top surface is adjacent to the gate structure, and The second well region has a doping concentration that decreases from the top surface to the bottom surface.
5. The transistor structure according to claim 1, characterized in that: A bottom surface of the drift region is lower than a bottom surface of the first isolation structure, and the drift region surrounds the first isolation structure.
6. The transistor structure according to claim 1, characterized in that: The drift region is also located in the first well region.
7. The transistor structure according to claim 1, characterized in that: A portion of the first well region is located directly below the gate structure.
8. The transistor structure according to claim 1, characterized in that: A portion of the second well region is located directly below the gate structure.
9. The transistor structure according to claim 1, characterized in that: A portion of the drift region is located directly below the gate structure.
10. The transistor structure according to claim 1, characterized in that: A portion of the first isolation structure is located directly below the gate structure.
11. The transistor structure according to claim 1, characterized in that: The gate structure comprises: a gate disposed on the substrate; and The gate dielectric layer is located between the gate and the substrate.
12. The transistor structure according to claim 1, wherein: The first well region and the second well region have a first conductivity type, and the drift region, the first doping region, and the second doping region have a second conductivity type.
13. The transistor structure according to claim 12, characterized in that: The substrate has the first conductivity type.
14. The transistor structure according to claim 12, characterized in that: Also includes: The third well region is located in the substrate below the first well region and the second well region, wherein the third well region has the second conductivity type.
15. The transistor structure according to claim 14, characterized in that: The first well region and the second well region are connected to the third well region.
16. The transistor structure according to claim 12, characterized in that: Also includes: A lightly doped drain region is located in the first well region between the first doped region and the gate structure, wherein the lightly doped drain region has the second conductivity type.
17. The transistor structure according to claim 16, characterized in that: The lightly doped drain region is located directly below the gate structure.
18. The transistor structure according to claim 12, characterized in that: Also includes: A body region is located in the first well region, wherein the first doped region is located between the gate structure and the body region, and the body region has the first conductivity type.
19. The transistor structure according to claim 18, characterized in that: Also includes: The second isolation structure is located in the substrate between the first doped region and the main region.
20. The transistor structure according to claim 19, characterized in that A bottom surface of the first well region is lower than a bottom surface of the second isolation structure, and the first well region surrounds the second isolation structure.