Semiconductor terminal structure with embedded FLR buried JTE, manufacturing method of semiconductor terminal structure and semiconductor device

Abstract

The invention provides a semiconductor terminal structure with an embedded FLR buried JTE, a manufacturing method of the semiconductor terminal structure and a semiconductor device, and belongs to the technical field of semiconductor devices. The semiconductor terminal structure comprises a substrate, an epitaxial layer and an interlayer dielectric layer which are stacked in sequence, a buried layer and a well region located on the buried layer are arranged in the epitaxial layer; the buried layer is divided into a plurality of buried suspended JTE partitions by partition regions; and a plurality of field limiting rings are at least arranged in the epitaxial layer closest to the main junction region of the semiconductor device. Wherein the doping types of the substrate, the epitaxial layer and the separation region are all a first type; the doping type of the buried layer, the well region and the field limiting ring is a second type. Through the structural design, the electric field of the semiconductor device can be better distributed, the aggregation degree of the electric field is reduced, and the voltage endurance capability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor terminal structure with an embedded FLR buried JTE and a manufacturing method thereof, and a semiconductor device including the semiconductor terminal structure. Background Art

[0002] Due to the curvature effect of the pn junction of wide bandgap semiconductor devices, the electric field is concentrated at the edge of the junction, causing the reverse blocking ability of the device to be seriously degraded, which in turn causes the device to be broken down prematurely, greatly reducing the withstand voltage level of the device. In order to solve the above problems, a terminal structure is usually designed in the semiconductor device to adjust the distribution of the electric field and increase the breakdown voltage of the device.

[0003] At present, the commonly used terminal structures in commercial wide bandgap semiconductor devices (such as silicon carbide devices) are field limiting ring (FLR) and / or junction terminal extension (JTE) structures. Although the terminal design with only field limiting rings is simple and easy to implement, and the device performance is relatively stable, it takes up more chip area and reduces chip utilization. Although the terminal design with only JTE has higher efficiency, the device is more sensitive to cross-sectional charge and the preparation process is more complicated, resulting in higher manufacturing costs. Therefore, the terminal structure combining FLR and JTE can better alleviate the electric field concentration phenomenon.

[0004] However, with the diversification of epitaxial structures of wide bandgap semiconductor devices, especially in trench MOSFET (metal-oxide-semiconductor field-effect transistor) devices, the terminal region of the device cannot use conventional FLR or JTE structures due to the design of doped regions to protect the trench corners of the trench gate. This is because the epitaxial structure that protects the trench corners of the trench gate will shield all FLR and JTE effects, resulting in failure of the terminal structure. Summary of the invention

[0005] Based on the above technical problems, the present invention provides a semiconductor terminal structure with embedded FLR buried JTE. The semiconductor terminal structure can be stably applied to semiconductor devices with gate groove corner protection zones, and can optimize the electric field distribution of the device and improve the breakdown voltage of the device; at the same time, it can reduce the sensitivity of the device to interface charge and improve the overall performance of the device.

[0006] Specifically, in order to achieve the above purpose, the present invention adopts the following technical solutions: A wide bandgap semiconductor terminal structure with embedded FLR buried JTE, comprising a substrate, an epitaxial layer and an interlayer dielectric layer stacked in sequence; a buried layer and a well region located above the buried layer are arranged in the epitaxial layer; the buried layer is divided into a plurality of buried suspended JTE partitions by a separation region; a plurality of field limiting rings are arranged in at least the epitaxial layer closest to the main junction region of the semiconductor device; the doping types of the substrate, the epitaxial layer and the separation region are all of the first type; the doping types of the buried layer, the well region and the field limiting ring are all of the second type.

[0007] In a preferred solution, the separation region is a first doping region, and the doping concentration of the first doping region is greater than the doping concentration of the epitaxial layer.

[0008] In a further preferred embodiment, the first doped region is a multi-layer structure, and the size of each layer along the direction from the substrate to the interlayer dielectric layer is different.

[0009] In a preferred solution, an electric field blocking layer is provided in the epitaxial layer between the buried layer and the well region.

[0010] In a preferred solution, a first trench is provided in the field limiting ring; and the first trench is filled with the interlayer dielectric layer.

[0011] In a further preferred embodiment, the first groove is a multi-level groove.

[0012] The present invention also provides a method for preparing the wide bandgap semiconductor terminal structure with embedded FLR and buried JTE, comprising the following steps: S1, growing an epitaxial layer on a substrate, and forming a buried layer in the epitaxial layer; the buried layer divides the epitaxial layer into a first epitaxial layer located below the buried layer and a second epitaxial layer located above the buried layer; forming a separation area in the buried layer to obtain a buried suspended JTE partition; S2, forming a well region in an upper layer of the second epitaxial layer; S3, forming an embedded FLR partition consisting of a plurality of field limiting rings in the epitaxial layer closest to the main junction region of the semiconductor device; S4. Depositing an interlayer dielectric layer on the upper surface of the second epitaxial layer.

[0013] The present invention also provides a semiconductor device with a wide bandgap semiconductor terminal structure including the embedded FLR buried JTE.

[0014] In a preferred solution, the semiconductor device includes a second doped region in the epitaxial layer in the main junction region, and the doping type of the second doped region is the second type.

[0015] In a further preferred solution, a second trench is provided in the second doping region, and the second trench is filled with the interlayer dielectric layer.

[0016] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) In the present invention, a composite terminal structure of an embedded FLR buried JTE is designed, and the size of each buried suspended JTE partition along the direction from the main junction region to the terminal region is adjusted, as well as the number of FLRs in each embedded FLR partition, the doping width of each FLR and the spacing between two adjacent FLRs are adjusted, so that the electric field of the device is better distributed, the degree of electric field concentration is reduced, and the voltage resistance of the device is improved.

[0017] (2) The separation area in the buried layer that is farthest from the main junction area (or closest to the scribe area) serves as the electric field cutoff area, which can prevent charges from entering the scribe area and avoid leakage of the device; at the same time, it can also quickly cut off the electric field, thereby achieving the purpose of alleviating the electric field strength and adjusting the electric field distribution.

[0018] (3) The well region can reduce the sensitivity of the terminal structure to the interface charge and prevent the electric field from gathering from the separation region to the device surface. At the same time, the well region can also serve as a JTE structure to further optimize the electric field distribution inside the device and improve the device's withstand voltage capability.

[0019] (4) The electric field blocking layer can further block the electric field passing through the separation region and optimize the electric field distribution inside the device, thereby further improving the breakdown characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1~Figure 4 A process diagram of preparing a semiconductor terminal structure in Example 3 of the present invention; Figure 5 A schematic diagram of the structure of a semiconductor device including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE provided by the present invention; Figure 6 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Figure 7 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Figure 8 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Fig. 9 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Fig.10 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Fig.11 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Fig.12 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Fig.13 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Fig.14 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Fig.15 A schematic structural diagram of another semiconductor device provided by the present invention including a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE; Fig.16 It is a schematic diagram of the preparation process of forming a buried layer in the epitaxial layer in step S1 of embodiment 3 of the present invention.

[0021] In the figure: 1, substrate; 2, epitaxial layer; 201, first epitaxial layer; 202, second epitaxial layer; 3, interlayer dielectric layer; 4, buried layer; 401, buried suspended JTE partition; 5, well region; 6, separation region; 601, first doped region; 7, embedded FLR partition; 701, field limiting ring; 8, electric field blocking layer; 9, anode; 10, cathode; 11, second doped region. DETAILED DESCRIPTION

[0022] The following content is combined with the embodiments to clearly and completely describe the technical solution of the present application so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made to the following implementation modes by those of ordinary skill in the art without creative work belongs to the protection scope of the present application.

[0023] Directional terms described in this application, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", etc., indicate directions or positional relationships based on directions or positional relationships in the drawings of the specification, or directions or positional relationships in which the products of this application are usually placed when in use, and are only for the convenience of describing and understanding the product structure of this application. Therefore, directional terms cannot be understood as limiting this application. In this application, unless otherwise clearly defined, expressions such as "upper", "above", "above", and "upper surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is higher in level than the second feature. Expressions such as "lower", "below", "below", and "lower surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is lower in level than the second feature. Ordinal numbers used in this application, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0024] Example 1 Reference Figure 5 , a wide bandgap semiconductor terminal structure with embedded FLR (field limiting ring) and buried JTE (junction terminal extension), comprising a substrate 1, an epitaxial layer 2 located on the upper surface of the substrate 1, and an interlayer dielectric layer 3 located on the upper surface of the epitaxial layer 2. A buried layer 4 and a well region 5 located above the buried layer 4 are provided in the epitaxial layer 2. The buried layer 4 is divided into a plurality of buried suspended JTE partitions 401 by a partition 6. The semiconductor device is divided into a main junction region A, a terminal region B, and a scribe region C. An embedded FLR partition 7 is provided at least in the epitaxial layer 2 closest to the main junction region A of the semiconductor device. A plurality of field limiting rings 701 are provided in each embedded FLR partition 7. The doping type of the substrate 1, the epitaxial layer 2, and the partition 6 is the first type. The doping type of the buried layer 4, the well region 5, and the field limiting ring 701 is the second type.

[0025] In the above scheme, the buried layer 4 is divided into a plurality of buried suspended JTE partitions 401, and an embedded FLR partition is provided in at least the epitaxial layer closest to the main junction region A. By designing the composite terminal structure of the embedded FLR buried JTE, and adjusting the size of each buried suspended JTE partition 401 along the direction from the main junction region A to the terminal region B, and adjusting the number of FLRs in each embedded FLR partition, the doping width of each FLR (the size of the FLR in the direction from the main junction region A to the terminal region B) and the spacing between two adjacent FLRs, the electric field of the device is better distributed, the degree of electric field concentration is reduced, and the withstand voltage of the device is improved. The partition region 6 farthest from the main junction region A in the buried layer 4 is used as an electric field cutoff region, which can prevent charges from entering the scribe region C and avoid leakage of the device; at the same time, the electric field can be quickly cut off, so as to achieve the purpose of alleviating the electric field strength and adjusting the electric field distribution. The well region 5 can reduce the sensitivity of the terminal structure to the interface charge and prevent the electric field from gathering from the separation region 6 to the device surface; at the same time, the well region can also serve as a JTE structure to further optimize the electric field distribution inside the device and enhance the voltage resistance of the device.

[0026] In a further preferred embodiment, Figure 6 As shown, an electric field blocking layer 8 is provided in the epitaxial layer 2 between the buried layer 4 and the well region 5. The doping type of the electric field blocking layer 8 is the second type. The electric field blocking layer 8 can further block the electric field passing through the separation region, optimize the electric field distribution inside the device, and thus further improve the breakdown characteristics of the device.

[0027] As an example, the material of the substrate 1 is at least one of SiC, GaN, Ga2O3, diamond, and AlN.

[0028] As an example, the well region 5 is continuously distributed in the epitaxial layer 2 (eg Figure 7 , 10 , 12). Or the well regions 5 are distributed in the epitaxial layer 2 at intervals (as shown in Figure 5 , 6 , 8, 9, 11, 13-15).

[0029] As an example, in some embodiments, the epitaxial layer 2 is used as the separation region 6 (eg Figure 8 In some other embodiments, the separation region 6 is a first doped region 601 (such as Figures 5 to 7 , 9~15).

[0030] As an example, in some embodiments, Figures 5 to 7As shown, the first doping region 601 is a single-layer structure. The width of each first doping region 601 (the size along the direction from the main junction region A to the terminal region B) can be the same or different. The distance between two adjacent first doping regions 601 can be the same or different. In other embodiments, the first doping region 601 is a multi-layer structure, and the width of each layer structure (the size along the direction from the main junction region A to the terminal region B) is different. Fig. 9 As shown, the first doping region 601 is a two-layer structure, and the width of the upper layer is greater than the width of the lower layer. It is understandable that the first doping region 601 can also be a multi-layer structure with other number of layers, and along the direction from the interlayer dielectric layer 3 to the substrate 1, the width of each layer structure gradually decreases or increases, or the width between different layers first decreases and then increases, or the width between different layers first increases and then decreases.

[0031] As an example, in some embodiments, Fig.10 , Fig.11 As shown, the embedded FLR partition 7 is only provided in the epitaxial layer 2 closest to the main junction region A. In other embodiments, as Figures 5 to 9 , Figures 12 to 15 As shown, a plurality of embedded FLR partitions 7 are arranged in the epitaxial layer 2. With respect to the buried suspended JTE partition 401, a plurality of embedded FLR partitions 7 can be arranged sequentially and continuously in the epitaxial layer 2 (eg, Figures 5 to 9 As shown), it can also be distributed in the epitaxial layer 2 at intervals (as shown Fig.12 As shown in FIG. 1 ). The number of field limiting rings 701 in each embedded FLR partition 7 may be the same or different. The width of each field limiting ring 701 (the size along the direction from the main junction region A to the terminal region B) may be the same or different. The distance between two adjacent field limiting rings 701 may be the same or different.

[0032] As an example, in some embodiments, Fig.13 As shown, along the direction from the interlayer dielectric layer 3 to the substrate 1, the doping depth of the field limiting ring 701 penetrates into the epitaxial layer 2 below the buried layer 4 (burying the suspended JTE partition 401). In other embodiments, as Fig.14 As shown, along the direction of the interlayer dielectric layer 3 pointing to the substrate 1, the doping depth of the field limiting ring 701 makes the field limiting ring 701 not contact the buried layer 4. At this time, the buried floating JTE partitions 401 are all floating JTEs. In other embodiments, such as Figures 5 to 12 As shown, along the direction from the interlayer dielectric layer 3 to the substrate 1 , the doping depth of the field limiting ring 701 penetrates into the buried layer 4 (ie, penetrates into the buried suspended JTE partition 401 ), but does not penetrate through the buried layer 4 .

[0033] As an example, in some embodiments, Fig.15As shown, a first groove is provided in the field limiting ring 701, and the first groove is filled with an interlayer dielectric layer 3. The number of levels of the first groove M≥1, that is, the first groove can be a single-level groove or a multi-level groove. The function of the first groove is to assist ion implantation to form the field limiting ring 701.

[0034] For example, if Figure 5 As shown, the buried layer 4 located in the terminal area B is divided into four separation areas 6 (i.e. Figure 5 The first doped region 601 on the upper surface is divided into four buried suspended JTE partitions 401. The partition region 6 closest to the scribe region C serves as an electric field cutoff region. The width of each partition region 6 can be the same or different; the distance between two adjacent partition regions 6 can be the same or different. In the epitaxial layer 2 where three of the four buried suspended JTE partitions 401 are located, there are corresponding embedded FLR partitions 7. Each embedded FLR partition 7 is composed of multiple field limiting rings 701. The number of field limiting rings 701 in each embedded FLR partition 7 can be the same or different; the width of each field limiting ring 701 can be the same or different; the distance between two adjacent field limiting rings 701 can be the same or different. By adjusting any one of the parameters or a combination thereof, such as the size and / or number of each separation region 6 along the direction from the main junction region A to the terminal region B, the distance between two adjacent separation regions 6, the doping width and / or number of the field limiting ring 701, the distance between two adjacent field limiting rings 701, etc., the distribution of the electric field in the device can be adjusted to improve the breakdown characteristics of the device.

[0035] Example 2 Continue to refer to Figure 5 , a semiconductor device, comprising the semiconductor terminal structure in embodiment 1. The semiconductor device also includes an anode 9, a cathode 10 and a second doping region 11. The second doping region 11 is arranged in the epitaxial layer 2 located in the main junction region A. The doping type of the second doping region 11 is a second type. The second doping region 11 forms a main junction with the epitaxial layer 2. The anode 9 is deposited on the upper surface of the second doping region 11. The cathode 10 is deposited on the surface of the substrate 1 away from the epitaxial layer 2.

[0036] As an example, Fig.13 As shown, along the direction from the interlayer dielectric layer 3 to the substrate 1, the doping depth of the second doping region 11 penetrates into the epitaxial layer 2 below the buried layer 4 (burying the suspended JTE partition 401). In other embodiments, as Fig.14 As shown, along the direction from the interlayer dielectric layer 3 to the substrate 1, the doping depth of the second doping region 11 makes the second doping region 11 not contact the buried layer 4. In other embodiments, as Figures 5 to 12As shown, along the direction from the interlayer dielectric layer 3 to the substrate 1 , the doping depth of the second doping region 11 penetrates into the buried layer 4 (ie, penetrates into the buried suspended JTE partition 401 ), but does not penetrate through the buried layer 4 .

[0037] As an example, Fig.15 As shown, a second trench is provided in the second doping region 11. The second trench is filled with an interlayer dielectric layer 3. The anode 9 covers the upper surface of the second doping region 11 and the upper surface of the interlayer dielectric layer 3 located in the second trench.

[0038] Example 3 Reference Figures 1 to 4 and Fig.16 A method for preparing a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE comprises the following steps: S1. growing an epitaxial layer on a substrate and forming a buried layer in the epitaxial layer; the buried layer divides the epitaxial layer into a first epitaxial layer below the buried layer and a second epitaxial layer above the buried layer; forming a separation region in the buried layer to obtain a buried suspended JTE partition; S2, forming a well region in the upper layer of the second epitaxial layer; S3, forming an embedded FLR partition consisting of a plurality of field limiting rings in the epitaxial layer closest to the main junction region of the semiconductor device; S4, depositing an interlayer dielectric layer on the upper surface of the second epitaxial layer.

[0039] As an example, the method of forming the buried layer in the epitaxial layer in step S1 is ion implantation. When the buried layers are spaced apart in the epitaxial layer, each buried layer is a buried suspended JTE partition; the epitaxial layer between two adjacent buried layers acts as a partition (e.g. Fig.16 When the buried layer is continuously distributed as a whole in the epitaxial layer, first doped regions are formed in the buried layer by ion implantation, and the first doped regions serve as separation regions (such as Figure 2 as shown).

[0040] As an example, in step S1, a first epitaxial layer is first grown on the substrate, a buried layer is then grown on the upper surface of the first epitaxial layer, and then a second epitaxial layer is grown on the upper surface of the buried layer. The first epitaxial layer and the second epitaxial layer are collectively referred to as epitaxial layers. A first doped region is formed in the buried layer by ion implantation and is spaced apart in the buried layer, and the first doped region serves as a separation region.

[0041] As an example, the method of forming the well region in step S2 is ion implantation.

[0042] As an example, the method of forming the field limiting ring in step S3 is ion implantation.

[0043] Example 4 Reference Figures 1 to 5 A method for preparing a semiconductor device includes the method for preparing a wide bandgap semiconductor terminal structure with an embedded FLR and buried JTE in Example 3, and further includes the following steps: In step S3, a second doped region is formed in the epitaxial layer of the main junction region by ion implantation; After the interlayer dielectric layer is deposited in step S4, the interlayer dielectric layer on the upper surface of the epitaxial layer in the main junction area is etched away, and an anode metal is deposited on the upper surface of the epitaxial layer in the main junction area to form an anode; then a drain metal is deposited on the lower surface of the substrate to form a drain electrode.

[0044] The above-described embodiments are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various changes and modifications. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A wide bandgap semiconductor terminal structure with embedded FLR buried JTE, characterized in that: It comprises a substrate, an epitaxial layer and an interlayer dielectric layer stacked in sequence; a buried layer and a well region located above the buried layer are arranged in the epitaxial layer; the buried layer is divided into a plurality of buried suspended JTE partitions by a separation region; at least in the epitaxial layer closest to the main junction region of the semiconductor device, a plurality of field limiting rings are arranged; the doping types of the substrate, the epitaxial layer and the separation region are all of the first type; the doping types of the buried layer, the well region and the field limiting ring are all of the second type.

2. The semiconductor terminal structure according to claim 1, characterized in that: The separation region is a first doping region, and the doping concentration of the first doping region is greater than the doping concentration of the epitaxial layer.

3. The semiconductor terminal structure according to claim 2, characterized in that: The first doped region is a multi-layer structure, and the size of each layer along the direction from the substrate to the interlayer dielectric layer is different.

4. The semiconductor terminal structure according to claim 1, characterized in that: An electric field blocking layer is arranged in the epitaxial layer between the buried layer and the well region.

5. The semiconductor terminal structure according to claim 1, characterized in that: A first trench is arranged in the field limiting ring; the first trench is filled with the interlayer dielectric layer.

6. The semiconductor terminal structure according to claim 5, characterized in that: The first groove is a multi-level groove.

7. The method for preparing a semiconductor terminal structure according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1, growing an epitaxial layer on a substrate, and forming a buried layer in the epitaxial layer; the buried layer divides the epitaxial layer into a first epitaxial layer located below the buried layer and a second epitaxial layer located above the buried layer; forming a separation area in the buried layer to obtain a buried suspended JTE partition; S2, forming a well region in an upper layer of the second epitaxial layer; S3, forming an embedded FLR partition consisting of a plurality of field limiting rings in the epitaxial layer closest to the main junction region of the semiconductor device; S4. Depositing an interlayer dielectric layer on the upper surface of the second epitaxial layer.

8. A semiconductor device, characterized in that: A semiconductor terminal structure comprising any one of claims 1 to 6.

9. The semiconductor device according to claim 8, characterized in that It includes a second doping region in the epitaxial layer located in the main junction region, and the doping type of the second doping region is a second type.

10. The semiconductor device according to claim 9, characterized in that A second trench is provided in the second doping region, and the second trench is filled with the interlayer dielectric layer.

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