Radiation hardening transistor module with high thermal stability and packaging method thereof

Abstract

According to the radiation hardening transistor module with high thermal stability and the packaging method of the radiation hardening transistor module, a low parasitic power combination framework is established through balance of a radiation hardening Si power device and a gallium nitride high electron mobility transistor power supply device; controlling the radiation hardening Si power device to be in a linear mode; constructing a combined power structure, integrating a whole application program development component and an IC, combining a passive element and a gallium nitride high electron mobility transistor power supply equipment power architecture, and carrying out radiation hardening channel metal-oxide-semiconductor field effect transistor combination; the layout of the gate driving circuit and the circuit board is optimized through circuit design, and the layout design of the board after overlapping verification is carried out, so that the radiation resistance of space application is improved; functional area SMD packaging is added, stress relief and thermal expansion relief are provided, the matching thermal expansion coefficient gradually changes from a ceramic substrate to a PCB electric base, and the mismatching stress of the thermal expansion coefficient is reduced by means of solder impregnation of the radiation-resistant reinforcing power discrete device and increase of the terminal side distance.

Description

Technical Field

[0001] The present invention relates to the field of high-end intelligent manufacturing technology for semiconductor radiation-resistant reinforced packaging, and more specifically, to a radiation-resistant reinforced transistor module with high thermal stability and a packaging method thereof. Background Art

[0002] At present, the reliability of electronic equipment operating in high radiation and high temperature difference environments in space is extremely important; Radiation hardening (rad hardening) performs high radiation and high temperature difference tasks in the presence of space radiation. There are many variables in the operation of aerospace devices and the system must provide consistent and reliable performance; Due to the material differences between PCB circuit boards and on-board power devices, maintaining reliable welding between the two, as well as maintaining the sealing integrity of highly reliable, sealed packaged devices is a major challenge; High-energy photons or particles can cause transient mutations, and if the voltage of the entire component exceeds its rated value, it will damage the transistor; How to achieve a better solution; Achieve high-reliability space missions and achieve radiation resistance with severe thermal cycle packaging design Strengthen (rad-strengthened) transistor modules and power metal oxide semi-field effect transistor devices to alleviate the thermal expansion difference and stress matching in the weld between the circuit board and the device package; specifically including: how to balance the radiation-resistant reinforcement, how to control the power device in linear mode, how to build a combined power structure to develop components and ICs, combine passive components and power supply equipment power architecture, how to optimize circuit design drive and layout and verify the improvement of radiation resistance of space applications, how to match the thermal expansion coefficient and reduce the high thermal expansion coefficient mismatch stress and other issues remain to be solved; therefore, it is necessary to propose a high thermal stability radiation-resistant reinforced transistor module and its packaging method to at least partially solve the problems existing in the prior art. Summary of the invention

[0003] A series of simplified concepts are introduced in the content of the invention, which will be further described in detail in the specific implementation method section; the content of the invention of the present invention does not mean to attempt to limit the key features and essential technical features of the technical solution claimed for protection, nor does it mean to attempt to determine the scope of protection of the technical solution claimed for protection.

[0004] To at least partially solve the above problems, the present invention provides a high thermal stability radiation hardened transistor module, comprising:

[0005] The radiation-hardened balancing submodule establishes a low parasitic power combination architecture by balancing the radiation-hardened Si power devices and the GaN high electron mobility transistor power devices; controls the radiation-hardened Si power devices in linear mode;

[0006] The program channel combination architecture submodule builds a combined power structure, integrates the entire application development components and ICs, combines passive components and GaN high electron mobility transistor power device power architecture, and performs radiation-hardened channel metal oxide semi-field effect transistor combination;

[0007] Overlap verification post-board layout submodule, which optimizes gate drive circuit and circuit board layout through circuit design, and performs overlap verification post-board layout design to improve radiation resistance in space applications;

[0008] Stress thermal expansion matching anti-radiation sub-module, add functional area SMD package, and provide stress relief and thermal expansion relief, match the thermal expansion coefficient gradient from the ceramic substrate to the PCB electrical base, and reduce the high thermal expansion coefficient mismatch stress through anti-radiation reinforcement power discrete device solder dipping and increased terminal side spacing.

[0009] Preferably, the radiation hardened balancing submodule comprises:

[0010] Low parasitic power combination architecture balancing unit, which establishes a low parasitic power combination architecture by balancing the radiation-hardened Si power devices and the GaN high electron mobility transistor power devices;

[0011] Control the radiation hardening unit and control the radiation hardening Si power device in linear mode through a linear control circuit to maintain radiation resistance and high reliability working in the SOA safe operation area.

[0012] Preferably, the program channel combination architecture submodule includes:

[0013] Vertically integrated architecture unit, which builds a combined power structure through vertical integration of devices, integrates the entire application development components and ICs, and combines passive components and GaN high electron mobility transistor power device power architecture;

[0014] The vertically integrated architecture unit is combined with a radiation-hardened channel metal oxide semi-conductor field effect transistor to set up adaptive packaging and maintain high performance operation in radiation environment.

[0015] Preferably, the overlap verification rear panel layout submodule comprises:

[0016] Gate drive layout optimization unit, which optimizes gate drive circuit and circuit board layout through circuit design to adapt to high reliability applications in strong radiation environments in space;

[0017] Overlap verification layout unit, through overlap verification of rear panel layout design, and use of new footprint compatible with radiation hardened P-channel MOSFET, improves radiation resistance performance for space applications.

[0018] Preferably, the stress thermal expansion matching radiation-resistant submodule comprises:

[0019] Thermal expansion stress relief unit, adding functional area SMD packaging and providing stress relief, thermal expansion relief between the anti-radiation reinforcement part and the circuit board to solve thermal expansion mismatch;

[0020] Gradual matching anti-radiation resistance reduction unit, matching thermal expansion coefficient gradient from ceramic substrate to PCB electrical base, reducing high thermal expansion coefficient mismatch stress through anti-radiation reinforcement power discrete device solder dipping and increased terminal side spacing, solving stress cracking and reducing thermal resistance and electrical resistance.

[0021] The present invention provides a method for packaging a radiation-hardened transistor module with high thermal stability, comprising:

[0022] S100, establishes a low parasitic power combination architecture by balancing radiation-hardened Si power devices and GaN high electron mobility transistor power devices; controls the radiation-hardened Si power devices in linear mode;

[0023] S200, builds a combined power structure, integrates the entire application development components and IC, combines passive components and GaN high electron mobility transistor power device power architecture, and performs radiation-hardened channel metal oxide semi-field effect transistor combination;

[0024] S300, which optimizes gate drive circuits and circuit board layout through circuit design, and performs overlap verification post-board layout design to improve radiation resistance for space applications;

[0025] S400, adds functional area SMD packaging, and provides stress relief and thermal expansion relief, matches the thermal expansion coefficient gradient from the ceramic substrate to the PCB electrical base, and reduces the high thermal expansion coefficient mismatch stress through anti-radiation reinforcement of power discrete device solder dipping and increased terminal side spacing.

[0026] Preferably, S100 includes:

[0027] S101, a low parasitic power combined architecture is established by balancing radiation-hardened Si power devices and GaN high electron mobility transistor power devices;

[0028] S102, controlling the radiation hardened Si power device to be in a linear mode through a linear control circuit, maintaining radiation resistance and high reliability to operate in a SOA safe operation area.

[0029] Preferably, S200 includes:

[0030] S201, building a combined power structure through vertical integration of devices, integrating the entire application development components and ICs, combining passive components and GaN high electron mobility transistor power device power architecture;

[0031] The S203, through a combination of radiation-hardened channel metal oxide semi-conductor field effect transistors, sets adaptive packaging and maintains high performance operation in radiation environments.

[0032] Preferably, S300 includes:

[0033] S301, through circuit design, optimizes gate drive circuit and circuit board layout to adapt to high reliability applications in strong radiation environments in space;

[0034] S302, through overlap verification of the backplane layout design, and using a new footprint compatible with radiation-hardened P-channel MOSFET, improves radiation resistance performance for space applications.

[0035] Preferably, S400 includes:

[0036] S401, add functional area SMD package and provide stress relief, thermal expansion relief between the anti-radiation reinforcement part and the circuit board to solve the thermal expansion mismatch;

[0037] S402, matching thermal expansion coefficient gradient from ceramic substrate to PCB electrical base, reducing high thermal expansion coefficient mismatch stress through radiation hardening power discrete device solder dipping and increasing terminal side spacing, solving stress cracking and reducing thermal resistance and electrical resistance.

[0038] Compared with the prior art, the present invention has at least the following beneficial effects:

[0039] The present invention discloses a high thermal stability radiation-hardened transistor module and a packaging method thereof, which adopts a radiation-hardened balancing submodule, establishes a low parasitic power combination architecture by balancing a radiation-hardened Si power device and a gallium nitride high electron mobility transistor power device; controls the radiation-hardened Si power device to be in a linear mode; a program channel combination architecture submodule is used to construct a combined power structure, integrate the entire application development component and IC, combine passive components and a gallium nitride high electron mobility transistor power device power architecture, and perform a radiation-hardened channel metal oxide semi-field effect transistor combination; an overlapping verification rear board layout submodule is used to optimize the gate drive circuit and circuit board layout through circuit design, and perform an overlapping verification rear board layout design to improve the radiation resistance of space applications; a stress thermal expansion matching radiation-hardened submodule is used to add a functional area SMD package, and provide stress relief and thermal expansion relief, match the thermal expansion coefficient from a ceramic substrate to a PCB electrical base gradient, and increase the terminal side spacing through the solder dipping of the radiation-hardened power discrete device Reduce the stress of high thermal expansion coefficient mismatch; can significantly improve the reliability of electronic equipment operating in high radiation and high temperature difference environments in space; the operation consistency and reliability of radiation-hardened devices are significantly improved; the welding reliability and sealing package integrity between PCB circuit boards and power devices on the board are greatly improved; high-energy photons or particles can cause transient mutations and significantly enhance the adaptation stability; can achieve high-reliability space missions. Radiation hardening of packages under severe thermal cycling conditions; the difference in weld thermal expansion between transistor modules and power metal oxide semi-conductor field effect transistor device circuit boards and device packages is significantly offset, and stress matching is significantly improved; significantly improve the balance of radiation hardening, and can control power devices in linear mode with greatly improved reliability; combine power structure development components and ICs and combine passive components and power supply equipment power architecture, and the stability is greatly improved; optimize drive, layout and verification to significantly improve the radiation resistance of space applications; can match thermal expansion coefficients and reduce high thermal expansion coefficient mismatch stress, significantly improving the radiation resistance of space applications.

[0040] The present invention describes a high thermal stability radiation-hardened transistor module and a packaging method thereof. Other advantages, objectives and features of the present invention will be partially reflected through the following description, and will also be partially understood by technicians in this field through research and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0042] Figure 1 This is a diagram of an embodiment of a high thermal stability radiation hardened transistor module according to the present invention.

[0043] Figure 2This is another embodiment of a high thermal stability radiation hardened transistor module macro structure according to the present invention.

[0044] Figure 3 This is a diagram of an application example of a high thermal stability radiation-hardened transistor module and a packaging method thereof according to the present invention. DETAILED DESCRIPTION

[0045] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments so that those skilled in the art can implement the invention with reference to the instructions. As shown in the drawings, the present invention provides a high thermal stability radiation-hardened transistor module, comprising:

[0046] The radiation-hardened balancing submodule establishes a low parasitic power combination architecture by balancing the radiation-hardened Si power devices and the GaN high electron mobility transistor power devices; controls the radiation-hardened Si power devices in linear mode;

[0047] The program channel combination architecture submodule builds a combined power structure, integrates the entire application development components and ICs, combines passive components and GaN high electron mobility transistor power device power architecture, and performs radiation-hardened channel metal oxide semi-field effect transistor combination;

[0048] Overlap verification post-board layout submodule, which optimizes gate drive circuit and circuit board layout through circuit design, and performs overlap verification post-board layout design to improve radiation resistance in space applications;

[0049] Stress thermal expansion matching anti-radiation sub-module, add functional area SMD package, and provide stress relief and thermal expansion relief, match the thermal expansion coefficient gradient from the ceramic substrate to the PCB electrical base, and reduce the high thermal expansion coefficient mismatch stress through anti-radiation reinforcement power discrete device solder dipping and increased terminal side spacing.

[0050] The principle and effect of the above technical solution are as follows: the present invention provides a high thermal stability radiation-hardened transistor module, including: a radiation-hardened balancing submodule, which establishes a low parasitic power combination architecture by balancing the radiation-hardened Si power device and the GaN high electron mobility transistor power device; controls the radiation-hardened Si power device to be in linear mode; a program channel combination architecture submodule, which constructs a combined power structure, integrates the entire application development components and IC, combines passive components and GaN high electron mobility transistor power device power architecture, and performs radiation-hardened channel metal oxide semi-field effect transistor combination; overlap verification rear board layout submodule, which optimizes gate drive circuit and circuit board layout through circuit design , and perform overlapping verification on the rear board layout design to improve the radiation resistance of space applications; stress thermal expansion matching radiation-resistant sub-modules, add functional area SMD packaging, and provide stress relief and thermal expansion relief, matching the thermal expansion coefficient from the ceramic substrate to the PCB electrical base gradient, and reducing the high thermal expansion coefficient mismatch stress through radiation-resistant reinforced power discrete device solder dipping and increased terminal side spacing; radiation-resistant reinforced Si power devices include: triode module radiation-resistant reinforced Si power devices and radiation-resistant reinforced SiMOSFETS; gallium nitride high electron mobility transistor power devices include: gallium nitride high electron mobility transistor lateral GaNHEMT power devices and gallium nitride high electron mobility transistor vertical GaN HEMT power supply equipment; can significantly improve the reliability of electronic equipment operating in high-radiation and high-temperature difference environments in space; the operating consistency and reliability of radiation-hardened devices are significantly improved; the welding reliability and sealed packaging integrity between PCB circuit boards and power devices on the board are greatly improved; high-energy photons or particles can cause transient mutations and significantly enhance the adaptation stability; can achieve high-reliability space missions. Radiation hardening of packages under severe thermal cycling conditions; the difference in weld thermal expansion between transistor modules and power metal oxide semi-conductor field effect transistor device circuit boards and device packages is significantly offset, and stress matching is significantly improved; the balance of radiation hardening is significantly improved, and the power devices can be controlled in linear mode, and the reliability is greatly improved; the power structure development components and ICs are combined and the passive components and power supply equipment power architecture are combined, and the stability is greatly improved; optimized driving, layout and verification significantly improve the radiation resistance of space applications; can match the thermal expansion coefficient and reduce the mismatch stress of high thermal expansion coefficient, significantly improving the radiation resistance of space applications.

[0051] In one embodiment, the radiation hardened balancing submodule includes:

[0052] Low parasitic power combination architecture balancing unit, which establishes a low parasitic power combination architecture by balancing the radiation-hardened Si power devices and the GaN high electron mobility transistor power devices;

[0053] Control the radiation hardening unit and control the radiation hardening Si power device in linear mode through a linear control circuit to maintain radiation resistance and high reliability working in the SOA safe operation area.

[0054] The principle and effect of the above technical solution are as follows: the radiation hardening balancing submodule includes: a low parasitic power combination architecture balancing unit, which establishes a low parasitic power combination architecture by balancing the radiation hardening Si power device and the GaN high electron mobility transistor power supply device; controls the radiation hardening unit to control the radiation hardening Si power device in linear mode through a linear control circuit to maintain radiation resistance and high reliability working in the SOA safe operation area; performs radiation hardening packaging simulation and thermal stability simulation in advance; establishes a low parasitic power combination architecture by balancing the radiation hardening Si power device and the GaN high electron mobility transistor power supply device. The power combination architecture includes: setting to reduce parasitic inductance in the gate drive loop; simulating the performance balance between high switching frequency and high electron mobility, balancing radiation-hardened Si power devices and GaN high electron mobility transistor power devices; pre-simulating radiation-hardened packaging and thermal stability simulation; balancing radiation-hardened Si power devices and GaN high electron mobility transistor power devices, increasing the switching frequency and gate-source voltage range to strongly change, and reducing the sensitivity of circuit parasitic effects; adapting to space flight applications; establishing a low parasitic power combination architecture; SOA safe operating area is represented as Safe OPerating Area; Linear control circuit includes: output sequence controller, PWM controller and compensation network; Turn-on components of linear regulator; Protection circuit, including input under-voltage protection and output over-voltage protection, hot plug and soft start, short circuit protection and output cut-off discharge; Select gate resistor with quality factor Q between critical damping and under-damping; Critical damping quality factor Q is preferably 0.5 and under-damping quality factor Q is preferably 1; If the quality factor is greater than 0.5, GaN high electron mobility transistor power device control speeds up turn-on and turn-off speed; First monitor the gate drive ringing frequency without external resistor; Set input capacitance; Calculate source inductance LS; According to critical damping quality factor Q, 0.5 and the underdamped quality factor Q is preferably 1, and the total series resistance when it is equal to the inductor reactance or twice the inductor reactance is calculated; the external gate resistance is obtained by subtracting the internal gate drive resistance and the transistor gate resistance from the total series resistance; the external gate resistance is iteratively calculated from the minimum value with a set precision micro-resistance increment, and a new external gate resistance value is cyclically calculated according to the ringing frequency, source inductance and input capacitance, and the balance parameters are adjusted iteratively; the radiation-resistant reinforcement includes: pre-burying electrode points on the inverted radiation-resistant substrate, and growing and forming a second integrated type emitter injection region at the corresponding electrode points by ion implantation; injecting the second integrated type emitter into the The second integrated type emitter well region is deposited on the surface of the region; the second integrated type collector and the first integrated type base are grown on the inverted radiation-resistant substrate, and the second integrated type collector injection region and the first integrated type base injection region are formed by ion implantation; the silicon oxide electrical isolation region is filled on the inverted radiation-resistant substrate; the n region and the p region are isolated to reduce interference; the second integrated type collector well region and the first integrated type base well region are deposited by depositing a silicon nitride layer and growing an oxide layer to cover and deposit; the second integrated type buried layer is formed by growing doped ion implantation; the first integrated type substrate silicon wafer is covered; the whole is subjected to radiation-resistant hardening packaging; and a radiation-resistant hardening structure is formed. .

[0055] In one embodiment, the program channel combination architecture submodule includes:

[0056] Vertically integrated architecture unit, which builds a combined power structure through vertical integration of devices, integrates the entire application development components and ICs, and combines passive components and GaN high electron mobility transistor power device power architecture;

[0057] The vertically integrated architecture unit is combined with a radiation-hardened channel metal oxide semi-conductor field effect transistor to set up adaptive packaging and maintain high performance operation in radiation environment.

[0058] The principles and effects of the above technical solution are: program channel combination architecture sub-module, including: vertical integration architecture unit, building a combined power structure through device vertical integration combination, integrating the entire application development components and IC, combining passive components and gallium nitride high electron mobility transistor power device power architecture; vertical integration architecture unit, through anti-radiation reinforced channel metal oxide semi-field effect transistor combination, setting adaptive packaging and maintaining high performance operation in radiation environment.

[0059] In one embodiment, the overlap verification post-board layout submodule includes:

[0060] Gate drive layout optimization unit, which optimizes gate drive circuit and circuit board layout through circuit design to adapt to high reliability applications in strong radiation environments in space;

[0061] Overlap verification layout unit, through overlap verification of rear panel layout design, and use of new footprint compatible with radiation hardened P-channel MOSFET, improves radiation resistance performance for space applications.

[0062] The principles and effects of the above technical solution are as follows: overlapping verification of the rear board layout sub-module, including: a gate drive layout optimization unit, which optimizes the gate drive circuit and circuit board layout through circuit design to adapt to high-reliability applications in strong radiation environments in space; an overlapping verification layout unit, which verifies the rear board layout design through overlapping verification, and uses a new footprint to be compatible with radiation-hardened P-channel MOSFET to improve the radiation resistance of space applications; and verifies the rear board layout design through overlapping verification, and uses a new footprint to be compatible with radiation-hardened P-channel MOSFET to improve the radiation resistance of space applications, including: through overlapping verification of the rear board layout design, the infrared HiRel's radiation-hardened metal-oxide-semiconductor field-effect transistor is designed to absorb more avalanche energy, and uses a new footprint to be compatible with radiation-hardened P-channel MOSFET, so that the device can withstand short pulse overshoot under the drain-source voltage, thereby improving the radiation resistance of space applications.

[0063] In one embodiment, the stress thermal expansion matching radiation resistant submodule comprises:

[0064] Thermal expansion stress relief unit, adding functional area SMD packaging and providing stress relief, thermal expansion relief between the anti-radiation reinforcement part and the circuit board to solve thermal expansion mismatch;

[0065] Gradual matching anti-radiation resistance reduction unit, matching thermal expansion coefficient gradient from ceramic substrate to PCB electrical base, reducing high thermal expansion coefficient mismatch stress through anti-radiation reinforcement power discrete device solder dipping and increased terminal side spacing, solving stress cracking and reducing thermal resistance and electrical resistance.

[0066] The principle and effect of the above technical solution are as follows: stress thermal expansion matching anti-radiation submodule, including: thermal expansion stress relief unit, adding functional area SMD package, and providing stress relief, thermal expansion relief is performed between the anti-radiation reinforcement part and the circuit board, and thermal expansion mismatch is solved; gradient matching anti-radiation resistance reduction unit, matching thermal expansion coefficient gradient from ceramic substrate to PCB electrical base, reducing high thermal expansion coefficient mismatch stress through anti-radiation reinforcement power discrete device solder dipping and increasing terminal side spacing, solving stress cracking and reducing thermal resistance and resistance; adding functional area SMD package, and providing stress relief, thermal expansion relief is performed between the anti-radiation reinforcement part and the circuit board, and solving thermal expansion mismatch includes: adding functional area SMD package, the power device is encapsulated in a sealed package mainly made of a combination of metal, ceramic and glass, and stress relief is provided in the form of copper tape lead connection to the SMD package, and ultra-infrared surface mount package is constructed, thermal expansion relief is performed between the anti-radiation reinforcement part and the circuit board, and thermal expansion mismatch is solved; SMD means surface mount;

[0067] Matching the thermal expansion coefficient from the ceramic substrate to the PCB electrical base gradually, reducing the high thermal expansion coefficient mismatch stress through anti-radiation reinforcement power discrete device solder dipping and increasing the terminal side spacing, solving stress cracking and reducing thermal resistance and electrical resistance, including: using gradient functional structure, matching thermal expansion coefficient auxiliary welding alloy materials, using thermal expansion coefficient gold-silicon alloy materials to assist welding PCB electrical base and transistor module, using thermal expansion coefficient gold-tin alloy materials to assist welding ceramic substrate and PCB electrical base; gold-silicon alloy material ratios include: gold-silicon The weight percentage ranges are 97.13%-97.17% and 2.87%-2.83%, preferably 97.15% and 2.85%, and the preferred error is not higher than 0.02%; the thermal expansion coefficient gold-tin alloy material ratio includes: the weight percentage ranges of gold and tin are 79.95%-80.05% and 20.05%-19.95%, preferably 80.00% and 20.00%, and the preferred error is not higher than 0.05%; low melting point eutectic welding vacuum atmosphere welding; the ceramic substrate includes silicon carbide ceramic The ceramic substrate forms a silicon carbide crystal structure by interlacing tetrahedrons of silicon-carbon and carbon-silicon. The composite structure with gradient variation is used to increase the interlacing density of silicon carbide fibers layer by layer according to the set thickness from the bottom surface 111 of the ceramic substrate to the welding surface 112 of the PCB electric base to form a silicon carbide fiber interlacing layer 113, so that the thermal expansion coefficient of the contact surface is matched consistently, and the temperature away from the contact surface gradually decreases and dissipates layer by layer. The particles are sintered and co-precipitated by temperature gradient, and the content of conductive particles is gradually increased at the contact part to form a conductive particle sedimentation layer 114. The thermal expansion coefficient is matched to change gradually from the ceramic substrate to the PCB electric base 115. The PCB electric base is matched from the ceramic substrate to assist in welding and matching the transistor module package. The terminal side spacing 116 is adjusted to match, and the terminal side spacing increases the space matching micro distance 117 to buffer the expansion and extrusion during thermal expansion. The stress of mismatching high thermal expansion coefficient is reduced by anti-radiation reinforcement of power discrete device solder dipping and increasing the terminal side spacing, so as to solve the stress cracking problem caused by the mismatching of thermal expansion coefficient between the power package and the circuit board, and reduce thermal resistance and electrical resistance.

[0068] The present invention provides a method for packaging a radiation-hardened transistor module with high thermal stability, comprising:

[0069] S100, establishes a low parasitic power combination architecture by balancing radiation-hardened Si power devices and GaN high electron mobility transistor power devices; controls the radiation-hardened Si power devices in linear mode;

[0070] S200, builds a combined power structure, integrates the entire application development components and IC, combines passive components and GaN high electron mobility transistor power device power architecture, and performs radiation-hardened channel metal oxide semi-field effect transistor combination;

[0071] S300, which optimizes gate drive circuits and circuit board layout through circuit design, and performs overlap verification post-board layout design to improve radiation resistance for space applications;

[0072] S400, adds functional area SMD packaging, and provides stress relief and thermal expansion relief, matches the thermal expansion coefficient gradient from the ceramic substrate to the PCB electrical base, and reduces the high thermal expansion coefficient mismatch stress through anti-radiation reinforcement of power discrete device solder dipping and increased terminal side spacing.

[0073] The principle and effect of the above technical solution are as follows: the present invention provides a high thermal stability radiation-hardened transistor module packaging method, including: establishing a low parasitic power combination architecture through balancing radiation-hardened Si power devices and gallium nitride high electron mobility transistor power devices; controlling the radiation-hardened Si power devices to be in linear mode; constructing a combined power structure, integrating the entire application development components and IC, combining passive components and gallium nitride high electron mobility transistor power device power architecture, and performing radiation-hardened channel metal oxide semi-field effect transistor combination; optimizing the gate drive circuit and circuit board layout through circuit design, and performing overlapping verification after the board layout design to improve the radiation resistance of space applications; adding functional area SMD packaging, and providing stress relief and thermal expansion relief, matching the thermal expansion coefficient from the ceramic substrate to the PCB electrical base gradient, and reducing the high thermal expansion coefficient mismatch stress through the radiation-hardened power discrete device solder dipping and the increase in the terminal side spacing; the radiation-hardened Si power device includes: a transistor module radiation-hardened Si power device and a radiation-hardened Si MOSFETS; Gallium nitride high electron mobility transistor power devices include: Gallium nitride high electron mobility transistor lateral GaN HEMT power devices and Gallium nitride high electron mobility transistor vertical GaN HEMT power devices; can significantly improve the reliability of electronic equipment operating in high radiation and high temperature difference environments in space; the operation consistency and reliability of radiation-hardened devices are significantly improved; the welding reliability and sealing package integrity between PCB circuit boards and power devices on the board are greatly improved; high-energy photons or particles can cause transient mutations and the adaptation stability is significantly enhanced; it can achieve high-reliability space missions. Radiation hardening of packages under severe thermal cycling conditions; the difference in weld thermal expansion between transistor modules and power metal oxide semi-field effect transistor device circuit boards and device packages is significantly offset, and stress matching is significantly improved; the balance of radiation hardening is significantly improved, and the power device can be controlled in linear mode with greatly improved reliability; combined power structure development components and ICs and combined passive components and power device power architectures, the stability is greatly improved; optimized drive and layout and verification significantly improve the radiation resistance of space applications; can match the thermal expansion coefficient and reduce the high thermal expansion coefficient mismatch stress, significantly improving the radiation resistance of space applications.

[0074] In one embodiment, S100 includes:

[0075] S101, a low parasitic power combined architecture is established by balancing radiation-hardened Si power devices and GaN high electron mobility transistor power devices;

[0076] S102, controlling the radiation hardened Si power device to be in a linear mode through a linear control circuit, maintaining radiation resistance and high reliability to operate in a SOA safe operation area.

[0077] The principle and effect of the above technical solution are: by balancing the radiation-hardened Si power device and the gallium nitride high electron mobility transistor power supply device, a low parasitic power combination architecture is established; by controlling the radiation-hardened Si power device in linear mode through a linear control circuit, the radiation resistance and high reliability are maintained to work in the SOA safe operation area; pre-perform radiation-hardened packaging simulation and thermal stability simulation; by balancing the radiation-hardened Si power device and the gallium nitride high electron mobility transistor power supply device, a low parasitic power combination architecture is established, including: setting to reduce the parasitic inductance in the gate drive loop; performing performance balance simulation between high switching frequency and high electron mobility, balancing the radiation-hardened Si power device and the gallium nitride high electron mobility transistor power supply device; pre-perform radiation-hardened packaging simulation and thermal stability simulation; by balancing the radiation-hardened Si power device and the gallium nitride high electron mobility transistor power supply device, the switching frequency and gate-source voltage range are strongly changed, and the circuit parasitic effect sensitivity is reduced; adapt to space flight space applications; establish a low parasitic power combination architecture; the SOA safe operation area is expressed as Safe OPerating Area; the linear control circuit includes: output sequence controller, PWM controller and compensation network; the conduction component of the linear regulator; the protection circuit includes input under-voltage protection and output over-voltage protection, hot plug and soft start, short circuit protection and output cut-off discharge; select the gate resistor with a quality factor Q between critical damping and under-damping; the critical damping quality factor Q is preferably 0.5 and the under-damping quality factor Q is preferably 1; if the quality factor is greater than 0.5, the GaN high electron mobility transistor power supply device control accelerates the turn-on and turn-off speed; first monitor the gate drive ringing frequency without external resistor; set the input capacitance; calculate the source inductance LS; according to the critical damping quality factor Q, preferably 0.5 and the underdamped quality factor Q is preferably 1, and the total series resistance when it is equal to the inductor reactance or twice the inductor reactance is calculated; the external gate resistance is obtained by subtracting the internal gate drive resistance and the transistor gate resistance from the total series resistance; the external gate resistance is iteratively calculated from the minimum value with a set precision micro-resistance increment, and a new external gate resistance value is cyclically calculated according to the ringing frequency, source inductance and input capacitance, and the balance parameters are adjusted iteratively; the radiation-resistant reinforcement includes: pre-burying electrode points on the inverted radiation-resistant substrate, and growing and forming a second integrated type emitter injection region at the corresponding electrode points by ion implantation; injecting the second integrated type emitter into the The second integrated type emitter well region is deposited on the surface of the region; the second integrated type collector and the first integrated type base are grown on the inverted radiation-resistant substrate, and the second integrated type collector injection region and the first integrated type base injection region are formed by ion implantation; the silicon oxide electrical isolation region is filled on the inverted radiation-resistant substrate; the n region and the p region are isolated to reduce interference; the second integrated type collector well region and the first integrated type base well region are deposited by depositing a silicon nitride layer and growing an oxide layer to cover and deposit; the second integrated type buried layer is formed by growing doped ion implantation; the first integrated type substrate silicon wafer is covered; the whole is subjected to radiation-resistant hardening packaging; and a radiation-resistant hardening structure is formed. .

[0078] In one embodiment, S200 includes:

[0079] S201, building a combined power structure through vertical integration of devices, integrating the entire application development components and ICs, combining passive components and GaN high electron mobility transistor power device power architecture;

[0080] The S203, through a combination of radiation-hardened channel metal oxide semi-conductor field effect transistors, sets adaptive packaging and maintains high performance operation in radiation environments.

[0081] The principle and effect of the above technical solution are: to build a combined power structure through vertical integration of devices, integrate the entire application development components and ICs, combine passive components and GaN high electron mobility transistor power device power architecture; through the combination of radiation-hardened channel metal oxide semi-conductor field effect transistors, set adaptive packaging and maintain high performance operation in radiation environment.

[0082] In one embodiment, S300 includes:

[0083] S301, through circuit design, optimizes gate drive circuit and circuit board layout to adapt to high reliability applications in strong radiation environments in space;

[0084] S302, through overlap verification of the backplane layout design, and using a new footprint compatible with radiation-hardened P-channel MOSFET, improves radiation resistance performance for space applications.

[0085] The principles and effects of the above technical solutions are: optimizing the gate drive circuit and circuit board layout through circuit design to adapt to high-reliability applications in the strong radiation environment of space; verifying the rear board layout design through overlap, and using a new footprint to be compatible with radiation-hardened P-channel MOSFET to improve the radiation resistance of space applications; verifying the rear board layout design through overlap, and using a new footprint to be compatible with radiation-hardened P-channel MOSFET to improve the radiation resistance of space applications, including: verifying the rear board layout design through overlap, infrared HiRel's radiation-hardened metal-oxide-semiconductor field-effect transistor is designed to absorb more avalanche energy, and using a new footprint to be compatible with radiation-hardened P-channel MOSFET, so that the device can withstand short pulse overshoot under drain-source voltage, thereby improving the radiation resistance of space applications.

[0086] In one embodiment, S400 includes:

[0087] S401, add functional area SMD package and provide stress relief, thermal expansion relief between the anti-radiation reinforcement part and the circuit board to solve the thermal expansion mismatch;

[0088] S402, matching thermal expansion coefficient gradient from ceramic substrate to PCB electrical base, reducing high thermal expansion coefficient mismatch stress through radiation hardening power discrete device solder dipping and increasing terminal side spacing, solving stress cracking and reducing thermal resistance and electrical resistance.

[0089] The principle and effect of the above technical solution are: adding a functional area SMD package and providing stress relief, performing thermal expansion relief between the radiation-resistant reinforcement part and the circuit board to solve the thermal expansion mismatch; matching the thermal expansion coefficient from the ceramic substrate to the PCB electrical base, reducing the high thermal expansion coefficient mismatch stress by solder dipping of the radiation-resistant reinforcement power discrete device and increasing the terminal side spacing, solving stress cracking and reducing thermal resistance and resistance; adding a functional area SMD package and providing stress relief, performing thermal expansion relief between the radiation-resistant reinforcement part and the circuit board to solve the thermal expansion mismatch includes: adding a functional area SMD package, the power device is encapsulated in a sealed package mainly made of a combination of metal, ceramic and glass, and stress relief is provided in the form of copper tape lead connection to the SMD package, constructing an ultra-infrared surface mount package, performing thermal expansion relief between the radiation-resistant reinforcement part and the circuit board to solve the thermal expansion mismatch;

[0090] Matching the thermal expansion coefficient from the ceramic substrate to the PCB electrical base gradually, reducing the high thermal expansion coefficient mismatch stress through anti-radiation reinforcement power discrete device solder dipping and increasing the terminal side spacing, solving stress cracking and reducing thermal resistance and electrical resistance, including: using gradient functional structure, matching thermal expansion coefficient auxiliary welding alloy materials, using thermal expansion coefficient gold-silicon alloy materials to assist welding PCB electrical base and transistor module, using thermal expansion coefficient gold-tin alloy materials to assist welding ceramic substrate and PCB electrical base; gold-silicon alloy material ratios include: gold-silicon The weight percentage ranges are 97.13%-97.17% and 2.87%-2.83%, preferably 97.15% and 2.85%, and the preferred error is not higher than 0.02%; the thermal expansion coefficient gold-tin alloy material ratio includes: the weight percentage ranges of gold and tin are 79.95%-80.05% and 20.05%-19.95%, preferably 80.00% and 20.00%, and the preferred error is not higher than 0.05%; low melting point eutectic welding vacuum atmosphere welding; the ceramic substrate includes silicon carbide ceramic The ceramic substrate forms a silicon carbide crystal structure by interlacing tetrahedrons of silicon-carbon and carbon-silicon. The composite structure with gradient variation is used to increase the interlacing density of silicon carbide fibers layer by layer according to the set thickness from the bottom surface 111 of the ceramic substrate to the welding surface 112 of the PCB electric base to form a silicon carbide fiber interlacing layer 113, so that the thermal expansion coefficient of the contact surface is matched consistently, and the temperature away from the contact surface gradually decreases and dissipates layer by layer. The particles are sintered and co-precipitated by temperature gradient, and the content of conductive particles is gradually increased at the contact part to form a conductive particle sedimentation layer 114. The thermal expansion coefficient is matched to change gradually from the ceramic substrate to the PCB electric base 115. The PCB electric base is matched from the ceramic substrate to assist in welding and matching the transistor module package. The terminal side spacing 116 is adjusted to match, and the terminal side spacing increases the space matching micro distance 117 to buffer the expansion and extrusion during thermal expansion. The stress of mismatching high thermal expansion coefficient is reduced by anti-radiation reinforcement of power discrete device solder dipping and increasing the terminal side spacing, so as to solve the stress cracking problem caused by the mismatching of thermal expansion coefficient between the power package and the circuit board, and reduce thermal resistance and electrical resistance.

[0091] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A radiation-hardened transistor module with high thermal stability, characterized in that: include: The radiation-hardened balancing submodule establishes a low parasitic power combination architecture by balancing the radiation-hardened Si power devices and the GaN high electron mobility transistor power devices; controls the radiation-hardened Si power devices in linear mode; The program channel combination architecture submodule builds a combined power structure, integrates the entire application development components and ICs, combines passive components and GaN high electron mobility transistor power device power architecture, and performs radiation-hardened channel metal oxide semi-field effect transistor combination; Overlap verification post-board layout submodule, which optimizes gate drive circuit and circuit board layout through circuit design, and performs overlap verification post-board layout design to improve radiation resistance in space applications; Stress thermal expansion matching anti-radiation sub-module, add functional area SMD package, and provide stress relief and thermal expansion relief, match the thermal expansion coefficient gradient from the ceramic substrate to the PCB electrical base, and reduce the high thermal expansion coefficient mismatch stress through anti-radiation reinforcement power discrete device solder dipping and increased terminal side spacing.

2. The high thermal stability radiation hardened transistor module according to claim 1, characterized in that: Radiation hardened balancing submodule, including: Low parasitic power combination architecture balancing unit, which establishes a low parasitic power combination architecture by balancing the radiation-hardened Si power devices and the GaN high electron mobility transistor power devices; Control the radiation hardening unit and control the radiation hardening Si power device in linear mode through a linear control circuit to maintain radiation resistance and high reliability working in the SOA safe operation area.

3. The high thermal stability radiation hardened transistor module according to claim 1, characterized in that: Program channel combination architecture submodule, including: Vertically integrated architecture unit, which builds a combined power structure through vertical integration of devices, integrates the entire application development components and ICs, and combines passive components and GaN high electron mobility transistor power device power architecture; The vertically integrated architecture unit is combined with a radiation-hardened channel metal oxide semi-conductor field effect transistor to set up adaptive packaging and maintain high performance operation in radiation environment.

4. The high thermal stability radiation hardened transistor module according to claim 1, characterized in that: Overlap verification post-board layout submodule, including: Gate drive layout optimization unit, which optimizes gate drive circuit and circuit board layout through circuit design to adapt to high reliability applications in strong radiation environments in space; Overlap verification layout unit, through overlap verification of rear panel layout design, and use of new footprint compatible with radiation hardened P-channel MOSFET, improves radiation resistance performance for space applications.

5. The high thermal stability radiation hardened transistor module according to claim 1, characterized in that: Stress thermal expansion matching and radiation-resistant submodules include: Thermal expansion stress relief unit, adding functional area SMD packaging and providing stress relief, thermal expansion relief between the anti-radiation reinforcement part and the circuit board to solve thermal expansion mismatch; Gradual matching anti-radiation resistance reduction unit, matching thermal expansion coefficient gradient from ceramic substrate to PCB electrical base, reducing high thermal expansion coefficient mismatch stress through anti-radiation reinforcement power discrete device solder dipping and increased terminal side spacing, solving stress cracking and reducing thermal resistance and electrical resistance.

6. A method for packaging a high thermal stability radiation hardened transistor module, characterized in that: include: S100, establishes a low parasitic power combination architecture by balancing radiation-hardened Si power devices and GaN high electron mobility transistor power devices; controls the radiation-hardened Si power devices in linear mode; S200, builds a combined power structure, integrates the entire application development components and IC, combines passive components and GaN high electron mobility transistor power device power architecture, and performs radiation-hardened channel metal oxide semi-field effect transistor combination; S300, which optimizes gate drive circuits and circuit board layout through circuit design, and performs overlap verification post-board layout design to improve radiation resistance for space applications; S400, adds functional area SMD packaging, and provides stress relief and thermal expansion relief, matches the thermal expansion coefficient gradient from the ceramic substrate to the PCB electrical base, and reduces the high thermal expansion coefficient mismatch stress through anti-radiation reinforcement of power discrete device solder dipping and increased terminal side spacing.

7. The method for packaging a high thermal stability radiation hardened transistor module according to claim 6, characterized in that: S100 includes: S101, a low parasitic power combined architecture is established by balancing radiation-hardened Si power devices and GaN high electron mobility transistor power devices; S102, controlling the radiation hardened Si power device to be in a linear mode through a linear control circuit, maintaining radiation resistance and high reliability to operate in a SOA safe operation area.

8. The method for packaging a high thermal stability radiation hardened transistor module according to claim 6, characterized in that: S200 includes: S201, building a combined power structure through vertical integration of devices, integrating the entire application development components and ICs, combining passive components and GaN high electron mobility transistor power device power architecture; The S203, through a combination of radiation-hardened channel metal oxide semi-conductor field effect transistors, sets adaptive packaging and maintains high performance operation in radiation environments.

9. The method for packaging a high thermal stability radiation hardened transistor module according to claim 6, characterized in that: S300 includes: S301, through circuit design, optimizes gate drive circuit and circuit board layout to adapt to high reliability applications in strong radiation environments in space; S302, through overlap verification of the backplane layout design, and using a new footprint compatible with radiation-hardened P-channel MOSFET, improves radiation resistance performance for space applications.

10. The method for packaging a high thermal stability radiation hardened transistor module according to claim 6, characterized in that: S400 includes: S401, add functional area SMD package and provide stress relief, thermal expansion relief between the anti-radiation reinforcement part and the circuit board to solve the thermal expansion mismatch; S402, matching thermal expansion coefficient gradient from ceramic substrate to PCB electrical base, reducing high thermal expansion coefficient mismatch stress through radiation hardening power discrete device solder dipping and increasing terminal side spacing, solving stress cracking and reducing thermal resistance and electrical resistance.

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