Manufacturing method of magnetic random access memory structure and magnetic random access memory structure

Abstract

The invention provides a manufacturing method of a magnetic random access memory structure and the magnetic random access memory structure. The manufacturing method comprises the steps that a semiconductor substrate is provided and comprises a first bottom interconnection structure and a bottom electrode layer, and the bottom electrode layer is provided with a second surface; a storage bit and a metal hard mask layer which are arranged in a stacked mode are sequentially formed on the second surface, the second surface comprises a third area and a fourth area surrounding the third area, and projections of the storage bit and the metal hard mask layer on the second surface are located in the third area; the side, away from the storage bit, of the metal hard mask layer is covered with a first reaction thin film, so that the first reaction thin film and the metal hard mask layer react to generate a top electrode layer, the top electrode layer is provided with a third surface and a fourth surface which are opposite, and the third surface comprises a fifth area and a sixth area surrounding the fifth area; the projection of the storage bit on the third surface is located in the fifth region; a top interconnect structure is formed on the fourth surface.

Description

Technical Field

[0001] The present invention relates to the technical field of magnetic random access memory, and in particular to a method for manufacturing a magnetic random access memory structure and a magnetic random access memory structure. Background Art

[0002] Large-capacity, high-performance memory chips have broad application prospects in 5G, Internet of Things, artificial intelligence, automotive electronics and other fields. Magnetic random access memory chips MRAM are expected to replace SRAM, DRAM and Flash, and become a new type of general-purpose memory with high integration, high-speed read and write and non-volatile. The MRAM storage bit is a 1T1R (MOS tube + magnetic tunnel junction MTJ) structure. The core device MTJ in the storage bit is a multi-layer film structure, mainly composed of a magnetic free layer, an insulating layer and a magnetic reference layer. The key insulating layer is only 1 nanometer thick and provides the main resistance of the MTJ. The magnetic free layer can change its state through a magnetic field or a spin-polarized current. The relative relationship between the magnetic free layer and the reference layer (parallel state / antiparallel state) determines the resistance of the bit, thereby storing "0" or "1" information.

[0003] On the one hand, due to the certain height difference between the array area and the logic area, the process window of the top interconnect structure is very limited. Over-etching of the top interconnect can easily cause damage to the key layer of the array area, and even lead to the risk of short circuit, which ultimately affects the chip yield. On the other hand, over-etching of the bottom electrode layer of the core device MTJ during the preparation process can cause the top interconnect on the MTJ side wall to contact the MTJ, resulting in a short circuit. Further sidewall cleaning etching causes the first bottom interconnect structure based on the Cu process to be affected by changes in temperature, stress, etc., resulting in the risk of Cu diffusion, which affects device connectivity and reduces process reliability.

[0004] Therefore, there is an urgent need for a method for manufacturing a magnetic random access memory structure to improve the etching process window. Summary of the invention

[0005] The main purpose of the present invention is to provide a method for manufacturing a magnetic random access memory structure and a magnetic random access memory structure to solve the problem that the etching process window in the prior art is very limited.

[0006] In order to achieve the above-mentioned object, according to one aspect of the present invention, a method for manufacturing a magnetic random access memory structure is provided, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first bottom interconnection structure and a bottom electrode layer, the bottom electrode layer being located on the surface of the first bottom interconnection structure, the bottom electrode layer having a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region surrounding the first region, and the contact portion between the first bottom interconnection structure and the bottom electrode layer being the first region of the first surface; sequentially forming stacked storage bits and a metal hard mask layer on the second surface, the second surface comprising a third region and a fourth region surrounding the third region, and the projection of the storage bits and the metal hard mask layer on the second surface being located in the third region; covering a first reaction film on a side of the metal hard mask layer away from the storage bits, so that the first reaction film and the metal hard mask layer react to generate a top electrode layer, the top electrode layer having a third surface and a fourth surface opposite to each other, the third surface comprising a fifth region and a sixth region surrounding the fifth region, and the projection of the storage bits on the third surface being located in the fifth region; forming a top interconnection structure on the fourth surface, the fourth surface comprising a seventh region and an eighth region surrounding the seventh region, and the contact portion between the top interconnection structure and the top electrode layer being located in the seventh region.

[0007] Furthermore, the step of forming a top electrode layer includes: heat treating the first reaction film and the metal hard mask layer so that at least a portion of the metal hard mask layer and the first reaction film located on the surface of the metal hard mask layer form a first metal compound layer, and the first metal compound layer is arranged in contact with the storage bit; removing the first reaction film located on both sides of the first metal compound layer so that the first metal compound layer forms a top electrode layer.

[0008] Furthermore, after the step of forming the storage bit and the metal hard mask layer, the method further includes: forming a sidewall protection layer on the semiconductor substrate, the sidewall protection layer at least covering the second region of the bottom electrode layer, the sidewall of the storage bit and the sidewall of the metal hard mask layer.

[0009] Furthermore, the step of forming a storage bit and a metal hard mask layer includes: sequentially depositing a storage film and a preliminary metal hard mask layer on a semiconductor substrate, and patterning the preliminary metal hard mask layer and the storage film by photolithography and etching to form a metal hard mask layer and a storage bit; or sequentially depositing a storage film and a preliminary metal hard mask layer on a semiconductor substrate, patterning the preliminary metal hard mask layer by photolithography and etching to form a metal hard mask layer, and etching the storage film according to the metal hard mask layer to form a storage bit.

[0010] Further, the semiconductor substrate includes an array area and a logic area, a first bottom interconnection structure, a bottom electrode layer, a storage bit and a top electrode layer are all located in the array area, and the top interconnection structure is also connected to a second bottom interconnection structure in the logic area, and the steps of forming the top interconnection structure include: depositing an insulating dielectric layer on a side of the top electrode layer away from the storage bit so that the insulating dielectric layer covers the top electrode layer and the semiconductor substrate; performing a first etching on the insulating dielectric layer and the semiconductor substrate to form a first through hole penetrating the insulating dielectric layer to the top electrode layer and a second through hole penetrating the insulating dielectric layer and the semiconductor substrate to the second bottom interconnection structure, and the projection of the first through hole on the fourth surface is located in the seventh area; performing a second etching on the insulating dielectric layer so that the opening of the end of the first through hole away from the top electrode layer is larger than the opening of the end of the first through hole close to the top electrode layer, and the opening of the end of the second through hole away from the second bottom interconnection structure is larger than the opening of the end of the second through hole close to the second bottom interconnection structure; depositing a metal material on a side of the insulating dielectric layer away from the semiconductor substrate so that the metal material fills the first through hole and the second through hole to form a top interconnection structure.

[0011] Furthermore, the step of forming a semiconductor substrate includes: providing a substrate having a bottom metal wiring layer; forming a plug structure in the substrate that extends from the surface of the substrate to the bottom metal wiring layer, wherein the plug structure and the bottom metal wiring layer constitute a first bottom interconnect structure; depositing a second reaction film on a surface of the plug structure away from the bottom metal wiring layer and allowing at least part of the material forming the plug structure to react with the second reaction film located on the surface of the plug structure to form a bottom electrode layer, wherein the semiconductor substrate includes a first bottom interconnect structure and a bottom electrode layer located on the surface of the first bottom interconnect structure.

[0012] Furthermore, the material of the plug structure includes but is not limited to any one of nickel, titanium, cobalt, platinum, gold, rhodium, tantalum, and tungsten, and the material of the second reaction film includes but is not limited to any one of silicon, germanium, and silicon germanium; or the material of the plug structure includes but is not limited to any one of silicon, germanium, and silicon germanium, and the material of the second reaction film includes but is not limited to any one of nickel, titanium, cobalt, platinum, gold, rhodium, tantalum, and tungsten.

[0013] Furthermore, the step of forming the bottom electrode layer includes: heat treating the material forming the plug structure and the second reaction film located on the surface of the plug structure to form a second metal compound layer; removing the portion of the plug structure on the side away from the bottom metal wiring layer except the second metal compound layer, so that the remaining second metal compound layer forms a bottom electrode layer, the bottom electrode layer has a first surface and a second surface relative to each other, the contact portion of the first bottom interconnect structure and the bottom electrode layer is a first area of ​​the first surface, and the first surface includes a first area and a second area surrounding the first area.

[0014] According to another aspect of the present invention, there is provided a magnetic random access memory structure formed by the above-mentioned manufacturing method, comprising: a semiconductor substrate, the semiconductor substrate comprising a first bottom interconnection structure and a bottom electrode layer, the bottom electrode layer being located on the surface of the first bottom interconnection structure, the bottom electrode layer having a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region surrounding the first region, and the contact portion between the first bottom interconnection structure and the bottom electrode layer being located in the first region; a storage bit being located on the second surface, the second surface comprising a third region and a fourth region surrounding the third region, and the projection of the storage bit on the second surface being located in the third region; a top electrode layer being located on a side of the storage bit away from the semiconductor substrate, the top electrode layer having a third surface and a fourth surface opposite to each other, the third surface comprising a fifth region and a sixth region surrounding the fifth region, and the projection of the storage bit on the third surface being located in the fifth region; and a top interconnection structure being located on the fourth surface, the fourth surface comprising a seventh region and an eighth region surrounding the seventh region, and the contact surface between the top interconnection structure and the top electrode layer being located in the seventh region.

[0015] Furthermore, it also includes: a sidewall protection layer, which at least covers the second region of the bottom electrode layer, the sidewall of the storage bit and the sidewall of the metal hard mask layer.

[0016] By applying the technical solution of the present invention, a method for manufacturing a magnetic random access memory structure is provided. Since the contact portion between the first bottom interconnection structure and the bottom electrode layer is located in the first region, and the contact portion between the top interconnection structure and the top electrode layer is located in the seventh region, the connection portion between the storage bit, the first bottom interconnection structure and the top interconnection structure will not extend beyond the top electrode layer and the bottom electrode layer, thereby reducing the risk of short circuit of the device, thereby improving the etching process window of the top interconnection structure, and avoiding the problem in the prior art that the top interconnection structure contacts the storage bit due to over-etching due to the very limited etching process window. Furthermore, since the metal hard mask layer and the storage unit are formed synchronously, and the top electrode layer is generated by the reaction of the metal hard mask layer and the first reaction film, when the position of the metal hard mask is determined, there is no need to use an additional mask to position the top electrode layer, and self-alignment can be achieved to form the top electrode layer, thereby further reducing the mask level, reducing the manufacturing cost, and improving the efficiency of the process manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0018] Figure 1A schematic cross-sectional structure diagram of depositing and etching a storage film and preparing a metal hard mask layer to form a storage bit and a metal hard mask layer in a method for manufacturing a magnetic random access memory structure according to an embodiment of the present invention is shown;

[0019] Figure 2 Shown in Figure 1 A schematic diagram of a cross-sectional structure of a sidewall protection layer formed on the structure shown;

[0020] Figure 3 Shown in Figure 2 A schematic cross-sectional structure diagram of depositing a first insulating dielectric layer on the structure shown;

[0021] Figure 4 Shown in Figure 3 A schematic cross-sectional structure diagram of depositing a first reactive film on the structure shown;

[0022] Figure 5 Shows the heat treatment Figure 4 After the structure shown, a schematic cross-sectional structure diagram of a metal compound layer is formed;

[0023] Figure 6 Shown in Figure 5 A schematic diagram of a cross-sectional structure of a top electrode layer formed on the basis of the structure shown;

[0024] Figure 7 A schematic cross-sectional structure diagram of forming a top interconnection structure in one embodiment is shown;

[0025] Figure 8 A schematic cross-sectional structure diagram of forming a top interconnection structure in another embodiment is shown;

[0026] Fig. 9 A schematic cross-sectional structure diagram of forming a plug structure in a substrate is shown;

[0027] Fig.10 Shown in Fig. 9 A schematic cross-sectional structure diagram of depositing a second reactive film on the structure shown;

[0028] Fig.11 Shown in the heat treatment Fig.10 The structure shown forms a schematic cross-sectional structure of a metal compound;

[0029] Fig.12 Shown in Fig.11 A schematic diagram of the cross-sectional structure of a bottom electrode layer is formed based on the structure.

[0030] The above drawings include the following reference numerals:

[0031] 101, semiconductor substrate; 10, first bottom interconnection structure; 20, bottom electrode layer; 30, storage film; 301, storage bit; 40, preliminary metal hard mask layer; 401, metal hard mask layer; 50, sidewall protection layer; 60, first insulating dielectric layer; 70, first reaction film; 80, metal compound layer; 90, top electrode layer; 100, top interconnection structure; 110, substrate; 120, bottom metal wiring layer; 130, plug structure; 140, second reaction film. DETAILED DESCRIPTION

[0032] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] As mentioned in the background technology, due to the height difference between the array area and the logic area, the process window of the top interconnect structure is very limited. Over-etching of the top interconnect can easily cause damage to the key layer of the array area, and even cause a short circuit risk, which ultimately affects the chip yield. On the other hand, over-etching of the bottom electrode layer of the core device MTJ during the preparation process will cause the top interconnect of the MTJ side wall to contact the MTJ, resulting in a short circuit. Further sidewall cleaning etching causes the first bottom interconnect structure based on the Cu process to be affected by changes in temperature, stress, etc., resulting in the risk of Cu diffusion, which affects the connectivity of the device and reduces the process reliability. Therefore, in order to solve the above technical problems, the inventors of this application provide a method for manufacturing a magnetic random access memory structure and a magnetic random access memory structure.

[0036] According to one aspect of the present application, in some optional embodiments, a method for manufacturing a magnetic random access memory structure is provided, the manufacturing method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first bottom interconnect structure and a bottom electrode layer, the bottom electrode layer being located on the surface of the first bottom interconnect structure, the bottom electrode layer having a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region surrounding the first region, and the contact portion between the first bottom interconnect structure and the bottom electrode layer being located in the first region; sequentially forming stacked storage bits and a metal hard mask layer on the second surface, the second surface comprising a third region and a fourth region surrounding the third region, and the projection of the storage bits and the metal hard mask layer on the second surface being located in the third region; covering a first reaction film on a side of the metal hard mask layer away from the storage bits so that the first reaction film and the metal hard mask layer react to generate a top electrode layer, the top electrode layer having a third surface and a fourth surface opposite to each other, the third surface comprising a fifth region and a sixth region surrounding the fifth region, and the projection of the storage bits on the third surface being located in the fifth region; forming a top interconnect structure on the fourth surface, the fourth surface comprising a seventh region and an eighth region surrounding the seventh region, and the contact portion between the top interconnect structure and the top electrode layer being located in the seventh region.

[0037] Specifically, the first bottom interconnect structure is located in the semiconductor substrate, and the bottom electrode layer extends from the upper surface of the semiconductor substrate to the first bottom interconnect structure in the semiconductor substrate, that is, the bottom electrode layer is located on the first bottom interconnect structure and is arranged in contact with the first bottom interconnect structure. Exemplarily, the material of the first bottom interconnect structure may include but is not limited to metal copper.

[0038] Specifically, the contact portion between the bottom electrode layer and the first bottom interconnect structure is located in a first region of the first surface of the bottom electrode layer, and the first surface also includes a second region surrounding the first region, so the size of the contact portion between the first bottom interconnect structure and the bottom electrode layer is smaller than the size of the bottom electrode layer. In addition, the side surface of the bottom electrode layer away from the first bottom interconnect structure is the second surface, and accordingly, the second surface includes a third region and a fourth region surrounding the third region. Since the projections of the storage bit and the metal hard mask layer sequentially stacked on the second surface are both located in the third region on the second surface, the size of the storage bit and the size of the metal hard mask layer are both smaller than the size of the bottom electrode layer.

[0039] Specifically, the metal hard mask layer is located on the side of the storage bit away from the bottom electrode layer, and the projections of the storage bit and the metal hard mask layer on the second surface completely overlap. In order to form the top electrode layer on the side of the storage bit away from the bottom electrode layer, and the top electrode layer is generated by a chemical reaction between the metal material of the metal hard mask layer and the reactant in the first reaction film, the first reaction film is covered at least on the side of the metal hard mask layer away from the storage bit, wherein the projection of the first reaction film on the second surface is the first projection, the projection area of ​​the projection of the metal hard mask layer on the second surface is smaller than the projection area of ​​the first projection, and the projection of the metal hard mask layer on the second surface is located in the first projection, so that after the first reaction film and the metal hard mask layer react to generate the top electrode layer, when the third surface where the top electrode layer contacts the storage bit includes a fifth region and a sixth region surrounding the fifth region, the projection of the storage bit on the third surface is located in the sixth region, that is, the size of the storage bit is smaller than the size of the top electrode layer.

[0040] Optionally, the storage bit may be a magnetic tunnel junction MTJ, and the material of the metal hard mask layer may include but is not limited to any one of Ti, Co, Ni, Pt, Ru, Rh, Ta and W. The material of the first reaction film may include but is not limited to any one of silicon, germanium and silicon germanium, and therefore, the material of the top electrode layer may include but is not limited to TiSi, NiSi, NiGe, etc., and those skilled in the art may make reasonable selections according to actual needs.

[0041] Optionally, the metal hard mask layer and the first reactive film can be deposited by conventional thin film preparation methods such as CVD, PVD and ALD, the thickness of the metal hard mask layer can be 200 to 1000 angstroms, and the thickness of the first reactive film can be 200 to 400 angstroms. Optionally, the process for forming the top electrode layer can be any one of a thermal annealing process or a microwave annealing process.

[0042] Specifically, the side of the top electrode layer away from the storage bit also has a fourth surface, and the fourth surface is used to connect the top interconnection structure. In order to form the top interconnection structure, an insulating material layer covering the fourth surface of the top electrode layer is first deposited on the side of the top electrode layer away from the storage bit, and then a photolithography process is used to form a top interconnection structure connected to the top electrode layer. It can be understood that since the size of the top electrode layer is larger than the size of the storage bit, when the insulating material layer is etched on the side of the top electrode layer away from the storage bit, the top electrode layer can prevent over-etching, and further, when the fourth surface is divided into a seventh area and an eighth area surrounding the seventh area, the contact portion of the top interconnection structure and the top electrode layer is arranged in the seventh area, which can further avoid damage to the storage bit.

[0043] Through the present application, since the contact portion between the first bottom interconnect structure and the bottom electrode layer is located in the first region, and the contact portion between the top interconnect structure and the top electrode layer is located in the seventh region, the connection portion between the storage bit, the first bottom interconnect structure and the top interconnect structure will not extend beyond the top electrode layer and the bottom electrode layer, thereby reducing the risk of short circuit in the device, thereby improving the photolithography process window of the top interconnect structure, and further, since the metal hard mask layer and the storage unit are formed synchronously, and the top electrode layer is generated by the reaction of the metal hard mask layer and the first reaction film, when the position of the metal hard mask is determined, there is no need to use an additional mask to position the top electrode layer, and self-alignment can be achieved to form the top electrode layer, thereby further reducing the mask level, reducing the manufacturing cost, and improving the efficiency of the process manufacturing.

[0044] In some optional embodiments, the method for manufacturing the magnetic random access memory structure further includes: in the process of forming the stacked storage bits and the metal hard mask layer, forming a dielectric hard mask sacrificial layer on the side of the metal hard mask layer away from the storage bits. Specifically, after sequentially depositing the storage film corresponding to the storage bit and the metal mask material corresponding to the metal hard mask layer, the dielectric mask material corresponding to the dielectric hard mask sacrificial layer can be further deposited to the side of the metal mask material away from the storage film, and then the dielectric mask material is patterned by a photolithography process to form a dielectric hard mask sacrificial layer, and the dielectric hard mask sacrificial layer can be used as a mask plate (i.e., a mask layer or an etching buffer structure) for forming the metal hard mask layer and the storage bits, so that the metal mask material and the storage film are sequentially etched according to the dielectric hard mask sacrificial layer to form the metal hard mask layer and the storage bits. Further, after the step of forming the metal hard mask layer and the storage bits, the dielectric hard mask sacrificial layer can be removed by a chemical mechanical polishing process to flatten the upper surface of the metal mask layer.

[0045] In some optional embodiments, the step of forming a top electrode layer includes: heat treating the first reaction film and the metal hard mask layer so that at least a portion of the metal hard mask layer and the first reaction film located on the surface of the metal hard mask layer form a first metal compound layer, and the first metal compound layer is arranged in contact with the storage bit; removing the first reaction film located on both sides of the first metal compound layer so that the first metal compound layer forms a top electrode layer.

[0046] Optionally, a barrier layer may be deposited on a side of the first reactive film away from the metal hard mask layer to prevent metal flow during the synthesis process of the first reactive film and the metal hard mask layer.

[0047] In the above-mentioned embodiment, the first reaction film is located on the side of the metal hard mask layer away from the storage bit. By heat treating the above-mentioned first reaction film and the metal hard mask layer, the first reaction film and at least part of the metal hard mask layer can undergo a chemical reaction, that is, the metal atoms in the metal hard mask layer diffuse into the first reaction film, thereby forming the above-mentioned first metal compound layer, and the first metal compound layer is arranged in contact with the storage bit. It can be understood that when the first reaction film in contact with the metal hard mask layer is insufficient, the metal atoms in the metal hard mask layer will diffuse in the first reaction film, so that the formed first metal compound layer The projection area on the second surface is usually larger than the projection area of ​​the storage bit on the second surface, and because the projection of the metal hard mask layer on the second surface coincides with the projection of the storage bit on the second surface, the projection of the storage bit on the second surface is located in the projection of the first metal compound layer on the second surface. In order to form a top electrode layer, the portion of the first reaction film that does not form the first metal silicide layer is removed, that is, the first reaction film that does not participate in the above-mentioned chemical reaction and is located on both sides of the first metal silicide layer is removed, so that the remaining first metal compound layer forms a top electrode layer located on the side of the storage bit away from the bottom electrode layer.

[0048] Optionally, the above-mentioned heat treatment may include an annealing process. Further, the annealing process may be performed in Ar / He / N2 or other inert gases, the treatment temperature may be 100 to 400°C, and the annealing time may be 10 to 60s.

[0049] In some optional embodiments, the steps of forming the storage bit 301 and the metal hard mask layer 401 include: Figure 1 As shown, a storage film 30 and a preliminary metal hard mask layer 40 are sequentially deposited on a semiconductor substrate 101 so that the storage film 30 covers the semiconductor substrate 101 and the preliminary metal hard mask layer 40 covers the storage film 30, and the preliminary metal hard mask layer 40 and the storage film 30 are patterned by photolithography and etching processes to form a metal hard mask layer 401 and a storage bit 301; or a storage film 30 and a preliminary metal hard mask layer 40 are sequentially deposited on a semiconductor substrate 101 so that the storage film 30 covers the semiconductor substrate 101 and the preliminary metal hard mask layer 40 covers the storage film 30, and the preliminary metal hard mask layer 40 is patterned by photolithography and etching processes to form a metal hard mask layer 401, and the storage film 30 is etched according to the metal hard mask layer 401 to form a storage bit 301. The above-mentioned storage bit 301 is arranged in contact with the bottom electrode layer 20, and the bottom electrode layer 20 is arranged in contact with the first bottom interconnect structure 10.

[0050] That is, in the above-mentioned embodiment, after the storage film 30 and the preliminary metal hard mask layer 40 are deposited, the metal hard mask layer 401 and the storage bit 301 can be simultaneously etched by using a photolithography and etching process. Alternatively, after the storage film 30 and the preliminary metal hard mask layer 40 are deposited, the metal hard mask layer 401 can be firstly etched by using a photolithography and etching process, and then the metal hard mask layer 401 is used as a mask layer to etch the storage bit 301. Those skilled in the art can reasonably select the process steps for forming the storage bit 301 and the metal hard mask layer 401.

[0051] In order to protect the storage bit 301 and prevent the metal hard mask layer 401, the storage bit 301 and the bottom electrode layer 20 from being over-etched, in some optional embodiments, after the step of forming the storage bit 301 and the metal hard mask layer 401, the method for manufacturing the magnetic random access memory structure further includes: Figure 2 As shown, a sidewall protection layer 50 is formed on the semiconductor substrate 101 , and the sidewall protection layer 50 at least covers the second region of the bottom electrode layer 20 , the sidewall of the storage bit 301 , and the sidewall of the metal hard mask layer 401 .

[0052] Optionally, since the bottom electrode layer 20 extends from the upper surface of the semiconductor substrate 101 to the first bottom interconnect structure 10, the storage bit 301 and the metal hard mask layer 401 are located on the side of the bottom electrode layer 20 away from the first bottom interconnect structure 10. Therefore, after the above-mentioned storage bit 301 and the metal hard mask layer 401 are formed, the upper surface of the semiconductor substrate 101 has an exposed surface that is not covered by the storage bit 301, and therefore the above-mentioned sidewall protection layer 50 can also cover the above-mentioned exposed surface.

[0053] It can be understood that there is a height difference between the metal hard mask layer 401 and the semiconductor substrate 101. In order to form a top electrode layer having a cross section larger than the cross section of the storage bit 301 on the side of the metal hard mask layer 401 away from the semiconductor substrate 101, first, the projection of the first reaction film deposited on the side of the metal hard mask layer 401 away from the semiconductor substrate 101 on the second surface can be made larger than the projection of the storage bit 301 on the second surface. Therefore, in some optional embodiments, before the step of forming the top electrode layer 90, the manufacturing method further includes: Figure 3As shown, a first insulating dielectric layer 60 is deposited on a side of the semiconductor substrate 101 having a first surface, so that the height of the first insulating dielectric layer 60 in a direction perpendicular to the first surface is at least consistent with the metal hard mask layer 401; further, in order to make the metal hard mask layer 401 have a planarized surface, a planarization process is used to remove part of the first insulating dielectric layer 60, so that the metal hard mask layer 401 has an exposed surface on the side away from the storage bit 301. Optionally, in the case where the sidewall protection layer 50 covers the first surface of the semiconductor substrate 101 except for the contact with the storage bit 301, part of the sidewall protection layer 50 is also located between the first insulating dielectric layer 60 and the semiconductor substrate 101.

[0054] Further, a first reaction film 70 is deposited on the planarized surface, such as Figure 4 As shown in FIG. 1 , the first reaction film 70 completely covers the surface of the first insulating dielectric layer 60 away from the semiconductor substrate 101 and the surface of the metal hard mask layer 401 away from the storage bit 301, and then a heat treatment is performed to cause the first reaction film 70 and at least a portion of the metal hard mask layer 401 to react chemically to form a metal compound layer 80, as shown in FIG. Figure 5 It can be understood that during the process of forming the metal compound layer 80, at least part of the metal hard mask layer 401 is consumed, and the first reaction film 70 in contact with the metal hard mask layer 401 is completely consumed, thereby forming Figure 5 Alternatively, since the first reaction film 70 in contact with the metal hard mask layer 401 is completely consumed by part of the metal hard mask layer 401, the metal atoms in the remaining metal hard mask layer 401 will diffuse into the first reaction film 70 that is not in contact with the metal hard mask layer 401, so the cross-sectional size of the formed metal compound layer 80 is generally larger than the cross-sectional size of the original metal hard mask layer 401, so that after removing the remaining first reaction film 70 that does not participate in the compound reaction, the remaining metal compound layer 80 can be formed as follows: Figure 6 As shown in the top electrode layer 90 , it can be understood that the cross-sectional dimension of the top electrode layer 90 is larger than the cross-sectional dimension of the storage bit 301 , that is, the projection of the storage bit 301 on the second surface is located in the projection of the top electrode layer 90 on the second surface.

[0055] Since the sidewall protection layer 50 may cover the area other than the second surface of the surface of the semiconductor substrate 101 in addition to covering the second area of ​​the bottom electrode layer 20, the sidewall of the storage bit 301 and the sidewall of the metal hard mask layer 401, in order to remove the sidewall protection layer 50 covering the area other than the second surface of the surface of the semiconductor substrate 101, in some optional embodiments, when the manufacturing method includes the step of forming the sidewall protection layer 50, after the step of forming the top electrode layer 90 and before the step of forming the top interconnect structure 100, the above manufacturing method further includes: Figure 7 As shown, using the top electrode layer 90 as a mask, the first insulating dielectric layer 60 and the sidewall protection layer 50 are sequentially etched to expose the surface of the semiconductor substrate 101 except for the second surface (the upper surface of the bottom electrode layer), that is, this process step does not require the use of an additional mask, thereby reducing the process cost.

[0056] Furthermore, in some optional embodiments, such as Figure 7 As shown, the semiconductor substrate 101 includes an array region and a logic region, the first bottom interconnect structure 10, the bottom electrode layer 20, the storage bit 301 and the top electrode layer 90 are all located in the array region, and the top interconnect structure 100 is also connected to the second bottom interconnect structure in the logic region. In order to form the top interconnect structure 100 on the side of the top electrode layer 90 away from the storage bit 301, an insulating dielectric layer is first deposited on the side of the top electrode layer 90 away from the storage bit 301 so that the insulating dielectric layer covers the top electrode layer 90 and the semiconductor substrate 101; the insulating dielectric layer and the semiconductor substrate 101 are first etched to form a dielectric layer that penetrates the insulating dielectric layer to the top electrode layer 90. A first through hole and a second through hole (not shown in the figure) penetrating the insulating dielectric layer and the semiconductor substrate 101 to the second bottom interconnection structure, the projection of the first through hole on the fourth surface is located in the seventh area; the insulating dielectric layer is etched for a second time so that the opening of the first through hole at one end away from the top electrode layer 90 is larger than the opening of the first through hole at one end close to the top electrode layer 90, and the opening of the second through hole at one end away from the second bottom interconnection structure is larger than the opening of the second through hole at one end close to the second bottom interconnection structure; metal material is deposited on the side of the insulating dielectric layer away from the semiconductor substrate 101 so that the metal material fills the first through hole and the second through hole, thereby forming a top interconnection structure 100.

[0057] or alternatively, as Figure 8As shown, in other embodiments, the sidewall protection layer 50 covering the surface of the semiconductor substrate 101 except the second surface can also be retained, so that after the step of forming the metal compound layer, it is only necessary to selectively remove the remaining first reaction film 70 that has not reacted to form the metal compound layer. The selective removal can include removing the first reaction film layer except the metal compound on the first insulating dielectric layer 60 based on the etching selectivity. Optionally, in the case where the sidewall protection layer 50 is still retained in the aforementioned manufacturing method, the insulating dielectric layer can cover the top electrode layer 90 and the sidewall protection layer 50, and then the insulating dielectric layer and the semiconductor substrate 101 are first etched to form a first through hole penetrating the insulating dielectric layer to the top electrode layer 90 and a first through hole penetrating the insulating dielectric layer to the top electrode layer 90. The insulating dielectric layer and the semiconductor substrate 101 are connected to a second through hole (not shown in the figure) of the second bottom interconnection structure, and the projection of the first through hole on the fourth surface is located in the seventh area; the insulating dielectric layer is etched for a second time to make the opening of the first through hole away from the top electrode layer 90 larger than the opening of the first through hole close to the top electrode layer 90, and to make the opening of the second through hole away from the second bottom interconnection structure larger than the opening of the second through hole close to the second bottom interconnection structure; metal material is deposited on the side of the insulating dielectric layer away from the semiconductor substrate 101 to fill the first through hole and the second through hole with the metal material to form a top interconnection structure 100, wherein the top interconnection structure 100 includes a top conductive layer corresponding to the first through hole and a top metal wiring layer corresponding to the second through hole.

[0058] In some optional implementations, the step of forming the semiconductor substrate 101 includes: Fig. 9 As shown, a substrate 110 is provided, and a bottom metal wiring layer 120 is provided in the substrate 110; a plug structure 130 is formed in the substrate 110, which extends from the surface of the substrate 110 to the bottom metal wiring layer 120, and the plug structure 130 and the bottom metal wiring layer 120 constitute a first bottom interconnection structure 10; a second reaction film 140 is deposited on a surface of the plug structure 130 away from the bottom metal wiring layer 120, as shown in FIG. Fig.10 As shown, at least part of the material forming the plug structure 130 reacts with the second reaction film 140 located on the surface of the plug structure 130 to form the bottom electrode layer 20, as shown in FIG. Figure 11 to Figure 12 As shown, the semiconductor substrate 101 includes a first bottom interconnect structure 10 and a bottom electrode layer 20 located on the surface of the first bottom interconnect structure 10 .

[0059] Exemplarily, the substrate may be a semiconductor or insulator substrate, the material of the plug structure may include but is not limited to any one of nickel, titanium, cobalt, platinum, gold, rhodium, tantalum, and tungsten, the material of the second reaction film may include but is not limited to any one of silicon, germanium, and silicon germanium, wherein the substrate 110 includes a bottom metal wiring layer 120, and in order to form a bottom electrode layer 20 connected to the bottom metal wiring layer, a bottom through hole extending from the upper surface of the substrate 110 to the bottom metal wiring layer 120 is first formed, and then a metal (including but not limited to nickel, titanium, cobalt, platinum, gold, The plug structure 130 is formed by a metal layer 120 (one of rhodium, tantalum, and tungsten), and the plug structure 130 has an exposed surface away from the bottom metal wiring layer 120, and then a second reaction film 140 is deposited on the substrate 110 (the material of the second reaction film 140 may include but is not limited to any one of silicon, germanium, and silicon germanium), so that the second reaction film 140 at least covers the exposed surface of the plug structure 130, and then a heat treatment is performed to make at least part of the metal material in the plug structure 130 and the material of the second reaction film 140 react to form a metal compound layer 80, such as Fig.11 As shown, after removing the second reaction film 140 located on the substrate 110 and not participating in the chemical reaction, the remaining metal compound layer 80 forms the bottom electrode layer 20, as shown in FIG. Fig.12 As shown, an insulating material layer is then used to fill the substrate 110, wherein the semiconductor substrate 101 includes the first bottom interconnect structure 10 and the bottom electrode layer 20. Optionally, part of the metal in the plug structure 130 is consumed to form the bottom electrode layer 20, that is, a part of the plug structure 130 away from the bottom metal wiring layer 120 is used to form the bottom electrode layer 20, and another part in contact with the bottom metal wiring layer 120 is used to electrically connect the bottom electrode layer 20 and the bottom metal wiring layer 120.

[0060] Optionally, the height from the upper surface of the plug structure 130 to the bottom metal wiring layer 120 can be lower than the height from the upper surface of the substrate 110 to the bottom metal wiring layer 120, so that there is a recessed area in the upper surface of the substrate 110. Therefore, the second reaction film 140 will fill the recessed area and contact with the plug structure 130, so that this method helps to align the bottom electrode layer.

[0061] Optionally, the material of the bottom electrode layer 20 may include but is not limited to TiSi, NiSi, NiGe, etc., and those skilled in the art may reasonably select it according to actual needs. Optionally, the second reaction film 140 may be deposited by conventional film preparation methods such as CVD, PVD and ALD, and the thickness of the second reaction film 140 may be 200 to 400 angstroms.

[0062] Exemplarily, the material of the plug structure includes but is not limited to any one of silicon, germanium and silicon germanium, and the material of the second reaction film includes but is not limited to any one of nickel, titanium, cobalt, platinum, gold, rhodium, tantalum and tungsten. Optionally, conventional thin film preparation methods such as CVD, PVD and ALD can be used to deposit the second reaction film. Optionally, the process of forming the bottom electrode layer can be any one of thermal annealing or microwave annealing.

[0063] Furthermore, in some optional embodiments, the heat treatment may be performed by direct heating; in other optional embodiments, the heat treatment may be performed by direct heating and microwaves may be used to heat the Fig.10 The structure shown is irradiated to promote the movement of metal atoms and accelerate the chemical reaction of forming the bottom electrode layer 20. Further, in the case where the material of the plug structure 130 is a metal material, the degree of metal diffusion can be limited by lowering the temperature, so that the metal material in the plug structure 130 reacts with the second reaction film 140 in direct contact with it to form a second metal compound layer. Optionally, the side wall of the second metal compound layer can be inclined or arc-shaped. Further, the above-mentioned inclination is represented by: on the cross-section of the second metal compound layer, the width of its upper surface (i.e., the side surface away from the bottom metal wiring layer) is greater than or less than the width of the lower surface (i.e., the side surface close to the bottom metal wiring layer).

[0064] Furthermore, the step of forming the bottom electrode layer includes: heat treating the second reaction film 140 and the plug structure 130 so that the material of the plug structure 130 reacts with the second reaction film 140 located on the surface of the plug structure 130 to form a second metal compound layer (i.e., the metal compound layer 80), and then removing the portion of the plug structure 130 away from the bottom metal wiring layer 120 except the second metal compound layer so that the remaining second metal compound layer forms the bottom electrode layer 20, such as Fig.11 and Fig.12 As shown, the bottom electrode layer 20 has a first surface and a second surface opposite to each other, the contact portion between the first bottom interconnect structure 10 and the bottom electrode layer 20 is a first region of the first surface, and the first surface includes a first region and a second region surrounding the first region, as shown in FIG. Fig.12 shown.

[0065] According to another aspect of the present invention, there is provided a magnetic random access memory structure, which is manufactured by the manufacturing method of the magnetic random access memory structure in any of the above-mentioned embodiments, and the magnetic random access memory structure comprises: a semiconductor substrate, the semiconductor substrate comprises a first bottom interconnection structure and a bottom electrode layer, the bottom electrode layer is located on the surface of the first bottom interconnection structure, the bottom electrode layer has a first surface and a second surface opposite to each other, the first surface comprises a first region and a second region surrounding the first region, and the contact portion between the first bottom interconnection structure and the bottom electrode layer is located in the first region; a storage bit, which is located on the second surface, and the second surface comprises a third region and a fourth region surrounding the third region, and the projection of the storage bit on the second surface is located in the third region; a top electrode layer, which is located on a side of the storage bit away from the semiconductor substrate, the top electrode layer has a third surface and a fourth surface opposite to each other, the third surface comprises a fifth region and a sixth region surrounding the fifth region, and the projection of the storage bit on the third surface is located in the fifth region; a top interconnection structure, which is located on the fourth surface, the fourth surface comprises a seventh region and an eighth region surrounding the seventh region, and the contact surface between the top interconnection structure and the top electrode layer is located in the seventh region.

[0066] In the above embodiment, since the contact portion between the first bottom interconnect structure and the bottom electrode layer is located in the first region, and the contact portion between the top interconnect structure and the top electrode layer is located in the seventh region, the connection portion between the storage bit, the first bottom interconnect structure and the top interconnect structure will not extend beyond the top electrode layer and the bottom electrode layer, thereby reducing the risk of short circuit in the device, thereby improving the process window of the top interconnect structure.

[0067] In some optional embodiments, the magnetic random access memory structure further includes: a sidewall protection layer, which at least covers the second region of the bottom electrode layer, the sidewalls of the storage bit, and the sidewalls of the metal hard mask layer.

[0068] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0069] Since the contact portion between the first bottom interconnect structure and the bottom electrode layer is located in the first region, and the contact portion between the top interconnect structure and the top electrode layer is located in the seventh region, the connection portion between the storage bit, the first bottom interconnect structure and the top interconnect structure will not extend beyond the top electrode layer and the bottom electrode layer, thereby reducing the risk of short circuit in the device, thereby improving the photolithography process window of the top interconnect structure, and further, since the metal hard mask layer and the storage unit are formed synchronously, and the top electrode layer is generated by the reaction of the metal hard mask layer and the first reaction film, when the position of the metal hard mask is determined, there is no need to use an additional mask to position the top electrode layer, and self-alignment can be achieved to form the top electrode layer, thereby further reducing the mask layers, reducing the manufacturing cost, and improving the efficiency of the process manufacturing.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a magnetic random access memory structure, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate comprises a first bottom interconnect structure and a bottom electrode layer, wherein the bottom electrode layer is located on a surface of the first bottom interconnect structure, wherein the bottom electrode layer has a first surface and a second surface opposite to each other, wherein the first surface comprises a first region and a second region surrounding the first region, and a contact portion between the first bottom interconnect structure and the bottom electrode layer is the first region; A stacked storage bit and a metal hard mask layer are sequentially formed on the second surface, wherein the second surface includes a third region and a fourth region surrounding the third region, and projections of the storage bit and the metal hard mask layer on the second surface are located in the third region; A first reaction film is covered on a side of the metal hard mask layer away from the storage bit, so that the first reaction film and the metal hard mask layer react to generate a top electrode layer, the top electrode layer has a third surface and a fourth surface opposite to each other, the third surface includes a fifth region and a sixth region surrounding the fifth region, and the projection of the storage bit on the third surface is located in the fifth region; A top interconnect structure is formed on the fourth surface, wherein the fourth surface includes a seventh region and an eighth region surrounding the seventh region, and a contact portion of the top interconnect structure with the top electrode layer is located in the seventh region.

2. The method according to claim 1, characterized in that The steps of forming the top electrode layer include: Thermally treating the first reaction film and the metal hard mask layer so that at least a portion of the metal hard mask layer and the first reaction film on the surface of the metal hard mask layer form a first metal compound layer, wherein the first metal compound layer is disposed in contact with the storage bit; The first reaction film located on both sides of the first metal compound layer is removed, so that the first metal compound layer forms the top electrode layer.

3. The method according to claim 1, characterized in that: After the steps of forming the storage bit and the metal hard mask layer, the method further includes: A sidewall protection layer is formed on the semiconductor substrate, wherein the sidewall protection layer at least covers the second region of the bottom electrode layer, the sidewall of the storage bit, and the sidewall of the metal hard mask layer.

4. The production method according to any one of claims 1 to 3, characterized in that: The steps of forming the storage bit and the metal hard mask layer include: Depositing a storage film and a preliminary metal hard mask layer on the semiconductor substrate in sequence, and patterning the preliminary metal hard mask layer and the storage film by photolithography and etching processes to form the metal hard mask layer and the storage bit; or A storage film and a preliminary metal hard mask layer are sequentially deposited on the semiconductor substrate, the preliminary metal hard mask layer is patterned by photolithography and etching processes to form the metal hard mask layer, and the storage film is etched according to the metal hard mask layer to form the storage bit.

5. The production method according to any one of claims 1 to 3, characterized in that: The semiconductor substrate comprises an array region and a logic region, the first bottom interconnect structure, the bottom electrode layer, the storage bit and the top electrode layer are all located in the array region, the top interconnect structure is also connected to the second bottom interconnect structure in the logic region, and the steps of forming the top interconnect structure include: Depositing an insulating dielectric layer on a side of the top electrode layer away from the storage bit, so that the insulating dielectric layer covers the top electrode layer and the semiconductor substrate; Performing a first etching on the insulating dielectric layer and the semiconductor substrate to form a first through hole penetrating the insulating dielectric layer to the top electrode layer and a second through hole penetrating the insulating dielectric layer and the semiconductor substrate to the second bottom interconnect structure, wherein a projection of the first through hole on the fourth surface is located in the seventh region; Performing a second etching on the insulating dielectric layer so that an opening of an end of the first through hole away from the top electrode layer is larger than an opening of an end of the first through hole close to the top electrode layer, and an opening of an end of the second through hole away from the second bottom interconnect structure is larger than an opening of an end of the second through hole close to the second bottom interconnect structure; A metal material is deposited onto a side of the insulating dielectric layer away from the semiconductor substrate, so that the metal material fills the first through hole and the second through hole to form the top interconnection structure.

6. The production method according to any one of claims 1 to 3, characterized in that: The steps of forming the semiconductor substrate include: Providing a substrate, wherein the substrate has a bottom metal wiring layer; A plug structure is formed in the substrate, extending from the surface of the substrate to the bottom metal wiring layer, wherein the plug structure and the bottom metal wiring layer constitute the first bottom interconnect structure; A second reaction film is deposited on the surface of the plug structure away from the bottom metal wiring layer, and at least part of the material forming the plug structure reacts with the second reaction film located on the surface of the plug structure to form the bottom electrode layer. The semiconductor substrate includes the first bottom interconnect structure and the bottom electrode layer located on the surface of the first bottom interconnect structure.

7. The manufacturing method according to claim 6, characterized in that: The material of the plug structure is not limited to any one of nickel, titanium, cobalt, platinum, gold, rhodium, tantalum and tungsten, and the material of the second reactive film is not limited to any one of silicon, germanium and silicon germanium; or The material of the plug structure includes but is not limited to any one of silicon, germanium and silicon germanium, and the material of the second reactive film includes but is not limited to any one of nickel, titanium, cobalt, platinum, gold, rhodium, tantalum and tungsten.

8. The manufacturing method according to claim 6, characterized in that: The step of forming the bottom electrode layer comprises: heat-treating the material forming the plug structure and the second reaction film on the surface of the plug structure to form a second metal compound layer; The portion of the plug structure on the side away from the bottom metal wiring layer except the second metal compound layer is removed so that the remaining second metal compound layer forms the bottom electrode layer, the bottom electrode layer has a first surface and a second surface relative to each other, the contact portion of the first bottom interconnect structure and the bottom electrode layer is a first area of ​​the first surface, and the first surface includes the first area and a second area surrounding the first area.

9. A magnetic random access memory structure manufactured by the manufacturing method according to any one of claims 1 to 8, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate comprises a first bottom interconnect structure and a bottom electrode layer, wherein the bottom electrode layer is located on a surface of the first bottom interconnect structure, wherein the bottom electrode layer has a first surface and a second surface opposite to each other, wherein the first surface comprises a first region and a second region surrounding the first region, and a contact portion between the first bottom interconnect structure and the bottom electrode layer is located in the first region; A storage bit is located on the second surface, and the second surface includes a third area and a fourth area surrounding the third area, and a projection of the storage bit on the second surface is located in the third area; a top electrode layer, located at a side of the memory bit away from the semiconductor substrate, the top electrode layer having a third surface and a fourth surface opposite to each other, the third surface including a fifth region and a sixth region surrounding the fifth region, and a projection of the memory bit on the third surface being located in the fifth region; A top interconnect structure is located on the fourth surface, wherein the fourth surface includes a seventh region and an eighth region surrounding the seventh region, and a contact surface between the top interconnect structure and the top electrode layer is located in the seventh region.

10. The magnetic random access memory structure according to claim 9, characterized in that: Also includes: The sidewall protection layer at least covers the second region of the bottom electrode layer, the sidewall of the storage bit and the sidewall of the metal hard mask layer.

Images