Data caching method, system and equipment based on multi-level caching architecture and medium

Abstract

The invention discloses a data caching method, system and device based on a multi-level caching architecture and a medium, and relates to the technical field of data caching, the method comprises the following steps: respectively determining a plurality of logic addresses corresponding to the same data block as associated addresses, and obtaining the address number of the logic addresses of each data block; for each data block, obtaining the access frequency of each associated address in the current cache cycle, calculating to obtain the association strength of each associated address according to the number of logical addresses corresponding to the data block, and deleting the associated address with the lowest association strength until the logical address of the data block is unique when a new logical address needs to be inserted; determining a logic address uniquely corresponding to the same data block as a non-associated address, and when a new data block needs to be inserted, deleting the data block with the lowest access frequency for the insertion of the new data block; and error discrimination of the cache data popularity is reduced and eliminated, and the utilization rate of the cache space is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of data cache technology, and more specifically, to a data cache method, system, device and medium based on a multi-level cache architecture. Background Art

[0002] There are two main ways to implement data caching: local caching and distributed caching. Local caching generally means that the application server stores data on the server's operating platform, supporting local disk storage and memory storage. Its advantage is fast access speed, but its disadvantage is that the size of the local space will limit the number of caches, and there will be data consistency issues when deploying clusters. The characteristics of distributed caching are that it can cache massive amounts of data through expansion, and has excellent cache expiration policies and disaster recovery mechanisms.

[0003] Due to the continuous increase in the scale of cloud computing and big data applications, high-performance storage systems have an increasing demand for cache performance. The limited SSD cache space is insufficient to accommodate most of the hot data in modern workloads, resulting in cache jitter, that is, valid cache data is repeatedly loaded into the cache, affecting the overall performance of the cache system; secondly, the number of erase and write times of the SSD device itself is limited. The inherent write operations of the cache and the cache write operations caused by read request misses will seriously aggravate the decay of the cache device's service life. Summary of the invention

[0004] The purpose of the present invention is to provide a data caching method, system, device and medium based on a multi-level cache architecture to solve the problems existing in the above-mentioned background technology.

[0005] The above technical objectives of the present invention are achieved through the following technical solutions: In a first aspect, the present application provides a data caching method based on a multi-level cache architecture, comprising the following specific steps: Obtain the user's access requirements, and obtain the corresponding data access type from the access requirements, and send an access request to the corresponding type architecture in the multi-level cache architecture according to the data access type; If the data block corresponding to the access requirement does not exist in the corresponding type architecture of the multi-level cache architecture, the corresponding data block is called in the database and cached in the corresponding type architecture. For the data blocks cached in each type architecture of the multi-level cache architecture, the following is also included: Obtaining at least one logical address corresponding to each data block, determining multiple logical addresses corresponding to the same data block as associated addresses, and obtaining the address quantity of the logical address of each data block; For each data block, obtain the access frequency of each associated address in the current cache cycle, and calculate the association strength of each associated address based on the number of logical addresses corresponding to the data block. When a new logical address needs to be inserted, delete the associated address with the lowest association strength until the logical address of the data block is unique. The logical address uniquely corresponding to the same data block is determined as a non-associated address. When a new data block needs to be inserted, the data block with the lowest access count is deleted to allow the new data block to be inserted.

[0006] The beneficial effects of the present invention are as follows: in this scheme, firstly, a multi-level cache architecture is constructed by using different cache type architectures, and different types of data blocks are stored in corresponding type architectures in the multi-level cache architecture. When actually used, the corresponding data access type is obtained according to the access requirements, and then an access request is sent to the corresponding type architecture in the multi-level cache architecture to access the corresponding data block in the corresponding type architecture. When the corresponding data block does not exist in the multi-level cache architecture, the corresponding data block is called from the database and cached in the corresponding type architecture. Secondly, the logical addresses of the data blocks existing in the multi-level cache architecture are replaced. Since the logical addresses corresponding to the data blocks can be There may be one or more, that is, one of the logical addresses cannot represent a unique data block, so it is necessary to effectively distinguish the logical addresses associated with the data blocks, so as to improve the cache performance; by obtaining one or more logical addresses corresponding to each data block, and the access frequency of each logical address; among them, for the case where a data block corresponds to multiple logical addresses, the association strength of each logical address is calculated, so that when a new logical address needs to be inserted, the logical address with low association strength is deleted according to the size of the association strength, until the number of logical addresses corresponding to this data block is unique, in this case, the corresponding logical address and data block can be deleted according to the number of accesses to the data block.

[0007] In this scheme, the feature that the data block content is referenced by multiple logical addresses is effectively utilized. Not only the types of logical addresses are effectively distinguished, but also the strength of the correlation between each logical address is further distinguished, thereby reducing the impact of logical addresses on cache metadata space occupancy and cache data replacement, and effectively improving the overall performance of the cache.

[0008] Based on the above technical solution, the present invention can also be improved as follows.

[0009] Furthermore, the above multiple associated addresses for each data block also include: Compare the association strength of each association address with a preset strength threshold, and delete the association address with an association strength less than the strength threshold until the logical address of the data block is unique; The association strength of each associated address in the historical cache week is compared with the association strength in the current cache week. If the association strength in the historical cache week is less than the association strength in the current cache week, the strength threshold is dynamically lowered; if the association strength in the historical cache week is greater than the association strength in the current cache week, the strength threshold is dynamically increased.

[0010] The beneficial effect of adopting the above further scheme is: through dynamic adjustment of the strength threshold, when the association strength in the historical cache week is less than the association strength in the current cache week, it indicates that the heat of the associated address is increasing, and lowering the strength threshold can extend the residence time of the logical address; and when the association strength in the historical cache week is greater than the association strength in the current cache week, it indicates that the heat of the associated address is decreasing, and increasing the strength threshold can shorten the residence time of the logical address, thereby improving cache performance.

[0011] Furthermore, the above-mentioned correlation strength is specifically: ; In the formula, Indicates that in the cache cycle t Internal association address si The strength of association, Indicates that in the cache cycle t- 1 Internal associated address si The strength of association, represents the global attenuation value, Indicates that in the cache cycle t Inner data block Bi The number of associated addresses, Represents a data block Bi The raw number of addresses associated with the .

[0012] Furthermore, the above logical addresses for each data block also include: The logical address space of the data block is evenly divided to obtain a plurality of data units corresponding to the data block and of a preset size, and access records of each data unit are obtained through a bitmap of the data block; The access records of each data unit are used to calculate the heat value of the logical address in the current cache cycle. If the heat value is not less than the preset heat threshold, the logical address is determined as hot data and moved to a frequently accessed location in the database.

[0013] The beneficial effect of adopting the above further scheme is: since currently when a data block is accessed, not all the data in the data block are accessed, but only part of the data in the data block, this situation will affect the popularity of the data block, and will generate many data blocks with incorrectly identified popularity, affecting the overall performance of the cache; by decomposing the data block into multiple data units of a preset size according to the logical address, and recording the access to each data unit, it can be clearly known whether the data block is a data block with higher popularity, that is, when each data unit is accessed more, the data block can be identified as a data block with higher popularity, and moving the high-popularity data block to a frequently accessed position can greatly improve the cache performance.

[0014] Furthermore, the above method also includes: When one of the logical addresses is located at the elimination position of the multi-level cache architecture, a fingerprint index is performed according to the fingerprint information of the logical address to determine whether there is a corresponding data block for the logical address, and if there is no corresponding data block for the logical address, the data block is deleted; There is a corresponding data block for the logical address. The access record of the logical address is extracted and the heat value in the current cache cycle is calculated. If the heat value of the logical address is less than the preset elimination threshold, it is deleted. If the heat value of the logical address is not less than the preset elimination threshold, the logical address is determined as a potential hot address.

[0015] The beneficial effect of adopting the above further scheme is: when a logical address is located in an obsolete position, it is necessary to search for a fingerprint index based on the fingerprint information of the logical address to determine whether the corresponding data block exists; if the data block does not exist, retaining the logical address cannot generate a cache hit, so the logical address and its related metadata information will be directly deleted from the cache; if the data block exists, the flag information, data block bitmap and historical access counter of the logical address will be further checked to determine the access status of each data unit of the logical address, thereby deciding whether to retain the logical address.

[0016] Furthermore, the heat values ​​of the above-mentioned logical addresses are specifically: ; In the formula, Indicates the heat value of the logical address. A Indicates the number of data units accessed at the logical address each time. B Indicates the total number of data units divided by the logical address. C Indicates the cumulative number of accesses to all data units of the logical address. D Indicates the number of times the logical address has been moved to a frequently accessed location in the database.

[0017] In a second aspect, the present application provides a data caching system based on a multi-level cache architecture, which is applied to any one of the data caching methods based on a multi-level cache architecture in the first aspect, including: The first module is used to obtain the user's access requirements, and obtain the corresponding data access type from the access requirements, and send an access request to the corresponding type architecture in the multi-level cache architecture according to the data access type; The second module is used to call the corresponding data block in the database and cache it in the corresponding type architecture if the data block corresponding to the access requirement does not exist in the corresponding type architecture of the multi-level cache architecture. The second module includes: The first submodule is used to obtain at least one logical address corresponding to each data block, determine multiple logical addresses corresponding to the same data block as associated addresses, and obtain the address quantity of the logical address of each data block; The second submodule is used to obtain the access frequency of each associated address in the current cache cycle for each data block, and calculate the association strength of each associated address according to the number of logical addresses corresponding to the data block. When a new logical address needs to be inserted, the associated address with the lowest association strength is deleted until the logical address of the data block is unique; The third submodule is used to determine the logical address uniquely corresponding to the same data block as a non-associated address, and when a new data block needs to be inserted, the data block with the lowest access count is deleted to allow the new data block to be inserted.

[0018] Furthermore, the second submodule includes: The fourth submodule is used to compare the association strength of each association address with a preset strength threshold, and delete the association address with an association strength less than the strength threshold, until the logical address of the data block is unique; The fifth submodule is used to compare the association strength of each associated address in the historical cache week with the association strength in the current cache week. If the association strength in the historical cache week is less than the association strength in the current cache week, the strength threshold is dynamically lowered; if the association strength in the historical cache week is greater than the association strength in the current cache week, the strength threshold is dynamically increased.

[0019] In a third aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any one of the methods in the first aspect when executing the computer program.

[0020] In a fourth aspect, the present application provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions enable a computer to execute any one of the methods in the first aspect.

[0021] Compared with the prior art, the present invention has at least the following beneficial effects: In the present application, firstly, a multi-level cache architecture is constructed by different cache type architectures, and different types of data blocks are stored in corresponding type architectures in the multi-level cache architecture. In actual use, the corresponding data access type is obtained according to the access requirements, and then an access request is sent to the corresponding type architecture in the multi-level cache architecture to access the corresponding data block in the corresponding type architecture. When the corresponding data block does not exist in the multi-level cache architecture, the corresponding data block is called from the database and cached in the corresponding type architecture; secondly, the logical addresses of each data block existing in the multi-level cache architecture are replaced. Since the logical addresses corresponding to each data block may have a or more, that is, one of the logical addresses cannot represent a unique data block, so it is necessary to effectively distinguish the logical addresses associated with the data blocks, so as to improve the cache performance; by obtaining one or more logical addresses corresponding to each data block, and the access frequency of each logical address; among them, for the case where a data block corresponds to multiple logical addresses, the association strength of each logical address is calculated, so that when a new logical address needs to be inserted, the logical address with low association strength is deleted according to the size of the association strength, until the number of logical addresses corresponding to this data block is unique, in this case, the corresponding logical address and data block can be deleted according to the number of accesses to the data block.

[0022] In the present application, the feature that the content of a data block is referenced by multiple logical addresses is effectively utilized, not only the types of logical addresses are effectively distinguished, but also the strength of the association of each logical address is further distinguished, thereby reducing the impact of the logical address on the cache metadata space and the cache data replacement, and effectively improving the overall performance of the cache; wherein: through dynamic adjustment of the strength threshold, when the association strength in the historical cache week is less than the association strength in the current cache week, it indicates that the heat of the associated address is increasing, and lowering the strength threshold can extend the residence time of the logical address, and when the association strength in the historical cache week is greater than the association strength in the current cache week, it indicates that the heat of the associated address is decreasing, and increasing the strength threshold can shorten the residence time of the logical address, thereby improving cache performance.

[0023] In the present application, since currently when a data block is accessed, not all the data in the data block is accessed, but only part of the data in the data block, this situation will affect the popularity of the data block, and will generate many data blocks with incorrectly identified popularity, affecting the overall performance of the cache; by decomposing the data block into multiple data units of a preset size according to the logical address, and recording the access to each data unit, it can be clearly known whether the data block is a data block with higher popularity, that is, when each data unit is accessed more, the data block can be identified as a data block with higher popularity, and moving the high-popularity data block to a frequently accessed position can greatly improve the cache performance.

[0024] In the present application, the effective data content and access behavior of each access request are fully considered, the access characteristics of the data block are accurately judged according to the access status of multiple data units in the data block, and corresponding operations are taken based on the access status of the data block data units to reduce and eliminate the erroneous judgment of the cache data heat, thereby effectively improving the utilization of the cache space. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings: Picture 1 A method flow chart of a caching method in an embodiment of the present invention; Picture 2 A connection diagram of a cache system in an embodiment of the present invention; Picture 3 Schematic diagram of the connection of electronic equipment in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0029] In the description of the embodiments of the present invention, "plurality" means at least 2.

[0030] Embodiment 1: In order to solve the problems of low overall performance of the current cache system and affecting the service life of hardware devices, this embodiment provides a data cache method based on a multi-level cache architecture, such as Picture 1 As shown, the following specific steps are included: S1, obtain the user's access requirements, and obtain the corresponding data access type from the access requirements, and send an access request to the corresponding type architecture in the multi-level cache architecture according to the data access type.

[0031] Among them, the multi-level cache architecture can be composed of Nginx local cache, Tomcat heap cache and Redis distributed cache, and each cache has its own unique role as a whole; and the multi-level cache architecture can be used in a variety of scenarios, such as computer systems, web systems, cloud computing, big data processing, etc.

[0032] S2: If the data block corresponding to the access requirement does not exist in the corresponding type architecture of the multi-level cache architecture, the corresponding data block is called in the database and cached in the corresponding type architecture.

[0033] In actual use, the corresponding data access type is obtained according to the access requirements, and then an access request is sent to the corresponding type architecture in the multi-level cache architecture to access the corresponding data block in the corresponding type architecture. When the corresponding data block does not exist in the multi-level cache architecture, the corresponding data block is called from the database and cached in the corresponding type architecture.

[0034] S21, for data blocks cached in various types of architectures of the multi-level cache architecture, also includes: obtaining at least one logical address corresponding to each data block, determining multiple logical addresses corresponding to the same data block as associated addresses, and obtaining the address quantity of the logical address of each data block.

[0035] S22, for each data block, obtain the access frequency of each associated address in the current cache cycle, and calculate the association strength of each associated address based on the number of logical addresses corresponding to the data block. When a new logical address needs to be inserted, delete the associated address with the lowest association strength until the logical address of the data block is unique.

[0036] Optionally, the multiple associated addresses for each data block further include: S221, comparing the association strength of each association address with a preset strength threshold, and deleting the association address with an association strength smaller than the strength threshold, until the logical address of the data block is unique.

[0037] S222, compare the association strength of each associated address in the historical cache week with the association strength in the current cache week. If the association strength in the historical cache week is less than the association strength in the current cache week, dynamically lower the strength threshold; if the association strength in the historical cache week is greater than the association strength in the current cache week, dynamically increase the strength threshold.

[0038] Specifically, through dynamic adjustment of the strength threshold, when the association strength in the historical cache cycle is less than the association strength in the current cache cycle, it indicates that the heat of the associated address is increasing. Lowering the strength threshold can extend the residence time of the logical address. When the association strength in the historical cache cycle is greater than the association strength in the current cache cycle, it indicates that the heat of the associated address is decreasing. Raising the strength threshold can shorten the residence time of the logical address, thereby improving cache performance.

[0039] The above-mentioned correlation strength is specifically: ; In the formula, Indicates that in the cache cycle t Internal association address si The strength of association, Indicates that in the cache cycle t- 1 Internal associated address si The strength of association, represents the global attenuation value, Indicates that in the cache cycle t Inner data block Bi The number of associated addresses, Represents a data block Bi The raw number of addresses associated with the .

[0040] Optionally, the above logical addresses for each data block further include: S223, equally divide the logical address space of the data block to obtain a plurality of data units corresponding to the data block and of a preset size, and obtain access records of each data unit through a bitmap of the data block.

[0041] S224, using the access records of each data unit to calculate the heat value of the logical address in the current cache cycle, if the heat value is not less than the preset heat threshold, the logical address is determined as hot data and moved to a frequently accessed position in the database.

[0042] Among them, since currently when a data block is accessed, not all the data in the data block are accessed, but only part of the data in the data block, this situation will affect the popularity of the data block, and will generate many data blocks with incorrectly identified popularity, affecting the overall performance of the cache.

[0043] Furthermore, by decomposing the data block into multiple data units of preset size according to the logical address and recording the access to each data unit, it is possible to clearly know whether the data block is a high-temperature data block. That is, when each data unit is accessed frequently, the data block can be identified as a high-temperature data block. Moving the high-temperature data block to a frequently accessed location can greatly improve the cache performance.

[0044] Optionally, the above method further includes: S225, when one of the logical addresses is located at an obsolete position of the multi-level cache architecture, fingerprint indexing is performed according to the fingerprint information of the logical address to determine whether there is a corresponding data block for the logical address, and if there is no corresponding data block for the logical address, the data block is deleted.

[0045] Among them, when a logical address is located in an obsolete position, it is necessary to find the fingerprint index based on the fingerprint information of the logical address to determine whether the corresponding data block exists; if the data block does not exist, retaining the logical address will not generate a cache hit, so the logical address and its related metadata information will be directly deleted from the cache.

[0046] S226, if there is a corresponding data block for the logical address, extract the access record of the logical address and calculate the heat value in the current cache cycle. If the heat value of the logical address is less than the preset elimination threshold, delete it. If the heat value of the logical address is not less than the preset elimination threshold, determine the logical address as a potential hot address.

[0047] If the data block exists, the flag information, data block bitmap and historical access counter of the logical address will be further checked to determine the access status of each data unit of the logical address, thereby deciding whether to retain the logical address.

[0048] Optionally, the heat value of each of the above logical addresses is specifically: ; In the formula, Indicates the heat value of the logical address. A Indicates the number of data units accessed at the logical address each time. B Indicates the total number of data units divided by the logical address. C Indicates the cumulative number of accesses to all data units of the logical address. DIndicates the number of times the logical address is moved to the frequently accessed location in the database; in the above formula, , The values ​​of and compare them, taking the larger of the two values.

[0049] S23, determining the logical address uniquely corresponding to the same data block as a non-associated address, and when a new data block needs to be inserted, deleting the data block with the lowest access count to allow the new data block to be inserted.

[0050] In this embodiment, the effective data content and access behavior of each access request are fully considered, the access characteristics of the data block are accurately judged according to the access status of multiple data units in the data block, and corresponding operations are taken based on the access status of the data block data units to reduce and eliminate erroneous judgments on the heat of cached data, thereby effectively improving the utilization of cache space.

[0051] Embodiment 2: The present application provides a data caching system based on a multi-level cache architecture, which is applied to any of the data caching methods based on a multi-level cache architecture in Embodiment 1, such as Picture 2 As shown, including: The first module is used to obtain the user's access requirements, and obtain the corresponding data access type from the access requirements, and send an access request to the corresponding type architecture in the multi-level cache architecture according to the data access type; The second module is used to call the corresponding data block in the database and cache it in the corresponding type architecture if the data block corresponding to the access requirement does not exist in the corresponding type architecture of the multi-level cache architecture. The second module includes: The first submodule is used to obtain at least one logical address corresponding to each data block, determine multiple logical addresses corresponding to the same data block as associated addresses, and obtain the address quantity of the logical address of each data block; The second submodule is used to obtain the access frequency of each associated address in the current cache cycle for each data block, and calculate the association strength of each associated address according to the number of logical addresses corresponding to the data block. When a new logical address needs to be inserted, the associated address with the lowest association strength is deleted until the logical address of the data block is unique; The third submodule is used to determine the logical address uniquely corresponding to the same data block as a non-associated address, and when a new data block needs to be inserted, the data block with the lowest access count is deleted to allow the new data block to be inserted.

[0052] Furthermore, the second submodule includes: The fourth submodule is used to compare the association strength of each association address with a preset strength threshold, and delete the association address with an association strength less than the strength threshold, until the logical address of the data block is unique; The fifth submodule is used to compare the association strength of each associated address in the historical cache week with the association strength in the current cache week. If the association strength in the historical cache week is less than the association strength in the current cache week, the strength threshold is dynamically lowered; if the association strength in the historical cache week is greater than the association strength in the current cache week, the strength threshold is dynamically increased.

[0053] Embodiment 3: This embodiment of the present application provides an electronic device, such as Picture 3 As shown, it includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, any method in Embodiment 1 is implemented.

[0054] Embodiment 4: The embodiment of the present application provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions enable a computer to execute any method in Embodiment 1.

[0055] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A data caching method based on a multi-level cache architecture, characterized in that: The specific steps include: Obtaining the user's access requirements, and obtaining a corresponding data access type from the access requirements, and sending an access request to a corresponding type architecture in the multi-level cache architecture according to the data access type; If the data block corresponding to the access requirement does not exist in the corresponding type architecture of the multi-level cache architecture, the corresponding data block is called in the database and cached in the corresponding type architecture. For the data blocks cached in each type architecture of the multi-level cache architecture, the method further includes: Obtaining at least one logical address corresponding to each data block, determining multiple logical addresses corresponding to the same data block as associated addresses, and obtaining the address quantity of the logical address of each data block; For each data block, the access frequency of each associated address in the current cache cycle is obtained, and the association strength of each associated address is calculated according to the number of logical addresses corresponding to the data block. When a new logical address needs to be inserted, the associated address with the lowest association strength is deleted until the logical address of the data block is unique. The logical address uniquely corresponding to the same data block is determined as a non-associated address. When a new data block needs to be inserted, the data block with the lowest access count is deleted to allow the new data block to be inserted.

2. The data caching method based on a multi-level cache architecture according to claim 1, characterized in that: For multiple associated addresses of each data block, it also includes: Comparing the association strength of each of the association addresses with a preset strength threshold, and deleting the association addresses whose association strength is less than the strength threshold, until the logical address of the data block is unique; The association strength in the historical cache week of each associated address is compared with the association strength in the current cache week. If the association strength in the historical cache week is less than the association strength in the current cache week, the strength threshold is dynamically lowered; if the association strength in the historical cache week is greater than the association strength in the current cache week, the strength threshold is dynamically increased.

3. The data caching method based on a multi-level cache architecture according to claim 1 or 2, characterized in that: The association strength is specifically: ； In the formula, Indicates that in the cache cycle t Internal association address si The strength of association, Indicates that in the cache cycle t- 1 Internal associated address si The strength of association, represents the global attenuation value, Indicates that in the cache cycle t Inner data block Bi The number of associated addresses, Represents a data block Bi The raw number of addresses associated with the .

4. The data caching method based on a multi-level cache architecture according to claim 1, characterized in that: For each logical address of each data block, it also includes: The logical address space of the data block is evenly divided to obtain a plurality of data units corresponding to the data block and of a preset size, and access records of each of the data units are obtained through a bitmap of the data block; The access records of each data unit are used to calculate the heat value of the logical address in the current cache cycle. If the heat value is not less than a preset heat threshold, the logical address is determined as hot data and moved to a frequently accessed position in the database.

5. The data caching method based on a multi-level cache architecture according to claim 4, characterized in that: The method further comprises: When one of the logical addresses is located at the elimination position of the multi-level cache architecture, a fingerprint index is performed according to the fingerprint information of the logical address to determine whether there is a corresponding data block for the logical address, and if there is no corresponding data block for the logical address, the data block is deleted; There is a corresponding data block for the logical address. The access record of the logical address is extracted and the heat value in the current cache cycle is calculated. If the heat value of the logical address is less than the preset elimination threshold, it is deleted. If the heat value of the logical address is not less than the preset elimination threshold, the logical address is determined as a potential hot address.

6. The data caching method based on a multi-level cache architecture according to claim 4 or 5, characterized in that: The heat value of each logical address is as follows: ； In the formula, Indicates the heat value of the logical address. A Indicates the number of data units accessed at the logical address each time. B Indicates the total number of data units divided by the logical address. C Indicates the cumulative number of accesses to all data units of the logical address. D Indicates the number of times the logical address has been moved to a frequently accessed location in the database.

7. A data caching system based on a multi-level cache architecture, applied to a data caching method based on a multi-level cache architecture according to any one of claims 1 to 6, characterized in that: include: The first module is used to obtain the user's access requirements, and obtain the corresponding data access type from the access requirements, and send an access request to the corresponding type architecture in the multi-level cache architecture according to the data access type; The second module is used to call the corresponding data block in the database and cache it in the corresponding type architecture if there is no data block corresponding to the access requirement in the corresponding type architecture of the multi-level cache architecture. The second module includes: The first submodule is used to obtain at least one logical address corresponding to each data block, determine multiple logical addresses corresponding to the same data block as associated addresses, and obtain the address quantity of the logical address of each data block; The second submodule is used to obtain the access frequency of each associated address in the current cache cycle for each data block, and calculate the association strength of each associated address according to the number of logical addresses corresponding to the data block. When a new logical address needs to be inserted, the associated address with the lowest association strength is deleted until the logical address of the data block is unique; The third submodule is used to determine the logical address uniquely corresponding to the same data block as a non-associated address, and when a new data block needs to be inserted, the data block with the lowest access count is deleted to allow the new data block to be inserted.

8. The data cache system based on a multi-level cache architecture according to claim 7, characterized in that: The second submodule includes: A fourth submodule, used for comparing the association strength of each of the association addresses with a preset strength threshold, and deleting the association addresses whose association strength is less than the strength threshold, until the logical address of the data block is unique; The fifth submodule is used to compare the association strength in the historical cache week of each associated address with the association strength in the current cache week. If the association strength in the historical cache week is smaller than the association strength in the current cache week, the strength threshold is dynamically lowered; if the association strength in the historical cache week is greater than the association strength in the current cache week, the strength threshold is dynamically increased.

9. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the data caching method based on a multi-level cache architecture according to any one of claims 1 to 6 is implemented.

10. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium stores computer instructions, and the computer instructions enable a computer to execute the data caching method based on a multi-level cache architecture according to any one of claims 1 to 6.

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