Configuration method and providing method of IO IP core with adjustable input threshold voltage and output current capability, device and chip

Abstract

The invention relates to the technical field of chip IP cores and EDA, in particular to a configuration method and providing method of an IOIP core with adjustable input threshold voltage and output current capacity, a device and a chip. An IO IP core provided by an existing process factory or an IP manufacturer is generally an integral module, can only provide fixed input threshold voltage and output current capacity with limited gears, and cannot be conveniently changed according to chip requirements. A special EDA tool is researched and developed, meanwhile, the circuit module and the layout of the IO IP core are subjected to customized design, and the configurable IO IP core comprising the IO core circuit module, the input threshold adjustable module and the output current adjustable module is reconstructed, so that user requirements are obtained through the customized EDA tool, and the modules in the configurable IO IP core are configured; and flexible configuration can be realized according to the actual complex application of the chip.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip IP core and EDA (Electronic Design Automation), and in particular to a configuration method and providing method, device and chip of an IO IP core with adjustable input threshold voltage and output current capability. Background Art

[0002] As the division of labor in chips becomes more and more detailed, the IO IP core has become one of the standard IPs provided by chip process manufacturers. The IO IP core design is a very important part of chip design, directly connecting the chip's internal core circuit, external packaging, and printed circuit board (PCB) and other external environments.

[0003] The input / output (I / O) unit not only receives and sends signals, but also performs level conversion on the signals and provides a large driving current. However, the IOIP cores provided by most mainstream process factories only have fixed input threshold voltages (input threshold high level voltage VIH, input threshold low level voltage VIL). Even for the same process node and the same operating voltage, the IO IP cores produced by different process factories have different input threshold high level voltages VIH and input threshold low level voltages VIL. For example, the input threshold high level voltage VIH uses 0.65*VDD, 0.8*VDD or an absolute level value (for example, 0.4V), and the input threshold low level voltage VIL uses 0.35*VDD, 0.3*VDD or an absolute level value (for example, 0.8V, 1.2V). For different analog chips and digital-analog hybrid chips, the input threshold voltage will have different definition ranges depending on the application.

[0004] At the same time, the output current capability of the IO IP core is also fixed. For example, Huahong HHGRACE only provides three output current capabilities: 4mA, 8mA, and 16mA; TSMC mainly provides four output current capabilities: 2mA, 4mA, 8mA, and 12mA; SMIC mainly provides six output current capabilities: 2mA, 4mA, 8mA, 12mA, 16mA, and 24mA. However, in actual industrial chip design, the required output current capability of the IO IP core is also different. Some only require uA-level output current capability, such as 100uA, 500uA, etc., while others require an output current capability greater than 24mA.

[0005] Therefore, most of the existing mainstream process factories only provide IO IP cores with fixed input threshold voltage and limited output current capabilities. As a result, the input threshold voltage and output current capabilities of the IO IP cores provided by the current process factories cannot meet the chip design for key industrial application scenarios such as electromagnetic heating, electricity, rail transportation, and automobiles. Summary of the invention

[0006] In order to solve the problems in the related art, the embodiments of the present disclosure provide a configuration method of an IO IP core with adjustable input threshold voltage and output current capability, and a providing method, device and chip.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for configuring an IOIP core with adjustable input threshold voltage and output current capability, the method being implemented based on a customized EDA tool, and the method comprising:

[0008] Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an input threshold adjustable module, and an output current adjustable module, and the IO basic circuit module includes an IO core circuit module;

[0009] Get the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current of the specified pin module input by the user for the customized IO IP core;

[0010] According to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module is configured, the input threshold adjustable module includes a first MOS module group, and the configuring of the input threshold adjustable module includes: selecting a MOS module from the first MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate a first control signal of the IO core circuit module;

[0011] According to the high-level output source current and the low-level output sink current, the output current adjustable module is configured, the output current adjustable module includes a second MOS module group, and the configuring of the output current adjustable module includes: selecting a MOS module from the second MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, wherein the configured output current adjustable module is used to provide a specified output current capability under the control of a second control signal of the IO core circuit module;

[0012] Connecting the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: a first control signal input port and a second control signal output port, the configured input threshold adjustable module includes: a first control signal output port, and the configured output current adjustable module includes: a second control signal input port;

[0013] The first control signal output port of the configured input threshold adjustable module is connected to the first control signal input port of the IO core circuit module, so as to provide a first control signal to the IO core circuit module;

[0014] The second control signal output port of the IO core circuit module is connected to the second control signal input port of the configured output current adjustable module, and is used to output a second control signal to the configured output current adjustable module based on the first control signal and the IO input signal;

[0015] The first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the first MOS module group, and the second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the second MOS module group.

[0016] According to an embodiment of the present disclosure, the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module respectively further include: a power supply voltage port and a ground port, and the power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply voltage, and the ground ports are all grounded.

[0017] According to an embodiment of the present disclosure, it also includes:

[0018] Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

[0019] According to an embodiment of the present disclosure, it also includes:

[0020] A bottom module is obtained, and the bottom of the designated pin module of the customized IO IP core is sealed by using the bottom module to generate a designated pin module with a sealed bottom.

[0021] According to an embodiment of the present disclosure, it also includes: generating a second designated pin circuit layout of the customized IO IP core based on the bottom-enclosed designated pin module.

[0022] According to an embodiment of the present disclosure, the configuration of the input threshold adjustable module further includes:

[0023] Determine a corresponding hysteresis voltage according to the input threshold high level voltage and the input threshold low level voltage;

[0024] A MOS module is selected from the first MOS module group according to the input threshold high level voltage, the input threshold low level voltage and the hysteresis voltage and the selected MOS module is connected to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module includes a hysteresis circuit module for realizing the hysteresis voltage.

[0025] According to an embodiment of the present disclosure, the MOS modules in the second MOS module group are divided into a plurality of unit output current adjustable modules;

[0026] The configuring the output current adjustable module comprises: selecting one or more unit output current adjustable modules from the plurality of unit output current adjustable modules according to the high level output source current and the low level output sink current, and when selecting a plurality of unit output current adjustable modules, the selected plurality of unit output current adjustable modules jointly provide the specified output current capability;

[0027] The unit output current adjustable module comprises a power supply voltage port, a ground port and a second control signal input port, the power supply voltage port of the unit output current adjustable module is connected to the power supply voltage, and the ground port of the unit output current adjustable module is grounded;

[0028] The second control signal output port of the IO core circuit module is connected to the second control signal input port of the selected unit output current adjustable module, and the second control signal input port of the selected unit output current adjustable module is connected to the MOS module selected from the second MOS module group.

[0029] According to an embodiment of the present disclosure, all MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules are selected; and / or

[0030] A portion of MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules is selected.

[0031] According to an embodiment of the present disclosure, it also includes:

[0032] Acquire at least one filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module being connected to a power supply voltage, and the ground port of the filling module being grounded;

[0033] Generate multiple pin modules of the customized IO IP core;

[0034] Splicing the plurality of pin modules to obtain a spliced ​​pin module;

[0035] The at least one filling module is used to fill the empty space in the splicing tube foot module to obtain a filled splicing tube foot module.

[0036] According to an embodiment of the present disclosure, it also includes: generating a multi-pin circuit layout of the customized IOIP core based on the filled splicing pin module.

[0037] According to an embodiment of the present disclosure, the customized EDA tool provides a graphical user interface GUI, and the GUI interface includes a plurality of customized input boxes;

[0038] The multiple customized input boxes include: an expected input threshold high level voltage input box, an expected input threshold low level voltage input box, an expected high level output source current input box, and an expected low level output sink current input box, so as to obtain the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the specified pin module of the customized IO IP core.

[0039] According to an embodiment of the present disclosure, the IO basic circuit module further includes: a default input threshold module and a default output current module;

[0040] When obtaining the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the designated pin module, disconnect the connection between the default input threshold module and the IO core circuit module, and disconnect the connection between the default output current module and the IO core circuit module.

[0041] According to an embodiment of the present disclosure, when a corresponding plurality of module layouts are generated based on the IO core circuit module, the configured input threshold adjustable module, and the configured output current adjustable module, the widths of the plurality of module layouts are consistent.

[0042] In a second aspect, an embodiment of the present disclosure provides a method for providing a configurable IO IP core, including:

[0043] Providing an input threshold adjustable module, the input threshold adjustable module comprising a first MOS module group, a power supply voltage port, a ground port and a first control signal output port, the customized EDA tool selecting a MOS module from the first MOS module group and connecting the selected MOS module according to an input threshold high level voltage and an input threshold low level voltage;

[0044] Providing an output current adjustable module, the output current adjustable module comprising a second MOS module group, a power supply voltage port, a ground port, and a second control signal input port, wherein the customized EDA tool selects a MOS module from the second MOS module group and connects the selected MOS module according to a high-level output pull current and a low-level output sink current;

[0045] An IO core circuit module is provided, which includes a power supply voltage port, a ground port, a first control signal input port and a second control signal output port, and is used to process a received IO input signal and output a second control signal.

[0046] According to an embodiment of the present disclosure, it also includes:

[0047] A hysteresis circuit module is provided, and the hysteresis circuit module is arranged in the input threshold adjustable module and is used to provide a hysteresis voltage.

[0048] According to an embodiment of the present disclosure, the output current adjustable module includes multiple unit output current adjustable modules, and the unit output current adjustable module includes multiple MOS modules, a power supply voltage port, a ground port and a second control signal input port. The MOS modules included in the multiple unit output current adjustable modules together constitute the second MOS module group.

[0049] According to an embodiment of the present disclosure, when at least one unit output current adjustable module among the plurality of unit output current adjustable modules is selected by a custom EDA tool, the selected unit output current adjustable module is connected to the second control signal output port of the IO core circuit module to provide a specified output current capability of the custom IO IP core;

[0050] When all or part of the MOS modules of the unit output current adjustable module are selected by a custom EDA tool, the selected MOS modules are connected to the second control signal output port of the IO core circuit module to provide the specified output current capability of the custom IO IP core.

[0051] According to an embodiment of the present disclosure, it also includes:

[0052] A filling module is provided, the filling module comprising: a power supply voltage port and a ground port, which is used to fill empty positions in a spliced ​​pin module of a custom IO IP core when generating multiple pin modules of a custom IO IP core based on a provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

[0053] According to an embodiment of the present disclosure, it also includes:

[0054] A bottom module is provided, and the bottom module is used to close the bottom of one or more pin modules when one or more pin modules of a customized IO IP core are generated based on the provided configurable IO IP core.

[0055] According to an embodiment of the present disclosure, it also includes:

[0056] Providing a default input threshold module, wherein the default input threshold module is used to provide a default first control signal;

[0057] A default output current module is provided, wherein the default output current module is used to provide a default output current capability.

[0058] In a third aspect, an embodiment of the present disclosure provides a configuration device for an IOIP core with adjustable input threshold voltage and output current capability, the device being implemented based on a customized EDA tool, and comprising:

[0059] A first acquisition module is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an input threshold adjustable module, and an output current adjustable module, and the IO basic circuit module includes an IO core circuit module;

[0060] The second acquisition module is configured to acquire the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the specified pin module of the customized IO IP core;

[0061] a voltage configuration module, configured to configure the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module including a first MOS module group, the configuring the input threshold adjustable module including: selecting a MOS module from the first MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, the configured input threshold adjustable module being used to generate a first control signal of the IO core circuit module;

[0062] a current configuration module, configured to configure the output current adjustable module according to the high-level output source current and the low-level output sink current, the output current adjustable module including a second MOS module group, the configuring the output current adjustable module including: selecting a MOS module from the second MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, the configured output current adjustable module being used to provide a specified output current capability under the control of a second control signal of the IO core circuit module;

[0063] A generating module is configured to connect the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: a first control signal input port and a second control signal output port, the configured input threshold adjustable module includes: a first control signal output port, and the configured output current adjustable module includes: a second control signal input port;

[0064] The first control signal output port of the configured input threshold adjustable module is connected to the first control signal input port of the IO core circuit module, so as to provide a first control signal to the IO core circuit module;

[0065] The second control signal output port of the IO core circuit module is connected to the second control signal input port of the configured output current adjustable module, and is used to output a second control signal to the configured output current adjustable module based on the first control signal and the IO input signal;

[0066] The first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the first MOS module group, and the second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the second MOS module group.

[0067] According to an embodiment of the present disclosure, the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module respectively further include: a power supply voltage port and a ground port, and the power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply voltage, and the ground ports are all grounded.

[0068] According to an embodiment of the present disclosure, it further includes: a third acquisition module configured to acquire a bottom module, wherein the bottom module is used to close the bottom of the designated pin module of the custom IO IP core to generate a designated pin module with a closed bottom.

[0069] According to an embodiment of the present disclosure, it also includes: a fourth acquisition module, configured to acquire at least one filling module, the filling module including: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; the filling module is used to fill the vacancies in the splicing pin module of the customized IO IP core to obtain the filled splicing pin module, wherein the splicing pin module is obtained by splicing multiple pin modules of the customized IOIP core.

[0070] In a fourth aspect, an embodiment of the present disclosure provides a device for providing a configurable IO IP core, including:

[0071] A first providing module is configured to provide an input threshold adjustable module, wherein the input threshold adjustable module includes a first MOS module group, a power supply voltage port, a ground port, and a first control signal output port, wherein the customized EDA tool selects a MOS module from the first MOS module group and connects the selected MOS module according to an input threshold high level voltage and an input threshold low level voltage;

[0072] A second providing module is configured to provide an output current adjustable module, wherein the output current adjustable module includes a second MOS module group, a power supply voltage port, a ground port, and a second control signal input port, wherein the customized EDA tool selects a MOS module from the second MOS module group and connects the selected MOS module according to a high-level output pull current and a low-level output sink current;

[0073] The third providing module is configured to provide an IO core circuit module, wherein the IO core circuit module includes a power supply voltage port, a ground port, a first control signal input port and a second control signal output port, and is used to process the received IO input signal and output a second control signal.

[0074] According to an embodiment of the present disclosure, it also includes:

[0075] The fourth providing module is configured to provide a hysteresis circuit module, wherein the hysteresis circuit module is arranged in the input threshold adjustable module and is used to provide a hysteresis voltage.

[0076] According to an embodiment of the present disclosure, it also includes:

[0077] A fifth providing module is configured to provide a filling module, wherein the filling module includes: a power supply voltage port and a ground port, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

[0078] According to an embodiment of the present disclosure, it also includes:

[0079] The sixth providing module is configured to provide a bottom module, wherein the bottom module is used to seal the bottom of the one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

[0080] According to an embodiment of the present disclosure, it also includes:

[0081] A seventh providing module is configured to provide a default input threshold module and a default output current module, wherein the default input threshold module is used to provide a default first control signal, and the default output current module is used to provide a default output current capability.

[0082] In a fifth aspect, an embodiment of the present disclosure provides a chip, comprising: a custom IO IP core manufactured using the method generated according to any one of the methods described in the first aspect, or a custom IO IP core manufactured using the configurable IO IP core provided by the method described in the second aspect.

[0083] In a sixth aspect, an embodiment of the present disclosure provides an electronic device, comprising the chip as described in the fifth aspect.

[0084] In a seventh aspect, an embodiment of the present disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method as described in any one of the first aspect or the second aspect.

[0085] In an eighth aspect, an embodiment of the present disclosure provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the method as described in any one of the first aspect or the second aspect.

[0086] According to the technical solution provided by the embodiment of the present disclosure, a customized EDA tool is used to obtain user requirements (input threshold high level voltage, input threshold low level voltage, high level output pull current and low level output sink current for the input of the designated pin module of the customized IO IP core), and a configurable IO IP core including an IO core circuit module, an input threshold adjustable module and an output current adjustable module is configured, a MOS module is selected from a first MOS module group of the input threshold adjustable module and the selected MOS module is connected to generate a configured input threshold adjustable module, a MOS module is selected from a second MOS module group of the output current adjustable module and the selected MOS module is connected to generate a configured output current adjustable module, the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are connected to generate a designated pin module of the customized IO IP core.

[0087] The present invention discloses the development of a special customized EDA tool, and at the same time customizes the circuit module and layout of the IO IP core, and reconstructs it into a configurable IO IP core including an IO core circuit module, an input threshold adjustable module, and an output current adjustable module. The configurable IO IP core can be adjusted according to the needs of the actual chip to achieve flexible configuration of the input threshold voltage and output current capability, so that the customized IO IP core generated by the customized EDA tool and the configurable IO IP core can meet the design requirements of complex industrial chips such as different input threshold voltages and output current capabilities.

[0088] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0090] Figure 1 A flowchart showing a configuration method of an IO IP core with adjustable input threshold voltage and output current capability according to an embodiment of the present disclosure;

[0091] Figure 2 A schematic diagram showing a configured input threshold adjustable module according to an embodiment of the present disclosure;

[0092] Figure 3 A working principle diagram of a hysteresis voltage provided by a hysteresis circuit module according to an embodiment of the present disclosure is shown;

[0093] Figure 4 A schematic diagram showing a unit output current adjustable module according to an embodiment of the present disclosure;

[0094] Figure 5 A schematic diagram showing another unit output current adjustable module according to an embodiment of the present disclosure;

[0095] Figure 6 A schematic diagram showing an IO basic circuit module according to an embodiment of the present disclosure is shown;

[0096] Figure 7 A schematic diagram showing the connection of an IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module in the configuration method of the IO IP core according to an embodiment of the present disclosure;

[0097] Figure 8 A schematic diagram showing splicing of pin modules in a configuration method of an IO IP core according to an embodiment of the present disclosure is shown;

[0098] Fig. 9 A flowchart showing a method for providing a configurable IO IP core according to an embodiment of the present disclosure is shown;

[0099] Fig.10 A schematic diagram showing a configuration device of an IO IP core with adjustable input threshold voltage and output current capability according to an embodiment of the present disclosure;

[0100] Fig.11 A schematic diagram showing an apparatus for providing a configurable IO IP core according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0101] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0102] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0103] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0104] In the present disclosure, if it involves operations of obtaining user information or user data or displaying user information or user data to others, the operations are all authorized and confirmed by the user, or actively selected by the user.

[0105] As mentioned above, most of the IO IP cores provided by most of the existing mainstream process factories only have fixed input threshold voltages (input threshold high level voltage VIH, input threshold low level voltage VIL). At the same time, the output current capability (high level output source current IOH and low level output sink current IOL) is also a limited number of values. As a result, the input threshold voltage and output current capabilities provided by the IO IP cores manufactured by current process factories or IP manufacturers cannot meet the chip design requirements for complex industrial application scenarios such as electromagnetic heating, industrial control, and aerospace.

[0106] After research, the inventors found that the reason why the existing IO IP core can only provide a fixed input threshold voltage and a limited number of output current capabilities is that the IO basic circuit module, as an integral module of the IO IP core, integrates multiple functions such as signal reception and transmission, level conversion, and providing driving current. However, as an integral module, the IO basic circuit module cannot be easily changed according to chip requirements, resulting in the existing IO IP core being able to provide only a few fixed input threshold voltages and output current capabilities, which brings a lot of inconvenience to chip design in complex industrial application scenarios and increases the difficulty of chip design.

[0107] The present disclosure provides a configuration method for an IO IP core with adjustable input threshold voltage and output current capability, the method being implemented based on a customized EDA tool and comprising:

[0108] A configurable IO IP core is obtained, wherein the configurable IO IP core includes an IO basic circuit module, an input threshold adjustable module, and an output current adjustable module, wherein the IO basic circuit module includes an IO core circuit module; an input threshold high level voltage, an input threshold low level voltage, a high level output pull current, and a low level output sink current input by a user for a specified pin module of a customized IO IP core are obtained; according to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module is configured, wherein the input threshold adjustable module includes a first MOS module group, wherein the configuring of the input threshold adjustable module includes: selecting a MOS module from the first MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold The value adjustable module is used to generate a first control signal of the IO core circuit module; according to the high-level output pull current and the low-level output sink current, the output current adjustable module is configured, the output current adjustable module includes a second MOS module group, and the configuration of the output current adjustable module includes: selecting a MOS module from the second MOS module group according to the high-level output pull current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, the configured output current adjustable module is used to provide a specified output current capability under the control of the second control signal of the IO core circuit module; connecting the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module to generate a specified pin module of the customized IO IP core.

[0109] Among them, the IO core circuit module includes: a first control signal input port and a second control signal output port, the configured input threshold adjustable module includes: a first control signal output port, and the configured output current adjustable module includes: a second control signal input port; the first control signal output port of the configured input threshold adjustable module is connected to the first control signal input port of the IO core circuit module, and is used to provide a first control signal to the IO core circuit module; the second control signal output port of the IO core circuit module is connected to the second control signal input port of the configured output current adjustable module, and is used to output a second control signal to the configured output current adjustable module based on the first control signal and the IO input signal; the first control signal output port of the configured input threshold adjustable module is connected to a MOS module selected from the first MOS module group, and the second control signal input port of the configured output current adjustable module is connected to a MOS module selected from the second MOS module group.

[0110] The present disclosure splits the existing overall IO basic circuit module into multiple modules (IO core circuit module, input threshold adjustable module, output current adjustable module) to obtain a configurable IO IP core. At the same time, since the existing EDA tools are all configured for the IO basic circuit module as a whole module, it is impossible to directly use the existing EDA tools to configure the configurable IO IP core including multiple modules obtained after the splitting. Therefore, the present disclosure develops a special EDA tool, and at the same time customizes the circuit module and layout of the IO IP core to reconstruct it into a configurable IO IP core including an IO core circuit module, an input threshold adjustable module and an output current adjustable module, so as to configure the configurable IO IP core using the obtained customized EDA tool, and use the input threshold voltage and output current capability requirements input from the customized EDA tool to adjust according to the needs of the actual chip, so as to realize flexible configuration of the input threshold voltage and output current capability, so that the customized IO IP core generated by the customized EDA tool and the configurable IO IP core can meet the design requirements of complex industrial chips such as different input threshold voltages and output current capabilities.

[0111] Figure 1 FIG. 1 is a flow chart showing a configuration method of an IO IP core with adjustable input threshold voltage and output current capability according to an embodiment of the present disclosure. Figure 1 As shown, the method is implemented based on a customized EDA tool, and the method includes the following steps S101 to S105:

[0112] According to the embodiment of the present disclosure, the following steps S101 to S105 are implemented based on the customized EDA tool. Since the configurable IO IP core is obtained by splitting and reconstructing the existing IO IP core, it cannot be directly configured using the existing EDA tool, so the IO IP core needs to be configured based on the customized EDA tool.

[0113] Specifically, in the customized EDA tool: multiple configurations are set in advance for the input threshold adjustable module, each configuration corresponds to a different input threshold high level voltage VIH and input threshold low level voltage VIL. The customized EDA tool makes a mapping relationship table of different configurations in the input threshold adjustable module and corresponding VIH and VIL, so that when the user inputs the desired input threshold high level voltage VIH and input threshold low level voltage VIL through the GUI interface provided by the customized EDA tool, the customized EDA tool directly calls the input threshold adjustable module of the corresponding configuration through the mapping relationship table.

[0114] According to an embodiment of the present disclosure, the customized EDA tool provides a GUI (graphical user interface), and the GUI interface includes multiple customized input boxes, and the multiple customized input boxes include: an expected input threshold high level voltage input box, an expected input threshold low level voltage input box, an expected high level output source current input box, and an expected low level output sink current input box, so as to obtain the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the specified pin module of the customized IO IP core.

[0115] Specifically, four input boxes are provided on the GUI interface of the customized EDA tool, namely: "Expected input threshold high level voltage VIH" input box, "Expected input threshold low level voltage VIL" input box, "Expected high level output source current IOH" input box, and "Expected low level output sink current IOL" input box. The user inputs the input threshold voltage and output current capability expected to be achieved for the specified pin module of the customized IOIP core from the four input boxes.

[0116] In the present disclosure, the voltage values ​​of the input threshold high level voltage and the input threshold low level voltage are relative. For example, when the input threshold high level voltage is 0.8*VDD, the input threshold low level voltage may be 0.35*VDD, 0.3*VDD, etc.; when the input threshold high level voltage is 4V, the input threshold low level voltage may be 0.8V, 1.2V, etc. Wherein, the input threshold high level voltage is less than the power supply voltage, and the input threshold low level voltage is greater than 0.

[0117] In step S101, a configurable IO IP core is obtained, wherein the configurable IO IP core includes an IO basic circuit module, an input threshold adjustable module, and an output current adjustable module, and the IO basic circuit module includes an IO core circuit module.

[0118] In the present disclosure, the configurable IO IP core is no longer an integral module, but includes modules such as an IO basic circuit module, an input threshold adjustable module, and an output current adjustable module, and the customized EDA tool obtained by customizing the EDA tool can perform more customizable and complex configurations on the input threshold voltage and output current capabilities of the configurable IO IP core.

[0119] In step S102, the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the designated pin module of the customized IO IP core are obtained.

[0120] According to an embodiment of the present disclosure, the designated pin module of the customized IO IP core is any pin module to be generated in the customized IO IP core; the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user are the input threshold voltage and output current capabilities that the designated pin module of the customized IO IP core is expected to be able to achieve.

[0121] In step S103, the input threshold adjustable module is configured according to the input threshold high level voltage and the input threshold low level voltage, and the input threshold adjustable module includes a first MOS module group. The configuring of the input threshold adjustable module includes: selecting a MOS module from the first MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, and the configured input threshold adjustable module is used to generate a first control signal of the IO core circuit module.

[0122] In the present disclosure, the first control signal is a control signal provided to the IO core circuit module, so that the IO core circuit module can compare and judge the IO input signal received from the outside with the first control signal, thereby obtaining a logical judgment result of the level voltage of the IO input signal.

[0123] The first MOS module group includes multiple MOS modules, each of which corresponds to a PMOS tube or NMOS tube when the custom IO IP core is implemented as an integrated circuit or chip, that is, the first MOS module group corresponds to a MOS tube group.

[0124] Figure 2 A schematic diagram of a configured input threshold adjustable module according to an embodiment of the present disclosure is shown.

[0125] like Figure 2 As shown, the configured input threshold adjustable module includes a power supply voltage port, a ground port and a first control signal output port.

[0126] According to an embodiment of the present disclosure, the power supply voltage port of the configured input threshold adjustable module is connected to the power supply voltage to provide an operating voltage for the configured input threshold adjustable module, and the ground port of the configured input threshold adjustable module is grounded.

[0127] According to an embodiment of the present disclosure, the first control signal output port of the configured input threshold adjustable module is connected to a MOS module selected from the first MOS module group, so that when the configured input threshold adjustable module is implemented as an integrated circuit or a chip, the first control signal is realized through the selected MOS tube.

[0128] According to an embodiment of the present disclosure, the configuration of the input threshold adjustable module also includes: determining a corresponding hysteresis voltage according to the input threshold high level voltage and the input threshold low level voltage; selecting a MOS module from the first MOS module group according to the input threshold high level voltage, the input threshold low level voltage and the hysteresis voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module includes a hysteresis circuit module for realizing the hysteresis voltage.

[0129] Figure 3 A working principle diagram of a hysteresis voltage provided by a hysteresis circuit module according to an embodiment of the present disclosure is shown.

[0130] like Figure 3 As shown, a hysteresis voltage Vhys is provided by a hysteresis circuit module, and the first control signal (VCH and VCL) is obtained by using the hysteresis voltage Vhys, an input threshold high voltage level VIH, and an input threshold low voltage level VIL, VCH=VIH-Vhys, VCL=VIL+Vhys.

[0131] In the present disclosure, after the input threshold high level voltage VIH and the input threshold low level voltage VIL are determined, the corresponding hysteresis voltage Vhys can be determined according to the values ​​of VIH and VIL. For example, the hysteresis voltage Vhys can be determined according to the difference between VIH and VIL and a preset ratio. Specifically, for example, when VIH = 0.8*VDD, VIL = 0.3*VDD, Vhys = (0.8*VDD-0.3*VDD) / 2 = 0.25*VDD. It should be understood by those skilled in the art that the above-mentioned method for solving the hysteresis voltage is only a specific example and is not a technical means for limiting the protection scope of the present disclosure. The hysteresis voltage can also be calculated using other solution methods, for example, Vhys = (0.8*VDD-0.3*VDD) / 3 = 0.2*VDD.

[0132] In a specific embodiment, assuming that VIH=0.8*VDD, VIL=0.3*VDD, Vhys=0.2*VDD, the first control signal can be determined: VCH=0.8*VDD-0.2*VDD=0.6*VDD, VCL=0.3*VDD+0.2*VDD=0.5*VDD, then when the voltage value of the IO input signal obtained from the IO core circuit module increases from 0 to VCH=0.6*VDD, the level voltage of the IO input signal is judged as a logic low level, in the interval where the voltage value of the IO input signal rises from VCH=0.6*VDD to VDD, and in the interval where the voltage value of the IO input signal drops from VDD to VCL=0.5*VDD, the level voltage of the IO input signal is judged as a logic high level, and in the interval where the voltage value of the IO input signal drops from VCL=0.5*VDD to 0, the level voltage of the IO input signal is judged as a logic low level.

[0133] When the customized IO IP core is implemented as an integrated circuit or chip, an analog voltage is generally obtained from an external device or sensor as an IO input signal. In order to prevent the obtained IO input signal from jumping back and forth between a voltage close to the input threshold high level voltage VIH and an input threshold low level voltage VIL, it is necessary to use the hysteresis voltage Vhys to correct VIH and VIL to obtain a first control signal for judgment, so that the voltage signal of the analog voltage is judged as a high level in the part that does not reach but is close to the input threshold high level voltage VIH, and is judged as a low level in the part that is higher than but close to the input threshold low level voltage VIL, thereby improving the stability and reliability of the integrated circuit or chip during operation.

[0134] Assume that the first MOS module group includes m PMOS modules and n NMOS modules; when configuring the input threshold adjustable module, p PMOS modules and q NMOS modules are selected from the first MOS module group for connection according to the input threshold high level voltage and the input threshold low level voltage, thereby generating a configured input threshold adjustable module to achieve the desired input threshold voltage and the corresponding hysteresis voltage, wherein p≤m, q≤n.

[0135] The inventors have found that in order to save the layout area of ​​the designed custom IO IP core when it is implemented as a circuit layout, and at the same time enable the input threshold voltage to achieve the desired input accuracy, the voltage values ​​of the input threshold high level voltage VIH and the input threshold low level voltage VIL can be set to an integer multiple of 0.01*VDD, 0.02*VDD, ..., 0.2*VDD, or the voltage values ​​of the input threshold high level voltage VIH and the input threshold low level voltage VIL can be set to an integer multiple of 0.01V, 0.02V, ..., 0.2V, thereby making the layout area of ​​the designed custom IO IP core as small as possible while the input threshold voltage can be set as many as possible. Those skilled in the art should understand that the value settings of the input threshold high level voltage VIH and the input threshold low level voltage VIL can be set according to the layout area of ​​the custom IO IP core required by the user and the desired accuracy of the input threshold voltage, and are not limited thereto.

[0136] For example, when the EDA tool configures the input threshold adjustable module to obtain the configured input threshold adjustable module, when the configured input threshold adjustable module is implemented as an integrated circuit or a chip, under a 0.18um design process (the minimum distance or feature size between circuits in chip manufacturing reaches 0.18 microns), when VIH=0.8*VDD, VIL=0.2*VDD, the EDA tool determines, based on the values ​​of the VIH and VIL, that 18 PMOS tubes and 12 NMOS tubes need to be selected from the first MOS tube group for connection, wherein 16 PMOS tubes and 10 NMOS tubes are used to achieve the desired VIH and VIL, and 2 PMOS tubes and 2 NMOS tubes are used to achieve the corresponding hysteresis voltage.

[0137] In a specific embodiment, the input threshold adjustable module may include an inverter module or a Schmitt trigger circuit module. The inverter module or the Schmitt trigger circuit module is connected to the first MOS module group, and according to the input threshold high level voltage VIH and the input threshold low level voltage VIL, the inverter module or the Schmitt trigger circuit module controls the on and off of different MOS modules in the first MOS module group, thereby selecting a MOS module from the first MOS module group and connecting the selected MOS module to achieve the desired input threshold voltage and hysteresis voltage.

[0138] The disclosed embodiment can pre-set multiple configurations for the input threshold adjustable module, and each configuration of the input threshold adjustable module includes different MOS modules and / or different MOS module connection methods, thereby corresponding to different input threshold high level voltages VIH and input threshold low level voltages VIL.

[0139] In another specific implementation, a plurality of MOS module groups are pre-set in the first MOS module group of the input threshold adjustable module, and each MOS module group corresponds to a different input threshold high level voltage VIH and input threshold low level voltage VIL.

[0140] Therefore, in the customized EDA tool, input threshold adjustable modules with different configurations are mapped with corresponding VIH and VIL to form a mapping relationship table, or different MOS module groups are mapped with corresponding VIH and VIL to form a mapping relationship table.

[0141] In step S104, the output current adjustable module is configured according to the high-level output source current and the low-level output sink current, and the output current adjustable module includes a second MOS module group. The configuring of the output current adjustable module includes: selecting a MOS module from the second MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, and the configured output current adjustable module is used to provide a specified output current capability under the control of a second control signal of the IO core circuit module.

[0142] According to an embodiment of the present disclosure, the configured output current adjustable module includes: a power supply voltage port, a ground port and a second control signal input port.

[0143] According to an embodiment of the present disclosure, the power supply voltage port of the configured output current adjustable module is connected to the power supply voltage to provide the operating voltage for the configured output current adjustable module, and the ground port of the configured output current adjustable module is grounded. The second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the second MOS module group, so that when the configured output current adjustable module is implemented as an integrated circuit or chip, the selected MOS module can provide a specified output current capability according to the second control signal of the IO core circuit module, thereby achieving the output current capability expected by the user.

[0144] According to an embodiment of the present disclosure, the MOS modules in the second MOS module group are divided into multiple unit output current adjustable modules; the configuration of the output current adjustable module includes: selecting one or more unit output current adjustable modules from the multiple unit output current adjustable modules according to the high-level output pull current and the low-level output sink current, the selected one or more unit output current adjustable modules provide the specified output current capability, that is, when one unit output current adjustable module is selected, the selected one unit output current adjustable module provides the specified output current capability, and when multiple unit output current adjustable modules are selected, the selected multiple unit output current adjustable modules jointly provide the specified output current capability.

[0145] Specifically, when the desired high-level output source current IOH and the low-level output sink current IOL are input through the GUI interface provided by the customized EDA tool, one or more unit output current adjustable modules can be directly selected to provide the desired output current capability.

[0146] The unit output current adjustable module includes a power supply voltage port, a ground port and a second control signal input port, the power supply voltage port of the unit output current adjustable module is connected to the power supply voltage, and the ground port of the unit output current adjustable module is grounded. The second control signal input port of the selected unit output current adjustable module is connected to the MOS module selected from the second MOS module group.

[0147] According to an embodiment of the present disclosure, all MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules are selected.

[0148] According to an embodiment of the present disclosure, a part of MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules is selected.

[0149] Figure 4A schematic diagram of a unit output current adjustable module according to an embodiment of the present disclosure; Figure 5 A schematic diagram showing another unit output current adjustable module according to an embodiment of the present disclosure.

[0150] like Figure 4 and Figure 5 As shown, the unit output current adjustable module includes an output PMOS unit and an output NMOS unit, the output PMOS unit includes a plurality of PMOS modules, and the output NMOS unit includes a plurality of NMOS modules.

[0151] In a specific implementation, assuming that IOH=3mA, IOL=5.1mA, and the unit output current capability provided by the unit output current adjustable module is 0.5mA, then IOH is 3mA / 0.5mA=6, which requires 6 complete output PMOS units, and IOL is 5.1mA / 0.5mA=10.2, which requires 10 complete output NMOS units and one output NMOS unit accounting for 20%, wherein the output NMOS unit accounting for 20% is: 20% of the NMOS modules are used in the multiple NMOS modules included in the output NMOS unit.

[0152] In the present disclosure, in the unit output current adjustable module, the second control signal of the IO core circuit module is received through the second control signal input port to control the PMOS module and the NMOS module connected to the second control signal input port in the output PMOS unit and the output NMOS unit respectively, so as to achieve the output current capability expected by the user.

[0153] The present disclosure divides the output current adjustable module into a plurality of unit output current adjustable modules, which not only improves the setting accuracy of the output current capability, but also further increases the flexibility of the output current capability configuration. Moreover, when the required high-level output source current IOH or low-level output sink current IOL is a relatively large value, a plurality of unit output current adjustable modules can be conveniently and directly selected for splicing, thereby simplifying the generation process of the customized IO IP core and improving the user experience.

[0154] Figure 6 A schematic diagram of an IO basic circuit module according to an embodiment of the present disclosure is shown.

[0155] like Figure 6As shown, the IO basic circuit module includes an IO core circuit module, and the IO core circuit module includes: a power supply voltage port, a ground port, a first control signal input port, and a second control signal output port. The power supply voltage port of the IO core circuit module is connected to the power supply voltage to provide the IO core circuit module with an operating voltage, and the ground port of the IO core circuit module is grounded.

[0156] In step S105, the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are connected to generate a designated pin module of the customized IO IP core, such as Figure 7 shown.

[0157] According to an embodiment of the present disclosure, the first control signal output port of the configured input threshold adjustable module is connected to the first control signal input port of the IO core circuit module, so as to provide a first control signal to the IO core circuit module.

[0158] According to an embodiment of the present disclosure, the second control signal output port of the IO core circuit module is connected to the second control signal input port of the configured output current adjustable module, and is used to output a second control signal to the configured output current adjustable module based on the first control signal and the IO input signal.

[0159] Specifically, in the obtained customized IO IP core, a first control signal is provided to the IO core circuit module through the configured input threshold adjustable module, the IO core circuit module generates a second control signal by combining the first control signal and the IO input signal received from the outside, and transmits the second control signal to the configured output current adjustable module, thereby providing a specified output current capability through the configured output current adjustable module under the control of the second control signal.

[0160] According to an embodiment of the present disclosure, when one or more unit output current adjustable modules are selected from the multiple unit output current adjustable modules based on the high-level output pull current and the low-level output sink current, the second control signal output port of the IO core circuit module is connected to the second control signal input port of the selected unit output current adjustable module.

[0161] According to an embodiment of the present disclosure, in addition to the IO core circuit module, the IO basic circuit module further includes: a default input threshold module and a default output current module.

[0162] For IO chips, the internal circuits generally use a low power supply voltage (such as 1.8V), and the circuit system outside the IO chip usually operates at a higher voltage. Therefore, the IO basic circuit module not only simply receives and sends signals, but also converts the signal level, thereby converting the external higher voltage into the lower voltage required internally, thereby meeting the needs of the IO chip to communicate with external devices or systems, such as data transmission, second control signal transmission, etc.

[0163] By default, the IO core circuit module in the IO basic circuit module is connected to the default input threshold module, and the IO core circuit module is connected to the default output current module, and a default first control signal is provided through the default input threshold module, and a default output current capability is provided through the default output current module.

[0164] Therefore, when the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current are not obtained from the user through a customized EDA tool, and only the default first control signal and the default output current capability are used to meet the needs, it can be achieved through the default input threshold module and the default output current module connected by default, which saves the user's operation time and facilitates the needs of simple chip design.

[0165] According to an embodiment of the present disclosure, when the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the designated pin module are obtained, the connection between the default input threshold module and the IO core circuit module, and the connection between the default output current module and the IO core circuit module are disconnected.

[0166] Specifically, when the user uses the customized EDA tool to input: input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current, the customized EDA tool disconnects the default input threshold module and the default output current module from the IO core circuit module to configure the input threshold adjustable module and the output current adjustable module according to the user's needs, and regenerates the specified pin module of the customized IO IP core whose input threshold voltage and output current capabilities meet the user's needs and process requirements.

[0167] The present disclosure can automatically select the MOS modules that need to be connected according to the requirements of different input threshold voltages and output current capabilities required by the actual chip, so as to form input threshold voltages and output current capabilities that meet the requirements, thereby achieving flexible configuration of input threshold voltages and output current capabilities.

[0168] According to an embodiment of the present disclosure, based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

[0169] According to an embodiment of the present disclosure, a bottom module is obtained, and the bottom of the designated pin module of the customized IO IP core is sealed using the bottom module to generate a designated pin module with a sealed bottom.

[0170] The present disclosure inserts a bottom module at the bottom of a designated pin module to achieve the requirement of closing the overall circuit layout and satisfy the design rule check.

[0171] According to an embodiment of the present disclosure, a second designated pin circuit layout of the customized IO IP core is generated based on the bottom-enclosed designated pin module.

[0172] The present disclosure can automatically generate a designated pin circuit layout based on the designated pin module of the designed custom IO IP core, thereby facilitating the subsequent manufacture of integrated circuits or chips.

[0173] Figure 8 A schematic diagram showing splicing pin modules in a configuration method of an IO IP core according to an embodiment of the present disclosure is shown.

[0174] like Figure 8 As shown, at least one filling module is obtained, and the filling module includes: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; multiple pin modules of the customized IO IP core are generated; the multiple pin modules are spliced ​​to obtain a spliced ​​pin module; and the vacancies in the spliced ​​pin module are filled with the at least one filling module to obtain a filled spliced ​​pin module.

[0175] According to an embodiment of the present disclosure, a multi-pin circuit layout of the customized IO IP core is generated based on the filled spliced ​​pin module.

[0176] In order to meet the design rule check (DRC) of the layout design, the present disclosure also provides a filling module so that the integrated circuit or chip can meet the design requirements during the manufacturing process.

[0177] According to an embodiment of the present disclosure, a plurality of bottom modules are provided, and the number of the bottom modules is consistent with the number of the plurality of pin modules; after obtaining the filled splicing pin module, the bottom of the filled splicing pin module is closed using the plurality of bottom modules to generate a splicing pin module with a closed bottom.

[0178] According to an embodiment of the present disclosure, when a corresponding plurality of module layouts are generated based on the IO core circuit module, the configured input threshold adjustable module, and the configured output current adjustable module, the widths of the plurality of module layouts are consistent.

[0179] According to an embodiment of the present disclosure, when corresponding multiple module layouts are generated based on the IO core circuit module, the configured input threshold adjustable module, the configured output current adjustable module, the filling module and the bottom module, the widths of the multiple module layouts are consistent.

[0180] In order to save the design area of ​​the circuit layout, the widths of the modules in the designated pin modules are set to be consistent, thereby saving design costs and reducing resource waste.

[0181] The present disclosure can automatically generate a designated pin circuit layout based on the designated pin module of the designed custom IO IP core, which facilitates the subsequent manufacture of integrated circuits or chips. When manufacturing based on the above circuit layout, it is necessary to manufacture according to the layout border. The layout border defines the physical shape of the circuit board after processing. The chip process manufacturer or manufacturer will cut and process the circuit board according to the layout border to ensure that the size and shape of the circuit board meet the design requirements.

[0182] Fig. 9 FIG. 1 is a flow chart showing a method for providing a configurable IO IP core according to an embodiment of the present disclosure. Fig. 9 As shown, the method includes steps S901 to S903.

[0183] In step S901, an input threshold adjustable module is provided, wherein the input threshold adjustable module includes a first MOS module group, a power supply voltage port, a ground port, and a first control signal output port. A customized EDA tool selects a MOS module from the first MOS module group and connects the selected MOS module according to an input threshold high level voltage and an input threshold low level voltage.

[0184] In step S902, an output current adjustable module is provided, and the output current adjustable module includes a second MOS module group, a power supply voltage port, a ground port and a second control signal input port. The customized EDA tool selects a MOS module from the second MOS module group and connects the selected MOS module according to the high-level output pull current and the low-level output sink current.

[0185] In step S903, an IO core circuit module is provided, wherein the IO core circuit module includes a power supply voltage port, a ground port, a first control signal input port and a second control signal output port, and is used to process the received IO input signal and output a second control signal.

[0186] The present disclosure can provide a configurable IO IP core for a customized EDA tool, so that the configurable IO IP core can be configured through the customized EDA tool to achieve flexible adjustment of input threshold voltage and output current capability.

[0187] According to an embodiment of the present disclosure, a hysteresis circuit module is provided. The hysteresis circuit module is arranged in the input threshold adjustable module and is used to provide a hysteresis voltage.

[0188] According to an embodiment of the present disclosure, the output current adjustable module includes multiple unit output current adjustable modules, and the unit output current adjustable module includes multiple MOS modules, a power supply voltage port, a ground port and a second control signal input port. The MOS modules included in the multiple unit output current adjustable modules together constitute the second MOS module group.

[0189] According to an embodiment of the present disclosure, when at least one unit output current adjustable module among the multiple unit output current adjustable modules is selected by a customized EDA tool, the selected unit output current adjustable module is connected to the second control signal output port of the IO core circuit module to provide the specified output current capability of the customized IO IP core.

[0190] According to an embodiment of the present disclosure, when all or part of the MOS modules of the unit output current adjustable module are selected by a custom EDA tool, the selected MOS modules are connected to the second control signal output port of the IO core circuit module to provide the specified output current capability of the custom IO IP core.

[0191] According to an embodiment of the present disclosure, a filling module is provided, the filling module comprising: a power supply voltage port and a ground port, for filling empty positions in a spliced ​​pin module of a custom IO IP core when generating multiple pin modules of a custom IO IP core based on a provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

[0192] According to an embodiment of the present disclosure, a bottom module is provided, which is used to seal the bottom of one or more pin modules of a customized IO IP core when generating the one or more pin modules of the customized IO IP core based on a provided configurable IO IP core.

[0193] According to an embodiment of the present disclosure, a default input threshold module is provided, and the default input threshold module is used to provide a default first control signal; a default output current module is provided, and the default output current module is used to provide a default output current capability.

[0194] The configurable IO IP core provided by the present disclosure has various forms, which can be an IP soft core designed by hardware description language (HDL), which allows users to flexibly modify and customize according to their needs, and each module in the provided configurable IO IP core can be in the form of a soft core; it can also be an IP solid core provided in the form of a gate-level circuit netlist to provide users with a more specific and optimized circuit design implementation, and each module in the provided configurable IO IP core can be in the form of a solid core; it can also be an IP hard core that provides a verified design circuit layout, and each module in the provided configurable IO IP core can be in the form of a hard core, which ensures the stability and reliability of the chip circuit design, and users can use it directly without further verification.

[0195] Fig.10 A schematic diagram showing a configuration device of an IO IP core with adjustable input threshold voltage and output current capability according to an embodiment of the present disclosure.

[0196] like Fig.10 As shown, the device is implemented based on a customized EDA tool, and the device 1000 includes: a first acquisition module 1001 , a second acquisition module 1002 , a voltage configuration module 1003 , a current configuration module 1004 and a generation module 1005 .

[0197] The first acquisition module 1001 is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an input threshold adjustable module, and an output current adjustable module, and the IO basic circuit module includes an IO core circuit module;

[0198] The second acquisition module 1002 is configured to acquire the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the specified pin module of the customized IO IP core;

[0199] The voltage configuration module 1003 is configured to configure the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module includes a first MOS module group, and the configuring of the input threshold adjustable module includes: selecting a MOS module from the first MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate a first control signal of the IO core circuit module;

[0200] The current configuration module 1004 is configured to configure the output current adjustable module according to the high-level output source current and the low-level output sink current, the output current adjustable module includes a second MOS module group, and the configuring of the output current adjustable module includes: selecting a MOS module from the second MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, wherein the configured output current adjustable module is used to provide a specified output current capability under the control of a second control signal of the IO core circuit module;

[0201] The generating module 1005 is configured to connect the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: a first control signal input port and a second control signal output port, the configured input threshold adjustable module includes: a first control signal output port, and the configured output current adjustable module includes: a second control signal input port;

[0202] The first control signal output port of the configured input threshold adjustable module is connected to the first control signal input port of the IO core circuit module, so as to provide a first control signal to the IO core circuit module;

[0203] The second control signal output port of the IO core circuit module is connected to the second control signal input port of the configured output current adjustable module, and is used to output a second control signal to the configured output current adjustable module based on the first control signal and the IO input signal;

[0204] The first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the first MOS module group, and the second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the second MOS module group.

[0205] According to an embodiment of the present disclosure, the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module respectively further include: a power supply voltage port and a ground port, and the power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply voltage, and the ground ports are all grounded.

[0206] According to an embodiment of the present disclosure, it further includes: a third acquisition module configured to acquire a bottom module, wherein the bottom module is used to close the bottom of the designated pin module of the custom IO IP core to generate a designated pin module with a closed bottom.

[0207] According to an embodiment of the present disclosure, it also includes: a fourth acquisition module, configured to acquire at least one filling module, the filling module including: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; the filling module is used to fill the vacancies in the splicing pin module of the customized IO IP core to obtain the filled splicing pin module, wherein the splicing pin module is obtained by splicing multiple pin modules of the customized IOIP core.

[0208] Fig.11 A schematic diagram of an apparatus 1100 for providing a configurable IO IP core according to an embodiment of the present disclosure is shown.

[0209] like Fig.11 As shown, the device 1100 includes a first providing module 1101 , a second providing module 1102 and a third providing module 1103 .

[0210] According to an embodiment of the present disclosure, the first providing module is configured to provide an input threshold adjustable module, wherein the input threshold adjustable module includes a first MOS module group, a power supply voltage port, a ground port and a first control signal output port, and the customized EDA tool selects a MOS module from the first MOS module group and connects the selected MOS module according to the input threshold high level voltage and the input threshold low level voltage.

[0211] According to an embodiment of the present disclosure, the second providing module is configured to provide an output current adjustable module, and the output current adjustable module includes a second MOS module group, a power supply voltage port, a ground port and a second control signal input port. The customized EDA tool selects a MOS module from the second MOS module group and connects the selected MOS module according to the high-level output pull current and the low-level output sink current.

[0212] According to an embodiment of the present disclosure, the third providing module is configured to provide an IO core circuit module, which includes a power supply voltage port, a ground port, a first control signal input port and a second control signal output port, and is used to process the received IO input signal and output a second control signal.

[0213] According to an embodiment of the present disclosure, it further includes: a fourth providing module, configured to provide a hysteresis circuit module, wherein the hysteresis circuit module is arranged in the input threshold adjustable module and is used to provide a hysteresis voltage.

[0214] According to an embodiment of the present disclosure, it also includes: a fifth providing module, configured to provide a filling module, the filling module including: a power supply voltage port and a ground port, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

[0215] According to an embodiment of the present disclosure, it also includes: a sixth providing module, configured to provide a bottom module, wherein the bottom module is used to seal the bottom of one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

[0216] According to an embodiment of the present disclosure, it also includes: a seventh providing module, configured to provide a default input threshold module and a default output current module, wherein the default input threshold module is used to provide a default first control signal, and the default output current module is used to provide a default output current capability.

[0217] The present disclosure provides a chip, including: a custom IO IP core manufactured according to the method described above, or a custom IO IP core manufactured according to the configurable IO IP core provided by the method described above.

[0218] The present disclosure provides an electronic device, comprising: the chip as described above.

[0219] The present disclosure provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the configuration method of configuring an IO IP core or the method of providing a configurable IO IP core as described in any of the preceding items is implemented.

[0220] The present disclosure provides a computer program product, including computer instructions, which, when executed by a processor, implement the configuration method of configuring an IO IP core or the method of providing a configurable IO IP core as described in any of the preceding items.

[0221] The flowchart and block diagram in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the method and computer program product according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0222] The units or modules involved in the embodiments described in the present disclosure may be implemented by software or programmable hardware. The units or modules described may also be set in a processor, and the names of these units or modules do not constitute limitations on the units or modules themselves in some cases.

[0223] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system in the above embodiment; or a computer-readable storage medium that exists independently and is not assembled into a device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the method described in the present disclosure.

[0224] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A configuration method for an IO IP core with adjustable input threshold voltage and output current capability, characterized in that: The method is implemented based on a customized EDA tool, including: Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an input threshold adjustable module, and an output current adjustable module, and the IO basic circuit module includes an IO core circuit module; Get the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current of the specified pin module input by the user for the customized IO IP core; According to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module is configured, the input threshold adjustable module includes a first MOS module group, and the configuring of the input threshold adjustable module includes: selecting a MOS module from the first MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate a first control signal of the IO core circuit module; According to the high-level output source current and the low-level output sink current, the output current adjustable module is configured, the output current adjustable module includes a second MOS module group, and the configuring of the output current adjustable module includes: selecting a MOS module from the second MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, wherein the configured output current adjustable module is used to provide a specified output current capability under the control of a second control signal of the IO core circuit module; Connecting the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: a first control signal input port and a second control signal output port, the configured input threshold adjustable module includes: a first control signal output port, and the configured output current adjustable module includes: a second control signal input port; The first control signal output port of the configured input threshold adjustable module is connected to the first control signal input port of the IO core circuit module, so as to provide the first control signal to the IO core circuit module; The second control signal output port of the IO core circuit module is connected to the second control signal input port of the configured output current adjustable module, and is used to output the second control signal to the configured output current adjustable module based on the first control signal and the IO input signal; The first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the first MOS module group, and the second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the second MOS module group.

2. The method according to claim 1, characterized in that The IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module respectively further include: a power supply voltage port and a ground port. The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply voltage, and the ground ports are all grounded.

3. The method according to claim 1, characterized in that Also includes: Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

4. The method according to claim 1, characterized in that: Also includes: A bottom module is obtained, and the bottom of the designated pin module of the customized IO IP core is sealed by using the bottom module to generate a designated pin module with a sealed bottom.

5. The method according to claim 4, characterized in that Also includes: Based on the bottom-enclosed designated pin module, a second designated pin circuit layout of the customized IO IP core is generated.

6. The method according to claim 1, characterized in that The configuration of the input threshold adjustable module also includes: Determine a corresponding hysteresis voltage according to the input threshold high level voltage and the input threshold low level voltage; A MOS module is selected from the first MOS module group according to the input threshold high level voltage, the input threshold low level voltage and the hysteresis voltage and the selected MOS module is connected to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module includes a hysteresis circuit module for realizing the hysteresis voltage.

7. The method according to claim 1, characterized in that: The MOS modules in the second MOS module group are divided into a plurality of unit output current adjustable modules; The configuring the output current adjustable module comprises: selecting one or more unit output current adjustable modules from the plurality of unit output current adjustable modules according to the high level output source current and the low level output sink current, and when selecting a plurality of unit output current adjustable modules, the selected plurality of unit output current adjustable modules jointly provide the specified output current capability; The unit output current adjustable module comprises a power supply voltage port, a ground port and a second control signal input port, the power supply voltage port of the unit output current adjustable module is connected to the power supply voltage, and the ground port of the unit output current adjustable module is grounded; The second control signal output port of the IO core circuit module is connected to the second control signal input port of the selected unit output current adjustable module, and the second control signal input port of the selected unit output current adjustable module is connected to the MOS module selected from the second MOS module group.

8. The method according to claim 7, characterized in that: All MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules are selected; and / or A portion of MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules is selected.

9. The method according to claim 1, characterized in that: Also includes: Acquire at least one filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module being connected to a power supply voltage, and the ground port of the filling module being grounded; Generate multiple pin modules of the customized IO IP core; Splicing the plurality of pin modules to obtain a spliced ​​pin module; The at least one filling module is used to fill the empty space in the splicing tube foot module to obtain a filled splicing tube foot module.

10. The method according to claim 9, characterized in that Also includes: Based on the filled spliced ​​pin module, a multi-pin circuit layout of the customized IO IP core is generated.

11. The method according to claim 1, characterized in that: The customized EDA tool provides a graphical user interface (GUI), wherein the GUI interface includes a plurality of customized input boxes; The multiple customized input boxes include: an expected input threshold high level voltage input box, an expected input threshold low level voltage input box, an expected high level output source current input box, and an expected low level output sink current input box, so as to obtain the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the specified pin module of the customized IO IP core.

12. The method according to claim 1, characterized in that The IO basic circuit module also includes: a default input threshold module and a default output current module; When obtaining the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the designated pin module, disconnect the connection between the default input threshold module and the IO core circuit module, and disconnect the connection between the default output current module and the IO core circuit module.

13. The method according to claim 1, characterized in that When a corresponding plurality of module layouts are generated based on the IO core circuit module, the configured input threshold adjustable module, and the configured output current adjustable module, the widths of the plurality of module layouts are consistent.

14. A method for providing a configurable IO IP core, characterized in that: include: Providing an input threshold adjustable module, the input threshold adjustable module comprising a first MOS module group, a power supply voltage port, a ground port and a first control signal output port, the customized EDA tool selecting a MOS module from the first MOS module group and connecting the selected MOS module according to an input threshold high level voltage and an input threshold low level voltage; Providing an output current adjustable module, the output current adjustable module comprising a second MOS module group, a power supply voltage port, a ground port, and a second control signal input port, wherein the customized EDA tool selects a MOS module from the second MOS module group and connects the selected MOS module according to a high-level output pull current and a low-level output sink current; An IO core circuit module is provided, which includes a power supply voltage port, a ground port, a first control signal input port and a second control signal output port, and is used to process a received IO input signal and output a second control signal.

15. The method according to claim 14, characterized in that Also includes: A hysteresis circuit module is provided, and the hysteresis circuit module is arranged in the input threshold adjustable module and is used to provide a hysteresis voltage.

16. The method according to claim 14, characterized in that The output current adjustable module includes multiple unit output current adjustable modules, and the unit output current adjustable module includes multiple MOS modules, a power supply voltage port, a ground port and a second control signal input port. The MOS modules included in the multiple unit output current adjustable modules together constitute the second MOS module group.

17. The method according to claim 16, characterized in that: When at least one of the plurality of unit output current adjustable modules is selected by the custom EDA tool, the selected unit output current adjustable module is connected to the second control signal output port of the IO core circuit module to provide a specified output current capability of the custom IO IP core; When all or part of the MOS modules of the unit output current adjustable module are selected by a custom EDA tool, the selected MOS modules are connected to the second control signal output port of the IO core circuit module to provide the specified output current capability of the custom IOIP core.

18. The method according to claim 14, characterized in that Also includes: A filling module is provided, the filling module comprising: a power supply voltage port and a ground port, which is used to fill empty positions in a spliced ​​pin module of a custom IO IP core when generating multiple pin modules of a custom IO IP core based on a provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

19. The method according to claim 14, characterized in that Also includes: A bottom module is provided, and the bottom module is used to close the bottom of one or more pin modules when one or more pin modules of a customized IO IP core are generated based on the provided configurable IO IP core.

20. The method according to claim 14, characterized in that Also includes: Providing a default input threshold module, wherein the default input threshold module is used to provide a default first control signal; A default output current module is provided, wherein the default output current module is used to provide a default output current capability.

21. A configuration device for an IO IP core with adjustable input threshold voltage and output current capability, characterized in that: The device is implemented based on a customized EDA tool, and the device includes: A first acquisition module is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO basic circuit module, an input threshold adjustable module, and an output current adjustable module, and the IO basic circuit module includes an IO core circuit module; The second acquisition module is configured to acquire the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user for the specified pin module of the customized IO IP core; a voltage configuration module, configured to configure the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module including a first MOS module group, the configuring the input threshold adjustable module including: selecting a MOS module from the first MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, the configured input threshold adjustable module being used to generate a first control signal of the IO core circuit module; a current configuration module, configured to configure the output current adjustable module according to the high-level output source current and the low-level output sink current, the output current adjustable module including a second MOS module group, the configuring the output current adjustable module including: selecting a MOS module from the second MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, the configured output current adjustable module being used to provide a specified output current capability under the control of a second control signal of the IO core circuit module; A generating module is configured to connect the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: a first control signal input port and a second control signal output port, the configured input threshold adjustable module includes: a first control signal output port, and the configured output current adjustable module includes: a second control signal input port; The first control signal output port of the configured input threshold adjustable module is connected to the first control signal input port of the IO core circuit module, so as to provide a first control signal to the IO core circuit module; The second control signal output port of the IO core circuit module is connected to the second control signal input port of the configured output current adjustable module, and is used to output a second control signal to the configured output current adjustable module based on the first control signal and the IO input signal; The first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the first MOS module group, and the second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the second MOS module group.

22. The device according to claim 21, characterized in that The IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module respectively further include: a power supply voltage port and a ground port. The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply voltage, and the ground ports are all grounded.

23. The device according to claim 21, characterized in that Also includes: The third acquisition module is configured to acquire a bottom module, where the bottom module is used to close the bottom of the designated pin module of the customized IO IP core to generate a designated pin module with a closed bottom.

24. The device according to claim 21, characterized in that Also includes: A fourth acquisition module is configured to acquire at least one filling module, wherein the filling module includes: a power supply voltage port and a ground port, wherein the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; the filling module is used to fill the vacancies in the splicing pin module of the custom IO IP core to obtain the filled splicing pin module, wherein the splicing pin module is obtained by splicing multiple pin modules of the custom IO IP core.

25. A device for providing a configurable IO IP core, characterized in that: include: A first providing module is configured to provide an input threshold adjustable module, wherein the input threshold adjustable module includes a first MOS module group, a power supply voltage port, a ground port, and a first control signal output port, wherein the customized EDA tool selects a MOS module from the first MOS module group and connects the selected MOS module according to an input threshold high level voltage and an input threshold low level voltage; A second providing module is configured to provide an output current adjustable module, wherein the output current adjustable module includes a second MOS module group, a power supply voltage port, a ground port, and a second control signal input port, wherein the customized EDA tool selects a MOS module from the second MOS module group and connects the selected MOS module according to a high-level output pull current and a low-level output sink current; The third providing module is configured to provide an IO core circuit module, wherein the IO core circuit module includes a power supply voltage port, a ground port, a first control signal input port and a second control signal output port, and is used to process the received IO input signal and output a second control signal.

26. The device according to claim 25, characterized in that Also includes: The fourth providing module is configured to provide a hysteresis circuit module, wherein the hysteresis circuit module is arranged in the input threshold adjustable module and is used to provide a hysteresis voltage.

27. The device according to claim 25, characterized in that Also includes: A fifth providing module is configured to provide a filling module, wherein the filling module includes: a power supply voltage port and a ground port, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

28. The device according to claim 25, characterized in that Also includes: The sixth providing module is configured to provide a bottom module, wherein the bottom module is used to seal the bottom of the one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

29. The device according to claim 25, characterized in that Also includes: A seventh providing module is configured to provide a default input threshold module and a default output current module, wherein the default input threshold module is used to provide a default first control signal, and the default output current module is used to provide a default output current capability.

30. A chip, characterized in that: The method comprises manufacturing a customized IO IP core generated by the method according to any one of claims 1 to 13, or manufacturing a customized IO IP core generated by the configurable IO IP core provided by the method according to any one of claims 14 to 20.

31. An electronic device, characterized in that: Comprising a chip according to claim 30.

32. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 20 is implemented.

33. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the method according to any one of claims 1 to 20.

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