Memory, operation method thereof and memory system

Abstract

The embodiment of the invention provides a memory, an operation method thereof and a memory system, the memory comprises a row hammer control circuit, the row hammer control circuit comprises a plurality of counters, and each counter is used for counting the number of visited times of a memory row and generating a first count value; the adjusting circuit is connected with the plurality of counters; the adjusting circuit is used for resetting each counter when the plurality of first count values reach a target threshold value so as to adjust each first count value to the same offset value and generate a plurality of second count values; the line hammer control circuit is also used for determining a target storage line according to the plurality of second count values.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a memory and an operating method thereof, and a memory system. Background Art

[0002] Counters are the most commonly used logic circuits in integrated circuits. Counters in integrated circuits are mainly used to count some items to achieve functions such as measurement, counting, control, and frequency division. For example, in a row hammer control circuit that solves the row hammer effect problem, the counter can count the number of times a storage row is accessed, so that the row hammer control circuit can determine the aggressor row based on the counting result, and then refresh the victim row adjacent to the aggressor row. In some scenarios, such as the above-mentioned row hammer control circuit, the number and counting capacity requirements of counters are relatively large, which will increase the power consumption of the memory, and they occupy more area of ​​the memory, which is not conducive to the miniaturization of the memory. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a memory, an operating method thereof, and a memory system.

[0004] According to a first aspect of the present disclosure, there is provided a memory, comprising:

[0005] A row hammer control circuit, comprising a plurality of counters, each of which is used to count the number of times a storage row is accessed and generate a first count value;

[0006] an adjusting circuit connected to the plurality of counters; the adjusting circuit is used for resetting each of the counters when the plurality of first count values ​​all reach a target threshold value, so as to adjust each of the first count values ​​by the same offset value to generate a plurality of second count values;

[0007] The row hammer control circuit is further configured to determine a target storage row according to the plurality of second count values.

[0008] According to a second aspect of the present disclosure, a memory system is provided, comprising: the memory according to any one of the first aspect of the present disclosure; and

[0009] The memory controller is connected to the memory and is used to control the memory.

[0010] According to a third aspect of the present disclosure, a method for operating a memory is provided, comprising:

[0011] Using a plurality of counters to count the number of accesses to a plurality of storage rows respectively, to generate a plurality of first count values;

[0012] When the plurality of first count values ​​all reach the target threshold, resetting each of the counters to adjust each of the first count values ​​by the same offset value to generate a plurality of second count values;

[0013] A target memory row is determined based on the plurality of second count values, and a refresh operation is performed on memory rows adjacent to the target memory row.

[0014] In the memory provided by the embodiment of the present disclosure, an adjustment circuit for the counter in the row hammer control circuit is added. The adjustment circuit can reset each counter when the first count values ​​of all counters reach the target threshold value, and adjust each first count value by the same offset value to obtain a second count value. Among them, the size relationship between all the second count values ​​is the same as the size relationship between all the first count values. Therefore, the target storage row determined according to multiple second count values ​​is the same as the target storage row determined according to multiple first count values. It can be seen that the adjustment circuit not only does not affect the row hammer control circuit to determine the target storage row, but can increase the remaining counting space of the counter after adjustment, thereby avoiding the problem of the counter being stuck due to the count values ​​of the counter being in a high level state. In addition, in the present disclosure, there is no need to increase the effective bits of the counter, that is, there is no need to increase the number of triggers in the counter, which saves the occupied area of ​​the counter, is conducive to the miniaturization of the memory, and can reduce the power consumption of the memory. Furthermore, the addition of the adjustment circuit does not affect the row hammer control circuit itself, other circuits in the memory, and circuits such as the memory controller. Therefore, this improvement has a short verification cycle and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1a A block diagram of an exemplary system with a memory provided for an embodiment of the present disclosure;

[0016] Figure 1b A block diagram of another exemplary system with a memory provided for an embodiment of the present disclosure;

[0017] Figure 2 is a schematic diagram of the hammering effect;

[0018] Figure 3 A schematic diagram of a memory provided by an embodiment of the present disclosure;

[0019] Figure 4a A schematic diagram of a hammer control circuit provided by an embodiment of the present disclosure;

[0020] Figure 4b A schematic diagram of a counting circuit provided in an embodiment of the present disclosure;

[0021] Figure 5 An operation schematic diagram of a counting circuit provided by an embodiment of the present disclosure;

[0022] Figure 6a and Figure 6b Another operation schematic diagram of a counting circuit provided in an embodiment of the present disclosure;

[0023] Figure 7 A schematic diagram of a memory provided by an embodiment of the present disclosure;

[0024] Figure 8 The regulating circuit provided in the embodiment of the present disclosure is Figure 6b Schematic diagram of the count values ​​of the multiple counters shown before and after adjustment;

[0025] Fig. 9 A schematic diagram of a counter provided in an embodiment of the present disclosure;

[0026] Fig.10 A schematic diagram of a hammer control circuit and a regulating circuit provided in an embodiment of the present disclosure;

[0027] Fig.11 for Fig.10 A schematic diagram of the regulating circuit shown before and after adjusting the count values ​​of multiple counters;

[0028] Fig.12 for Fig.10 The bar diagram of the regulating circuit shown before and after adjusting the count values ​​of multiple counters;

[0029] Fig.13 A schematic diagram of another hammer control circuit and regulating circuit provided in an embodiment of the present disclosure;

[0030] Fig.14 for Fig.13 A schematic diagram of the regulating circuit shown before and after adjusting the count values ​​of multiple counters;

[0031] Fig.15 for Fig.13 The bar diagram of the regulating circuit shown before and after adjusting the count values ​​of multiple counters;

[0032] Fig.16 A schematic diagram of a hammer control circuit and a regulating circuit provided in an embodiment of the present disclosure;

[0033] Fig.17 for Fig.16 A schematic diagram of the regulating circuit shown before and after adjusting the count values ​​of multiple counters;

[0034] Fig.18 for Fig.16 The bar diagram of the regulating circuit shown before and after adjusting the count values ​​of multiple counters;

[0035] Fig.19A schematic diagram of a hammer control circuit and a regulating circuit provided in an embodiment of the present disclosure;

[0036] Fig. 20 for Fig.19 A schematic diagram of the regulating circuit shown before and after adjusting the count values ​​of multiple counters;

[0037] Fig.21 for Fig.19 The bar diagram of the regulating circuit shown before and after adjusting the count values ​​of multiple counters;

[0038] Fig. 22 A schematic diagram of a delay circuit provided in an embodiment of the present disclosure;

[0039] Fig.23 A schematic diagram of another regulating circuit provided in an embodiment of the present disclosure;

[0040] Fig.24 A schematic diagram of another hammer control circuit and regulating circuit provided in an embodiment of the present disclosure;

[0041] Fig.25 for Fig.24 The schematic diagram of the operation method of the hammer control circuit and the regulating circuit shown;

[0042] Fig.26 A flowchart of a method for operating a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The technical solution of the present disclosure is further elaborated in detail below in conjunction with the drawings and specific embodiments of the specification. In the description of the present disclosure, it should be understood that the terms "length", "width", "depth", "upper", "lower", "outer" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0044] Figure 1a and Figure 1b is a block diagram of an exemplary system with a memory provided by an embodiment of the present disclosure. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1aAs shown in , the system 100 may include a host 110 and a memory system 120, the memory system 120 having one or more memories 130 and a memory controller 140. The host 110 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 110 may be configured to send data to the memory system 120 or receive data from the memory system 120.

[0045] In some embodiments, the memory controller 140 is coupled to the memory 130 and the host 110, and is configured to control the memory 130. The memory controller 140 can operate the memory 130 by providing a combination of various control signals and address signals. For example, the memory controller 140 can control the memory 130 to perform read and write operations. The memory controller 140 can also control the memory 130 to perform a refresh operation. The memory 130 may include all types of memories that perform refresh operations to maintain data stored in storage cells. For example, the memory 130 may include a dynamic random access memory (DRAM). The dynamic random access memory includes, but is not limited to, a double data rate synchronous dynamic random access memory (DDR SDRAM, DDR for short).

[0046] The memory 130 may include a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array may be a DRAM memory cell array, wherein each DRAM memory cell may include a transistor and a capacitor, wherein the gate of the transistor is connected to a word line, the source is connected to a bit line, and the drain is connected to the capacitor. The memory cell array includes a plurality of memory rows, and the memory cells of each memory row are coupled to the same word line, and the word line is coupled to a row decoder. The column decoder is coupled to a plurality of memory columns through a plurality of bit lines.

[0047] The peripheral circuit can be coupled to the memory cell array through word lines and bit lines. The peripheral circuit can control the on and off of the transistor by controlling the word line voltage, thereby reading the data information stored in the capacitor through the bit line, or writing the data information into the capacitor.

[0048] In some embodiments, the memory controller 140 may provide an activation command ACT, a read command RD, and a write command WT to access the memory 130. The activation command ACT is a row access command. The memory controller 140 simultaneously issues the activation command ACT and the row address signal. The memory 130 synchronously receives the activation command ACT and the row address signal, and enables the word line of the memory cell array according to the row address signal.

[0049] The memory controller 140 may also provide a read command RD to control the memory 130 to perform a read operation, or provide a write command WT to control the memory 130 to perform a write operation. The column address signal and the read command / write command are issued simultaneously.

[0050] For example, the memory 130 may synchronously receive a read command RD and a column address signal and select a bit line of a memory cell array according to the column address signal, thereby performing a read operation on data in a memory cell located at an intersection of an enabled word line and the selected bit line.

[0051] For example, the memory 130 may synchronously receive a write command WT and a column address signal, and select a bit line of the memory cell array according to the column address signal. The memory 130 may receive data sent from the memory controller 140 during a write operation, and may store the received data in a memory cell located at the intersection of an enabled word line and a selected bit line.

[0052] In some embodiments, the memory controller 140 may provide a refresh command REF to control the memory 130 to perform a refresh operation. For example, the memory controller 140 provides the refresh command REF to the memory 130 at a fixed cycle. One refresh command REF is only valid for one storage row, and the memory 130 may perform a refresh operation on all storage rows in sequence according to the refresh command REF. In some embodiments, when the memory 130 performs a refresh, it does not need to provide row address information externally, and the memory can automatically generate row addresses in sequence.

[0053] In some embodiments, Figure 1b As shown, the memory 130 may also be directly coupled to the host 110 and perform various operations under the control of the host 110. By way of example, the host 110 may provide various combinations of control signals and address signals instead of the above-mentioned memory controller to operate the memory 130. For example, the host provides an activation command ACT and row address information to activate a storage row of the memory, provides a read command RD and a column address signal to perform a read operation, provides a write command WT and a column address signal to perform a write operation, and provides a refresh command REF to perform a refresh operation.

[0054] In DRAM, if a certain storage row is repeatedly accessed during a refresh window, the charge of the storage cells in the storage rows physically adjacent to the storage row will leak, which is the row hammer effect. Figure 2 is a schematic diagram of the hammering effect. Figure 2 As shown in FIG. 1 , the memory row that is repeatedly accessed is called the aggressor row. The memory row that is physically adjacent to the aggressor row (e.g. Figure 2 The upper and lower storage rows that are physically adjacent to the aggressor row are called victim rows. The victim row suffers from charge loss due to repeated accesses to the aggressor row. If the aggressor row is accessed a certain number of times, the row hammering effect may cause data corruption in the victim row.

[0055] A more effective method to solve the row hammering effect is target row refresh (TRR). Target row refresh means finding the aggressor row and refreshing its victim row. By refreshing the victim row, the data in the storage unit of the victim row is retained.

[0056] In some embodiments, the memory can track the row address signal sent by the memory controller in synchronization with the activation command, thereby obtaining the number of times each storage row is accessed, and then determining the storage row with the most accesses within a period of time. The row with the most accesses is the aggressor row (that is, the target storage row). The memory can refresh the victim row of the aggressor row, thereby weakening the adverse effects of the row hammering effect.

[0057] Figure 3 A schematic diagram of a memory provided in accordance with an embodiment of the present disclosure. Figure 3 Shows Figure 1a and Figure 1b An example of a memory in . Figure 3 As shown, the memory may include a memory cell array 131 and peripheral circuits, wherein the peripheral circuits may include a control logic circuit 132, an address buffer 133, a refresh circuit 134, a row decoder 135, a column decoder 136, an I / O gating circuit 137, a data I / O buffer 138, and a row hammer control circuit 200, etc.

[0058] The address buffer 133 may receive a row address signal and a column address signal from the memory controller 140 or the host 110. The address buffer 133 may provide the received column address signal to the column decoder 136, and provide the received row address signal to the row decoder 135 and the row hammer control circuit 200. The address buffer 133 receives the row address signal synchronously with the control logic circuit 132 receiving the activation command ACT.

[0059] The control logic circuit 132 may receive various commands CMD from the memory controller 140 or the host 110 and generate various control signals for controlling the operation of the memory 130. Specifically, the command decoder 1321 in the control logic circuit 132 is used to receive various commands CMD and generate various control signals. The control logic circuit 132 may read data from or write data to the memory cell array 131, or perform other operations by using control signals. For example, the control logic circuit 132 may receive an activation command ACT to control the row decoder 135 to activate the memory row indicated by the row address signal. The control logic circuit 132 may receive a refresh command REF to control the refresh circuit 134 to perform a refresh operation on a certain memory row. Although Figure 3 The control logic circuit 132 and the address buffer 133 in FIG. 1 are shown as separate components, but the control logic circuit 132 and the address buffer 133 may also be an integral component. Figure 3 , the active command ACT and the row address signal are shown as separate signals, but the row address signal can be considered to be included in the active command ACT. Similarly, the column address signal can also be considered to be included in the read command RD or the write command WT.

[0060] The row decoder 135 may decode the row address signal received from the address buffer 133 to select a word line WL corresponding to the accessed row address from a plurality of word lines WL, and may connect the selected word line WL to a word line driver. The column decoder 136 may select a specific bit line BL from a plurality of bit lines BL connected to the memory cell array 131. The column decoder 136 may select one bit line or may select a plurality of bit lines BL in a burst mode.

[0061] The data I / O buffer 138 can receive data from the host 110 or the memory controller 140 or transmit data to the host 110 or the memory controller 140. The I / O gating circuit 137 is connected to the data I / O buffer 138, and the I / O gating circuit 137 can receive data from the data I / O buffer 138 and write it into the memory cell array 131, or read data from the memory cell array 131 and transmit it to the data I / O buffer 138.

[0062] The row hammer control circuit 200 can monitor the number of times the storage row is accessed, and detect the row address of the target storage row that is frequently accessed during the refresh window. For example, the row hammer control circuit 200 is connected to the address buffer 133 and the refresh circuit 134. The row hammer control circuit 200 is used to receive the accessed row address provided by the address buffer 133, and count the number of times each storage row is accessed, determine the storage row with the most accesses as the target storage row, and determine the row address to be refreshed of the victim row based on the target storage row, and provide the row address to be refreshed to the refresh circuit 134.

[0063] The refresh circuit 134 can perform a refresh operation on the row address to be refreshed in response to the refresh command REF and the row address to be refreshed provided by the row hammer control circuit 200 to retain the data in the storage cells of the victim row (i.e., the adjacent storage row of the target storage row), thereby weakening the adverse effects of the row hammer effect.

[0064] Figure 4a A schematic diagram of a hammer control circuit provided by an embodiment of the present disclosure, Figure 4b Schematic diagram of a counting circuit provided by an embodiment of the present disclosure. Figure 4a and Figure 4b As shown, the hammer control circuit 200 includes a counting circuit 220 and a counting control circuit 230 .

[0065] The counting circuit 220 is connected to the address buffer 133, and includes a plurality of address registers 221 and a plurality of counters 222. Each address register 221 is connected to a corresponding counter 222. Each address register 221 can be used to store a row address, and the counter 222 is used to count the number of times the row address in the address register 221 connected thereto is accessed.

[0066] In some embodiments, after receiving the accessed row address, the counting circuit 220 may store the accessed row address in a vacant address register 221 and set the count value of the counter 222 corresponding to the address register 221 to 1.

[0067] In some embodiments, the number of address registers 221 is less than the number of storage rows in the memory cell array 131; when row addresses are stored in all address registers 221, after receiving the accessed row address, the counting circuit 220 matches the accessed row address with the row addresses stored in all address registers 221 to obtain a matching result;

[0068] The counting control circuit 230 is connected to the counting circuit 220, wherein when the matching result is that the accessed row address is the same as the row address stored in the first address register 221, the counting control circuit 230 is used to increase the count value of the counter 222 corresponding to the first address register 221 by 1;

[0069] When the matching result is that the accessed row address and the row addresses stored in all address registers 221 are different, the counting control circuit 230 is used to replace the row address in the second address register 221 with the accessed row address, and increase the count value of the counter 222 corresponding to the second address register 221 by 1; the second address register 221 is the address register 221 occupied by the row address with the least number of accesses.

[0070] Here, the naming of the first address register and the second address register is only for convenience of description. The first address register or the second address register does not specifically refer to an address register at a certain physical position in the counting circuit. On the contrary, the first address register or the second address register may be any address register in the counting circuit. In some cases, the first address register and the second address register may be the same address register.

[0071] In some embodiments, when the matching result is that the accessed row address is the same as the row address stored in the first address register 221, the counting circuit 220 may not send the matching result to the counting control circuit 230, but the counting circuit 220 itself may increase the count value of the counter 222 corresponding to the first address register 221 by 1.

[0072] In some embodiments, when the matching result is that the accessed row address and the row addresses stored in all address registers 221 are different, the counting control circuit 230 is also used to indicate (ie select) the second address register 221 corresponding to the row address that has been accessed the least number of times.

[0073] In some embodiments, the counting circuit 220 further includes: a plurality of content-addressable memories (CAMs) 223, each of which is connected to an address register 221 and a counter 222 corresponding to the address register 221. The content-addressable memory 223 is used to receive an accessed address, and match the accessed address with a row address stored in the corresponding address register 221 to obtain a matching result, and transmit the matching result to the counting control circuit 230. The counting control circuit 230 can be connected to a plurality of address registers 221, a plurality of content-addressable memories 223, and a plurality of counters 222.

[0074] Figure 5 The present invention provides an operation schematic diagram of a counting circuit according to an embodiment of the present invention. Figure 5 From left to right, the current state of the row address stored in the address register and the count value of the counter, the state after receiving the first activation command ACT1, the state after receiving the second activation command ACT2, and the state after executing the row hammer refresh command are shown in sequence. Figure 5 As shown, the counting circuit includes 4 address registers and 4 counters. The row addresses and access times stored in the 4 address registers and 4 counters in the current state are: 0XA0 address has 0XA9 access times, 0XB0 address has 0X80 access times, 0XC0 address has 0XB1 access times, and 0XD0 address has 0XCA access times.

[0075] See also Figure 5When the counting circuit receives the accessed row address 0XA0 synchronized with the first activation command ACT1, it is determined through matching that the address register has stored the address 0XA0, so the access count of the address 0XA0 stored in the counting circuit is increased by 1, so that the access count increases from 0XA9 to 0XAA.

[0076] Continue to see Figure 5 , when the counting circuit receives the accessed row address 0XE0 synchronized with the second activation command ACT2, it is determined through matching that the accessed address 0XE0 does not match all the row addresses currently stored in the counting circuit, and all the address registers are already occupied. In this case, the 0XB0 address entry with the least number of accesses (0X80) can be ejected, and the accessed address 0XE0 is stored in the address register, and the count value of the counter corresponding to the address register is increased by 1. Therefore, the number of accesses corresponding to the accessed address 0XE0 is 0X81. The purpose of this is to prevent malicious attacks by hackers. If the count value of the counter corresponding to the address register is set to 1 after the accessed address 0XE0 is stored in the address register, hackers will be given the opportunity to maliciously attack the data of a certain storage row. For example, if a hacker wants to attack a designated storage row, he can first frequently access the designated storage row so that it is accessed more times but is not the most accessed of all address registers, and then mask it as the storage row with the least access times, and replace the row address of the designated storage row by sending another storage row address, so that the number of times the designated storage row is accessed becomes 0. If the designated storage row is accessed again, its number of accesses will be counted from 0, making it difficult for the designated storage row to become the storage row with the most accesses, and thus it cannot be determined as the target storage row to execute the refresh command, resulting in data loss. In order to prevent malicious attacks by hackers, in the row hammer control circuit provided by the present disclosure, if the address entry in the address register is replaced, when the row address is accessed again, its number of accesses is not zero, so that the row address has the opportunity to become the most accessed and the refresh command is executed.

[0077] In some embodiments, the counting control circuit 230 is also used to indicate the target row address that has been accessed the most times, and the row hammer control circuit 200 is also used to determine the row address to be refreshed based on the target row address, and provide the row address to be refreshed to the refresh circuit 134; wherein the storage row corresponding to the target row address that has been accessed the most times is the target storage row, and the storage row corresponding to the row address to be refreshed is an adjacent storage row of the target storage row.

[0078] The refresh circuit 134 is connected to the command decoder 1321 , and is used for performing a refresh operation on the row address to be refreshed in response to a refresh command REF and the row address to be refreshed.

[0079] In this embodiment, the row hammer control circuit 200 indicates the target row address that is accessed the most times and determines the row address to be refreshed, which is the row address of the adjacent storage row of the target storage row; the refresh circuit 134 responds to the refresh command REF and the row address to be refreshed, and performs a refresh operation on the row address to be refreshed, which can reduce the impact of the row hammer effect on the adjacent storage rows (i.e., the victim rows) of the target storage row and avoid data loss in the victim rows.

[0080] In some embodiments, the row hammer control circuit 200 is used to increase the target row address by 1 and / or decrease it by 1 (+1 and / or -1) to generate a row address to be refreshed, that is, a row address of an adjacent storage row of the target storage row. In some embodiments, the operation of determining the row address to be refreshed from the target row address can be performed by the counting control circuit 230, or can be implemented by other circuits in the row hammer control circuit. For example, the row hammer control circuit 200 can also include: an address generation circuit, the address generation circuit is connected to the counting control circuit 230, the address generation circuit is used to obtain the target row address and determine the row address to be refreshed, and transmit the row address to be refreshed to the refresh circuit 134.

[0081] It should be noted that the memory controller only provides a refresh command REF to the memory, and does not distinguish whether the refresh command provided to the memory is a row hammer refresh command RH REF. According to the received refresh command REF, the row hammer control circuit 200 inside the memory 130 will provide row address information of the adjacent storage row of the target storage row at intervals, so that the refresh circuit 134 can perform a refresh operation on the adjacent storage row of the target storage row. The refresh operation can be regarded as a row hammer refresh command RH REF.

[0082] For other refresh commands REF that are not row hammer refresh commands RH REF, the memory controls the refresh circuit 134 to perform a conventional refresh operation according to these refresh commands REF. For example, the memory performs refresh operations on storage rows in sequence in a certain order.

[0083] In some embodiments, the row hammer control circuit 200 periodically selects the refresh command REF as the row hammer refresh command RH REF. It can be understood that the row hammer control circuit 200 selects a refresh command REF as the row hammer refresh command RH REF after every preset number of refresh commands REF. For example, the row hammer control circuit 200 is used to select a refresh command REF as the row hammer refresh command RH REF after every 7 refresh commands REF. That is, with 8 refresh commands REF as a cycle, the row hammer control circuit 200 is used to select the last refresh command REF in this cycle as the row hammer refresh command RH REF.

[0084] For example, the row hammer control circuit 200 may include a command counter for counting the refresh command REF, and when the count value is the maximum count value of the command counter, the refresh command REF corresponding to the count value is selected as the row hammer refresh command RH REF. Taking the above-mentioned selection of a refresh command REF as the row hammer refresh command RH REF after every 7 refresh commands REF as an example, the maximum count value of the command counter may be 7, and after reaching the maximum value, the count value of the command counter is reset to 0. The row hammer control circuit 200 is used to determine that the refresh command REF corresponding to the count value is the row hammer refresh command RH REF when the count value of the command counter is 7.

[0085] In some embodiments, the count control circuit 230 is further configured to reset the number of accesses of the row address with the most accesses to the minimum number of accesses among all the row addresses when or after the refresh circuit 134 performs a refresh operation.

[0086] like Figure 5 As shown, the count control circuit 230 indicates the 0XD0 address with the most access times (0XCA), and resets the access times of the 0XD0 address to the minimum access times among all row addresses after the refresh circuit 134 performs the refresh operation. The minimum access times among the four row addresses is 0X81, so the access times of the 0XD0 address are reset to 0X81.

[0087] It can be understood that after performing a refresh operation on the adjacent storage rows of the target storage row, the number of accesses corresponding to the target storage row is reset to the minimum number of accesses in order to avoid repeatedly specifying a storage row as the target storage row, which makes it impossible to refresh the adjacent storage rows of other storage rows with a larger number of accesses, and thus be adversely affected by the row hammering effect.

[0088] As described above, in the present disclosure, the counting circuit 220 performs three operations, namely, an increase operation, a replacement operation, and an additional refresh operation. The increase operation is that when the matching result is that the accessed row address is the same as the row address stored in one of the address registers, the count value of the counter corresponding to the address register is increased by 1. The replacement operation is that when the matching result is that the accessed row address and the row addresses stored in all address registers are different, the row address with the least number of accesses is replaced with the accessed row address, and the count value of the counter corresponding to the address register is increased by 1. The additional refresh operation is that when or after the refresh circuit 134 executes the row hammer refresh command RH REF, the number of accesses of the row address with the most accesses is reset to the minimum number of accesses among all row addresses.

[0089] Figure 6a and Figure 6b Another operation schematic diagram of the counting circuit provided in the embodiment of the present disclosure. Figure 6a The left side in the figure shows the current count values ​​of multiple counters of the counting circuit, and the right side shows the count values ​​of multiple counters after the row hammer refresh command RH REF is executed. Figure 6b The count values ​​of the plurality of counters at a certain time after the increment operation, the replacement operation, and the reset operation are performed multiple times are shown.

[0090] like Figure 6a As shown, the counting circuit includes 8 address registers and 8 counters. The row address in the address register corresponding to counter 4 is accessed the most times. Therefore, the row address in the address register corresponding to counter 4 is the row address of the target storage row. After executing the row hammer refresh command RH REF, the counting circuit performs an additional refresh operation to reset the count value of counter 4 to the minimum value of all count values. Therefore, the count values ​​of counter 4 and counter 2 are tied as the minimum values.

[0091] Continue to see Figure 6a and Figure 6b , the additional refresh operation resets the maximum count value to the minimum count value, so that the difference between the count values ​​of different counters is reduced. And as the activation command ACT continues to increase, the minimum count value also continues to increase, so that the count values ​​of all counters are in a high value state, which may eventually cause multiple counters to get stuck. One way to alleviate this problem is to increase the effective bits of each counter to increase the maximum count value of the counter, but this will take up more area, which is not conducive to the miniaturization of the memory, and will increase the power consumption of the memory.

[0092] Figure 7 A schematic diagram of another memory provided by an embodiment of the present disclosure, in some embodiments, such as Figure 7 As shown, the memory includes:

[0093] The row hammer control circuit 200 includes a plurality of counters 222, each counter 222 being used to count the number of times a storage row is accessed and generate a first count value;

[0094] The regulating circuit 300 is connected to the plurality of counters 222; the regulating circuit 300 is used to reset each counter 222 when the plurality of first count values ​​all reach the target threshold value, so as to adjust each first count value by the same offset value and generate a plurality of second count values;

[0095] The row hammer control circuit 200 is further configured to determine a target storage row according to a plurality of second count values.

[0096] In some embodiments, the target threshold value may be a specific value, such as 128. Multiple first count values ​​all reach the target threshold value, which means that each first count value is greater than or equal to the target threshold value. In other embodiments, the target threshold value may be a range, such as 160 to 191. Multiple first count values ​​all reach the target threshold value, which means that each first count value is within the range indicated by the target threshold value.

[0097] In the present disclosure, the row hammer control circuit 200 is used to reduce the impact of the row hammer effect on the adjacent storage rows of the target storage row. The row hammer control circuit 200 uses multiple counters 222 to count the number of times each accessed storage row is accessed to generate a first count value. Each storage row in the memory cell array may be an accessed storage row.

[0098] The present disclosure does not limit the specific implementation method of the row hammer control circuit 200 using multiple counters 222 to count the number of times a storage row is accessed. In some embodiments, the row hammer control circuit 200 may include the same number of entries and counters as the storage rows in the storage cell array to count the number of times each storage row in the storage cell array is accessed. In some other embodiments, in order to avoid malicious attacks by hackers, the counting circuit 220 in the row hammer control circuit 200 shown in any of the above embodiments of the present disclosure can also be used to count the number of times a storage row is accessed. That is, Figure 7 The multiple counters 222 shown may be the multiple counters 222 in the counting circuit 220 of any of the above-mentioned embodiments of the present disclosure.

[0099] In the above of the present disclosure, the row hammer control circuit 200 determines the target storage row according to the first count values ​​of the plurality of counters 222. For example, the row hammer control circuit 200 selects the storage row corresponding to the largest first count value among all the first count values ​​as the target storage row.

[0100] like Figure 6b As shown, as the activation commands continue to increase, the first count value of the counter continues to increase, so that the first count values ​​of all counters are in a high value state, which may cause multiple counters to get stuck. In this embodiment, a regulating circuit 300 connected to all counters 222 is set. The regulating circuit 300 is used to reset each counter 222 when all first count values ​​reach the target threshold, adjust each first count value to the same offset value, and generate multiple second count values. The row hammer control circuit 200 determines the target storage row according to the multiple second count values.

[0101] The target threshold value can be set according to actual needs, and the present disclosure does not limit the specific value of the target threshold value. By way of example, the target threshold value can be equal to one-half of the counting capacity of the counter. For example, if the counting capacity of an 8-bit binary counter is 256, then the target threshold value can be 128. By way of example, the target threshold value can also be equal to three-quarters of the counting capacity of the counter. For example, for an 8-bit binary counter, the target threshold value can also be 192. Also by way of example, the target threshold value can also be: greater than or equal to three-eighths of the counting capacity and less than seven-eighths of the counting capacity. For example, for an 8-bit binary counter, the target threshold value can also be 160 to 191.

[0102] Figure 8 The regulating circuit provided in the embodiment of the present disclosure is Figure 6b Schematic diagram of the first count values ​​of multiple counters before and after adjustment. For example, Figure 8 In , the target threshold is equal to half of the counting capacity of the counter. Figure 8 As shown, when the first count value of each counter reaches the target threshold, the adjustment circuit resets each counter, reduces each first count value by the same offset value, and updates the reduced first count value to the second count value.

[0103] The adjustment circuit 300 reduces all first count values ​​by the same offset value, which is equivalent to folding the bar graphs of all first count values ​​along the target threshold and hiding a section of the bar graph. Figure 8 As shown, after folding, all second count values ​​maintain the original size order. In other words, the size relationship between all second count values ​​is the same as the size relationship between all first count values. Therefore, selecting the storage row corresponding to the maximum second count value from all second count values ​​as the target storage row is the same as the target storage row determined by selecting the storage row corresponding to the maximum first count value from all first count values, that is, the target storage row determined according to multiple second count values ​​is the same as the target storage row determined according to multiple first count values. This shows that the adjustment circuit provided in this embodiment can adjust the first count values ​​of all counters to the same offset value, which will not only not affect the determination of the target storage row by the row hammer control circuit, but also increase the remaining counting space of the counter after adjustment, which is equivalent to a counter with infinite counting capacity. Even if the activation commands continue to increase, the probability of the counter being stuck is greatly reduced, and basically no stuck occurs. In addition, the adjustment circuit of this embodiment does not need to increase the effective bits of the counter, that is, it does not need to increase the number of triggers in the counter, which saves the occupied area of ​​the counter, is conducive to the miniaturization of the memory, and can reduce the power consumption of the memory.

[0104] It should be understood that the adjustment circuit 300 provided in this embodiment can be applied not only to the hammer control circuit 200, but also to other circuits including multiple counters, for increasing the remaining counting space of the counter without increasing the effective bits of the counter.

[0105] It should also be understood that the adjustment circuit 300 provided in this embodiment can be used not only to increase the remaining counting space of the adder counter, but also to increase the remaining counting space of the subtraction counter.

[0106] In some embodiments, when at least one first count value is less than a target threshold, the regulating circuit does not operate, thereby reducing the influence of the regulating circuit on the hammer control circuit.

[0107] In some embodiments, each counter 222 includes a plurality of triggers, each trigger corresponds to a valid bit of the first count value, and the output terminal level of the trigger is used to indicate the value of the valid bit.

[0108] When the value of the preset valid bit among the valid bits of multiple first count values ​​is the same, the adjustment circuit is used to reset the output level of the trigger corresponding to the preset valid bit to set the value of the preset valid bit to the preset value; wherein the first count value for resetting the preset valid bit is updated to the second count value.

[0109] Fig. 9 Schematic diagram of a counter provided in an embodiment of the present disclosure. The counter 222 is an asynchronous addition counter. Fig. 9 As shown, the counter 222 includes 8 flip-flops, namely DFF0, DFF1, DFF2, DFF3, DFF4, DFF5, DFF6 and DFF7. These 8 flip-flops constitute an 8-bit binary counter, and the output ends of the flip-flops DFF0, DFF1, DFF2, DFF3, DFF4, DFF5, DFF6 and DFF7 correspond to the valid bits Q of the count value respectively. 0 , Q 1 , Q 2 , Q 3 , Q 4 , Q 5 , Q 6 and Q 7 Among them, Q 7 is the most significant bit of the count value, Q 0 is the least significant bit of the count value. The count value of the binary counter 222 can be expressed as Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Q 0, for example 10001111.

[0110] The output level of the trigger is used to indicate the value of the valid bit. The output of the trigger can have a high level or a low level. In this embodiment and the following embodiments of the present disclosure, the output of the trigger is a high level to indicate that the value of the corresponding valid bit is 1, and the output of the trigger is a low level to indicate that the value of the corresponding valid bit is 0. In some other embodiments, the output of the trigger can be a high level to indicate that the value of the corresponding valid bit is 0, and the output of the trigger can be a high level to indicate that the value of the corresponding valid bit is 1.

[0111] The initial value of each valid bit can be 0 or 1. The present disclosure does not limit this. The following embodiments of the present disclosure take the initial value of the valid bit as 0 to illustrate the technical solution of the present disclosure.

[0112] The preset valid bit is specified from multiple valid bits of the count value. The preset valid bit may include one or more valid bits. However, the number of valid bits in the preset valid bit is less than the total number of valid bits in the first count value. The preset valid bit may include one or more of the most significant bit, the second most significant bit, the second most significant bit, etc. among the multiple valid bits. The number of valid bits included in the preset valid bit and the position of the included valid bits depend on the demand for the target threshold.

[0113] In some embodiments, the preset valid bit may be the most significant bit among the multiple valid bits of the first count value.

[0114] In some other embodiments, the preset valid bits may include: a plurality of valid bits arranged sequentially from the most significant bit to the least significant bit of the first count value; the number of valid bits in the preset valid bits is less than the number of valid bits in the first count value. By way of example, the preset valid bits may include the most significant bit and the second most significant bit. By way of example, the preset valid bits may include the most significant bit, the second most significant bit, and the second-most significant bit.

[0115] In some embodiments, when the preset valid bits include multiple valid bits, the so-called "the values ​​of the preset valid bits in the valid bits of multiple first count values ​​are the same" means that the values ​​of the valid bits in the same position in the preset valid bits of all first count values ​​are correspondingly equal. For example, the preset valid bits include the most significant bit and the second most significant bit, and the so-called "the values ​​of the preset valid bits in the valid bits of multiple first count values ​​are the same" means that the most significant bits of all first count values ​​are the same, and the second most significant bits of all first count values ​​are also the same. The most significant bit and the second most significant bit can be the same or different. In other words, when the values ​​of the preset valid bits of multiple first count values ​​are the same, the values ​​of the multiple valid bits in the preset valid bits can be different. For example, the value of the most significant bit can be 1, and the value of the second most significant bit can be 0.

[0116] It can be understood that the target threshold should be greater than the initial value. Therefore, when the values ​​of the preset valid bits of the multiple first count values ​​are the same, the value of the preset valid bit should also be different from the initial value of the preset valid bit. The so-called initial value of the preset valid bit means that the value of each valid bit in the preset valid bit is the initial value.

[0117] “The value of the preset valid bit is different from the initial value of the preset valid bit” may mean that the value of at least one valid bit among the multiple valid bits of the preset valid bit is different from the initial value. Of course, the values ​​of the multiple valid bits of the preset valid bit may all be different from the initial value.

[0118] The adjustment circuit sets the value of the preset valid bit to a preset value so that each first count value is adjusted by the same offset value. The preset value is less than the target threshold. Wherein, when the target threshold indicates a range, the preset value is less than the minimum value in the range. For example, the offset value is equal to the difference between the target threshold and the preset value.

[0119] In some embodiments, the preset value is an initial value of a preset valid bit. The initial value is the minimum preset value. At this time, the offset value is equal to the target threshold.

[0120] In some embodiments, the regulating circuit includes:

[0121] An adjusting unit, wherein the multiple input terminals of the adjusting unit are connected to the output terminals of the triggers corresponding to the preset valid bits in the multiple counters, and the output terminals of the adjusting unit are connected to the reset terminals or the set terminals of the triggers corresponding to the preset valid bits in the multiple counters;

[0122] When the values ​​of the preset valid bits of the plurality of first count values ​​are the same, the adjustment unit is used to send a control signal to a reset terminal or a set terminal of a trigger corresponding to the preset bit to set the value of the preset valid bit to a preset value.

[0123] In some embodiments, the reset terminal of the trigger is used to set the output terminal of the trigger to an initial level, such as a low level, indicating "0". The set terminal of the trigger is used to set the output terminal of the trigger to a non-initial level, such as a high level, indicating "1".

[0124] In some embodiments, the preset values ​​include "1" and "0", so the adjustment circuit can send a control signal to the reset terminal or the set terminal of multiple triggers corresponding to the preset valid bits to set the values ​​of the preset valid bits to the preset values.

[0125] In some embodiments, the preset value is an initial value of a preset valid bit; the adjustment unit is used to send a control signal to a reset terminal of a trigger corresponding to the preset bit to set the value of the preset valid bit to the initial value.

[0126] The multiple input terminals of the regulating circuit are connected to the output terminals of the preset triggers in the multiple counters, and the output terminals of the regulating circuit are connected to the reset terminals of the preset triggers in the multiple counters;

[0127] In some embodiments, the adjusting unit comprises:

[0128] An AND gate circuit, wherein the multiple input terminals of the AND gate circuit are respectively connected to the output terminals of the triggers corresponding to the preset valid bits in the multiple counters, and the output terminal of the AND gate circuit is connected to the reset terminals of the triggers corresponding to the preset valid bits in the multiple counters;

[0129] Among them, when the output terminal levels of the triggers corresponding to the preset valid bits in multiple counters are the same, and the output terminal level of the trigger corresponding to each valid bit in the preset valid bits is different from the initial level, a control signal is sent to the reset terminal of the trigger corresponding to the preset valid bit to set the output terminal of the trigger corresponding to the preset valid bit to the initial level, and the initial level indicates the initial value of the valid bit.

[0130] Here, taking the initial value of 0 as an example, "the output levels of the triggers corresponding to the preset valid bits in multiple counters are the same, and the output level of the trigger corresponding to each valid bit in the preset valid bits is different from the initial level" indicates that the value of each valid bit in the preset valid bits of multiple first count values ​​is 1.

[0131] The following is a detailed description in conjunction with Embodiments 1 and 2.

[0132] Embodiment 1: Fig.10 A schematic diagram of a hammer control circuit and a regulating circuit provided in an embodiment of the present disclosure. Fig.11 and Fig.12 They are Fig.10 The schematic diagram and bar chart of the regulating circuit before and after adjusting the count values ​​of multiple counters. Fig.10 The counter in can be Fig. 9 The counter shown. Fig.10 As shown, in this embodiment, the preset valid bit is the most significant bit of the first count value, and the most significant bit corresponds to the flip-flop DFF7. The initial value of the most significant bit is 0.

[0133] In this embodiment, the regulating circuit 300 includes a regulating unit 310, and the regulating unit 310 includes: an AND gate circuit 311, multiple input terminals of the AND gate circuit 311 are connected to the output terminals of all the flip-flops DFF7 corresponding to the most significant bits, and the output terminal of the AND gate circuit 311 is connected to the reset terminals of all the flip-flops DFF7. The AND gate circuit 311 is used to send a control signal to the reset terminal of the flip-flop DFF7 when the output terminals of all the flip-flops DFF7 are set to a high level (indicating that the value of the most significant bit is 1), so that the output terminals of all the flip-flops DFF7 are set to a low level (indicating that the value of the most significant bit is reset to 0).

[0134] Fig.11 Take 4 address registers and 4 counters as an example. Fig.11 As shown, the row addresses and access times stored in the four address registers and four counters in the current state are: the access times of the 0XA0 address is 0X8F (10001111), where the brackets are the binary data corresponding to the hexadecimal 0X8F; the access times of the 0XB0 address is 0X7F (01111111), the access times of the 0XC0 address is 0X8A (10001010); the access times of the 0XD0 address is 0X8B (10001011).

[0135] When the counting circuit receives the accessed address 0XB0 synchronized with the third active command ACT3, the access count of the address 0XB0 in the counting circuit increases by 1, and thus the access count increases from 0X7F to 0X80 (10000000).

[0136] When the number of times the address 0XB0 is accessed becomes 0X80 (10000000), the values ​​of the most significant bits of all counters change from the initial value 0 to 1. At this time, the adjustment circuit 300 resets the trigger DFF7 corresponding to the most significant bit, so that the values ​​of the most significant bits of all counters become 0.

[0137] Continue to see Fig.11 Before resetting the flip-flop DFF7, the four first count values ​​are ordered by size: 0X8F>0X8B>0X8A>0X80. The row address of the target storage row determined by the maximum count value among the four first count values ​​is 0XA0.

[0138] After resetting the trigger DFF7, the number of times the 0XA0 address, 0XB0 address, 0XC0 address, and 0XD0 address are accessed is 0X0F (00001111), 0X00 (00000000), 0X0A (00001010), and 0X0B (00001011). The four second count values ​​are sorted by size: 0X0F>0X0B>0X0A>0X00, among which the 0XA0 address is the address with the most access times, so the storage row corresponding to the 0XA0 address is the target storage row. It can be seen that after resetting the counters, the size relationship of the count values ​​of all counters does not change, so the determined target storage row does not change.

[0139] Fig.12 Take 8 address registers and 8 counters as an example. The 8 address registers and 8 counters may include Fig.11The four address registers and four counters shown in FIG. 4 are 8-bit binary counters with a counting capacity of 256 decimal. The most significant bit of the first count value is 1, indicating that the first count value is equal to or greater than 10000000, so it can be understood that the target threshold is 10000000 (corresponding to hexadecimal 0X80 and binary 128). The target threshold is half of the counting capacity of the counter.

[0140] The adjustment circuit 300 sets the most significant bit of each first count value to 0, which is equivalent to reducing each first count value by 10,000,000. Fig.12 As described above, reducing each first count value by 10000000 is equivalent to folding the bar graph of the first count value along the target threshold value Th to hide a section of the bar graph, and the size relationship between the multiple second count values ​​obtained remains unchanged from the size relationship between the multiple first count values. Therefore, the adjustment of the counter by the adjustment circuit will not affect the determination of the target storage row.

[0141] In this embodiment, the preset value of the most significant bit is an initial value, and thus the preset value is 0. The offset value is equal to the target threshold value, which is 100000000.

[0142] Embodiment 2: Fig.13 A schematic diagram of another hammer control circuit and regulation circuit provided in an embodiment of the present disclosure. Fig.14 and Fig.15 They are Fig.13 The schematic diagram and bar diagram of the adjustment circuit 300 before and after adjusting the count values ​​of the multiple counters 222. Fig.13 As shown, in this embodiment, the preset valid bits include the most significant bit and the second most significant bit of the first count value, which correspond to the trigger DFF7 and the trigger DFF6 respectively.

[0143] The adjustment unit 310 includes: an AND gate circuit 312, wherein multiple input terminals of the AND gate circuit 312 are respectively connected to the triggers DFF7 corresponding to all the most significant bits and the triggers DFF6 corresponding to the second most significant bits, and the output terminal of the AND gate circuit 312 is connected to the reset terminals of all preset triggers DFF7 and DFF6.

[0144] The AND gate circuit 312 is used to send a control signal to the reset terminal of each preset trigger DFF7 and DFF6 when the output terminals of all preset triggers DFF7 and DFF6 are at a high level (indicating that the values ​​of the most significant bit and the second most significant bit are both 1), so that the output terminal of each preset trigger DFF7 and DFF6 is reset to a low level, indicating that the values ​​of the most significant bit and the second most significant bit are both 0, that is, the initial value of the preset valid bit is 00, and multiple second count values ​​are obtained.

[0145] In some embodiments, the AND gate circuit 312 may include an AND gate. In other embodiments, the AND gate circuit 311 may include a NAND gate and a NOT gate connected in series. The circuit of the NAND gate is simpler than that of the AND gate and occupies less area. Therefore, the AND gate circuit 312 composed of the NAND gate and the NOT gate occupies less layout area.

[0146] Fig.14 Take 4 address registers and 4 counters as an example. Fig.14 As shown, the row addresses and access times stored in the four address registers and four counters in the current state are: the access times of the address 0XA0 is 0XDF (11011111), the access times of the address 0XB0 is 0XCA (11001010), the access times of the address 0XC0 is 0XBF (10111111); the access times of the address 0XD0 is 0XFB (11111011).

[0147] When the counting circuit receives the accessed address 0XC0 synchronized with the fourth active command ACT4, the access count of the address 0XC0 in the counting circuit increases by 1, and thus the access count increases from 0XBF to 0XC0 (11000000).

[0148] When the number of times the address 0XC0 is accessed becomes 0XC0 (11000000), the values ​​of the most significant bit and the second most significant bit of all counters change from the initial value 0 to 1. At this time, the adjustment circuit resets the triggers DFF7 and DFF6 corresponding to the most significant bit and the second most significant bit, so that the values ​​of the most significant bit and the second most significant bit of all counters become 0.

[0149] like Fig.14 As shown, before resetting the flip-flops DFF7 and DFF6, the four first count values ​​are ordered by size: 0XFB>0XDF>0XCA>0XC0. The row address of the target storage row determined by the maximum count value among the four first count values ​​is 0XD0.

[0150] After resetting triggers DFF7 and DFF6, the number of accesses to the 0XA0 address, 0XB0 address, 0XC0 address, and 0XD0 address are 0X1F (00011111), 0X0A (00001010), 0X00 (00000000), and 0X3B (00111011), respectively. The order of the four second count values ​​is: 0X3B>0X1F>0X0A>0X00, among which the 0XD0 address is the address with the most accesses, so the storage row corresponding to the 0XD0 address is the target storage row. It can be seen that after resetting the counters, the size relationship of the count values ​​of all counters does not change, so the determined target storage row does not change.

[0151] Fig.15 Take 8 address registers and 8 counters as an example. The 8 address registers and 8 counters may include Fig.14 The four address registers and four counters shown in FIG. 4 are 8-bit binary counters with a counting capacity of 256 in decimal. The most significant bit and the second most significant bit of the first count value are 1, indicating that the first count value is equal to or greater than 11000000. It can be understood that the target threshold is 11000000 (corresponding to hexadecimal 0XC0 and binary 192). The target threshold is three quarters of the counting capacity of the counter.

[0152] The adjustment circuit 300 resets the most significant bit and the second most significant bit of each first count value to 0, which is equivalent to reducing each first count value by 11000000. Fig.15 As described above, reducing each first count value by 11000000 is equivalent to folding the bar graph of the first count values ​​along the target threshold value Th to hide a section of the bar graph. The size relationship between the multiple second count values ​​obtained remains unchanged from the size relationship between the multiple first count values. Therefore, the adjustment of the counter by the adjustment circuit will not affect the determination of the target storage row.

[0153] In this embodiment, the preset value of the most significant bit is an initial value, and thus the preset value is 0. The offset value is equal to the target threshold value, which is 110000000.

[0154] In some embodiments, the preset valid bits include first-type valid bits and second-type valid bits; and the adjustment unit includes:

[0155] A plurality of NOT gate circuits, wherein input ends of the plurality of NOT gate circuits are connected to output ends of triggers corresponding to first-type valid bits in a plurality of counters;

[0156] An AND gate circuit comprises a plurality of first input terminals and a plurality of second input terminals, wherein the first input terminals are connected to the output terminals of the NOT gate circuit, the plurality of second input terminals are connected to the output terminals of the triggers corresponding to the second type of valid bits in the plurality of counters, and the output terminals of the AND gate circuit are connected to the reset terminals of the triggers corresponding to the second type of valid bits in the plurality of counters;

[0157] Among them, when the output terminal level of the trigger corresponding to the first type of valid bit in multiple counters is equal to the initial level, and the output terminal level of the trigger corresponding to the second type of valid bit is the same and different from the initial level, the adjustment unit is used to send a control signal to the reset terminal of the trigger corresponding to the second type of valid bit so that the output terminal level of the trigger corresponding to the second type of valid bit is set to the initial level.

[0158] It should be understood that the output end of the AND gate circuit can also be connected to the reset end of the flip-flop corresponding to the first type of valid bit, so that the output end of the flip-flop corresponding to the first type of valid bit also performs a reset operation. Although the input end level of the flip-flop before and after reset is the initial level, the reset operation can also be performed.

[0159] The following is an analysis in conjunction with Example 3. Fig.16 A schematic diagram of another hammer control circuit and regulation circuit provided in an embodiment of the present disclosure. Fig.17 and Fig.18 They are Fig.16 The schematic diagram and bar diagram of the regulating circuit before and after adjusting the count values ​​of multiple counters. Fig.16 As shown, in this embodiment, the preset valid bits include the most significant bit, the second most significant bit and the second most significant bit of the first count value, which correspond to the trigger DFF7, the trigger DFF6 and the trigger DFF5 respectively. Among them, the second most significant bit is the first type of valid bit, and the most significant bit and the second most significant bit are the second type of valid bits.

[0160] The adjustment unit 310 includes a plurality of NOT gate circuits 314 and AND gate circuits 313, wherein the input end of each NOT gate circuit 314 is connected to the output end of a flip-flop DFF6 corresponding to the second most significant bit in a counter;

[0161] Multiple first input terminals of the AND gate circuit 313 are connected to the output terminals of the multiple NOT gate circuits 314, and multiple second input terminals of the AND gate circuit 313 are connected to the flip-flop DFF7 corresponding to the most significant bit and the flip-flop DFF5 corresponding to the second most significant bit in all the counters;

[0162] The adjustment unit 310 is used to send a control signal to the reset end of each preset trigger DFF7 and DFF5 when the output end of all triggers DFF6 is at a low level (indicating that the value of the second most significant bit is 0) and the output end of all triggers DFF7 and DFF5 is at a high level (indicating that the values ​​of the most significant bit and the second most significant bit are both 1), so that the output end of each preset trigger DFF7 and DFF5 is reset to a low level (indicating that the values ​​of the most significant bit and the second most significant bit are both 0). In this way, the output ends of all triggers DFF7, DFF6 and DFF5 are at a low level, indicating that the value of the preset valid bit is the initial value 000, and multiple second count values ​​are obtained.

[0163] In this embodiment, the control signal acting on the reset terminal is a reset signal, and the reset signal includes a valid pulse, and the valid pulse has a high level. That is, the reset signal is valid at a high level. When the reset terminal of the trigger receives a high level, the trigger is reset to set the output terminal to a low level state.

[0164] The logic of the AND gate circuit 313 is that when all input terminals are at high level at the same time, the output terminal is set to high level. Therefore, the output terminal level of the flip-flop DFF6 needs to be inverted by the NOT gate circuit before being input to the AND gate circuit.

[0165] In some embodiments, each NOT gate circuit 314 may include an odd number of NOT gates (eg, inverters), such as 1, 3, or 5.

[0166] In some embodiments, Fig.16 As shown, the AND gate circuit 313 may include a plurality of AND gates 3131 , 3132 , 3133 , and 3134 , and the plurality of AND gates 3131 , 3132 , 3133 , and 3134 may form a multi-stage sub-circuit. Fig.16 In the embodiment, AND gates 3131, 3132, and 3133 constitute a first-level subcircuit, and AND gate 3134 constitutes a second-level subcircuit. The multiple input terminals of AND gate 3132 include multiple first input terminals of AND gate circuit 313, the multiple input terminals of AND gates 3131 and 3132 include multiple second input terminals of AND gate circuit 313, the input terminal of AND gate 3134 is connected to the output terminals of AND gates 3131, 3132, and 3133, and the output terminal of AND gate 3134 is the output terminal of AND gate circuit 313.

[0167] Fig.17 Take 4 address registers and 4 counters as an example. Fig.17 As shown, the row addresses and access times stored in the four address registers and four counters in the current state are: the access times of the address 0XA0 is 0XA7 (10100111), the access times of the address 0XB0 is 0X9F (10011111), the access times of the address 0XC0 is 0XBF (10111111); the access times of the address 0XD0 is 0XBB (10111011).

[0168] When the counting circuit receives the accessed address 0XB0 synchronized with the fifth active command ACT5, the access count of the address 0XB0 in the counting circuit increases by 1, and thus the access count increases from 0X9F to 0XA0 (10100000).

[0169] When the number of accesses to address 0XB0 becomes 0XA0 (10100000), the values ​​of the most significant bit, the second most significant bit, and the second most significant bit of all counters are the same, and are displayed as 101. At this time, the adjustment circuit resets the flip-flops DFF7 and DFF5 corresponding to the most significant bit and the second most significant bit, so that the values ​​of the most significant bit, the second most significant bit, and the second most significant bit of all counters become 0.

[0170] like Fig.17As shown, before resetting the flip-flops DFF7 and DFF5, the four first count values ​​are ordered by size: 0XBF>0XBB>0XA7>0XA0. The row address of the target storage row determined by the maximum count value among the four first count values ​​is 0XC0.

[0171] After resetting the triggers DFF7 and DFF5, the number of accesses to the 0XA0 address, 0XB0 address, 0XC0 address, and 0XD0 address is 0X07 (00000111), 0X00 (00000000), 0X1F (00011111), and 0X1B (00011011). The four second count values ​​are sorted by size: 0X1F>0X1B>0X0A>0X00, among which the 0XB0 address is the address with the most accesses, so the storage row corresponding to the 0XB0 address is the target storage row. It can be seen that after resetting the counters, the size relationship of the count values ​​of all counters does not change, so the determined target storage row does not change.

[0172] Fig.18 Take 8 address registers and 8 counters as an example. The 8 address registers and 8 counters may include Fig.17 The four address registers and four counters shown in FIG. 4 are 8-bit binary counters with a counting capacity of 256 in decimal. The most significant bit, the second most significant bit, and the second most significant bit of the first count value are 1, 0, and 1, respectively, indicating that the first count value should be equal to or greater than 10100000 (corresponding to 160 in decimal) and less than 11000000 (corresponding to 192 in decimal). Then, the target threshold is greater than or equal to three-eighths of the counting capacity of the counter and less than seven-eighths of the counting capacity.

[0173] The adjustment circuit 300 sets the most significant bit and the second most significant bit corresponding to the flip-flops DFF7 and DFF5 to 0, which is equivalent to reducing each first count value by 10100000. Fig.18 As described above, reducing each first count value by 10100000 is equivalent to folding the bar graph of the first count value along the target threshold value Th to hide a section of the bar graph, and the size relationship between the multiple second count values ​​obtained remains unchanged from the size relationship between the multiple first count values. Therefore, the adjustment of the counter by the adjustment circuit will not affect the determination of the target storage row.

[0174] Fig.19 A schematic diagram of another hammer control circuit and regulation circuit provided in an embodiment of the present disclosure. Fig. 20 and Fig.21 They are Fig.19The schematic diagram and bar diagram of the regulating circuit before and after adjusting the count values ​​of multiple counters. In this embodiment, the preset valid bits include the most significant bit, the second most significant bit and the second most significant bit of the first count value, which correspond to the trigger DFF7, the trigger DFF6 and the trigger DFF5 respectively. Among them, the second most significant bit is the first type of valid bit, and the most significant bit and the second most significant bit are the second type of valid bits.

[0175] and Fig.16 The same is that the input terminals of the multiple NOT gate circuits 314 are connected to the output terminals of the trigger DFF6 corresponding to the second most significant bit in all counters; the multiple first input terminals of the AND gate circuit 313 are connected to the output terminals of the multiple NOT gate circuits 314, and the multiple second input terminals of the AND gate circuit 313 are connected to the trigger DFF7 corresponding to the most significant bit and the trigger DFF5 corresponding to the second most significant bit in all counters; the output terminal of the AND gate circuit 313 is connected to the reset terminals of all triggers DFF7 and DFF5;

[0176] Different from Fig.16 In this embodiment, the output end of the AND gate circuit 313 is also connected to the set end of all the flip-flops DFF6;

[0177] The adjustment unit 310 is used to send a control signal to the reset terminal of each preset trigger DFF7 and DFF5 and the set terminal of the trigger DFF6 when the output terminal of all triggers DFF6 is at a low level (indicating that the value of the second most significant bit is 0) and the output terminal of all triggers DFF7 and DFF5 is at a high level (indicating that the values ​​of the most significant bit and the second most significant bit are both 1), so that the output terminal of each preset trigger DFF7 and DFF5 is reset to a low level (indicating that the values ​​of the most significant bit and the second most significant bit are both 0), and the output terminal of each preset trigger DFF6 is reset to a high level (indicating that the value of the second most significant bit is 1), indicating that the preset values ​​of the preset valid bits are 0, 1, 0, and multiple second counting values ​​are obtained.

[0178] In this embodiment, the control signal acting on the set terminal is a set signal, and the set signal includes a valid pulse, and the valid pulse has a high level. That is, the set signal is valid at a high level. When the set terminal of the trigger receives a high level, the trigger is set so that the output terminal is set to a high level state.

[0179] Fig. 20 Take 4 address registers and 4 counters as an example. The current status of the 4 address registers and 4 counters is the same as the status after receiving the fifth activation command ACT5. Fig.17 , so it is not traceable.

[0180] When the number of accesses to the address 0XB0 becomes 0XA0 (10100000), the values ​​of the most significant bit, the second most significant bit, and the second most significant bit of all counters are the same, and the values ​​of the preset significant bits are 1, 0, and 1. At this time, the adjustment unit 310 resets the flip-flops DFF7, DFF6, and DFF5, so that the values ​​of the most significant bit, the second most significant bit, and the second most significant bit of all counters become 0, 1, and 0, respectively.

[0181] After resetting the triggers DFF7, DFF6, and DFF5, the number of times the 0XA0 address, 0XB0 address, 0XC0 address, and 0XD0 address are accessed is 0X47 (01000111), 0X40 (01000000), 0X5F (01011111), and 0X5B (01011011). The four second count values ​​are sorted by size: 0X5F>0X5B>0X4A>0X40, among which the 0XB0 address is the address with the most access times, so the storage row corresponding to the 0XB0 address is the target storage row. It can be seen that after resetting the counters, the size relationship of the count values ​​of all counters does not change, so the determined target storage row does not change.

[0182] Fig.21 Taking 8 address registers and 8 counters as an example, the adjustment unit 310 changes the values ​​of the most significant bit, the second most significant bit and the second most significant bit to 0, 1 and 0 respectively, which is equivalent to the offset value of each first count value being the difference between 10100000 (corresponding to decimal 160) and 01000000 (corresponding to decimal 64), which is 96 in decimal. Fig.21 The dotted box on each counter represents the size of the offset value. All first count values ​​are adjusted by the same offset value (such as the offset value is 96). The size relationship between the multiple second count values ​​obtained remains the same as the size relationship between the multiple first count values. Therefore, the adjustment of the counter by the adjustment circuit will not affect the determination of the target storage row.

[0183] It should be understood that in some other embodiments, the target threshold value may also be seven eighths of the counting capacity of the counter, and taking the counting capacity as 256 as an example, the target threshold value may be 224. Correspondingly, the preset valid bits are the highest bit, the second highest bit, and the second second highest bit, and when the value of each valid bit in the preset valid bits is 1, the value of each valid bit in the preset valid bits is set to 0.

[0184] In some embodiments, Fig.10 , Fig.13 , Fig.16 and Fig.19 As shown, the regulating circuit 300 also includes:

[0185] The delay unit 320 has one end connected to the output end of the adjustment unit 310, and the other end connected to the reset end or the set end of the trigger corresponding to the preset valid bit in the plurality of counters 222; the delay unit 320 is used to extend the pulse width of the effective pulse of the control signal. In other words, the delay unit is used to extend the time length that the output end of the AND gate circuits 311, 312 and 313 is set to a high level.

[0186] like Fig.10 As shown, due to the large number of preset triggers, the line lengths from the output of the AND gate circuit 311 to the reset end of the trigger corresponding to each preset valid bit are not exactly the same, and the trigger with a short line may be reset first and its output end may be set to a low level. At this time, the input ends of the AND gate circuit 311 will not all be high levels, causing the output end of the AND gate circuit 311 to switch to a low level, thereby causing the trigger with a long line to be unable to be reset, and its output end cannot be reset to a low level.

[0187] Therefore, in this embodiment, after the delay unit 320 is set at the output end of the AND gate circuit 311, when the trigger with a short line is reset, causing the output end of the AND gate circuit 311 to switch to a low level, the delay unit 320 can delay the time for the low level to reach the reset end of other triggers, thereby extending the maintenance time of the high level at the output end of the AND gate circuit 311, that is, extending the pulse width of the effective pulse of the reset signal, thereby resetting all triggers.

[0188] From another perspective, the delay unit 320 delays the time for the signal at the output end of the AND gate circuit 311 to reach the reset end of the trigger, thereby delaying the time for the output end of the AND gate circuit 311 to switch from a high level to a low level, that is, extending the time for the AND gate circuit 311 to be set to a high level.

[0189] In some embodiments, Fig. 22 As shown, the delay unit 320 may include an even number of NOT gates 321 connected in series. For example, 2 NOT gates, 4 NOT gates, 6 NOT gates, etc. The number of NOT gates included in the delay unit 320 depends on the required time length for the output end of the AND gate circuit 311 to be set to a high level. Therefore, it can be adjusted according to actual needs.

[0190] Fig.23 FIG. 1 is a schematic diagram of another regulating circuit provided by an embodiment of the present disclosure. Fig.23 As shown, the regulating unit includes an AND gate circuit 315, and the AND gate circuit 315 may include multiple stages of sub-circuits 301, 302, and each stage of sub-circuits 301, 302 includes one or more AND gate logic units (such as 3151);

[0191] Among them, the input ends of the multiple AND gate logic units in the first-level sub-circuit 301 are connected to the output ends of the triggers DFF7 and DFF6 corresponding to the preset valid bits in the multiple counters 222, the input ends of the AND gate logic units in the next-level sub-circuit are connected to the output ends of the AND gate logic units in the previous-level sub-circuit, and the output ends of the AND gate logic units in the last-level sub-circuit 302 are connected to the reset ends of the triggers DFF7 and DFF6 corresponding to the preset valid bits in the multiple counters 222.

[0192] For example, the regulating circuit 300 further includes a delay unit 320 , which is located between the output end of the last-stage sub-circuit 302 and the reset ends of the flip-flops DFF7 and DFF6 corresponding to the preset valid bits of the plurality of counters 222 .

[0193] In some embodiments, in the first stage sub-circuit 301, the preset valid bits corresponding to the triggers connected to the input terminals of each AND gate logic unit 3151 are the same. Fig.23 As shown, the first-stage sub-circuit 301 includes a first AND gate logic unit 3151 and a second AND gate logic unit 3152. The first AND gate logic unit 3151 is connected to the output end of the trigger DFF7, and the second AND gate logic unit 3152 is connected to the output end of the trigger DFF6.

[0194] It should be understood that in other embodiments, the preset valid bits corresponding to the triggers connected to the input terminals of each AND gate logic unit may also be different. The input terminals of each AND gate logic unit may be connected to the triggers corresponding to all preset valid bits of several counters 222 nearby.

[0195] In some embodiments, each AND gate logic unit (such as 3151) may include four input terminals.

[0196] In some embodiments, each AND gate logic unit (such as 3151) may include a NAND gate and a NOT gate connected in series.

[0197] As shown above, the disclosed embodiment adds a regulating circuit for the counter in the row hammer control circuit. The regulating circuit is composed of only a simple AND gate and NOT gate, or a NAND gate and a NOT gate. Although the circuit is simple, it is powerful and can fold the count values ​​of all counters, thereby increasing the counting space of the counters without increasing the effective bits of the counters, and can avoid the problem of the count values ​​of the counters being stuck at a high level. And after the regulating circuit folds the count values ​​of all counters, it will not affect the size relationship between these count values, so it will not affect the row hammer control circuit to determine the target storage row, and therefore will not affect the row hammer control circuit to weaken the row hammer effect on the storage cell array. In addition, the addition of the regulating circuit does not affect the row hammer control circuit itself, other circuits in the memory, and circuits such as the memory controller. Therefore, this improvement has a short verification cycle and low cost.

[0198] Fig.24 A schematic diagram of another hammer control circuit and regulating circuit provided in an embodiment of the present disclosure; Fig.25 for Fig.24 A schematic diagram of the method of operation of the circuit shown is shown. Fig.24 and Fig.25 As shown, when the memory receives a command CMD from the memory controller, it determines whether the command CMD is an activation command ACT?

[0199] If the command CMD is the active command ACT, the command decoder 1321 transmits the accessed row address information included in the row address information synchronized with the active command ACT to the counting circuit 220 .

[0200] After receiving the accessed row address, the counting circuit 220 matches the accessed row address with the row addresses stored in all address registers 221 to obtain a matching result.

[0201] When the matching result is that the accessed row address is the same as the row address stored in the first address register 221 , the count value of the counter 222 corresponding to the first address register 221 is increased by 1; that is, an increase operation is performed.

[0202] When the matching result is that the accessed row address is different from the row addresses stored in all address registers 221, the row address in the second address register 221 with the least number of accesses is replaced with the accessed row address, and the count value of the counter 222 corresponding to the second address register 221 is increased by 1; that is, the replacement operation is performed.

[0203] If the command CMD is not the activation command ACT, the command decoder 1321 continues to determine whether the command CMD is a refresh command REF. If it is a refresh command REF, it is provided to the row hammer control circuit 200, and the row hammer control circuit 200 further determines whether the refresh command is a row hammer refresh command RH REF. The determination method is as described above, so it is not repeated.

[0204] Continue to see Fig.24 and Fig.25 If it is a row hammer refresh command RH REF, the row hammer control circuit 200 indicates the target row address that has been accessed the most times, determines the row address to be refreshed based on the target row address, and transmits the row address to be refreshed to the refresh circuit 134; the storage row corresponding to the row address that has been accessed the most times is the target storage row, and the storage row corresponding to the row address to be refreshed is the victim row.

[0205] The refresh circuit 134 performs a refresh operation on the adjacent memory rows of the target memory row in response to the refresh command REF and the address of the row to be refreshed.

[0206] After the refresh circuit 134 completes the refresh operation on the row address to be refreshed, the counting circuit 220 resets the access count of the row address with the largest number of accesses to the minimum number of accesses in all address registers 221 , that is, performs an additional refresh operation.

[0207] The above-mentioned increase operation and replacement operation will increase a first count value. Therefore, after these two operations, the adjustment circuit 300 will determine whether the first count values ​​of all counters 222 are greater than or equal to the target threshold value, for example, the adjustment circuit 300 will determine whether the value of the most significant bit of all counters 222 is 1. When the first count values ​​of all counters 222 are greater than or equal to the target threshold value, for example, the value of the most significant bit of all counters 222 is 1, the adjustment circuit 300 resets the plurality of counters 222 to obtain a second count value. When the condition that the first count values ​​of all counters 222 are greater than or equal to the target threshold value is not met, the adjustment circuit 300 does not operate.

[0208] It should be understood that the regulation circuit 300 may regulate the multiple counters 222 after any of the two operations. No matter which operation the counting circuit 220 performs, the regulation circuit 300 will reset the counters to obtain a second count value as long as the condition is met.

[0209] pass Fig.24 and Fig.25It can be seen that the operation of the counter 222 by the adjustment circuit 300 does not affect the determination of the row address with the least number of accesses in the replacement operation and the determination of the row address with the most number of accesses in the additional refresh operation by the count control circuit 230. Therefore, the adjustment circuit 300 does not affect the operation process of the row hammer control circuit 200.

[0210] Continue to see Fig.24 and Fig.25 If the refresh command REF is not the row hammer refresh command RH REF, it is determined that the refresh command REF is a regular refresh command REF. The refresh circuit 134 performs a regular refresh operation according to the regular refresh command REF. For example, the refresh circuit 134 performs a refresh operation on the storage rows in a certain order.

[0211] The present disclosure also provides a method for operating a memory. Fig.26 The flowchart of a method for operating a memory provided by an embodiment of the present disclosure is shown in FIG. Fig.26 As shown, the operation method includes:

[0212] S100: using a plurality of counters to respectively count the number of accesses to a plurality of storage rows, and generating a plurality of first count values;

[0213] S200: When the plurality of first count values ​​all reach the target threshold, reset each counter to adjust each first count value by the same offset value to generate a plurality of second count values;

[0214] S300: Determine a target storage row based on a plurality of second count values, and perform a refresh operation on storage rows adjacent to the target storage row.

[0215] In some embodiments, each counter includes a plurality of triggers, each trigger corresponds to a valid bit of the first count value, and the output terminal level of the trigger is used to indicate the value of the valid bit; step S200 specifically includes:

[0216] When the value of the preset valid bit among the valid bits of multiple first count values ​​is the same, the output level of the trigger corresponding to the preset valid bit is reset to set the value of the preset valid bit to the preset value; wherein the first count value of the reset preset valid bit is updated to the second count value.

[0217] In some embodiments, the preset valid bits of each first count value may include one or more valid bits.

[0218] In some embodiments, the preset valid bit may be the most significant bit among the multiple valid bits of the first count value.

[0219] In some embodiments, the preset valid bits may include: a plurality of valid bits arranged sequentially from the most significant bit of the first count value to the least significant bit; the number of valid bits in the preset valid bits is less than the number of valid bits in the first count value. By way of example, the preset valid bits may include the most significant bit and the second most significant bit. By way of example, the preset valid bits may include the most significant bit, the second most significant bit, and the second most significant bit.

[0220] In some implementations, the memory includes an adjustment circuit, the adjustment circuit includes: an adjustment unit, multiple input terminals of the adjustment unit are connected to output terminals of triggers corresponding to preset valid bits in multiple counters, and the output terminal of the adjustment unit is connected to reset terminals or set terminals of triggers corresponding to preset valid bits in multiple counters; step S200 specifically includes:

[0221] When the values ​​of the preset valid bits of the plurality of first count values ​​are the same, a control signal is sent to a reset terminal or a set terminal of a trigger corresponding to the preset bit to set the value of the preset valid bit to a preset value.

[0222] In some embodiments, the initial value of each valid bit in the preset valid bits is 0; step S200 specifically includes:

[0223] When the value of each valid bit in the preset valid bits of multiple first count values ​​is 1, a control signal is sent to the reset end of each trigger corresponding to the preset valid bit to set the value of each valid bit in the preset valid bit to 0, so that the preset valid position is the initial value, and multiple second count values ​​are obtained.

[0224] In some embodiments, the output terminal of the trigger is at a high level to indicate that the value of the valid bit is 1, and the output terminal of the trigger is at a low level to indicate that the value of the valid bit is 0; the initial value of the valid bit is 0.

[0225] In some embodiments, the adjustment unit includes an AND gate circuit, multiple input terminals of the AND gate circuit are respectively connected to output terminals of triggers corresponding to preset valid bits in multiple counters, and the output terminal of the AND gate circuit is connected to reset terminals of triggers corresponding to preset valid bits in multiple counters; step S200 specifically includes:

[0226] When the output levels of the triggers corresponding to the preset valid bits in multiple counters are the same, and the output level of the trigger corresponding to each valid bit in the preset valid bits is different from the initial level, a control signal is sent to the reset end of the trigger corresponding to the preset valid bit to set the output end of the trigger corresponding to the preset valid bit to the initial level, and the initial level indicates an initial value.

[0227] In some embodiments, the preset valid bits include a first type of valid bits and a second type of valid bits; the adjustment unit includes: a NOT gate circuit and an AND gate circuit, wherein a plurality of input terminals of the NOT gate circuit are connected to output terminals of triggers corresponding to the first type of valid bits in a plurality of counters; the AND gate circuit includes a first input terminal and a plurality of second input terminals, the first input terminal is connected to the output terminal of the NOT gate circuit, the plurality of second input terminals are connected to output terminals of triggers corresponding to the second type of valid bits in a plurality of counters, and the output terminal of the AND gate circuit is connected to a reset terminal of the triggers corresponding to the second type of valid bits in a plurality of counters; step S200 specifically includes:

[0228] When the output terminal level of the trigger corresponding to the first type of valid bit in multiple counters is equal to the initial level, and the output terminal level of the trigger corresponding to the second type of valid bit is the same as and different from the initial level, a control signal is sent to the reset terminal of the trigger corresponding to the second type of valid bit to set the output terminal level of the trigger corresponding to the second type of valid bit to the initial level.

[0229] In some embodiments, the control signal includes a valid pulse; the memory further includes a delay unit, the delay unit is connected to the output end of the adjustment unit and the reset end or the set end of the trigger corresponding to the plurality of preset valid bits. Correspondingly, the operation method further includes:

[0230] Lengthen the pulse width of the effective pulse of the control signal.

[0231] In some embodiments, the control signal includes a reset signal and a set signal, and the effective pulses of the reset signal and the set signal have a high level, that is, the reset signal and the control signal are both effective at a high level, and the pulse width of the effective pulse of the control signal is extended, including:

[0232] The delay adjustment unit sets the output end to the high level time.

[0233] In the memory operation method provided by the embodiment of the present disclosure, when the first count values ​​of the multiple counters of the row hammer control circuit reach the target threshold value, the multiple counters are reset to adjust each first count value by the same offset value to obtain a second count value. The row hammer control circuit determines the target storage row according to the multiple second count values ​​and performs a refresh operation on the adjacent storage rows of the target storage row. This operation method will not affect the operation of the row hammer control circuit, and can increase the remaining count space of the counter after resetting the counter, avoiding the problem of the counter being stuck due to the count values ​​of the counters being all at a high level.

[0234] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: A row hammer control circuit, comprising a plurality of counters, each of which is used to count the number of times a storage row is accessed and generate a first count value; an adjusting circuit connected to the plurality of counters; the adjusting circuit is used for resetting each of the counters when the plurality of first count values ​​all reach a target threshold, adjusting each of the first count values ​​by the same offset value, and generating a plurality of second count values; The row hammer control circuit is further configured to determine a target storage row according to the plurality of second count values.

2. The memory according to claim 1, characterized in that: Each of the counters comprises a plurality of triggers, each of the triggers corresponds to a valid bit of the first count value, and the output terminal level of the trigger is used to indicate the value of the valid bit; When the value of a preset valid bit among the valid bits of multiple first count values ​​is the same, the adjustment circuit is used to reset the output level of the trigger corresponding to the preset valid bit to set the value of the preset valid bit to a preset value; wherein the first count value for resetting the preset valid bit is updated to the second count value.

3. The memory according to claim 2, characterized in that: The preset valid bits of each of the first count values ​​include one valid bit or a plurality of valid bits.

4. The memory according to claim 2, characterized in that: The preset valid bit is the most significant bit among the multiple valid bits of the first count value; or, The preset valid bits include: a plurality of valid bits arranged in sequence from the most significant bit to the least significant bit of the first count value; The number of valid bits in the preset valid bits is smaller than the number of valid bits in the first count value.

5. The memory according to claim 2, characterized in that: The regulating circuit comprises: An adjusting unit, wherein a plurality of input terminals of the adjusting unit are connected to output terminals of triggers corresponding to the preset valid bits in the plurality of counters, and an output terminal of the adjusting unit is connected to reset terminals or set terminals of triggers corresponding to the preset valid bits in the plurality of counters; When the values ​​of the preset valid bits of a plurality of the first count values ​​are the same, the adjustment unit is used to send a control signal to a reset end or a set end of a trigger corresponding to the preset valid bit to set the value of the preset valid bit to a preset value.

6. The memory according to claim 5, characterized in that: The preset value is the initial value of the preset valid bit; The adjusting unit is used to send a control signal to a reset terminal of a trigger corresponding to the preset valid bit, so as to set the value of the preset valid bit to the initial value.

7. The memory according to claim 6, characterized in that: The adjustment unit comprises: An AND gate circuit, wherein the multiple input ends of the AND gate circuit are respectively connected to the output ends of the triggers corresponding to the preset valid bits in the multiple counters, and the output end of the AND gate circuit is connected to the reset ends of the triggers corresponding to the preset valid bits in the multiple counters; Among them, when the output terminal levels of the triggers corresponding to the preset valid bits in multiple counters are the same, and the output terminal level of the trigger corresponding to each valid bit in the preset valid bits is different from the initial level, the adjustment unit sends a control signal to the reset terminal of the trigger corresponding to the preset valid bit to set the output terminal of the trigger corresponding to the preset valid bit to the initial level, and the initial level indicates the initial value.

8. The memory according to claim 6, characterized in that: The preset valid bits include first-type valid bits and second-type valid bits; the adjustment unit includes: A plurality of NOT gate circuits, wherein input ends of the plurality of NOT gate circuits are connected to output ends of triggers corresponding to the first type of valid bits in the plurality of counters; An AND gate circuit, comprising a plurality of first input terminals and a plurality of second input terminals, wherein the first input terminals are connected to the output terminals of the NOT gate circuit, the plurality of second input terminals are connected to the output terminals of the flip-flops corresponding to the second type of valid bits in the plurality of counters, and the output terminal of the AND gate circuit is connected to the reset terminals of the flip-flops corresponding to the second type of valid bits in the plurality of counters; Among them, when the output end level of the trigger corresponding to the first type of valid bit in the multiple counters is equal to the initial level, and the output end level of the trigger corresponding to the second type of valid bit is the same as and different from the initial level, the adjustment unit is used to send a control signal to the reset end of the trigger corresponding to the second type of valid bit so that the output end level of the trigger corresponding to the second type of valid bit is set to the initial level.

9. The memory according to claim 5, characterized in that: The control signal includes a valid pulse; the regulating circuit also includes: A delay unit, one end of which is connected to the output end of the regulating unit, and the other end is connected to the reset end or the set end of the trigger corresponding to the preset valid bit in the multiple counters; the delay unit is used to extend the pulse width of the valid pulse.

10. The memory according to claim 1, characterized in that: The row hammer control circuit is used for comparing the plurality of second count values, and taking the storage row corresponding to the maximum count value among the plurality of second count values ​​as the target storage row; The row hammer control circuit is further used to determine the adjacent storage row of the target storage row according to the target storage row; The memory further comprises: a refresh circuit connected to the row hammer control circuit, wherein the refresh circuit is used to perform a refresh operation on a storage row adjacent to the target storage row.

11. A memory system, characterized in that: include: The memory as claimed in any one of claims 1 to 10; as well as, The memory controller is connected to the memory and is used to control the memory.

12. A method for operating a memory, characterized in that: include: Using a plurality of counters to count the number of accesses to a plurality of storage rows respectively, to generate a plurality of first count values; When the plurality of first count values ​​all reach the target threshold, resetting each of the counters to adjust each of the first count values ​​by the same offset value to generate a plurality of second count values; A target memory row is determined based on the plurality of second count values, and a refresh operation is performed on memory rows adjacent to the target memory row.

13. The memory operation method according to claim 11, characterized in that: Each of the counters comprises a plurality of triggers, each of the triggers corresponds to a valid bit of the first count value, and the output terminal level of the trigger is used to indicate the value of the valid bit; When the plurality of first count values ​​all reach the target threshold, resetting each of the counters comprises: When the value of a preset valid bit among the valid bits of multiple first count values ​​is the same, the output level of the trigger corresponding to the preset valid bit is reset to set the value of the preset valid bit to a preset value; wherein the first count value of which the preset valid bit is reset is updated to the second count value.

14. The memory operation method according to claim 13, characterized in that: The preset valid bits of each of the first count values ​​include one valid bit or a plurality of valid bits.

15. The memory operation method according to claim 13, characterized in that: The preset valid bit is the most significant bit among the multiple valid bits of the first count value; or, The preset valid bits include: a plurality of valid bits arranged in sequence from the most significant bit to the least significant bit of the first count value; The number of valid bits in the preset valid bits is smaller than the number of valid bits in the first count value.

16. The memory operation method according to claim 13, characterized in that: The memory includes a regulating circuit, which includes: a regulating unit, wherein a plurality of input terminals of the regulating unit are connected to output terminals of triggers corresponding to the preset valid bits in a plurality of the counters, and an output terminal of the regulating unit is connected to reset terminals or set terminals of triggers corresponding to the preset valid bits in a plurality of the counters; When the values ​​of the preset valid bits among the valid bits of the plurality of first count values ​​are the same, resetting the output terminal level of the trigger corresponding to the preset valid bit to set the value of the preset valid bit to a preset value comprises: When the values ​​of the preset valid bits of the plurality of first count values ​​are the same, a control signal is sent to a reset terminal or a set terminal of a trigger corresponding to the preset bit to set the value of the preset valid bit to a preset value.

17. The memory operating method according to claim 16, characterized in that: The regulating circuit further comprises: a delay unit, one end of which is connected to the output end of the regulating unit, and the other end of which is connected to the reset end or the set end of the trigger corresponding to the preset valid bit in the plurality of counters; the control signal comprises a valid pulse; The operation method further includes: The pulse width of the effective pulse of the control signal is extended.

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