Method for manufacturing metal zero-layer cross-section layer
By using TiN material and multiple patterned etching processes to form a dielectric window in the manufacturing process of the metal zero-layer cutoff layer, and using the second dielectric layer to fill and etch, the problems of boron atom lateral diffusion and missing defects are solved, and the stable and controllable key dimensional control of the metal zero-layer cutoff layer is achieved.
Patent Information
- Application Number
- CN202411464808.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-03-04
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
In the existing manufacturing methods of metal zero-layer cutoff layers, the unexpected lateral diffusion of boron atoms makes it difficult to control the key dimensions, and the long-term process flow is prone to residual etching by-products, resulting in the occurrence of missing defects.
The first dielectric window is formed by using TiN as the material of the metal zero-layer cut-off layer through multiple patterning etching processes, and these windows are filled and extended with the second dielectric layer. The first dielectric layer is then removed, and the first TiN layer is etched using the second dielectric layer as a mask to form a stable metal zero-layer cut-off layer.
By avoiding lateral diffusion caused by boron injection, precise control of the critical dimensions of the metal zero-layer cutoff layer is achieved, preventing the occurrence of lost defects, and expanding the process window.
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Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a metal zero cut layer (cut of M0, M0C). Background Art
[0002] When forming M0C, the advanced process platform uses boron implantation (IMP) to perform ion implantation process on amorphous silicon (A-Si). Since the wet etch rate of A-Si without B implantation in ammonia water is fast, the A-Si is removed by utilizing the different selectivity in the solution, leaving the A-Si implanted by B to form M0C.
[0003] like Figures 1A to 1D FIG. 1 is a schematic diagram of the device structure in each step of the existing method for manufacturing a metal zero layer truncation layer; the method comprises the following steps:
[0004] like Figure 1A As shown, an amorphous silicon layer 102 is formed on the underlying structure 101 .
[0005] Then, multiple masks are used for exposure to define the boron ion implantation area. The following is an exposure corresponding to one mask for illustration:
[0006] like Figure 1A As shown, three photoresist material layers 103 are formed in sequence, and the three photoresist material layers 103 include: a carbon coating (SOC) layer 103a, a silicon-based anti-reflective layer (Si-ARC) 103b and a photoresist 103c.
[0007] A photolithography process is performed to pattern the photoresist 103c.
[0008] like Figure 1B As shown, etching is performed to transfer the photoresist 103c pattern to the silicon-based anti-reflection layer 103b and the carbon coating 103a in sequence. Generally, the photoresist 103c is consumed during the downward transfer of the pattern.
[0009] like Figure 1C As shown, boron implantation as indicated by arrow line 104 is performed, and the boron implantation will implant boron into the amorphous silicon layer 102 in the opening area. Figure 1C In the figure, the amorphous silicon layer into which the boron impurities are implanted is represented by a single reference numeral 102a.
[0010] like Figure 1D As shown, the remaining three photoresist material layers 103 are then removed.
[0011] Afterwards, you can repeat Figures 1A to 1D The corresponding process forms more required amorphous silicon layers 102 a implanted with boron impurities.
[0012] Then, etching is performed in aqueous ammonia to form an MOC composed of the remaining amorphous silicon layer 102 a implanted with boron impurities.
[0013] However, due to the relatively small atomic mass of the boron atoms implanted by ions, there is strong unexpected lateral diffusion, which makes it difficult to control the critical dimension (CD) of the M0C. Figure 2A FIG. 1 is a schematic diagram of a device structure when the existing method for manufacturing a metal zero-layer cutoff layer generates lateral diffusion of boron; Figure 2A Part of the structure of the bottom structure 101 is also formed, including: a TiN layer 101a as a metal hard mask layer, an ALD OX layer 101b and a PEOX layer 101c. ALD OX represents an oxide layer (OX) formed by an ALD process, and PEOX represents an oxide layer formed by a PECVD process. Figure 2A The boron impurity is represented by reference numeral 105, and reference numeral 106 represents the boundary of the ion implantation region defined by Figure 2A It can be seen that the boron impurities 105 will diffuse laterally to the outside of the boundary 106, so that the CD of the MOC will increase.
[0014] At the same time, due to the limitation of the minimum step (Min Pitch) of lithography, the M0C process needs to be repeated four times. The long process flow is prone to residual etching by-products on the A-Si surface. The etching by-products contain F, which makes it easy for the etching by-products to combine with water vapor to form condensation (Condense) clusters and other defects (defects), which will block Boron IMP and eventually form a M0C missing (Missing) defect, causing great loss to product yield.
[0015] like Figure 2B As shown, it is a schematic diagram of the device structure when the existing method for manufacturing the metal zero layer cut-off layer produces a metal zero layer cut-off layer missing defect; Figure 1A-Figure 1D The steps will be repeated for many times, so the long process flow is likely to produce residual F-containing etching byproducts on the surface of the A-Si, i.e., amorphous silicon layer 102, and will combine with water vapor to form condensation group 107. The condensation group 107 will block Boron IMP, so that the bottom area of the condensation group 107 will have an area 102b where boron cannot be injected. In this way, the amorphous silicon layer in area 102b will be removed during the subsequent etching in ammonia water, which will cause a loss defect in MOC.
[0016] Therefore, in the existing methods, the unexpected lateral diffusion of boron atoms will make M0C CD difficult to control; the Condense caused by the waiting time (Q-Time) between process steps blocks Boron IMP, forming a M0C Missing defect. Summary of the invention
[0017] The technical problem to be solved by the present invention is to provide a method for manufacturing a metal zero layer cutoff layer, which can stabilize and control the critical dimension (CD) of the metal zero layer cutoff layer and prevent the occurrence of metal zero layer cutoff layer loss defects and thereby expand the process window.
[0018] In order to solve the above technical problems, the present invention provides a method for manufacturing a metal zero layer cutoff layer, comprising the following steps:
[0019] Step 1: forming a first TiN layer and a first dielectric layer in sequence on the top surface of the underlying structure.
[0020] Step 2: cyclically perform a plurality of patterning etching processes to form a pattern structure of the first dielectric layer through the plurality of patterning etching processes, wherein the pattern structure of the first dielectric layer includes a plurality of first dielectric windows where the first dielectric layer is removed.
[0021] Each of the patterning etching processes forms a portion of the first dielectric window, and the number of cycles of the patterning etching process includes opening all required first dielectric windows.
[0022] Step 3: forming a second dielectric layer to completely fill each of the first dielectric windows and extend to the surface outside the first dielectric window; the material of the second dielectric layer is different from that of the first dielectric layer.
[0023] Step 4: Perform chemical mechanical polishing or back etching to remove the second dielectric layer above the top surface of the first dielectric layer outside the first dielectric window, and the second dielectric layer is only retained in the first dielectric window, and the top surface of the retained second dielectric layer is flush with the top surface of the first dielectric layer.
[0024] Step five: removing the first dielectric layer.
[0025] Step six: using the second dielectric layer as a mask to etch the first TiN layer to form a first dielectric window, the first TiN layer outside the first dielectric window is removed, and the first TiN layer remaining in the first dielectric window area is used as a metal zero layer cutoff layer.
[0026] A further improvement is that step 1 further includes forming a dielectric cap layer (Cap) on the surface of the first dielectric layer; the material of the dielectric cap layer is different from the material of the first dielectric layer.
[0027] A further improvement is that the material of the dielectric cap layer is the same as the material of the second dielectric layer.
[0028] A further improvement is that the material of the first dielectric layer includes silicon nitride.
[0029] The material of the dielectric cap layer includes an oxide layer.
[0030] A further improvement is that each of the patterned etching processes comprises the following sub-steps:
[0031] Step 21 : forming three photoresist material layers in sequence, wherein the three photoresist material layers include: an organic dielectric layer (ODL), a silicon-based hard mask layer (SHB) and a photoresist.
[0032] Step 22: Perform a photolithography process to pattern the photoresist.
[0033] Step 23: Perform etching to transfer the photoresist pattern to the silicon-based hard mask layer and the organic dielectric layer in sequence.
[0034] Step 24: Perform etching to further transfer the pattern from the silicon-based hard mask layer to the dielectric cap layer and the first dielectric layer.
[0035] Step 25: then remove the three photoresist material layers.
[0036] A further improvement is that the material of the organic dielectric layer includes a carbon coating.
[0037] A further improvement is that the material of the silicon-based hard mask layer includes a silicon-based anti-reflection layer.
[0038] A further improvement is that the maximum number of cycles of the patterning etching process is more than 4 times.
[0039] A further improvement is that the underlying structure includes: a semiconductor substrate.
[0040] A semiconductor device is formed on the semiconductor substrate, and the semiconductor device includes: a gate structure formed on the semiconductor substrate, a source region and a drain region of the semiconductor device are formed in the semiconductor substrate on both sides of each gate structure, and a channel region is formed in the semiconductor substrate covered by the gate structure.
[0041] The gate structure is a metal gate.
[0042] The zeroth interlayer film is filled in the region between the metal gates, and a top surface of the zeroth interlayer film is flush with a top surface of the metal gates.
[0043] A first interlayer film is formed on a top surface of the zeroth interlayer film and a top surface of the metal gate.
[0044] A further improvement is that, in step five, a wet etching process is used to remove the first dielectric layer, and phosphoric acid is used as an etching solution in the wet etching process.
[0045] A further improvement is that in step 4, the chemical mechanical polishing or the etching back stops at the top surface of the first dielectric layer.
[0046] The present invention adopts TiN as the material of the metal zero layer cutoff layer. When patterning the first TiN layer, a first dielectric layer, a dielectric cap layer and a material layer of a photolithography process such as a stacked structure of three photolithography material layers are adopted. The pattern is transferred downward layer by layer to the first dielectric layer through an etching process. Then, the first dielectric window area is used as the formation area of the metal zero layer cutoff layer by forming a second dielectric layer to fill the first dielectric window and removing the first dielectric layer. The present invention avoids the need to use a process of implanting boron into amorphous silicon in the existing method by etching downward layer by layer, so that the lateral diffusion of the implanted boron can be prevented from having an adverse effect on the CD of the metal zero layer cutoff layer. Therefore, the present invention can achieve precise control of the CD of the metal zero layer cutoff layer.
[0047] In addition, in the existing method, the formation area of the metal zero layer cutoff layer is defined by the boron injection area. In the multiple cycles of the patterned boron injection process, there will be a situation where the local area of the formation area of the metal zero layer cutoff layer will block the boron injection, thus causing the defect of missing metal zero layer cutoff layer. However, each patterned etching process of the multiple patterned etching processes of the present invention will form a first dielectric window that completely removes the first dielectric layer. Since the first dielectric window is completely opened, the first TiN layer in the metal zero layer cutoff layer defined by the first dielectric window will be completely retained, so the defect of missing metal zero layer cutoff layer will not occur.
[0048] Therefore, the present invention can make the CD of the metal zero layer cut-off layer stable and controllable and can prevent the occurrence of metal zero layer cut-off layer loss defects and thus expand the process window. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0050] Figure 1A-Figure 1D It is a schematic diagram of the device structure in each step of the existing method for manufacturing the metal zero layer cutoff layer;
[0051] Figure 2A It is a schematic diagram of the device structure when the existing method for manufacturing the metal zero-layer cutoff layer produces lateral diffusion of boron;
[0052] Figure 2B It is a schematic diagram of the device structure when the existing method for manufacturing the metal zero layer cut-off layer produces a metal zero layer cut-off layer missing defect;
[0053] Figure 3 is a flow chart of a method for manufacturing a metal zero layer cutoff layer according to an embodiment of the present invention;
[0054] Figure 4A-4H It is a schematic diagram of the device structure in each step of the method for manufacturing the metal zero layer cutoff layer according to an embodiment of the present invention;
[0055] Figure 5 It is a schematic diagram of the underlying structure of a method for manufacturing a metal zero layer cutoff layer in some embodiments of the present invention. DETAILED DESCRIPTION
[0056] like Figure 3 As shown, it is a flow chart of a method for manufacturing a metal zero layer cutoff layer according to an embodiment of the present invention; FIG. 4A to FIG. 4G , which is a schematic diagram of the device structure in each step of the method for manufacturing the metal zero layer cutoff layer according to an embodiment of the present invention; Figure 5 , which is a schematic diagram of a bottom structure 201 of a method for manufacturing a metal zero layer truncation layer in some embodiments of the present invention. The method for manufacturing a metal zero layer truncation layer in an embodiment of the present invention comprises the following steps:
[0057] Step 1: Figure 4A As shown, a first TiN layer 202 and a first dielectric layer 203 are sequentially formed on the top surface of the underlying structure 201 .
[0058] In the embodiment of the present invention, a dielectric cap layer 204 is further formed on the surface of the first dielectric layer 203 ; the material of the dielectric cap layer 204 is different from that of the first dielectric layer 203 .
[0059] The material of the dielectric cap layer 204 is the same as the material of the subsequent second dielectric layer 207 .
[0060] In some preferred embodiments, the material of the first dielectric layer 203 includes silicon nitride.
[0061] The material of the dielectric capping layer 204 includes an oxide layer.
[0062] In some embodiments, Figure 5 As shown, the underlying structure 201 includes: a semiconductor substrate 301 .
[0063] A semiconductor device is formed on the semiconductor substrate 301, and the semiconductor device includes: a gate structure formed on the semiconductor substrate 301, a source region and a drain region of the semiconductor device are formed in the semiconductor substrate 301 on both sides of each gate structure, and a channel region is formed in the semiconductor substrate 301 covered by the gate structure. The gate structure is a metal gate.
[0064] Figure 5 Two semiconductor devices are shown in the figure, namely NMOS and PMOS.
[0065] Shallow trench isolation 302 is formed on the semiconductor substrate 301 .
[0066] In the NMOS formation region, a deep N well (DNW) 303 is formed on the semiconductor substrate 301, a P well (PW) 304 is formed in the deep N well 303, and a gate structure 306a includes a gate dielectric layer, an N-type metal work function layer (NWF) and a metal gate conductive material layer. An embedded SiP epitaxial layer 307 is formed in the source region and the drain region.
[0067] In the formation region of NMOS, a deep N well (DNW) 303 is formed on the semiconductor substrate 301, a P well (PW) 304 is formed in the deep N well 303, and a gate structure is indicated by a mark 306a, and the gate structure 306a includes a gate dielectric layer, an N-type metal work function layer (NWF) and a metal gate conductive material layer. An embedded SiP epitaxial layer 307 is formed in the formation region of the source region and the drain region.
[0068] In the formation region of PMOS, an N well (NW) 305 is formed in the semiconductor substrate 301, and the gate structure is indicated by a mark 306b, and the gate structure 306b includes a gate dielectric layer, a P-type metal work function layer (PWF) and a metal gate conductive material layer. An embedded SiGe epitaxial layer 308 is formed in the formation region of the source region and the drain region. Usually, an NWF is also superimposed on the top of the PWF.
[0069] The zeroth interlayer film 310 is filled in the region between the metal gates and the top surface of the zeroth interlayer film 310 is flush with the top surface of the metal gates. Figure 5 In the embodiment, the zeroth interlayer film 310 is an oxide layer formed by PECVD process, namely PEOX. In some embodiments, a contact etch stop layer (CESL) 309 is also included, and the material of the contact etch stop layer 309 includes silicon nitride.
[0070] The first interlayer film is formed on the top surface of the zeroth interlayer film 310 and the top surface of the metal gate. Figure 5 In the embodiment, the first interlayer film includes a silicon nitride layer 311, a PEOX layer 312, a TiN layer 313 as a metal hard mask layer, an ALD OX layer 314 and a PEOX layer 315. ALD OX represents an oxide layer formed by an ALD process.
[0071] Step 2: Repeat the patterning etching process multiple times to form a pattern structure of the first dielectric layer 203 through the patterning etching process multiple times. The pattern structure of the first dielectric layer 203 includes a plurality of first dielectric windows where the first dielectric layer 203 is removed. Figure 4D As shown, two first media windows are shown, respectively indicated by reference numerals 206a and 206b.
[0072] Each patterning etching process forms a portion of the first dielectric window respectively, and the number of cycles of the patterning etching process includes opening all required first dielectric windows. Figure 4D In the embodiment, the first dielectric windows 206a and 206b are formed by different patterning etching processes. Since one photolithography process cannot achieve the definition and transfer of all the first dielectric windows, multiple photomasks are required to achieve this.
[0073] In the embodiment of the present invention, FIG. 4A to FIG. 4C A schematic diagram of the device structure showing each step of a patterning etching process, each patterning etching process includes the following sub-steps:
[0074] Step 21: Figure 4A As shown, three photoresist material layers 205 are formed in sequence, and the three photoresist material layers 205 include: an organic dielectric layer 205a, a silicon-based hard mask layer 205b and a photoresist 205c.
[0075] In some implementations, the material of the organic dielectric layer 205a includes a carbon coating.
[0076] The material of the silicon-based hard mask layer 205 b includes a silicon-based anti-reflection layer.
[0077] Step 22: Figure 4A As shown, a photolithography process is performed to pattern the photoresist 205c.
[0078] Step 23: Figure 4B As shown, etching is performed to transfer the photoresist 205c pattern to the silicon-based hard mask layer 205b and the organic dielectric layer 205a in sequence. In some embodiments, the photoresist 205c is consumed during the pattern transfer process.
[0079] Step 24: Figure 4B As shown, etching is performed to further transfer the pattern from the silicon-based hard mask layer 205b to the dielectric cap layer 204 and the first dielectric layer 203. In some embodiments, the silicon-based hard mask layer 205b will be consumed during the downward transfer of the pattern; the thickness of the organic dielectric layer 205a will also be reduced. In FIG4b, the pattern transferred to the first dielectric layer 203 is the first dielectric window 206a.
[0080] Step 25: Figure 4C As shown, the three photoresist material layers 205 are then removed.
[0081] In some embodiments, the maximum number of cycles of the patterning etching process is more than 4 times. Figure 4DAs shown, the first dielectric window 206b can be obtained by repeating steps 21 to 25. Each cycle of the pattern etching process can obtain a portion of the first dielectric window, and after all the cycles of the pattern etching process are completed, all the required first dielectric windows can be obtained.
[0082] Step 3: Figure 4E As shown, the second dielectric layer 207 is formed to completely fill each first dielectric window and extend to the surface outside the first dielectric window; the material of the second dielectric layer 207 is different from that of the first dielectric layer 203 .
[0083] Step 4: Figure 4F As shown, chemical mechanical polishing is performed to remove the second dielectric layer 207 on the top surface of the first dielectric layer 203 outside the first dielectric window, and the second dielectric layer 207 is only retained in the first dielectric window, and the top surface of the retained second dielectric layer 207 is flush with the top surface of the first dielectric layer 203.
[0084] In other embodiments, etching back or chemical mechanical polishing and etching back may be used to remove the second dielectric layer 207 on the top surface of the first dielectric layer 203 outside the first dielectric window.
[0085] The chemical mechanical polishing or etching back stops at the top surface of the first dielectric layer 203 .
[0086] Step 5: Figure 4G As shown, the first dielectric layer 203 is removed.
[0087] In the embodiment of the present invention, a wet etching process is used to remove the first dielectric layer 203 , and phosphoric acid is used as an etching solution in the wet etching process.
[0088] Step 6: Figure 4H As shown, the first TiN layer 202 is etched using the second dielectric layer 207 as a mask to remove the first TiN layer 202 outside the first dielectric window, and the first TiN layer 202 retained in the first dielectric window area is used as a metal zero layer cutoff layer.
[0089] The embodiment of the present invention adopts TiN as the material of the metal zero layer cutoff layer. When patterning the first TiN layer 202, a stacked structure of a first dielectric layer 203, a dielectric cap layer 204 and a material layer of a photolithography process, such as a three-layer photolithography material layer 205, is adopted. The pattern is transferred downward layer by layer to the first dielectric layer 203 through an etching process. Then, the first dielectric window area is used as the formation area of the metal zero layer cutoff layer by forming a second dielectric layer 207 to fill the first dielectric window and removing the first dielectric layer 203. The present invention avoids the need to use a process of implanting boron into amorphous silicon in the existing method by etching downward layer by layer, so that the lateral diffusion of the injected boron can be prevented from having an adverse effect on the CD of the metal zero layer cutoff layer. Therefore, the embodiment of the present invention can achieve precise control of the CD of the metal zero layer cutoff layer.
[0090] In addition, in the existing method, the formation area of the metal zero layer cutoff layer is defined by the boron injection area. In the multiple cycles of the patterned boron injection process, there will be a situation where the local area of the formation area of the metal zero layer cutoff layer will block the boron injection, thus causing the defect of missing metal zero layer cutoff layer. However, in the multiple patterned etching processes of the embodiment of the present invention, each patterned etching process will form a first dielectric window that completely removes the first dielectric layer 203. Since the first dielectric window is completely opened, the first TiN layer 202 in the metal zero layer cutoff layer subsequently defined by the first dielectric window will be completely retained, so the defect of missing metal zero layer cutoff layer will not occur.
[0091] Therefore, the embodiments of the present invention can make the CD of the metal zero layer cut-off layer stable and controllable and can prevent the occurrence of metal zero layer cut-off layer loss defects and thus expand the process window.
[0092] The method of the embodiment of the present invention adopts a new stacked film layer (New film stack) when forming M0C: that is, TiN / SIN / Cap OX / SOC / Si-ARC / PR is used to replace the existing A-Si / SOC / Si-ARC / PR; Tri-layer and (&) SIN ET+OX Dep+OX CMP+SiN RM+TiN ET are used, and the pattern is transferred layer by layer to the metal hard mask TiN, that is, the first TiN layer 202, and TiN becomes the M0C that blocks the MOA layer etching (Block MOA ET), and MOA is located in the metal zero layer of the active area. The M0C formed by the method of the embodiment of the present invention has the advantages of stable and controllable CD and can expand the M0C Missing defect window.
[0093] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing a metal zero-layer cutoff layer, characterized in that: The steps include: Step 1: forming a first TiN layer and a first dielectric layer in sequence on the top surface of the underlying structure; Step 2: performing a pattern etching process repeatedly to form a pattern structure of the first dielectric layer through the pattern etching process repeatedly, wherein the pattern structure of the first dielectric layer includes a plurality of first dielectric windows where the first dielectric layer is removed; Each of the patterned etching processes forms a portion of the first dielectric window respectively, and the number of cycles of the patterned etching process includes opening all the required first dielectric windows; Step 3: forming a second dielectric layer to completely fill each of the first dielectric windows and extend to the surface outside the first dielectric windows; The material of the second dielectric layer is different from the material of the first dielectric layer; Step 4: Perform chemical mechanical polishing or back etching to remove all the second dielectric layer above the top surface of the first dielectric layer outside the first dielectric window, and the second dielectric layer is only retained in the first dielectric window, and the top surface of the retained second dielectric layer is flush with the top surface of the first dielectric layer; Step 5: removing the first dielectric layer; Step six: using the second dielectric layer as a mask to etch the first TiN layer to form a first dielectric window, the first TiN layer outside the first dielectric window is removed, and the first TiN layer remaining in the first dielectric window area is used as a metal zero layer cutoff layer.
2. The method for manufacturing a metal zero layer cutoff layer according to claim 1, characterized in that: Step 1 also includes forming a dielectric cap layer on the surface of the first dielectric layer; the material of the dielectric cap layer is different from the material of the first dielectric layer.
3. The method for manufacturing a metal zero layer cutoff layer according to claim 2, characterized in that: The material of the dielectric cap layer is the same as that of the second dielectric layer.
4. The method for manufacturing a metal zero layer cutoff layer according to claim 3, characterized in that: The material of the first dielectric layer includes silicon nitride; The material of the dielectric cap layer includes an oxide layer.
5. The method for manufacturing a metal zero layer cutoff layer according to claim 2, characterized in that: Each of the graphic etching processes comprises the following sub-steps: Step 21, sequentially forming three photoresist material layers, wherein the three photoresist material layers include: an organic dielectric layer, a silicon-based hard mask layer, and a photoresist; Step 22, performing a photolithography process to pattern the photoresist; Step 23, performing etching to transfer the photoresist pattern to the silicon-based hard mask layer and the organic dielectric layer in sequence; Step 24, performing etching to further transfer the pattern from the silicon-based hard mask layer to the dielectric cap layer and the first dielectric layer; Step 25: then remove the three photoresist material layers.
6. The method for manufacturing a metal zero layer cutoff layer according to claim 5, characterized in that: The material of the organic dielectric layer includes a carbon coating.
7. The method for manufacturing a metal zero layer cutoff layer according to claim 5, characterized in that: The material of the silicon-based hard mask layer includes a silicon-based anti-reflection layer.
8. The method for manufacturing a metal zero layer cutoff layer according to claim 5, characterized in that: The maximum number of cycles of the patterning etching process is more than 4 times.
9. The method for manufacturing a metal zero layer cutoff layer according to claim 1, characterized in that: The underlying structure includes: a semiconductor substrate; A semiconductor device is formed on the semiconductor substrate, the semiconductor device comprising: a gate structure formed on the semiconductor substrate, a source region and a drain region of the semiconductor device are formed in the semiconductor substrate on both sides of each gate structure, and a channel region is formed in the semiconductor substrate covered by the gate structure; The gate structure is a metal gate; A zero-th interlayer film is filled in the region between the metal gates, and a top surface of the zero-th interlayer film is flush with a top surface of the metal gates; A first interlayer film is formed on a top surface of the zeroth interlayer film and a top surface of the metal gate.
10. The method for manufacturing a metal zero layer cutoff layer according to claim 4, characterized in that: In step five, a wet etching process is used to remove the first dielectric layer, and phosphoric acid is used as an etching solution in the wet etching process.
11. The method for manufacturing a metal zero layer cutoff layer according to claim 1, characterized in that: In step 4, the chemical mechanical polishing or the etching back stops at the top surface of the first dielectric layer.
Citation Information
Patent Citations
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CN111435651A
Rear-section metal cutting process method
CN118588553A