Storage device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a storage device, a manufacturing method thereof and electronic equipment. The storage device comprises a circuit board; the memory is positioned on the circuit board; and the system-on-chip chip is positioned on one side, far away from the circuit board, of the memory. The system-on-chip chip is exposed out of the side, away from the circuit board, of the storage device, a large amount of heat generated by the system-on-chip chip can be dissipated through the exposed surface more quickly, the heat dissipation path is smoother, the heat dissipation capacity of the storage device can be effectively improved, and degradation of the device performance can be effectively avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a storage device and a manufacturing method thereof, and an electronic device. Background Art

[0002] The storage device includes a memory and a system chip connected to each other, wherein the system chip is used to control the access of data in the memory. In the three-dimensional stacking process, the memory and the system chip on chip are arranged in a stacked manner, which can effectively improve the computing performance.

[0003] However, during the operation of the storage device, the storage device will generate a large amount of heat energy. Due to the packaging structure of the stacking process, the heat generated during the operation is difficult to dissipate effectively, which can easily cause the problem of device performance degradation.

[0004] It can be seen that the heat dissipation problem of three-dimensional stacked storage devices is a key to the development of the industry. Summary of the invention

[0005] The problem solved by the present invention is how to improve the heat dissipation capability of a three-dimensionally stacked storage device.

[0006] In order to solve the above problems, the present invention provides a method for manufacturing a storage device, comprising:

[0007] forming a memory; forming a system-on-chip chip; bonding the system-on-chip chip and the memory; mounting the memory on a circuit board, wherein the memory is located between the system-on-chip chip and the circuit board.

[0008] Optionally, the step of forming a memory includes: providing at least two memory wafers; and stacking and bonding at least two of the memory wafers.

[0009] Optionally, the method further includes: before installing the memory on a circuit board, forming a first redistribution layer located on one side of the memory; in the step of installing the memory on a circuit board, the first redistribution layer is located between the memory and the circuit board.

[0010] Optionally, the step of forming a memory includes: forming at least two stacked memory wafers, wherein the at least two stacked memory wafers include: a bottom memory wafer; in the step of forming a first redistribution layer located on one side of the memory, the first redistribution layer is formed on the surface of the bottom memory wafer.

[0011] Optionally, it also includes: before bonding the system-on-chip chip and the memory, forming a second redistribution layer located on the other side of the memory; in the step of bonding the system-on-chip chip and the memory, the second redistribution layer is located between the system-on-chip chip and the memory.

[0012] Optionally, the step of forming a memory includes: forming at least two stacked memory wafers, wherein the at least two stacked memory wafers include: a top memory wafer; in the step of forming a second redistribution layer located on the other side of the memory, the second redistribution layer is formed on the surface of the top memory wafer.

[0013] Optionally, it also includes: providing an auxiliary logic chip; after forming the system-on-chip chip, before bonding the system-on-chip chip and the memory, bonding the system-on-chip chip and the auxiliary logic chip; in the step of bonding the system-on-chip chip and the memory, bonding the system-on-chip chip bonded with the auxiliary logic chip and the memory, wherein the auxiliary logic chip is located between the system-on-chip chip and the memory.

[0014] Optionally, the method further includes: providing a substrate; after forming the memory, before mounting the memory on a circuit board, mounting the memory on the substrate; during the step of mounting the memory on the circuit board, mounting the substrate on the circuit board.

[0015] Optionally, the bonding step includes: forming a first structure to be bonded; thinning the first structure to be bonded through the back side; forming a through-silicon via in the thinned first structure to be bonded; forming a bonding connection layer on the back side of the first structure to be bonded having the through-silicon via; forming a second structure to be bonded, the front side of the second structure to be bonded having a bonding connection layer; and bonding the bonding connection layer of the first structure to be bonded and the bonding connection layer of the second structure to be bonded.

[0016] Optionally, the step of forming a memory includes: forming at least two stacked memory wafers, wherein the at least two stacked memory wafers include: a top memory wafer; in the step of forming a first structure to be bonded, the first structure to be bonded includes a system-on-chip chip; in the step of forming a second structure to be bonded, the second structure to be bonded includes the top memory wafer, the top memory wafer is thinned and silicon through vias are formed in the top memory wafer.

[0017] Accordingly, the present invention further provides a storage device, comprising:

[0018] A circuit board; a memory, the memory being located on the circuit board; and a system-on-chip chip, the system-on-chip chip being located on a side of the memory away from the circuit board.

[0019] Optionally, the storage device has at least two memories; at least two memories are stacked along the direction of the connection between the circuit board and the system-on-chip chip.

[0020] Optionally, it also includes: a first redistribution layer, wherein the first redistribution layer is located between all memories and the circuit board.

[0021] Optionally, the memory closest to the circuit board is a bottom layer memory; and the first redistribution layer is located on a surface of the bottom layer memory facing the circuit board.

[0022] Optionally, it also includes: a second redistribution layer, wherein the second redistribution layer is located between all memories and the system-on-chip chip.

[0023] Optionally, the memory closest to the system-on-chip chip is a top-layer memory; and the second redistribution layer is located on a surface of the top-layer memory facing the system-on-chip chip.

[0024] Optionally, it also includes: an auxiliary logic chip, wherein the auxiliary logic chip is located between the system-on-chip chip and all memories.

[0025] Optionally, it also includes: a substrate, wherein the substrate is located between the circuit board and all memories.

[0026] In addition, the present invention also provides an electronic device, including: a storage device, and the storage device is the storage device of the present invention.

[0027] Optionally, it also includes: thermal conductive adhesive, wherein the thermal conductive adhesive covers the surface of the system-on-chip chip facing away from the memory.

[0028] Optionally, it further includes: a heat dissipation device, which is arranged on a surface of the system-on-chip chip that is opposite to the memory.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the technical solution of the present invention, the system-on-chip chip is located on the side of the memory away from the circuit board. The system-on-chip chip is exposed on the side of the memory away from the circuit board, and a large amount of heat generated by the system-on-chip chip can be dissipated more quickly through the exposed surface, and the heat dissipation path is smoother, which can effectively improve the heat dissipation capacity of the storage device and effectively avoid the degradation of device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic diagram of the structure of a storage device;

[0032] Figure 2 is a schematic cross-sectional structural diagram of some embodiments of the storage device of the present invention;

[0033] Figures 3 to 23 It is a schematic cross-sectional structure diagram of each step of some embodiments of the storage device manufacturing method of the present invention. DETAILED DESCRIPTION

[0034] As can be seen from the background technology, the three-dimensional stacked storage device in the prior art has a heat dissipation problem. Now, the cause of the heat dissipation problem is analyzed in combination with the structure of a three-dimensional stacked storage device:

[0035] refer to Figure 1 , showing a schematic structural diagram of a storage device.

[0036] The storage device is a three-dimensional stacked storage device, which includes: a circuit board 11, a system-on-chip chip (SOC chip) 12 and a memory stack 14, wherein the memory stack 14 includes a plurality of stacked memories 13, and the system-on-chip chip 12 and the memory stack 14 are sequentially stacked on the surface of the circuit board 11.

[0037] During the operation of the storage device, the main heat is generated by the system-on-chip chip 12. However, the system-on-chip chip 12 is located between the memory stack 14 and the circuit board 11. The heat dissipation path of the system-on-chip chip 12 is seriously congested, and it is difficult to contact with an external heat dissipation device (such as a heat sink, a cooling fan, etc.), thereby causing a heat dissipation problem for the storage device.

[0038] In order to solve the above technical problem, the present invention provides a storage device, comprising:

[0039] A circuit board; a memory, the memory being located on the circuit board; and a system-on-chip chip, the system-on-chip chip being located on a side of the memory away from the circuit board.

[0040] According to the technical solution of the present invention, the system-on-chip chip is exposed on a side of the memory away from the circuit board. A large amount of heat generated by the system-on-chip chip can be dissipated more quickly through the exposed surface, and the heat dissipation path is smoother, which can effectively improve the heat dissipation capacity of the storage device and effectively avoid degradation of device performance.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] refer to Figure 2 , showing schematic cross-sectional structures of some embodiments of the storage device of the present invention.

[0043] The storage device comprises:

[0044] Circuit board 110;

[0045] A memory 120, wherein the memory 120 is located on the circuit board 110;

[0046] The system-on-chip chip 130 is located on a side of the memory 120 away from the circuit board 110 .

[0047] The system-on-chip chip 130 is located on a side of the memory 120 away from the circuit board 110, and is exposed on a side of the memory 120 away from the circuit board 110. A large amount of heat generated by the system-on-chip chip 130 can be dissipated more quickly through the exposed surface, and the heat dissipation path is smoother, which can effectively improve the heat dissipation capacity of the storage device and effectively avoid degradation of device performance.

[0048] The technical solution of the storage device embodiment is described in detail below with reference to the accompanying drawings.

[0049] The circuit board 110 is used to connect the storage device with an external circuit.

[0050] Specifically, in some embodiments, the circuit board 110 may be a printed circuit board (Printed Circuit Board, PCB); in other embodiments, the circuit board may also be a flexible printed circuit (Flexible Printed Circuit, FPC).

[0051] In some embodiments of the present invention, the storage device further includes: a substrate 111, and the substrate 111 is located between the circuit board 110 and all the memories 120. The substrate 111 can realize the circuit connection between the circuit board 110 and the memories 120.

[0052] Specifically, the substrate 111 may be a silicon substrate. For example, the substrate 111 may be a single crystal substrate, a polycrystalline silicon substrate or an amorphous silicon substrate; the substrate may also be a germanium substrate, a gallium arsenide substrate or a silicon germanium substrate; the substrate may also be selected from a substrate having an epitaxial layer or a silicon structure on an epitaxial layer; the substrate may also be other semiconductor materials, and the present invention does not impose any limitation on this.

[0053] In some embodiments of the present invention, the substrate 111 is electrically connected to the circuit board 110 via a ball grid array (BGA) 101. Specifically, Figure 2 As shown, the surface of the substrate 111 facing the circuit board 110 has a ball grid array 101 , and the ball grid array 101 includes: a plurality of solder balls 112 , and the solder balls 112 of the ball grid array 101 are in contact with the surface of the circuit board 110 .

[0054] The memory 120 is used to store data.

[0055] Specifically, in some embodiments, the memory 120 may be a dynamic random access memory (DRAM); in other embodiments, the memory may also be a temporary memory (Random Access Memory, RAM) such as a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), or a double data rate synchronous dynamic random access memory (DDR SDRAM).

[0056] In some other embodiments, the memory may also be a mask random access memory (MASK ROM), a programmable red-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory (Flash memory) or other read-only memory (ROM).

[0057] In some embodiments of the present invention, the storage device has at least two memories 120; at least two memories 120 are stacked along the direction of the connection between the circuit board 110 and the system-on-chip chip 130. Specifically, the storage device includes: a memory stack 109, and the memory stack 109 includes: at least two stacked memories 120.

[0058] Specifically, in the memory stack 109, each memory 120 is provided with a through-silicon via (TSV) for electrical connection with adjacent memories 120 and other chips, and adjacent memories 120 are electrically connected through their respective bonding connection layers.

[0059] For example, Figure 2As shown, among two adjacent memories 120, the first side of one memory 120 has a bonding connection layer; the second side of the other memory 120 also has a bonding connection layer; the bonding connection layers of the two memories 120 are connected by fusion bonding (Fusing Bonding), for example, by hydrophilic fusion bonding.

[0060] It should be noted that hydrophilic melt bonding is a process in which a clean polished wafer is hydrophilically cleaned to form a hydrophilic surface with a high hydroxyl (-OH) density. Water molecules in the atmospheric environment are easily adsorbed on the hydrophilic surface. At room temperature, two wafers with hydrophilic surfaces are bonded together. During high-temperature annealing, the weak intermolecular forces (van der Waals forces and hydrogen bonds) between the interfaces are converted into stronger Si-O-Si covalent bonds, thereby obtaining a strong bonding interface, so that the polished semiconductor wafers can be bonded together without the use of adhesives.

[0061] It should also be noted that, for a memory 120, the first side of the memory 120 is arranged opposite to the second side of the memory 120; and since each memory 120 is provided with a through silicon via, each memory 120 is thinned, that is, the substrate of each memory 120 is thinned.

[0062] In some embodiments of the present invention, the storage device further includes: a first redistribution layer 121, and the first redistribution layer 121 is located between all memories 120 and the circuit board 110. The first redistribution layer (RDL) 121 is used to realize the electrical connection between the memory 120 and the circuit board 110.

[0063] In some embodiments, the memory 120 closest to the circuit board 110 is a bottom-layer memory 120 b ; the first redistribution layer 121 is located on a surface of the bottom-layer memory 120 b facing the circuit board 110 .

[0064] The first redistribution layer 121 has a metal layer and a dielectric material filled between the metal layers to form metal wiring. The first redistribution layer 121 rearranges the input and output ports (IO ports) of the bottom memory 120b, arranges the input and output ports of the bottom memory 120b to an area with more space, and forms a surface array layout.

[0065] Specifically, Figure 2 In some of the embodiments shown, the first redistribution layer 121 is located on the surface of the bottom memory 120b facing the substrate 111, and the first redistribution layer 121 and the substrate 111 are electrically connected via metal bumps 120a.

[0066] In some embodiments of the present invention, the storage device further includes: a second redistribution layer 122, which is located between all memories 120 and the system-on-chip chip 130. The second redistribution layer 122 is used to realize electrical connection between the memories 120 and the system-on-chip chip 130.

[0067] In some embodiments, the memory 120 closest to the system-on-chip chip 130 is a top-layer memory 120 t ; the second redistribution layer 122 is located on a surface of the top-layer memory 120 t facing the system-on-chip chip 130 .

[0068] The top-level memory 120t is provided with silicon through vias, and the second redistribution layer 122 has metal layers and dielectric materials filled between the metal layers to form metal wiring. The metal wiring in the second wiring layer 122 is electrically connected to the silicon through vias in the top-level memory 120t to be electrically connected to the system-on-chip chip 130.

[0069] The SoC chip 130 is used to control the memory 120 .

[0070] The system on chip (SOC) 130 is used to control the memory 120 . For example, the SOC 130 is used to perform operations such as reading, writing, and erasing data on the memory 120 .

[0071] The system-on-chip chip 130 is located on the side of all memories 120 facing away from the circuit board 110. The system-on-chip chip 130 is exposed. A large amount of heat generated by the system-on-chip chip 130 can be dissipated more quickly through the exposed surface, and the heat dissipation path is smoother, which can effectively improve the heat dissipation capacity of the storage device and effectively avoid the degradation of device performance.

[0072] In some embodiments of the present invention, the storage device further includes: an auxiliary logic chip 131, which is located between the system-on-chip chip 130 and all memories 120. The auxiliary logic chip 131 is used to supplement the system-on-chip chip 130 to control the memory 120.

[0073] Specifically, the surface of the auxiliary logic chip 130 facing the memory 120 has a bonding connection layer; the bonding connection layer on the surface of the auxiliary logic chip 130 facing the memory 120 is fusion-bonded to the second wiring layer 122 .

[0074] The surface of the auxiliary logic chip 130 facing the system-on-chip chip 130 also has a bonding connection layer, and the surface of the system-on-chip chip 130 facing the circuit board 110 has a bonding connection layer for electrically connecting with the memory 120; the bonding connection layer of the auxiliary logic chip 130 facing the surface of the system-on-chip chip 130 is melt-bonded to the bonding connection layer of the system-on-chip chip 130.

[0075] Correspondingly, the present invention also provides an electronic device.

[0076] The electronic device comprises a storage device, and the storage device is the storage device of the present invention.

[0077] Specifically, the storage device is the storage device of the present invention. The specific technical solution of the storage device is referred to the embodiment of the storage device above, and the present invention will not be repeated here.

[0078] In some embodiments of the present invention, the electronic device further includes: thermally conductive adhesive, wherein the thermally conductive adhesive covers a surface of the system-on-chip chip 130 facing away from the memory 120 .

[0079] The surface of the system-on-chip chip 130 facing away from the memory 120 is exposed, and the thermal conductive adhesive is directly coated on the surface of the system-on-chip chip 130 facing away from the memory 120 , which can achieve rapid dissipation of heat generated by the system-on-chip chip 130 and higher heat dissipation efficiency.

[0080] In some embodiments of the present invention, the electronic device further includes: a heat dissipation device, which is disposed on a surface of the system-on-chip chip 130 that is away from the memory 120 .

[0081] The surface of the system-on-chip chip 130 facing away from the memory 120 is exposed, and the heat dissipation device directly acts on the surface of the system-on-chip chip 130 facing away from the memory 120, which can dissipate the heat generated by the system-on-chip chip 130 more quickly and has higher heat dissipation efficiency.

[0082] Specifically, the heat dissipation device may be a heat dissipation fan, a heat sink, etc.; in addition, the heat dissipation device may be directly fixed to the surface of the system-on-chip chip 130 facing away from the memory 120 by means of a thermally conductive adhesive.

[0083] Accordingly, the present invention also provides a method for manufacturing a storage device, comprising:

[0084] refer to Figures 3 to 11 , forming a memory; reference Figure 12 to Figure 13 , forming a system-on-chip chip; reference Figures 14 to 22 , bonding the system-on-chip chip and the memory; referring to Fig.23 , mounting the memory on a circuit board, wherein the memory is located between the system-on-chip chip and the circuit board.

[0085] It should be noted that the manufacturing method is suitable for manufacturing the storage device of the present invention. The specific technical solution of the manufacturing method can refer to the embodiment of the aforementioned storage device.

[0086] The technical solution of the manufacturing method of the storage device is described in detail below with reference to the accompanying drawings.

[0087] refer to Figures 3 to 11 , forming a memory.

[0088] In some embodiments of the present invention, the step of forming a memory includes: providing at least two memory wafers; and stacking and bonding at least two of the memory wafers.

[0089] In some embodiments, the step of providing at least two memory wafers includes: Figure 3 As shown, a first memory wafer 221 is provided; Figure 7 As shown, a second memory wafer 222 is provided; the step of stacking and bonding at least two of the memory wafers includes: bonding the first memory wafer 221 and the second memory wafer 222 to form the memory double-layer structure 2020 (as shown in FIG. Figure 8 shown).

[0090] In some embodiments of the present invention, the bonding step includes: forming a first structure to be bonded; thinning the first structure to be bonded through the back side; forming a through-silicon via in the thinned first structure to be bonded; forming a bonding connection layer on the back side of the first structure to be bonded with the through-silicon via; forming a second structure to be bonded, the front side of the second structure to be bonded having a bonding connection layer; bonding the bonding connection layer of the first structure to be bonded and the bonding connection layer of the second structure to be bonded.

[0091] Specifically, in the step of forming the first structure to be bonded, the first memory wafer 221 is the first structure to be bonded.

[0092] like Figure 3 As shown, a bonding layer 221a is provided on the front side of the first memory wafer 221, and the bonding layer 221a has a metal layer and a dielectric material filled between the metal layers to form a metal wiring. For example, in the bonding layer 221a, the metal layer includes: a bottom metal M1 and a top metal TM, the bottom metal M1 is located between the top metal TM, and the bottom metal M1, the top metal TM and the first memory wafer 221 are filled with a dielectric material.

[0093] In some embodiments, the bonding step further comprises: Figure 3 As shown, a carrier wafer 201 is provided; Figure 4 As shown, the carrier wafer 201 is bonded to the front side of the first memory wafer 221 ; and the first memory wafer 221 is flipped over through the carrier wafer 201 .

[0094] like Figure 4 As shown, in the step of bonding the carrier wafer 201 to the front side of the first memory wafer 221 , the surface of the bonding connection layer 221 a on the front side of the first memory wafer 221 is bonded to the surface of the carrier wafer 201 .

[0095] Specifically, in the step of thinning the first structure to be bonded through the back surface, after the first memory wafer 221 is turned over, Figure 5 As shown, the first memory wafer 221 is thinned; in the step of forming a through silicon via in the thinned first structure to be bonded, as shown Figure 6 As shown, a through silicon via TSV1 is formed in the thinned first memory wafer 221; in the step of forming a bonding connection layer on the back side of the first structure to be bonded with the through silicon via, as shown in FIG. Figure 6 As shown, a bonding connection layer 221 b is formed on the back side of the thinned first memory wafer 221 .

[0096] like Figure 5 As shown, the first memory wafer 221 has a substrate (not shown in the figure). In the step of thinning the first memory wafer 221, part of the material of the substrate of the first memory wafer 221 is removed from the back side to thin the first memory wafer 221.

[0097] For example, after the first memory wafer 221 is positively bonded to the carrier wafer 201 , the first memory wafer 221 and the carrier wafer 201 after the bonding are reversed, and the back side of the first memory wafer 221 is ground or etched to thin the first memory wafer 221 .

[0098] like Figure 6 As shown, the through silicon via TSV1 penetrates the first memory wafer 221, and the two ends of the through silicon via TSV1 are respectively exposed from the front and back sides of the first memory wafer 221. In some exemplary embodiments, one end of the through silicon via TSV1 is electrically connected to the metal layer in the bonding connection layer 221a on the front side of the first memory wafer 221, and in an exemplary manner, one end of the through silicon via TSV1 is in contact with the bottom metal M1 in the bonding connection layer 221a; the other end of the through silicon via TSV1 is exposed from the back side of the first memory wafer 221.

[0099] The bonding connection layer 221b has a metal layer and a dielectric material filled between the metal layers to form a metal wiring. For example, in the bonding connection layer 221b, the metal layer includes: a back metal BSM and a bonding via via. The back metal BSM is located on the back side of the first memory wafer 221, and the back metal BSM is electrically connected to the through silicon via TSV1, for example, the back metal BSM is in contact with the through silicon via TSV1 exposed on the back side of the first memory wafer 221; the bonding via via is located on the surface of the back metal BSM facing away from the first memory wafer 221, and the bonding via via is exposed on the surface of the bonding connection layer 221b.

[0100] Specifically, in the step of forming a second structure to be bonded, wherein the front side of the second structure to be bonded has a bonding connection layer, as Figure 7 As shown, the second memory wafer 222 is the second structure to be bonded, and a bonding connection layer 222 a is provided on the front side of the second memory wafer 222 .

[0101] The front side of the second memory wafer 222 has a bonding layer 222a, and the bonding layer 222a has a metal layer and a dielectric material filled between the metal layers to form a metal wiring. For example, in the bonding layer 222a, the metal layer includes: a bottom metal M1, a top metal TM, and a bonding via via; wherein the bottom metal M1 is located between the top metal TM and the second memory wafer 222, the bonding via via is located on a side of the top metal TM away from the bottom metal M1, and the bonding via via is exposed on the surface of the bonding layer 222a.

[0102] Specifically, in the step of bonding the bonding connection layer of the first structure to be bonded and the bonding connection layer of the second structure to be bonded, Figure 8 As shown, the bonding connection layer 221 b on the back side of the first memory wafer 221 and the bonding connection layer 222 a on the front side of the second memory wafer 221 are bonded relative to each other.

[0103] For example, in the step of bonding the bonding connection layer 221b on the back side of the first memory wafer 221 and the bonding connection layer 222a on the front side of the second memory wafer 221 relative to each other, the bonding connection layer 221b on the back side of the first memory wafer 221 and the bonding connection layer 222a on the front side of the second memory wafer 221 can be bonded relative to each other by melt bonding to form the memory double-layer structure.

[0104] It should be noted that in the step of bonding the bonding connection layer 221b on the back side of the first memory wafer 221 and the bonding connection layer 222a on the front side of the second memory wafer 221 relative to each other, the bonding vias via in the bonding connection layer 221b are in contact with the bonding vias via in the bonding connection layer 222a to achieve electrical connection.

[0105] In some embodiments of the present invention, in the step of providing at least two memory wafers, more than two, that is, greater than or equal to three, of the memory wafers are provided; the step of stacking and bonding at least two of the memory wafers also includes: stacking and bonding at least two of the memory double-layer structures.

[0106] In some embodiments, in the process of stacking and bonding at least two of the memory double-layer structures, in the step of forming a first structure to be bonded, as Fig. 9 As shown, the memory double-layer structure 2021 is formed, that is, the memory double-layer structure 2021 is the first structure to be bonded; in the step of thinning the first structure to be bonded through the back side, the second memory wafer 222 in the memory double-layer structure 2021 is thinned; in the step of forming silicon through vias in the thinned first structure to be bonded, silicon through vias TSV2 are formed in the thinned second memory wafer 222; in the step of forming a bonding connection layer on the back side of the first structure to be bonded with silicon through vias, a bonding connection layer 222b is formed on the back side of the thinned second memory wafer 222.

[0107] Specifically, the step of thinning the second memory wafer 222 in the memory double-layer structure 2021 can refer to the aforementioned step of thinning the first memory wafer 221, for example, grinding or etching the substrate of the second memory wafer 222 in the memory double-layer structure 2021 to thin the second memory wafer 222 in the memory double-layer structure 2021.

[0108] The specific technical solution of the step of forming the through silicon via TSV2 in the thinned second memory wafer 222 can refer to the technical solution of the aforementioned step of forming the through silicon via TSV1 in the first memory wafer 221. For example, the through silicon via TSV2 passes through the second memory wafer 222, one end of which is in contact with the bottom metal M1 in the bonding connection layer 222a on the front side of the second memory wafer 222, and the other end is exposed on the back side of the second memory wafer 222.

[0109] The technical solution for the step of forming a bonding connection layer 222b located on the back side of the second memory wafer 222 can refer to the technical solution for forming a bonding connection layer 221b located on the back side of the first memory wafer 221. For example, the back metal BSM is located on the back side of the second memory wafer 222 and is in contact with the through silicon via TSV2 exposed on the back side of the second memory wafer 222; the bonding via via is located on the surface of the back metal BSM facing away from the second memory wafer 222 and is exposed on the surface of the bonding connection layer 222b.

[0110] In some embodiments, in the process of stacking and bonding at least two of the memory double-layer structures, in the step of forming the second structure to be bonded, as Fig.10 As shown, the memory double-layer structure 2022 is formed, that is, the memory double-layer structure 2022 is the second structure to be bonded.

[0111] Specifically, the steps of forming the memory double-layer structure 2022 include: Fig.10 As shown, remove the carrier wafer 201 (as shown Figure 8 As shown), the bonding connection layer 221a on the front side of the first memory wafer 221 is exposed; a bonding via via is formed in the bonding connection layer 221a, wherein the bonding via via is electrically connected to the metal layer in the bonding connection layer 221a, and for example, one end of the bonding via via is in contact with the top metal TM in the bonding connection layer 221a, and the other end is exposed from the bonding connection layer 221a.

[0112] In some embodiments, in the step of bonding the bonding connection layer of the first structure to be bonded and the bonding connection layer of the second structure to be bonded, Fig.11 As shown, the memory double-layer structure 2021 and the memory double-layer structure 2022 are bonded and connected.

[0113] Specifically, in the step of bonding the memory double-layer structure 2021 and the memory double-layer structure 2022 together, the bonding connection layer 222b on the back side of the thinned second memory wafer 222 in the memory double-layer structure 2021 and the bonding connection layer 221a on the front side of the first memory wafer 221 in the memory double-layer structure 2022 are bonded relative to each other, wherein the bonding vias via in the bonding connection layer 222b are in contact with the bonding vias via in the bonding connection layer 221a to achieve electrical connection.

[0114] refer to Figure 12 to Figure 13 , the manufacturing method also includes: forming a system-on-chip chip.

[0115] In some embodiments of the present invention, the step of forming a system-on-chip chip includes: forming a system-on-chip wafer SOC.

[0116] Specifically, Fig.12 As shown, the surface of the system-on-chip wafer soc has a bonding connection layer soc1, and the bonding connection layer soc1 has a metal layer and a dielectric material filled between the metal layers to form a metal wiring. For example, in the bonding connection layer soc1, the metal layer includes: a top metal TM and a bonding via via, the top metal TM is located between the bonding via via and the system-on-chip wafer soc, one end of the bonding via via is in contact with the top metal, and the other end of the bonding via via is exposed on the surface of the bonding connection layer soc1.

[0117] In some embodiments of the present invention, the manufacturing method further includes: providing an auxiliary logic chip; and after forming the system-on-chip chip, bonding the system-on-chip chip and the auxiliary logic chip.

[0118] In some embodiments, the step of providing an auxiliary logic chip includes: forming an auxiliary logic wafer au.

[0119] Specifically, Fig.12 As shown, the surface of the auxiliary logic wafer au has a bonding connection layer au1, and the bonding connection layer au1 has a metal layer and a dielectric material filled between the metal layers to form a metal wiring. For example, in the bonding connection layer au1, the metal layer includes: a bottom metal M1, a top metal TM and a bonding via via, the bottom metal M1 is located between the top metal TM and the system-on-chip wafer soc, the bonding via via is located on the side of the top metal away from the bottom metal M1, and one end of the bonding via via is in contact with the top metal, and the other end of the bonding via via is exposed on the surface of the bonding connection layer au1.

[0120] In some embodiments, such as Fig.13 As shown, in the step of bonding the system-on-chip chip and the auxiliary logic chip, the system-on-chip wafer soc and the auxiliary logic wafer au are bonded.

[0121] Specifically, in the step of bonding the system-on-chip wafer soc and the auxiliary logic wafer au, the bonding connection layer soc1 in the system-on-chip wafer soc is bonded relative to the bonding connection layer au1 in the auxiliary logic wafer au.

[0122] It should be noted that in the step of bonding the bonding layer soc1 in the system-on-chip wafer soc to the bonding layer au1 in the auxiliary logic wafer au, the bonding vias via in the bonding layer soc1 are in contact with the bonding vias via in the bonding layer au1 to achieve electrical connection.

[0123] refer to Figures 14 to 22 The manufacturing method further includes: bonding the system-on-chip chip and the memory.

[0124] Specifically, the step of bonding the system-on-chip chip and the memory includes: bonding the system-on-chip wafer soc and at least one of the memory wafers.

[0125] In some embodiments of the present invention, the manufacturing method further includes: after forming the system-on-chip chip, bonding the system-on-chip chip and the auxiliary logic chip; in the step of bonding the system-on-chip chip and the memory, bonding the system-on-chip chip bonded with the auxiliary logic chip and the memory, and the auxiliary logic chip is located between the system-on-chip chip and the memory.

[0126] Specifically, the step of bonding the system-on-chip chip bonded with the auxiliary logic chip and the memory includes: Figures 14 to 22 As shown, a system-on-chip wafer soc bonded with an auxiliary logic wafer au and at least one memory double-layer structure are bonded.

[0127] In some embodiments, in the process of bonding the system-on-chip wafer soc bonded with the auxiliary logic wafer au and at least one memory double-layer structure, in the step of forming the first structure to be bonded, as Fig.14 As shown, a system-on-chip wafer SOC bonded with an auxiliary logic wafer au is formed, that is, the system-on-chip wafer SOC bonded with the auxiliary logic wafer au is the first structure to be bonded; in the step of thinning the first structure to be bonded through the back side, the auxiliary logic wafer au is thinned; in the step of forming through silicon vias in the thinned first structure to be bonded, a through silicon via TSV3 is formed in the thinned auxiliary logic wafer au; in the step of forming a bonding connection layer on the back side of the first structure to be bonded with the through silicon vias, a bonding connection layer au2 is formed on the back side of the thinned auxiliary logic wafer au.

[0128] Specifically, the step of thinning the auxiliary logic wafer au may refer to the aforementioned step of thinning the first memory wafer 221 , for example, grinding or etching the substrate of the auxiliary logic wafer au to thin the auxiliary logic wafer au.

[0129] The specific technical solution of the step of forming the through silicon via TSV3 in the thinned auxiliary logic wafer au can refer to the technical solution of the aforementioned step of forming the through silicon via TSV1 in the first memory wafer 221. For example, the through silicon via TSV3 passes through the auxiliary logic wafer au, one end of which is in contact with the bottom metal M1 in the bonding connection layer au1 on the front side of the auxiliary logic wafer au, and the other end is exposed on the back side of the auxiliary logic wafer au.

[0130] The technical solution for the step of forming the bonding connection layer au2 located on the back side of the auxiliary logic wafer au after thinning can refer to the technical solution for forming the bonding connection layer 221b located on the back side of the first memory wafer 221. For example, the bonding connection layer au2 is located on the back side of the second memory wafer 222, and the bonding connection layer au2 has a metal layer and a dielectric material filled between the metal layers to form a metal wiring. For example, in the bonding connection layer au2, the metal layer includes: a back metal BSM and a bonding via via. The back metal BSM is located on the back side of the auxiliary logic wafer au, and the back metal BSM is electrically connected to the through silicon via TSV3, for example, the back metal BSM is in contact with the through silicon via TSV3 exposed on the back side of the auxiliary logic wafer au; the bonding via via is located on the surface of the back metal BSM facing away from the auxiliary logic wafer au, and the bonding via via is exposed on the surface of the bonding connection layer au2.

[0131] In some embodiments, in the process of bonding a system-on-chip wafer soc bonded with an auxiliary logic wafer au and at least one memory double-layer structure, in the step of forming a second structure to be bonded, at least one memory double-layer structure is formed, that is, at least one memory double-layer structure is the second structure to be bonded.

[0132] For example, Fig.15 As shown, the step of forming at least one memory double-layer structure includes: forming a stacked bonded memory double-layer structure 2023 and a memory double-layer structure 2024; therefore, in the step of forming the second structure to be bonded, the stacked bonded memory double-layer structure 2023 and the memory double-layer structure 2024 are the second structure to be bonded.

[0133] It should be noted that, in some exemplary embodiments, the steps of forming a stacked bonded memory double-layer structure 2023 and a memory double-layer structure 2024 include: removing the carrier wafer to expose the bonding connection layer 221a on the front side of the first memory wafer 221 in the memory double-layer structure 2023; forming a bonding via via in the bonding connection layer 221a, wherein the bonding via via is electrically connected to the metal layer in the bonding connection layer 221a, and, by way of example, one end of the bonding via via is in contact with the top metal TM in the bonding connection layer 221a, and the other end is exposed from the bonding connection layer 221a.

[0134] In some embodiments, in the step of bonding the bonding connection layer of the first structure to be bonded and the bonding connection layer of the second structure to be bonded, Fig.16 As shown, the system-on-chip wafer soc bonded with the auxiliary logic wafer au and the stacked bonded memory double-layer structure 2023 and the memory double-layer structure 2024 are bonded.

[0135] Specifically, in the step of bonding the system-on-chip wafer soc bonded with the auxiliary logic wafer au and the stacked bonded memory double-layer structure 2023 and the memory double-layer structure 2024, the bonding connection layer au2 on the back side of the auxiliary logic wafer au and the bonding connection layer 221a on the front side of the first memory wafer 2021 in the memory double-layer structure 2023 are bonded relative to each other, wherein the bonding vias via in the bonding connection layer au2 are in contact with the bonding vias via in the bonding connection layer 221a to achieve electrical connection.

[0136] It should be noted that if Fig.16 As shown, in some embodiments, the step of forming a memory includes: forming at least two stacked memory wafers, wherein the at least two stacked memory wafers include: a top memory wafer 220t; in the step of forming a first structure to be bonded, the first structure to be bonded is a system-on-chip wafer soc bonded with an auxiliary logic wafer au, that is, the first structure to be bonded includes: a system-on-chip chip; in the step of forming a second structure to be bonded, the second structure to be bonded is at least one memory double-layer structure, that is, the second structure to be bonded includes the top memory wafer 220t, as shown in FIG. Fig.16 As shown, the top memory wafer 220t is thinned and through silicon vias (not shown) are formed in the top memory wafer 220t.

[0137] In some embodiments of the present invention, the manufacturing method further includes: before bonding the system-on-chip chip and the memory, forming a second redistribution layer located on the other side of the memory; in the step of bonding the system-on-chip chip and the memory, the second redistribution layer is located between the system-on-chip chip and the memory.

[0138] In some embodiments, such as Fig.16 As shown, the step of forming a memory includes: forming at least two stacked memory wafers, wherein the at least two stacked memory wafers include: a top memory wafer 220t; in the step of forming a second redistribution layer located on the other side of the memory, the second redistribution layer RDL2 is formed on the surface of the top memory wafer 200t.

[0139] Specifically, the top memory wafer 220t is the memory wafer closest to the system-on-chip wafer soc. Fig.16 As shown, the memory double-layer structure 2023 is the memory double-layer structure closest to the system-on-chip wafer soc, and the memory wafer closest to the system-on-chip wafer soc in the memory double-layer structure 2023 is the top memory wafer 220t; in the step of forming a second redistribution layer located on the other side of the memory, the second redistribution layer RDL2 is formed on the surface of the bonding connection layer 221a on the back side of the top memory wafer 200t; in the step of bonding the system-on-chip chip and the memory, the second redistribution layer RDL2 and the bonding connection layer au2 on the back side of the auxiliary logic wafer au are bonded relative to each other.

[0140] In some embodiments of the present invention, the step of forming at least one memory double-layer structure further includes: Figures 17 to 21 As shown, a stacked and bonded memory double-layer structure 2025 and a memory double-layer structure 2026 are formed; Fig. 22 As shown, in the step of bonding the system-on-chip wafer soc bonded with the auxiliary logic wafer au and at least one memory double-layer structure, the system-on-chip wafer soc bonded with the auxiliary logic wafer au, the memory double-layer structure 2023, and the memory double-layer structure 2024 is bonded to the stacked bonded memory double-layer structure 2025 and the memory double-layer structure 2026.

[0141] In some embodiments, in the process of bonding the system-on-chip wafer soc bonded with the auxiliary logic wafer au, the memory double-layer structure 2023, and the memory double-layer structure 2024 to the stacked bonded memory double-layer structure 2025 and the memory double-layer structure 2026, in the step of forming the first structure to be bonded, as shown in FIG. Fig.17As shown, a system-on-chip wafer SOC bonded with an auxiliary logic wafer au, a memory double-layer structure 2023, and a memory double-layer structure 2024 is formed, that is, the first structure to be bonded is a system-on-chip wafer SOC bonded with an auxiliary logic wafer au, a memory double-layer structure 2023, and a memory double-layer structure 2024; in the step of thinning the first structure to be bonded through the back, the second memory wafer 222 in the memory double-layer structure 2024 is thinned; in the step of forming silicon through vias in the thinned first structure to be bonded, silicon through vias TSV4 are formed in the thinned second memory wafer 222; in the step of forming a bonding connection layer on the back of the first structure to be bonded with the silicon through vias, a bonding connection layer 222b is formed on the back of the thinned second memory wafer 222.

[0142] Specifically, the step of thinning the second memory wafer 222 in the memory double-layer structure 2024 can refer to the aforementioned step of thinning the first memory wafer 221, for example, grinding or etching the substrate of the second memory wafer 222 in the memory double-layer structure 2024 to thin the second memory wafer 222 in the memory double-layer structure 2024.

[0143] The specific technical solution of the step of forming the through silicon via TSV4 in the thinned second memory wafer 222 can refer to the technical solution of the aforementioned step of forming the through silicon via TSV1 in the first memory wafer 221. For example, the through silicon via TSV4 passes through the second memory wafer 222, one end of which is in contact with the bottom metal M1 in the bonding connection layer 222a on the front side of the second memory wafer 222, and the other end is exposed on the back side of the second memory wafer 222.

[0144] The technical solution for the step of forming a bonding connection layer 222b located on the back side of the second memory wafer 222 can refer to the technical solution for forming a bonding connection layer 221b located on the back side of the first memory wafer 221. For example, the back metal BSM is located on the back side of the second memory wafer 222 and is in contact with the through silicon via TSV4 exposed on the back side of the second memory wafer 222; the bonding via is located on the surface of the back metal BSM facing away from the second memory wafer 222 and is exposed on the surface of the bonding connection layer 222b.

[0145] In some embodiments, in the process of bonding the system-on-chip wafer soc bonded with the auxiliary logic wafer au, the memory double-layer structure 2023, and the memory double-layer structure 2024 to the stacked bonded memory double-layer structure 2025 and the memory double-layer structure 2026, in the step of forming the second structure to be bonded, as shown in FIG. Figure 18 to Figure 19As shown, a stacked and bonded memory double-layer structure 2025 and a memory double-layer structure 2026 are formed.

[0146] In some embodiments of the present invention, the manufacturing method further includes: forming a first redistribution layer RDL1 located at one side of the memory.

[0147] like Figure 18 to Figure 19 As shown, in some embodiments, the step of forming a memory includes: forming at least two stacked memory wafers, wherein the at least two stacked memory wafers include: a bottom memory wafer 220b; in the step of forming a first redistribution layer RDL1 located on one side of the memory, the first redistribution layer RDL1 is formed on the surface of the bottom memory wafer 220b.

[0148] Specifically, in the step of forming at least two stacked memory wafers, the memory wafer in the memory double-layer structure 2026 that is away from the carrier wafer 201 is the bottom memory wafer 220 b .

[0149] In some embodiments, the step of forming the first redistribution layer RDL1 on the surface of the bottom memory wafer 220b includes: Fig.18 As shown, the bottom memory wafer 220b is thinned; through silicon vias TSV5 are formed in the thinned bottom memory wafer 220b; and a back side metal BSM is formed on the back side of the bottom memory wafer 220b having the through silicon vias TSV5.

[0150] Specifically, the step of thinning the bottom memory wafer 220b may refer to the aforementioned step of thinning the first memory wafer 221, for example, grinding or etching the substrate of the bottom memory wafer 220b to thin the bottom memory wafer 220b.

[0151] The specific technical solution of the step of forming the through silicon via TSV5 located in the thinned underlying memory wafer 220b can refer to the technical solution of the aforementioned step of forming the through silicon via TSV1 located in the first memory wafer 221. For example, the through silicon via TSV5 penetrates the thinned underlying memory wafer 220b, one end of which is in contact with the underlying metal M1 in the bonding connection layer 222a on the front side of the underlying memory wafer 220b, and the other end is exposed on the back side of the underlying memory wafer 220b.

[0152] The technical solution for the step of forming a back metal BSM located on the back side of the bottom memory wafer 220b having the through silicon via TSV5 can refer to the technical solution for forming a back metal BSM in the bonding connection layer 221b located on the back side of the first memory wafer 221. For example, the back metal BSM is located on the back side of the second memory wafer 222 and is in contact with the through silicon via TSV2 exposed on the back side of the second memory wafer 222.

[0153] In some embodiments, the step of forming the first redistribution layer RDL1 on the surface of the bottom memory wafer 220b further includes: Fig.19 As shown, a first redistribution layer RDL1 is formed on the back metal BSM surface on the back side of the underlying memory wafer 220b, wherein the first redistribution layer RDL1 has a metal layer RDLM and a dielectric material filled between the metal layers to form metal wiring, wherein the metal layer RDLM of the first redistribution layer RDL1 is in contact and connected with the back metal BSM on the back side of the underlying memory wafer 220b.

[0154] In some embodiments, in the step of bonding the bonding connection layer of the first structure to be bonded and the bonding connection layer of the second structure to be bonded, Figure 20 to Figure 22 As shown, the system-on-chip wafer soc bonded with the auxiliary logic wafer au, the memory double-layer structure 2023, and the memory double-layer structure 2024 is bonded to the stacked bonded memory double-layer structure 2025 and the memory double-layer structure 2026.

[0155] In some exemplary embodiments, the manufacturing method further comprises: Fig. 20 As described, before bonding the system-on-chip wafer soc with the stacked bonded memory double-layer structure 2025 and the memory double-layer structure 2026, providing a carrier wafer 202; bonding the carrier wafer 202 with the stacked bonded memory double-layer structure 2025 and the memory double-layer structure 2026; as described Fig.21 As shown, through the carrier wafer 202, the stacked and bonded memory double-layer structure 2025 and the memory double-layer structure 2026 are reversed; the carrier wafer 201 (as shown in FIG. Fig. 20 As shown), exposing the bonding connection layer 221a of the first memory wafer 221 in the memory double-layer structure 2025; as shown Fig. 22 As shown, the system-on-chip wafer soc and the stacked bonded memory double-layer structure 2025 and the memory double-layer structure 2026 are bonded.

[0156] like Fig. 20As shown, in the step of bonding the carrier wafer 202 to the stacked bonded memory double-layer structure 2025 and the memory double-layer structure 2026, the surface of the carrier wafer 202 is bonded to the surface of the first redistribution layer RDL1.

[0157] like Fig. 22 As shown, the auxiliary logic wafer AU, the memory double-layer structure 2023 and the memory double-layer structure 2024 are sequentially stacked and bonded on the system-on-chip wafer SOC; in the step of bonding the system-on-chip wafer SOC and the stacked and bonded memory double-layer structure 2025 and the memory double-layer structure 2026, the bonding connection layer 222b on the back side of the second memory wafer 222 in the memory double-layer structure 2024 and the bonding connection layer 221a on the front side of the first memory wafer 221 in the memory double-layer structure 2025 are bonded and connected, wherein the bonding vias via in the bonding connection layer 222b are in contact with the bonding vias via in the bonding connection layer 221a to achieve electrical connection.

[0158] After bonding the system-on-chip chip and the memory, the manufacturing method further includes: mounting the memory on a circuit board, wherein the memory is located between the system-on-chip chip and the circuit board.

[0159] Specifically, in the step of mounting the memory on a circuit board, at least two stacked and bonded memory wafers are mounted on the circuit board.

[0160] In some embodiments of the present invention, a first redistribution layer RDL1 is also formed on one side of the memory; in the step of installing the memory on a circuit board, the first redistribution layer is located between all memories and the circuit board, that is, the side on which the first redistribution layer RDL1 is formed is installed on the circuit board.

[0161] Specifically, the step of mounting the side formed with the first redistribution layer RDL1 to the circuit board includes: Fig. 22 As shown, remove the carrier wafer 202 (as shown Fig.21 As shown), the first redistribution layer RDL1 is exposed; as shown Fig.23 As shown, an opening r1 is formed in the first redistribution layer RDL1 , and the metal layer RDLM of the first redistribution layer RDL1 is exposed at the bottom of the opening; and a solder ball is formed in the opening r1 .

[0162] In some embodiments of the present invention, Figure 2As shown, the manufacturing method further includes: providing a substrate; after forming a memory, before mounting the memory on a circuit board, mounting the memory on the substrate; in the step of mounting the memory on a circuit board, mounting the substrate on the circuit board.

[0163] In some embodiments, such as Figure 2 As shown, a first redistribution layer is also formed on one side of the memory; in the step of mounting the memory on the substrate, the first redistribution layer is located between the substrate and the memory. Specifically, in the step of mounting the memory on the substrate, the memory wafer is soldered to the substrate through the solder balls in the openings r1 in the first redistribution layer RDL1.

[0164] The substrate has metal layers and dielectric materials filled between the metal layers to form metal wiring; a solder pad is exposed on the first surface of the substrate; in the step of installing the memory on the substrate, the solder ball in the opening r1 in the first redistribution layer RDL1 is soldered and connected to the solder pad exposed on the first surface of the substrate.

[0165] The second surface of the substrate has solder balls; in the step of installing the substrate on the circuit board, the solder balls on the second surface of the substrate are connected to the solder joints on the circuit board by welding, so as to achieve the installation connection between the substrate and the circuit board.

[0166] It should be noted that, in some embodiments of the present invention, the manufacturing method adopts a wafer-level manufacturing process; therefore, the manufacturing method also includes: soldering the memory wafer to the substrate through the solder balls in the opening r1 in the first redistribution layer RDL1, and before installing the substrate on the circuit board, cutting the memory wafer to obtain a memory chip structure; in the step of installing the substrate on the circuit board, installing the memory chip structure on the circuit board to obtain a single storage device.

[0167] In other embodiments of the present invention, the manufacturing method may also include: after mounting the substrate on the circuit board, cutting the memory wafer to obtain individual storage devices.

[0168] In summary, the system-on-chip chip is located on the side of the memory away from the circuit board. The system-on-chip chip is exposed on the side of the memory away from the circuit board, and a large amount of heat generated by the system-on-chip chip can be dissipated more quickly through the exposed surface, and the heat dissipation path is smoother, which can effectively improve the heat dissipation capacity of the storage device and effectively avoid the degradation of device performance.

[0169] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for manufacturing a storage device, characterized in that: include: forming a memory; forming a system-on-chip; Bonding the system-on-chip chip and the memory; The memory is mounted on a circuit board, the memory being located between the system-on-chip chip and the circuit board.

2. The manufacturing method according to claim 1, characterized in that The steps of forming the memory include: Provide at least 2 memory wafers; At least two of the memory wafers are stacked and bonded.

3. The manufacturing method according to claim 1, characterized in that: Also includes: Before mounting the memory on a circuit board, forming a first redistribution layer located on one side of the memory; In the step of mounting the memory on a circuit board, the first redistribution layer is located between the memory and the circuit board.

4. The manufacturing method according to claim 3, characterized in that: The step of forming a memory includes: forming at least two stacked memory wafers, wherein the at least two stacked memory wafers include: a bottom memory wafer; In the step of forming a first redistribution layer located on one side of the memory, the first redistribution layer is formed on the surface of the bottom memory wafer.

5. The manufacturing method according to claim 1, characterized in that: Also includes: Before bonding the system-on-chip chip and the memory, forming a second redistribution layer located on the other side of the memory; In the step of bonding the system-on-chip chip and the memory, the second redistribution layer is located between the system-on-chip chip and the memory.

6. The manufacturing method according to claim 5, characterized in that: The step of forming a memory includes: forming at least two stacked memory wafers, wherein the at least two stacked memory wafers include: a top memory wafer; In the step of forming a second redistribution layer located on the other side of the memory, the second redistribution layer is formed on the surface of the top memory wafer.

7. The manufacturing method according to claim 1, characterized in that: Also includes: Provide auxiliary logic chips; After forming the system-on-chip chip, before bonding the system-on-chip chip to the memory, bonding the system-on-chip chip to the auxiliary logic chip; In the step of bonding the system-on-chip chip and the memory, the system-on-chip chip bonded with the auxiliary logic chip and the memory are bonded, and the auxiliary logic chip is located between the system-on-chip chip and the memory.

8. The manufacturing method according to claim 1, characterized in that: Also includes: providing a substrate; After forming the memory, before mounting the memory on the circuit board, mounting the memory on the substrate; In the step of mounting the memory on a circuit board, the substrate is mounted on the circuit board.

9. The manufacturing method according to claim 1, characterized in that: The bonding step comprises: forming a first structure to be bonded; Thinning the first structure to be bonded through the back surface; forming a through silicon via in the thinned first structure to be bonded; forming a bonding connection layer on the back side of the first structure to be bonded having the through silicon via formed therein; forming a second structure to be bonded, wherein the front surface of the second structure to be bonded has a bonding connection layer; The bonding connection layer of the first structure to be bonded is bonded to the bonding connection layer of the second structure to be bonded.

10. The manufacturing method according to claim 9, characterized in that: The step of forming a memory includes: forming at least two stacked memory wafers, wherein the at least two stacked memory wafers include: a top memory wafer; In the step of forming a first structure to be bonded, the first structure to be bonded comprises a system-on-chip chip; In the step of forming a second structure to be bonded, the second structure to be bonded includes the top memory wafer, the top memory wafer is thinned, and a through silicon via is formed in the top memory wafer.

11. A storage device, characterized in that: include: Circuit boards; A memory, wherein the memory is located on the circuit board; A system-on-chip chip is located on a side of the memory away from the circuit board.

12. The storage device according to claim 11, wherein: The storage device has at least 2 memories; At least two of the memories are stacked along the direction of the connection between the circuit board and the system-on-chip chip.

13. The storage device according to claim 11, wherein: Also includes: A first redistribution layer is located between all memories and the circuit board.

14. The storage device according to claim 13, wherein: The memory closest to the circuit board is the bottom memory; The first redistribution layer is located on a surface of the bottom memory facing the circuit board.

15. The storage device according to claim 11, wherein: Also includes: A second redistribution layer is located between all memories and the system-on-chip chip.

16. The storage device according to claim 15, wherein: The memory closest to the system-on-chip chip is the top memory; The second redistribution layer is located on a surface of the top memory facing the system-on-chip chip.

17. The storage device according to claim 11, wherein: Also includes: An auxiliary logic chip is located between the system-on-chip chip and all memories.

18. The storage device according to claim 11, wherein: Also includes: A substrate is located between the circuit board and all memories.

19. An electronic device, characterized in that: It comprises: a storage device, wherein the storage device is as described in any one of claims 11 to 18.

20. The electronic device according to claim 19, characterized in that Also includes: Thermally conductive adhesive covers a surface of the system-on-chip chip that faces away from the memory.

21. The electronic device according to claim 19, characterized in that: Also includes: A heat dissipation device is arranged on a surface of the system-on-chip chip that is away from the memory.

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