Voltage amplification circuit based on inverter structure and control method thereof

Abstract

The invention discloses a voltage amplification circuit based on an inverter structure and a control method thereof, and belongs to the technical field of integrated circuits, the voltage amplification circuit comprises an input stage and a load stage, the input stage comprises an input stage inverter consisting of a pair of common source NMOS (N-channel Metal Oxide Semiconductor) tubes and a pair of PMOS (P-channel Metal Oxide Semiconductor) tubes, and the load stage comprises a load stage inverter consisting of another pair of common source NMOS tubes and PMOS tubes. The input end of the input-stage phase inverter is connected with power supply voltage, the output end of the input-stage phase inverter is connected with the input end of the load-stage phase inverter, and the resistor is connected between the input end and the output end of the load-stage phase inverter. The high-speed circuit can have high linearity under the condition that the output voltage swing is large, the influence of different transconductance caused by the fact that an input-stage MOS tube of a traditional gm-gm structure enters a linear region and a load-stage MOS tube is still located in a saturation region is avoided, and the performance of the high-speed circuit with high requirements for the output swing and the linearity can be improved. The device has the advantages of being simple in structure and easy to implement, and meanwhile time cost is saved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a voltage amplifier circuit based on an inverter structure and a control method thereof. Background Art

[0002] With the rise of emerging applications such as the Internet of Things, artificial intelligence, and autonomous driving, the demand for semiconductor chips is also increasing. These emerging applications have brought new challenges to chip performance, power consumption, and cost, and have promoted the continuous innovation and development of semiconductor processes. In order to further improve the high-speed and low-power performance of transistors, the transistor process has been continuously reduced. At present, the development has entered the 7-nanometer and below nodes, and even 5-nanometer processes have begun to be studied. At the same time, the breakdown voltage of the core transistors of the chip continues to decrease, which brings greater challenges to the design of large-swing and high-linearity amplifier circuits.

[0003] Traditional amplifier circuits based on CMOS inverter structures usually benefit from the advantages of current multiplexing. The total transconductance is the sum of the device transconductances. Therefore, at a given current, it can provide a higher transconductance. Its structure belongs to a class AB amplifier, which is more efficient than a class A amplifier and is suitable for low-power scenarios. In low power supply voltage situations, this structure has no load of the same level and does not require additional voltage margin. Therefore, it is often used in advanced process low-voltage amplifier circuits. However, when the input signal swing is large, the structural circuit changes from a class A operating mode to a class B operating mode, and its transconductance changes significantly, resulting in limited linearity. To this end, the Chinese invention patent application with publication number CN116155217A, published on May 23, 2023, proposes a "gm-gm" structure to optimize linearity. It is based on a CMOS inverter and combines a diode-connected load composed of an inverter with shorted inputs and outputs, which expands the linearity to a certain extent. However, when the input signal swing increases further, the transistors in the front-stage inverter structure will enter the linear region, while the rear-stage transistors are always in the saturation region due to diode connection, causing the "gm-gm" linear method to fail.

[0004] Therefore, it is necessary to propose a low-voltage and high-linearity amplifier circuit to further optimize the linearity. Summary of the invention

[0005] The purpose of the present invention is to overcome the problem of poor linearity of existing amplifier circuits under large signals. A voltage amplifier circuit based on an inverter structure and a control method thereof are proposed, which can output large signals. At the same time, when the front-stage transistor enters the linear region, the rear-stage transistor is also forced to enter the linear region. The same gm change can ensure the integrity of the signal, and the linearity will not deteriorate under large signals.

[0006] In order to achieve the above object, the present invention adopts the following technical scheme:

[0007] A voltage amplifier circuit based on an inverter structure comprises an input stage and a load stage, wherein the input stage comprises an input stage inverter composed of a pair of common source NMOS tubes and PMOS tubes, and the load stage comprises a load stage inverter composed of another pair of common source NMOS tubes and PMOS tubes, wherein the input end of the input stage inverter is connected to a power supply voltage, the output end of the input stage inverter is connected to the input end of the load stage inverter, and a resistor is connected between the input end and the output end of the load stage inverter.

[0008] Furthermore, the input-stage inverter includes a first PMOS tube MP1 and a second NMOS tube MN2, the source of the first PMOS tube MP1 is connected to the power supply voltage, the gate of the first PMOS tube MP1 is connected to the gate of the second NMOS tube MN2 to form an input node of the input-stage inverter, the drain of the first PMOS tube MP1 is connected to the drain of the second NMOS tube MN2 to form an output node of the input-stage inverter, and the source of the second NMOS tube MN2 is grounded.

[0009] Furthermore, the load-stage inverter includes a third PMOS tube MP3 and a fourth NMOS tube MN4, the source of the third PMOS tube MP3 is connected to the power supply voltage, the gate of the third PMOS tube MP3 is connected to the gate of the fourth NMOS tube MN4 to form an input node of the load-stage inverter, the drain of the third PMOS tube MP3 is connected to the drain of the fourth NMOS tube MN4 to form an output node of the load-stage inverter, and the source of the fourth NMOS tube MN4 is grounded.

[0010] Further, the output node of the input-stage inverter is connected to the input node of the load-stage inverter.

[0011] Further, the input node of the load-stage inverter and the output node of the load-stage inverter are connected via a resistor.

[0012] A control method for a voltage amplifier circuit based on an inverter structure, using the voltage amplifier circuit based on an inverter structure, comprises the following steps: a pair of common source NMOS tubes and PMOS tubes of an input stage are in opposite working states, another pair of common source NMOS tubes and PMOS tubes of a load stage are in opposite working states, the voltage amplifier circuit is equivalent to a common source stage amplifier circuit with a load being a diode, the drain voltage of the input stage and the drain voltage of the load stage are inverted through a resistor, and when the voltage swing becomes larger, the MOS tubes of the input stage and the MOS tubes of the load stage both enter a linear region.

[0013] Further, when the voltage of the output node of the input stage is at a high level, the third PMOS transistor MP3 is turned off, the fourth NMOS transistor MN4 is turned on, and all currents flow through the resistor to reduce the drain voltage of the load stage to a low level.

[0014] Furthermore, when the voltage of the output node of the input stage is at a low level, the fourth NMOS transistor MN4 is turned off, the third PMOS transistor MP3 is turned on, and all currents flow through the resistor to raise the drain voltage of the load stage to a high level.

[0015] Furthermore, the resistor isolates the gate capacitance and the drain capacitance of the load stage, and the capacitance of the output node of the load stage is reduced.

[0016] A semiconductor chip is provided with the voltage amplifier circuit based on the inverter structure.

[0017] Compared with the prior art, the present invention has the following beneficial technical effects:

[0018] The present invention proposes a voltage amplifier circuit based on an inverter structure, in which the output end of an input-stage inverter is connected to the input end of a load-stage inverter, and a resistor is connected between the input end and the output end of the load-stage inverter. The circuit can have high linearity when the output voltage swing is large, avoids the influence of different transconductance caused by the input-stage MOS tube of the traditional gm-gm structure entering the linear region while the load-stage MOS tube is still in the saturation region, can improve the performance of high-speed circuits with high requirements on output swing and linearity, and has the advantages of simple structure and easy implementation, while saving time cost.

[0019] The voltage amplifier circuit based on the inverter structure proposed in the present invention is equivalent to a common source amplifier with a diode as the load when the input signal is a large signal, compared with the traditional load inverter with the gate and drain short-circuited, and the transfer function is:

[0020]

[0021] The load-level MOS tube is always in the saturation region, but the output node voltage is too high or too low, which will force the input-level MOS tube into the linear region. At this time, the linearity of the circuit will be seriously affected. The improvement of the load level in the present invention can better solve this problem.

[0022] Furthermore, the resistor R ensures that the drain voltages of the input-stage MOS tube and the load-stage MOS tube are in anti-phase. By selecting appropriate MOS size and resistor value, when the voltage swing increases, both the input tube and the load tube enter the linear region, and the change trends of the transconductance are close, so the linearity of the circuit is improved.

[0023] Furthermore, when the same large current flows through, the load-level MOS tube enters the linear region, which will reduce its transconductance, which is equivalent to reducing the denominator of the circuit transfer function and increasing the low-frequency gain.

[0024] Furthermore, the gate-drain capacitance of the load-level MOS tube is isolated by resistance, which is equivalent to reducing the capacitance of the output node and improving the circuit bandwidth.

[0025] The voltage amplifier circuit based on the inverter structure proposed by the present invention can improve the performance of high-speed circuits with high requirements on output swing and linearity, and has the advantages of simple structure and easy implementation, while saving time cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings in the specification are used to provide further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0027] Figure 1 The present invention is a circuit diagram of a voltage amplifier circuit based on an inverter structure. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] Embodiment 1

[0031] This embodiment provides a voltage amplifier circuit based on an inverter structure, including an input stage and a load stage, both of which are inverters composed of a pair of common-source NMOS tubes and PMOS tubes, and the difference between the input stage and the load stage is that a resistor is connected between the input and output of the inverter. When the circuit works normally, a pair of different-type MOS tubes in the input stage and the load stage are always one closed and one opened, and the overall circuit is equivalent to a common-source amplifier circuit whose load is a special diode-connected MOS device.

[0032] See also Figure 1 The present invention is a voltage amplifier circuit based on an inverter structure, including an input stage and an output stage; the input stage is used to receive an input signal, including a first PMOS tube MP1 of a common source stage and a second NMOS tube MN2 of a common source stage; the load stage is used to provide an output swing, including a third PMOS tube MP3 of a common source, a fourth NMOS tube MN4 of a common source stage and a resistor R.

[0033] The input stage includes a first PMOS transistor MP1 and a second NMOS transistor MN2.

[0034] The first PMOS tube MP1 includes a source, a gate and a drain; the source of the first PMOS tube MP1 is connected to the power supply voltage; the gate of the first PMOS tube MP1 is connected to the gate of the second NMOS tube MN2 to form an input node; the drain of the first PMOS tube MP1 is connected to the drain of the second NMOS tube MN2, and then connected to the gate of the third PMOS tube MP1 and the gate of the fourth NMOS tube MN2 to form an output node.

[0035] The second NMOS tube MN2 includes a source, a gate and a drain; the source of the second NMOS tube MN2 is connected to the power ground; the gate of the second NMOS tube MN2 is connected to the gate of the first PMOS tube MP1 to form an input node; the drain of the second NMOS tube MN2 is connected to the drain of the first PMOS tube MP1, and then connected to the gate of the third PMOS tube MP1 and the gate of the fourth NMOS tube MN2 to form an output node.

[0036] The load stage includes a third PMOS transistor MP3, a fourth NMOS transistor MN4 and a resistor R.

[0037] The third PMOS tube MP3 includes a source, a gate and a drain; the source of the third PMOS tube MP3 is connected to the power supply voltage; the gate of the third PMOS tube MP3 is connected to the gate of the fourth NMOS tube MN4, and then connected to the drains of the first PMOS tube MP1 and the second NMOS tube MN2 to form an output node; the drain of the third PMOS tube MP3 is connected to the drain of the fourth NMOS tube MN4.

[0038] The fourth NMOS tube MN4 includes a source, a gate and a drain; the source of the fourth NMOS tube MN4 is connected to the power ground; the gate of the fourth NMOS tube MN4 is connected to the gate of the third PMOS tube MP3, and then connected to the drains of the first PMOS tube MP1 and the second NMOS tube MN2 to form an output node; the drain of the fourth NMOS tube MN4 is connected to the drain of the third PMOS tube MP3.

[0039] The specific working process of the voltage amplifier circuit based on the inverter structure of the present invention is as follows:

[0040] The input signal is input from the input node. When the input signal is a large signal, a pair of different types of MOS tubes at the input stage and the load stage are always one closed and one open. The overall circuit is equivalent to a common source amplifier circuit whose load is a special diode-connected MOS device. The input signal is amplified and output from the output node.

[0041] Embodiment 2

[0042] A voltage amplifier circuit based on an inverter structure comprises an input stage and a load stage, wherein the input stage comprises an input stage inverter composed of a pair of common source NMOS tubes and PMOS tubes, and the load stage comprises a load stage inverter composed of another pair of common source NMOS tubes and PMOS tubes, wherein the input end of the input stage inverter is connected to a power supply voltage, the output end of the input stage inverter is connected to the input end of the load stage inverter, and a resistor is connected between the input end and the output end of the load stage inverter.

[0043] Preferably, the input-stage inverter includes a first PMOS tube MP1 and a second NMOS tube MN2, the source of the first PMOS tube MP1 is connected to the power supply voltage, the gate of the first PMOS tube MP1 is connected to the gate of the second NMOS tube MN2 to form an input node of the input-stage inverter, the drain of the first PMOS tube MP1 is connected to the drain of the second NMOS tube MN2 to form an output node of the input-stage inverter, and the source of the second NMOS tube MN2 is grounded.

[0044] Preferably, the load-stage inverter includes a third PMOS tube MP3 and a fourth NMOS tube MN4, the source of the third PMOS tube MP3 is connected to the power supply voltage, the gate of the third PMOS tube MP3 is connected to the gate of the fourth NMOS tube MN4 to form an input node of the load-stage inverter, the drain of the third PMOS tube MP3 is connected to the drain of the fourth NMOS tube MN4 to form an output node of the load-stage inverter, and the source of the fourth NMOS tube MN4 is grounded.

[0045] Preferably, the output node of the input-stage inverter is connected to the input node of the load-stage inverter.

[0046] Preferably, the input node of the load-stage inverter and the output node of the load-stage inverter are connected via a resistor.

[0047] Embodiment 3

[0048] A control method for a voltage amplifier circuit based on an inverter structure, using the voltage amplifier circuit based on an inverter structure described in the second embodiment, comprises the following steps: a pair of common source NMOS tubes and PMOS tubes of an input stage are in opposite working states, another pair of common source NMOS tubes and PMOS tubes of a load stage are in opposite working states, the voltage amplifier circuit is equivalent to a common source stage amplifier circuit with a load being a diode, the drain voltage of the input stage and the drain voltage of the load stage are inverted through a resistor, and when the voltage swing becomes larger, the MOS tubes of the input stage and the MOS tubes of the load stage both enter a linear region.

[0049] Preferably, when the voltage of the output node of the input stage is at a high level, the third PMOS transistor MP3 is turned off, the fourth NMOS transistor MN4 is turned on, and all currents flow through the resistor to reduce the drain voltage of the load stage to a low level.

[0050] Preferably, when the voltage of the output node of the input stage is at a low level, the fourth NMOS transistor MN4 is turned off, the third PMOS transistor MP3 is turned on, and all currents flow through the resistor to raise the drain voltage of the load stage to a high level.

[0051] Preferably, the resistor isolates the gate capacitance and the drain capacitance of the load stage, and the capacitance of the output node of the load stage is reduced.

[0052] Embodiment 4

[0053] A semiconductor chip is provided with a voltage amplifier circuit based on an inverter structure as described in the second embodiment.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit its protection scope. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that after reading the present invention, those skilled in the art can still make various changes, modifications or equivalent substitutions to the specific implementation methods of the invention, but these changes, modifications or equivalent substitutions are all within the protection scope of the pending claims of the invention.

Claims

1. A voltage amplifier circuit based on an inverter structure, characterized in that: The invention comprises an input stage and a load stage. The input stage comprises an input stage inverter composed of a pair of common source NMOS tubes and PMOS tubes. The load stage comprises a load stage inverter composed of another pair of common source NMOS tubes and PMOS tubes. The input end of the input stage inverter is connected to the power supply voltage. The output end of the input stage inverter is connected to the input end of the load stage inverter. A resistor is connected between the input end and the output end of the load stage inverter.

2. The voltage amplifier circuit based on the inverter structure according to claim 1, characterized in that: The input stage inverter includes a first PMOS tube MP1 and a second NMOS tube MN2, wherein the source of the first PMOS tube MP1 is connected to the power supply voltage, the gate of the first PMOS tube MP1 is connected to the gate of the second NMOS tube MN2 to form an input node of the input stage inverter, the drain of the first PMOS tube MP1 is connected to the drain of the second NMOS tube MN2 to form an output node of the input stage inverter, and the source of the second NMOS tube MN2 is grounded.

3. The voltage amplifier circuit based on the inverter structure according to claim 2, characterized in that: The load-level inverter includes a third PMOS tube MP3 and a fourth NMOS tube MN4, the source of the third PMOS tube MP3 is connected to the power supply voltage, the gate of the third PMOS tube MP3 is connected to the gate of the fourth NMOS tube MN4 to form an input node of the load-level inverter, the drain of the third PMOS tube MP3 is connected to the drain of the fourth NMOS tube MN4 to form an output node of the load-level inverter, and the source of the fourth NMOS tube MN4 is grounded.

4. The voltage amplifier circuit based on the inverter structure according to claim 3, characterized in that: The output node of the input stage inverter is connected to the input node of the load stage inverter.

5. The voltage amplifier circuit based on the inverter structure according to claim 3, characterized in that: An input node of the load-stage inverter and an output node of the load-stage inverter are connected via a resistor.

6. A control method for a voltage amplifier circuit based on an inverter structure, using a voltage amplifier circuit based on an inverter structure as claimed in any one of claims 1 to 5, characterized in that: The method comprises the following steps: a pair of common source NMOS tubes and PMOS tubes of the input stage are in opposite working states, another pair of common source NMOS tubes and PMOS tubes of the load stage are in opposite working states, the voltage amplifier circuit is equivalent to a common source amplifier circuit whose load is a diode, the drain voltage of the input stage and the drain voltage of the load stage are inverted through a resistor, and when the voltage swing becomes larger, the MOS tubes of the input stage and the MOS tubes of the load stage both enter the linear region.

7. The control method of a voltage amplifier circuit based on an inverter structure according to claim 6, characterized in that: When the voltage at the output node of the input stage is at a high level, the third PMOS transistor MP3 is turned off, the fourth NMOS transistor MN4 is turned on, and all currents flow through the resistor to reduce the drain voltage of the load stage to a low level.

8. The control method of a voltage amplifier circuit based on an inverter structure according to claim 6, characterized in that: When the voltage of the output node of the input stage is at a low level, the fourth NMOS transistor MN4 is turned off, the third PMOS transistor MP3 is turned on, and all currents flow through the resistor to raise the drain voltage of the load stage to a high level.

9. The control method of a voltage amplifier circuit based on an inverter structure according to claim 6, characterized in that: The resistor isolates the gate capacitance and drain capacitance of the load stage, and the capacitance of the output node of the load stage is reduced.

10. A semiconductor chip, characterized in that: Install a voltage amplifier circuit based on an inverter structure as described in any one of claims 1-5.

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