Printed circuit board

Abstract

The present disclosure provides a printed circuit board including: a first wiring portion including a plurality of first wirings; a first integrated circuit chip connected to one side of the first wiring portion, the first integrated circuit chip configured to convert N signals into one signal, where N is a natural number greater than or equal to 2; a second integrated circuit chip connected to the other side of the first wiring portion opposite to the side connected to the first integrated circuit chip, the second integrated circuit chip configured to convert one signal into N signals; a second-first wiring portion connected to the first integrated circuit chip, the second-first wiring portion including a plurality of second-first wirings; and a second-second wiring portion connected to the second integrated circuit chip, the second-second wiring portion including a plurality of second-second wirings. X and Y1 satisfy Y1 / N < X, where X is the number of the plurality of first wirings, and Y1 is the number of the plurality of second-first wirings.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0116513 filed on September 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Multi-chip packages (including memory chips such as high bandwidth memory (HBM), processor chips such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), and logic chips such as application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs)) have been used to process data that has been growing exponentially due to the recent development of artificial intelligence (AI) technology. In addition, with the rapid increase in the number of CPU cores and GPU cores of server products, chiplet technology that can effectively increase the number of cores has become popular, and the demand for high-density circuits that connect logic semiconductors and memory semiconductors to each other or connect logic semiconductors to logic semiconductors to each other has also increased rapidly. Therefore, chip-to-chip interconnection has been required. Designing boards that allow die-to-die interconnection requires technology for implementing fine circuits, so research has been conducted to implement high-density fine circuits on large-area boards, improve reliability, and increase yield. Summary of the invention

[0004] An aspect of the present disclosure provides a printed circuit board capable of performing a normal function even when a defect occurs.

[0005] Another aspect of the present disclosure provides a printed circuit board having an improved yield even when fine wiring is implemented.

[0006] Another aspect of the present disclosure provides a printed circuit board having improved reliability.

[0007] According to one aspect of the present disclosure, there is provided a printed circuit board, the printed circuit board including: a first wiring portion including a plurality of first wirings; a first integrated circuit chip connected to one side of the first wiring portion, the first integrated circuit chip being configured to convert N signals into one signal (where N is a natural number greater than or equal to 2); a second integrated circuit chip connected to the other side of the first wiring portion opposite to the side connected to the first integrated circuit chip, the second integrated circuit chip being configured to convert one signal into N signals; a second-first wiring portion connected to the first integrated circuit chip, the second-first wiring portion including a plurality of second-first wirings; and a second-second wiring portion connected to the second integrated circuit chip, the second-second wiring portion including a plurality of second-second wirings. X and Y1 may satisfy Y1 / N < X, where X is the number of the plurality of first wirings and Y1 is the number of the plurality of second-first wirings.

[0008] According to one aspect of the present disclosure, there is provided a printed circuit board, the printed circuit board including: a first insulating portion including a plurality of first insulating layers and a plurality of cavities respectively passing through a part of the plurality of first insulating layers; a first integrated circuit chip mounted in one of the plurality of cavities, the first integrated circuit chip including a multiplexer (MUX) circuit; a second integrated circuit chip mounted in another of the plurality of cavities, the second integrated circuit chip including a demultiplexer (DEMUX) circuit; a second insulating portion provided to span a part of the first integrated circuit chip and a part of the second integrated circuit chip; and a first wiring portion provided on and / or in the second insulating portion, the first wiring portion connecting the first integrated circuit chip and the second integrated circuit chip to each other. The first wiring portion may include a plurality of first wirings. At least one of the plurality of first wirings may be open, or at least two of the plurality of first wirings may be short-circuited to each other such that the open first wiring or the short-circuited first wiring is not used as a path between the first integrated circuit chip and the second integrated circuit chip.

[0009] According to one aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a first insulating portion, comprising a plurality of first insulating layers and a plurality of cavities respectively passing through a portion of the plurality of first insulating layers; a first integrated circuit chip, disposed in one of the plurality of cavities; a second integrated circuit chip, disposed in another of the plurality of cavities; a second insulating portion, disposed to span a portion of the first integrated circuit chip and a portion of the second integrated circuit chip; and a wiring portion, disposed on and / or in the second insulating portion, the wiring portion comprising a plurality of wirings connecting the first integrated circuit chip and the second integrated circuit chip to each other. Signal transmission between the first integrated circuit chip and the second integrated circuit chip is performed in the following manner: a defective wiring among the plurality of wirings is bypassed to a dummy wiring among the plurality of wirings through channel switching.

[0010] A printed circuit board according to an example embodiment of the present disclosure may perform a normal function even when a defect occurs.

[0011] A printed circuit board according to example embodiments of the present disclosure may have an improved yield even when fine wiring is implemented.

[0012] A printed circuit board according to example embodiments of the present disclosure may have improved reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram of an example of an electronic device system; Figure 2 is a schematic perspective view of an example of an electronic device; Figure 3 is a schematic plan view of a portion of a printed circuit board according to an example; Figure 4 is a schematic plan view of a variation of a printed circuit board according to an example; Figure 5 is a schematic plan view of a variation of a printed circuit board according to an example; Fig. 6A and Figure 6B is a schematic cross-sectional view of a printed circuit board according to an example; Fig. 7A and Figure 7B is a schematic cross-sectional view of a printed circuit board according to another example; Fig. 8A and Figure 8B is a schematic cross-sectional view of a printed circuit board according to another example; Fig.9A and Fig. 9B is a schematic cross-sectional view of a printed circuit board according to another example; and Fig. 10A and Fig. 10B is a schematic cross-sectional view of a printed circuit board according to another example. DETAILED DESCRIPTION

[0014] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of components in the drawings may be exaggerated or reduced.

[0015] Electronic Devices Figure 1 is a schematic block diagram of an example of an electronic device system.

[0016] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the mainboard 1010. Such components may be connected to other electronic components to be described below via various signal lines 1090.

[0017] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory); application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, or microcontrollers; and logic chips, such as analog-to-digital converters or application-specific integrated circuits (ASICs). However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0018] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth ® , the third generation mobile communication technology (3G) protocol, the fourth generation mobile communication technology (4G) protocol and the fifth generation mobile communication technology (5G) protocol and any other wireless protocol and wired protocol specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with various other wireless standards or protocols or wired standards or protocols or components operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020.

[0019] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 or the network-related components 1030.

[0020] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically or electrically connected to the mainboard 1010 or that are not physically or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0021] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device for processing data.

[0022] Figure 2 is a schematic perspective view of an example of an electronic device.

[0023] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the electronic component 1120 may be the above-mentioned chip-related component, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0024] Printed Circuit Board Figure 3 is a schematic plan view of a portion of a printed circuit board according to an example. Figure 4 is a schematic plan view of a modification of a printed circuit board according to an example.

[0025] Reference Figure 3 According to an example, a semiconductor package may include: a first insulating portion 110 (eg, Fig. 6A and Figure 6B); a first wiring portion 120, disposed on and / or in the first insulating portion 110, the first wiring portion 120 including a plurality of first wirings 121; a first integrated circuit chip 210, connected to one side of the first wiring portion 120; a second integrated circuit chip 220, connected to the opposite side of the first wiring portion 120; a second-first wiring portion 130, having a side connected to the first integrated circuit chip 210, the second-first wiring portion 130 including a plurality of second-first wirings 131; and a second-second wiring portion 140, having a side connected to the second integrated circuit chip 220, the second-second wiring portion 140 including a plurality of second-second wirings 141.

[0026] A printed circuit board according to an example may include first and second integrated circuit chips 210 and 220 disposed on a first insulating part 110. The first and second integrated circuit chips 210 and 220 may respectively include integrated circuits (ICs) in which hundreds to millions of circuits are integrated in a single chip.

[0027] The first integrated circuit chip 210 may include a multiplexer (MUX) circuit that converts N signals (where N is a natural number greater than or equal to 2) into one signal, and the second integrated circuit chip 220 may include a demultiplexer (DEMUX) circuit that converts one signal into N signals (where N is a natural number greater than or equal to 2). A multiplexer circuit (multiplexing circuit) may refer to a circuit that converts multiple signal paths into one signal path and transmits signals using methods such as time delay control. A demultiplexer circuit (inverse multiplexing circuit) may convert one signal path into multiple signal paths and transmit signals using methods such as time delay control. In this case, N presented at a ratio of N:1 of the multiplexer circuit included in the first integrated circuit chip 210 may not correspond to N presented at a ratio of 1:N of the demultiplexer circuit included in the second integrated circuit chip 220.

[0028] The first integrated circuit chip 210 may use a multiplexer circuit to transmit a signal input through the second-first wiring section 130 to the first wiring section 120. In this case, the first integrated circuit chip 210 may select various transmission signal paths. That is, the integrated circuit of the first integrated circuit chip 210 may select a wiring to be used among the plurality of first wirings 121, and may be set not to use a pad connected to an open wiring.

[0029] The second integrated circuit chip 220 may transmit the signal input through the first wiring portion 120 to the second-second wiring portion 140 using a demultiplexer circuit. In this case, the second integrated circuit chip 220 may receive the signal through a pad connected to the first wiring portion 120.

[0030] As shown in Fig. 6A the first integrated circuit chip 210 and the second integrated circuit chip 220 can operate separately from the first semiconductor chip 230 and the second semiconductor chip 240, so that the first integrated circuit chip 210 and the second integrated circuit chip 220 can check and correct defects in the first wiring 121 in a state where the first integrated circuit chip 210 and the second integrated circuit chip 220 are installed. In this case, I2C communication can be used as a method of externally controlling the first integrated circuit chip 210 and the second integrated circuit chip 220 to correct the defective first wiring 121, but the present disclosure is not limited thereto. Any communication method for controlling an integrated circuit (such as SPI communication) can be used without limitation. In this case, I2C communication that can perform control without using an internal clock can be preferably used.

[0031] The second-first wiring portion 130 can be an input portion input to the first integrated circuit chip 210, and the first wiring portion 120 can be an output portion of the first integrated circuit chip 210. In addition, the first wiring portion 120 can be an input portion of the second integrated circuit chip 220, and the second-second wiring portion 140 can be an output portion of the second integrated circuit chip 220.

[0032] In this case, when the number of the plurality of first wirings 121 is X, the number of the plurality of second-first wirings 131 is Y1, and the number of the plurality of second-second wirings 141 is Y2, Y1 / N < X can be satisfied, and Y2 / N < X can be satisfied. With respect to the first integrated circuit chip 210, the number of the plurality of first wirings 121 is greater than the number of input signals converted by the first integrated circuit chip 210. That is, in the process of transmitting a signal of a printed circuit board input through the second-first wiring portion 130 and output to the second-second wiring portion 140 through the first wiring portion 120, the plurality of first wirings 121 of the first wiring portion 120 can include a larger number of wirings than the required number of wirings. In this case, the larger number of wirings can be used as dummy elements, that is, dummy channels (or dummy wirings). In this case, the number of dummy channels can be X - (Y1 / N), or can be X - (Y2 / N).

[0033] Many defects may occur in the operation of manufacturing a printed circuit board. One of the defects may be an open circuit phenomenon. The open circuit phenomenon may be a concept including a state in which a wiring is cut or a state in which a wiring has too high resistance, and may mean a state in which two components cannot be electrically connected to each other. In other words, the process of patterning the wiring may include the following operations: removing at least a portion of the metal included in the wiring; however, in this case, a portion of the metal that needs to be connected to the wiring may be removed to cause an open circuit defect. Generally, when an open circuit phenomenon occurs during wiring patterning, the printed circuit board may have a defect and may therefore fail to perform its function. However, the printed circuit board according to the example may include a greater number of first wirings 121 than the number of necessary first wirings 121. Therefore, even when an open circuit phenomenon occurs in one of the first wirings 121, the wiring in which the open circuit phenomenon occurs may be switched to another additional wiring. In other words, signal transmission may be performed by bypassing the defective wiring to another wiring using lane shifting. In this case, channel switching may be performed by immediately changing the defective channel to a dummy channel, rather than changing the defective channels to subsequent channels one by one in sequence.

[0034] Figure 3 The first wiring section 120 is shown without an open circuit phenomenon. Figure 4 1 is a plan view of the first wiring section 120 in which an open circuit phenomenon has occurred. As a non-limiting specific example, the first integrated circuit chip 210 is shown as performing a 2:1 signal conversion, and the second integrated circuit chip 220 is shown as performing a 1:2 signal conversion. The number of input signals input to the first integrated circuit chip 210 is shown as 16, and the number of output signals output by the second integrated circuit chip 220 is shown as 16. In addition, the number of the plurality of first wirings 121 of the first wiring section 120 is shown as 10. That is, as Figure 3 and Figure 4 As shown in , X may be 10, Y1 and Y2 may be 16, N may be 2, Y1 / N<X may be satisfied, and Y2 / N<X may be satisfied. However, such a configuration is only an example, and the number of signals and wirings is not limited thereto. Figure 3 As shown in , the number of first wirings 121 required in the first wiring portion 120 may be 8, but the number of the plurality of first wirings 121 may be implemented as 10, so that two first wirings 121 may be dummy channels.

[0035] Reference Figure 4, at least one of the plurality of first wirings 121 may be open-circuited. When at least one of the plurality of first wirings 121 is open-circuited, the first integrated circuit chip 210 and the second integrated circuit chip 220 may not be connected to each other through the open-circuited wiring. That is, the open-circuited wiring may not electrically connect the first integrated circuit chip 210 and the second integrated circuit chip 220 to each other. This may be because: in the operation of manufacturing the printed circuit board, a defect occurs due to the open-circuit phenomenon in the operation of implementing the first wiring 121. However, the defect can be solved by bypassing the open-circuited wiring to a dummy channel using the first integrated circuit chip 210 and the second integrated circuit chip 220. In this case, the first integrated circuit chip 210 and the second integrated circuit chip 220 may be designed to use a dummy channel instead of a defective wiring. However, the present disclosure is not limited thereto, and channel switching may also be performed by skipping the defective wiring and connecting subsequent wirings in sequence. The printed circuit board according to the example can detect defects occurring in the first wiring portion 120 before mounting the first semiconductor chip 230 and the second semiconductor chip 240, so that it can be more conducive to designing the printed circuit board to bypass the defective wiring directly to the dummy channel, rather than using the first semiconductor chip 230 and the second semiconductor chip 240 to move the defective wiring one by one to each adjacent wiring.

[0036] In this case, when the number of open-circuit wirings among the plurality of first wirings 121 is Z, Y1 / N≤XZ and Y2 / N≤XZ may be satisfied. That is, the printed circuit board may be designed to include a greater number of dummy channels than the number of wirings having defects caused by the open-circuit phenomenon. That is, when dummy channels are designed in a design operation, even when a certain number of defects occur, normal operation may be performed by switching to dummy channels using channel switching. In the event that a wiring defect occurs in a conventional printed circuit board, the printed circuit board may not be able to perform its function and may therefore be discarded. However, in a printed circuit board according to the example, even when a defect occurs, the defective wiring may be bypassed to the dummy channel so that the occurrence of a certain degree of defects may not be identified as a defect occurring in the entire printed circuit board. That is, even in the event that a defect occurs in a portion of the first wiring portion 120, the entire printed circuit board may not be defective and may therefore be operated as a high-quality printed circuit board. Therefore, the printed circuit board may have an improved yield. In addition, as Figure 4 As shown in , one or more first wirings among the plurality of first wirings 121 may be disposed in a region between a defective wiring and a dummy wiring.

[0037] Reference Figure 5, at least two of the plurality of first wirings 121 of the first wiring section 120 may be short-circuited to each other. When at least two of the plurality of first wirings 121 are short-circuited to each other, the first integrated circuit chip 210 and the second integrated circuit chip 220 may not exchange electrical signals due to the short-circuited wiring. That is, the first integrated circuit chip 210 and the second integrated circuit chip 220 may not be electrically connected to each other due to the short-circuited wiring. In this case, the first integrated circuit chip 210 and the second integrated circuit chip 220 not being connected to each other may mean a state in which electrical signal transmission from the first integrated circuit chip 210 to the second integrated circuit chip 220 cannot be performed, and the short-circuited wiring cannot be used as a path between the first integrated circuit chip 210 and the second integrated circuit chip 220, rather than the first integrated circuit chip 210 and the second integrated circuit chip 220 not being physically connected to each other. That is, the short-circuit phenomenon may be a phenomenon in which a defect occurs in the operation of manufacturing a printed circuit board. However, the printed circuit board according to the example can handle the defect by bypassing the two short-circuited wirings into different dummy channels respectively using the first integrated circuit chip 210 and the second integrated circuit chip 220. In this case, the first integrated circuit chip 210 and the second integrated circuit chip 220 may be designed to use a dummy channel instead of a defective wiring. However, the present disclosure is not limited thereto, and channel switching may be performed by skipping defective wiring and sequentially connecting subsequent wirings. The printed circuit board according to the example may detect defects occurring in the first wiring portion 120 before mounting the first semiconductor chip 230 and the second semiconductor chip 240, so that it may be more advantageous to design the printed circuit board to bypass the defective wiring directly to the dummy channel, rather than using the first semiconductor chip 230 and the second semiconductor chip 240 to move the defective wiring one by one to each adjacent wiring.

[0038] For defects caused by short circuits, similar to the case of defects caused by open circuit phenomena, the number of dummy channels may be designed to be greater than the number of wirings in which short circuits occur. That is, as described above, when the number of wirings in which short circuits occur is Z, Y1 / N≤XZ and Y2 / N≤XZ may be satisfied. A short circuit may occur between at least two different wirings among the plurality of first wirings 121, so Z may be greater than or equal to 2. In this case, a short circuit may not occur only in one portion, but may occur in two or more portions respectively, or defects in which three or more first wirings 121 are short-circuited to each other may occur.

[0039] Wiring defects in printed circuit boards are not limited to Figure 4 or Figure 5 The wiring defects shown in and can be further varied. For example, Figure 4 The defects caused by the open circuit phenomenon shown in Figure 5The defects caused by short circuits shown in may occur simultaneously. As another example, wiring defects may occur in various ways such as resistance increase caused by impurities or defects in some wiring caused by undulations. However, the present disclosure is not limited thereto, and there may be defects that occur when the first wiring portion 120 is connected to the first integrated circuit chip 210 and / or the second integrated circuit chip 220, such as defects in vias connected to the wiring, defects that occur during welding, etc. That is, as described above, various defects can be overcome by changing the wiring to a dummy channel, and a high-quality printed circuit board can be provided.

[0040] The printed circuit board according to the example can control defects caused by the open circuit phenomenon even in the operation before the first semiconductor chip 230 and the second semiconductor chip 240 are installed. For example, in conventional printed circuit boards and packages, defects can usually be controlled after all semiconductor chips are installed. However, in the printed circuit board according to the example, defects can be controlled even in the operation before the first semiconductor chip 230 and the second semiconductor chip 240 are installed. Defects in the wiring can be checked in the state where the first integrated circuit chip 210 and the second integrated circuit chip 220 have been installed, and another wiring can be used by the first integrated circuit chip 210 and the second integrated circuit chip 220 according to the inspection result, thereby improving the design freedom of the semiconductor chip. That is, in general, it may be necessary to use a semiconductor chip with a channel switching function, and it may be necessary to perform a separate correction operation by the semiconductor chip. However, the printed circuit board according to the example can freely use the first wiring 121 without the need for a semiconductor chip. Therefore, power consumption may not be required, and wiring defects in the printed circuit board can be overcome before the semiconductor chip is installed. That is, unlike a conventional printed circuit board or a semiconductor package, the printed circuit board according to the example can control defective wiring even when the first semiconductor chip 230 and the second semiconductor chip 240 are not installed. That is to say, Figure 3 and Figure 4 As shown in FIG. 1 , even when the first semiconductor chip 230 and the second semiconductor chip 240 are not included, the printed circuit board according to the example may complete the quality inspection and may be used as a printed circuit board.

[0041] In the printed circuit board according to the example, the first semiconductor chip 230 and the second semiconductor chip 240 may be electrically connected to each other, and may have a signal path flowing in the order of the first semiconductor chip 230, the second-first wiring part 130, the first integrated circuit chip 210, the first wiring part 120, the second integrated circuit chip 220, the second-second wiring part 140 and the second semiconductor chip 240. The signal path can be confirmed by analyzing the surface of each layer of the completed printed circuit board one by one. That is, before the first semiconductor chip 230 and the second semiconductor chip 240 are connected to each other or in a state where the first semiconductor chip 230 and the second semiconductor chip 240 are removed, the surface of the upper layer of the first wiring part 120 connected to the first integrated circuit chip 210 and the second integrated circuit chip 220 can be removed one by one to confirm whether the second-first wiring part 130 and the second-second wiring part 140 are connected to the first integrated circuit chip 210 and the second integrated circuit chip 220, respectively. The above process may be repeatedly performed to confirm that the signal path has been formed. The present disclosure is not limited thereto, and any other method of analyzing the signal path may be used without limitation.

[0042] Figure 3 and Figure 4 The connection between the first integrated circuit chip 210 and the second integrated circuit chip 220 with respect to the wiring of the first wiring portion 120 of the printed circuit board is shown. In the printed circuit board, the arrangement relationship between the first integrated circuit chip 210 and the second integrated circuit chip 220 and the arrangement relationship between the first wiring portion 120, the second-first wiring portion 130 and the second-second wiring portion 140 may be varied. Hereinafter, the arrangement relationship will be described in detail using a cross-sectional view.

[0043] Fig. 6A and Figure 6B is a schematic cross-sectional view of a printed circuit board according to an example.

[0044] The first insulating part 110 may include a plurality of first insulating layers 111, each of which may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material prepared by impregnating an inorganic filler, an organic filler, and / or a glass fiber (such as a glass fabric such as glass cloth) in the above resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the first insulating layer 111 may be a prepreg (PPG) or a copper-clad resin (RCC), but the present disclosure is not limited thereto, and may be an Ajinomoto deposited film (ABF), a photosensitive dielectric (PID), FR-4, bismaleimide triazine (BT), etc. However, the present disclosure is not limited thereto, and other materials with excellent rigidity may be used as needed. The first insulating layer 111 may include an insulating layer as a core layer.

[0045] The first wiring portion 120 disposed on and / or in the first insulating portion 110 may include a plurality of first wirings 121 and a plurality of first vias 122. Each of the plurality of first wirings 121 and each of the plurality of first vias 122 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. Each of the first wirings 121 and the first vias 122 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the chemical copper plating layer as the electroless plating layer. As needed, each of the first wirings 121 and the first vias 122 may also include a copper foil.

[0046] The first wiring 121 and the first via 122 may perform various functions according to the design of the corresponding layer. For example, a ground pattern / ground via, a power pattern / power via, a signal pattern / signal via, etc. may be included. Here, in addition to the ground pattern / ground via, the power pattern / power via, etc., the signal pattern / signal via may include a pattern / via for transmitting various signals (e.g., a data signal, etc.). The above patterns may include a line pattern, a surface pattern and / or a pad pattern, respectively.

[0047] The first via 122 may include a micro via. The micro via may be a filled via formed by filling a via hole with a metal material, or a conformal via formed by disposing a metal material along a wall surface of the via hole. The micro via may be provided as a stacked via and / or a staggered via.

[0048] The first wiring 121 and the first via 122 may be formed integrally with each other, but the present disclosure is not limited thereto. The first wiring 121 and / or the first via 122 may be formed using one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-sealing (TT) process, and a subtractive process, but the present disclosure is not limited thereto, and any method capable of forming a circuit in a printed circuit board may be used without limitation.

[0049] The second-first wiring portion 130 and the second-second wiring portion 140 may also be disposed on and / or in the first insulating portion 110, and the second-first wiring portion 130 may include the second-first wiring 131 and the second-first via 132, and the second-second wiring portion 140 may include the second-second wiring 141 and the second-second via 142. The second-first wiring portion 130 and the second-second wiring portion 140 may be connected to the first integrated circuit chip 210 and the second integrated circuit chip 220, respectively. In addition, the first semiconductor chip 230 may be connected to the other side of the second-first wiring portion 130 opposite to the side connected to the first integrated circuit chip 210, and the second semiconductor chip 240 may be connected to the other side of the second-second wiring portion 140 opposite to the side connected to the second integrated circuit chip 220.

[0050] The second-first wiring 131 included in the second-first wiring portion 130 and the second-second wiring 141 included in the second-second wiring portion 140 may respectively have the same features as those of the first wiring 121, but the present disclosure is not necessarily limited thereto, and may have features different from those of the first wiring 121. Similarly, the second-first via 132 and the second-second via 142 may respectively have the same features as those of the first via 122.

[0051] The printed circuit board according to the example may further include a third wiring portion 150 disposed on and / or in the first insulating portion 110. The third wiring portion 150 may be connected to the first integrated circuit chip 210 and the second integrated circuit chip 220, and may also be connected to the first semiconductor chip 230 and the second semiconductor chip 240. The third wiring portion 150 may include a third wiring 151 and a third via 152, and the third wiring 151 and the third via 152 may have the same features as the first wiring 121 and the first via 122, respectively, but the present disclosure is not necessarily limited thereto. The third wiring portion 150 may differ from the first wiring portion 120, the second-first wiring portion 130, and the second-second wiring portion 140 in that the third wiring portion 150 is configured to connect two components of the first semiconductor chip 230, the second semiconductor chip 240, the first integrated circuit chip 210, and the second integrated circuit chip 220 to each other.

[0052] The first integrated circuit chip 210 may include a body 211 and a pad 212, and the second integrated circuit chip 220 may include a body 221 and a pad 222. The integrated circuit may be implemented in the bodies 211 and 221, and may be mounted on a printed circuit board through the pads 212 and 222. With respect to the features of the first integrated circuit chip 210 and the second integrated circuit chip 220, the above description may be applied, and thus a repeated description will be omitted.

[0053] The printed circuit board according to the example may include the connection members 300, at least one of which connects the first integrated circuit chip 210, the first wiring part 120, the second-first wiring part 130, and the third wiring part 150 to each other, and at least another of the connection members 300 connects the second integrated circuit chip 220, the first wiring part 120, the second-second wiring part 140, and the third wiring part 150 to each other. The connection member 300 may be formed using a conductive material such as solder, but the material of the connection member 300 is not particularly limited thereto. In addition, the connection method of the connection member 300 is not limited thereto, and may include a pad, a solder ball, a pin, etc. In addition, the connection member 300 may be formed using multiple layers or a single layer. When formed using multiple layers, the connection member 300 may include a copper column and solder. When formed using a single layer, the connection member 300 may include tin-silver solder or copper, but the present disclosure is not limited thereto. The number and arrangement of the connection members 300 and the distance between the connection members 300 are not particularly limited, and may be fully modified by those skilled in the art according to their design.

[0054] As long as the first integrated circuit chip 210 and the second integrated circuit chip 220 include the above-mentioned circuits, they may be used without limitation, and they may have other functions, for example, they may have the functions of a controller, a processor, or a memory in the same manner as other semiconductor chips.

[0055] Reference Figure 6B , the printed circuit board according to an example may further include a first semiconductor chip 230 and a second semiconductor chip 240 .

[0056] The first semiconductor chip 230 and the second semiconductor chip 240 may be integrated circuits (ICs) that integrate hundreds to millions of circuits into a single chip. Each of the ICs may be a processor chip, specifically, an application processor (AP), such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, but the present disclosure is not limited thereto. For example, each of the ICs may be a logic chip, such as an analog-to-digital converter, an application-specific IC (ASIC), a memory controller (MC) chip, or a field programmable gate array (FPGA); or each of the ICs may be a memory chip, such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, a resistive random access memory (RRAM) chip, an electrically erasable programmable read-only memory (EEPROM) chip, or a high bandwidth memory (HBM) chip, and the above chips may be provided in combination with each other.

[0057] The first semiconductor chip 230 may include a body 231 and a pad 232, and the second semiconductor chip 240 may include a body 241 and a pad 242. The surface of the first semiconductor chip 230 provided with the pad 232 of the wiring portion for connecting to the printed circuit board may be an effective surface, the surface of the second semiconductor chip 240 provided with the pad 242 of the wiring portion for connecting to the printed circuit board may be an effective surface, and the surfaces of the first semiconductor chip 230 and the second semiconductor chip 240 opposite to the effective surface may be an ineffective surface, but the present disclosure is not limited thereto. The first semiconductor chip 230 and the second semiconductor chip 240 may be formed based on an effective wafer, respectively. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a substrate included in the bodies 231 and 241. Various circuits may be formed in the first semiconductor chip 230 and the second semiconductor chip 240.

[0058] The first semiconductor chip 230 may be connected to each of the second-first wiring portion 130 and the third wiring portion 150 through the connection member 300 , and the second semiconductor chip 240 may be connected to each of the second-second wiring portion 140 and the third wiring portion 150 through the connection member 300 .

[0059] The wiring parts of the printed circuit board according to the example may be connected to each other so that the signal path between them has the shortest distance. In particular, the path between the second-first wiring part 130 and the second-second wiring part 140 may preferably be implemented as the shortest path. That is, the first semiconductor chip 230 and the first integrated circuit chip 210 may preferably be connected to each other to have the shortest path between them, and the second integrated circuit chip 220 and the second semiconductor chip 240 may preferably be connected to each other to have the shortest path between them, but the present disclosure is not necessarily limited to this. The first integrated circuit chip 210 and the second integrated circuit chip 220 may correct defects occurring in the first wiring part 120. Therefore, the first semiconductor chip 230 and the first integrated circuit chip 210 may be connected to each other to have the shortest path between them, and the second semiconductor chip 240 and the second integrated circuit chip 220 may be connected to each other to have the shortest path between them, thereby reducing the defect rate.

[0060] The printed circuit board according to the example is not limited to Fig. 6A and Figure 6B In particular, the lower portion of the first insulating portion 110 may further include other insulating layers and wiring layers, and Fig. 6A and Figure 6B Only the upper side of the printed circuit board is shown, and it may also include conventional components of the printed circuit board. For example, the printed circuit board according to the example may also include a solder resist layer. That is, the printed circuit board may also include components that can be used by those skilled in the art.

[0061] Fig. 7A and Figure 7B is a schematic cross-sectional view of a printed circuit board according to another example.

[0062] Reference Fig. 7A and Figure 7B , the first insulating portion 110 may further include a cavity C passing through at least a portion of the plurality of first insulating layers 111. The cavity C is shown as passing through at least some of the plurality of first insulating layers 111, but the present disclosure is not limited thereto, and the cavity C may pass through only a portion of one first insulating layer 111. A known method of forming the cavity C may be used. Various methods of forming the cavity C may be used so that the shape of the cavity C may vary. The first integrated circuit chip 210 and the second integrated circuit chip 220 may be mounted in the cavity C, respectively.

[0063] Fig. 6A and Figure 6B The configuration of the printed circuit board according to the example shown in FIG. 1 except for the cavity C can be applied to Fig. 7A and Figure 7B A printed circuit board according to another example is shown in the figure, and thus repeated descriptions related thereto will be omitted.

[0064] Fig. 8A and Figure 8B is a schematic cross-sectional view of a printed circuit board according to another example.

[0065] Reference Fig. 8A and Figure 8B , the first insulating part 110 may further include a core 112. The core 112 may include a material prepared by impregnating an inorganic filler, an organic filler and / or a glass fiber (such as a glass fabric using glass cloth as an example) in a resin, and may be an insulating material such as a prepreg (PPG), a resin clad copper (RCC), a copper clad laminate (CCL), etc., but the present disclosure is not limited thereto. In this case, the core 112 may be thicker than the first insulating layer 111. In addition, the core 112 may include a cavity C (or, may be referred to as a through portion C).

[0066] The first integrated circuit chip 210 and the second integrated circuit chip 220 may be respectively mounted in the cavity C and may be respectively connected through vias. That is, the first integrated circuit chip 210 and the second integrated circuit chip 220 may be connected to the first wiring 121 through the first via 122. In addition, the first integrated circuit chip 210 may be connected to each of the second-first via 132 and the third via 152, and the second integrated circuit chip 220 may be connected to each of the second-second via 142 and the third via 152. In this case, the first semiconductor chip 230 may be directly disposed on the first integrated circuit chip 210. In this case, it may be advantageous to connect the first semiconductor chip 230 and the first integrated circuit chip 210 to each other so that there is a shortest path between the first semiconductor chip 230 and the first integrated circuit chip 210. The first semiconductor chip 230 and the first integrated circuit chip 210 may be connected to each other through the second-first via 132. In this case, the second-first via 132 may have a stacked via structure so that the first semiconductor chip 230 and the first integrated circuit chip 210 are connected to each other so that there is a shortest path between the first semiconductor chip 230 and the first integrated circuit chip 210. The second semiconductor chip 240 and the second integrated circuit chip 220 may also have the same arrangement, but the present disclosure is not necessarily limited thereto.

[0067] In addition to the arrangement of the first insulating portion 110, the first integrated circuit chip 210 and the second integrated circuit chip 220 and the connection between the first insulating portion 110, the first integrated circuit chip 210 and the second integrated circuit chip 220, Fig. 6A and Figure 6B The structure of the printed circuit board according to the example shown in Fig. 7A and Figure 7B The structure of the printed circuit board according to another example shown in Fig. 8A and Figure 8B A printed circuit board according to another example is shown in the figure, and thus repeated descriptions related thereto will be omitted.

[0068] Fig.9A and Fig. 9B is a schematic cross-sectional view of a printed circuit board according to another example.

[0069] Reference Fig.9A and Fig. 9B, the first semiconductor chip 230 may be directly disposed on the first integrated circuit chip 210 to overlap a portion of the first integrated circuit chip 210. Even in this case, the first semiconductor chip 230 and the first integrated circuit chip 210 may be connected to each other to have the shortest path therebetween, and the second-first via 132 may have a stacked via structure. The second semiconductor chip 240 and the second integrated circuit chip 220 may also have the same arrangement, but the present disclosure is not necessarily limited thereto.

[0070] In addition to the arrangement of the first semiconductor chip 230 and the second semiconductor chip 240, Fig. 6A and Figure 6B The structure of the printed circuit board according to the example shown in Fig. 7A and Figure 7B The structure of the printed circuit board according to another example is shown in Fig. 8A and Figure 8B The structure of the printed circuit board according to another example shown in Fig.9A and Fig. 9B A printed circuit board according to another example is shown in the figure, and thus repeated descriptions related thereto will be omitted.

[0071] Fig. 10A and Fig. 10B is a schematic cross-sectional view of a printed circuit board according to another example.

[0072] Reference Fig. 10A and Fig. 10B , the first insulating portion 110 may be disposed on the first integrated circuit chip 210 and the second integrated circuit chip 220, and the printed circuit board according to another example may further include a second insulating layer 113 having a cavity C. The second insulating layer 113 may include an insulating material, and the insulating material may be selected from the same insulating material group as the insulating material group of the first insulating layer 111, and may include the same insulating material as the insulating material of the first insulating layer 111, but the present disclosure is not necessarily limited thereto. In this case, the second insulating layer 113 may be disposed to be spaced apart from the first insulating layer 111, and the first wiring portion 120 implemented in the first insulating portion 110 may be connected to the first integrated circuit chip 210 and the second integrated circuit chip 220 through the connecting member 300.

[0073] The printed circuit board according to another example may have an additional form in which the first wiring portion 120 connecting the first integrated circuit chip 210 and the second integrated circuit chip 220 to each other has a predetermined structure and is attached on the first integrated circuit chip 210 and the second integrated circuit chip 220. Fig. 10A and Fig. 10BThe first insulating portion 110 connecting the first integrated circuit chip 210 and the second integrated circuit chip 220 to each other shown in FIG. 1 can overcome defects occurring in the first wiring portion 120 implemented in the first insulating portion 110. Since such a structure is made possible, wiring defects occurring in a connection structure connecting semiconductor chips to each other can be solved.

[0074] In this case, the first integrated circuit chip 210 and the first semiconductor chip 230 may be directly connected to each other through the connection member 300, and the second integrated circuit chip 220 and the second semiconductor chip 240 may be directly connected to each other through the connection member 300. Since the semiconductor chip and the integrated circuit chip may be directly connected to each other, the second-first wiring portion 130 and the second-second wiring portion 140 may be omitted, and a defect rate that may occur when the semiconductor chip and the integrated circuit chip are connected to each other may be reduced.

[0075] exist Fig. 10A and Fig. 10B , the first insulating portion 110 is shown as being disposed on the second insulating layer 113, but the present disclosure is not necessarily limited thereto, and the first insulating portion 110 may also be disposed in the cavity C of the second insulating layer 113. In this case, the first semiconductor chip 230 and the second semiconductor chip 240 may be disposed on the second insulating layer 113, and the first integrated circuit chip 210 and the second integrated circuit chip 220 may be disposed in the cavity formed in the second insulating layer 113. Even in this case, the first insulating portion 110 and the first wiring portion 120 may also serve as a connection structure that connects the first semiconductor chip 230 and the second semiconductor chip 240 to each other.

[0076] In addition to the arrangement of the first insulating portion 110 and the connection between the semiconductor chip and the integrated circuit chip, Fig. 6A and Figure 6B The structure of the printed circuit board according to the example shown in Fig. 7A and Figure 7B The structure of the printed circuit board according to another example is shown in Fig. 8A and Figure 8B The structure of the printed circuit board according to another example is shown in Fig.9A and Fig. 9B The structure of the printed circuit board according to another example shown in Fig. 10A and Fig. 10B A printed circuit board according to another example is shown in the figure, and thus repeated descriptions related thereto will be omitted.

[0077] As used herein, a cross-sectional view may indicate a view of the cross-sectional shape of an object when the object is cut vertically, or a view showing the cross-sectional shape of an object when the object is viewed from a side view. In addition, a plan view may be a view showing the shape of an object when the object is cut horizontally, or may be a view showing the planar shape of an object when the object is viewed from a top view or a bottom view.

[0078] As used herein, for convenience, "upper" in upper side, upper part, upper surface, etc. is used to indicate a direction toward a surface on which electronic components can be mounted based on a cross section of the drawings, and "lower" in lower side, lower part, lower surface, etc. is used to indicate the opposite direction thereof. However, the above directions are defined for convenience of description. Therefore, it should be understood that the scope of the claims is not particularly limited by the above directions.

[0079] As used herein, the term "connection" may refer not only to "direct connection" but also to "indirect connection" via an adhesive layer or the like. The term "electrical connection" may include both a case where components are "physically connected" and a case where components are "not physically connected." In addition, the terms "first," "second," and the like may be used to distinguish a component from another component, and may not limit the order and / or importance associated with the components, etc. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of example embodiments.

[0080] As used herein, the term "exemplary embodiment" or "example" is provided to emphasize a particular feature, structure, or characteristic, and does not necessarily refer to the same exemplary embodiment or "example". In addition, in one or more exemplary embodiments, the particular characteristics or features may be combined in any suitable manner. For example, unless described to be contrary to or inconsistent with the contents in other exemplary embodiments, the contents described in a particular exemplary embodiment may also be used in other exemplary embodiments even if not described in other exemplary embodiments.

[0081] The terms used herein are only used to describe specific example embodiments, and the present disclosure is not limited thereby.As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0082] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A first wiring portion, including a plurality of first wirings; A first integrated circuit chip, connected to one side of the first wiring portion, the first integrated circuit chip being configured to convert N signals into one signal, where N is a natural number greater than or equal to 2; A second integrated circuit chip, connected to the other side of the first wiring portion opposite to the side connected to the first integrated circuit chip, the second integrated circuit chip being configured to convert one signal into N signals; A second-first wiring portion, connected to the first integrated circuit chip, the second-first wiring portion including a plurality of second-first wirings; and A second-second wiring portion, connected to the second integrated circuit chip, the second-second wiring portion including a plurality of second-second wirings, where X and Y1 satisfy Y1 / N < X, where X is the number of the plurality of first wirings, and Y1 is the number of the plurality of second-first wirings.

2. The printed circuit board according to claim 1, wherein: X and Y2 satisfy Y2 / N < X, where Y2 is the number of the plurality of second-second wirings.

3. The printed circuit board according to claim 1, wherein: At least one of the plurality of first wirings is open, such that the first integrated circuit chip and the second integrated circuit chip are not connected to each other through the at least one first wiring.

4. The printed circuit board according to claim 3, wherein: X, Y1, and Z satisfy Y1 / N ≤ X - Z, where Z is the number of the at least one first wiring.

5. The printed circuit board according to claim 1, wherein At least two of the plurality of first wirings are short-circuited to each other, such that the short-circuited first wirings are not used as a path between the first integrated circuit chip and the second integrated circuit chip.

6. The printed circuit board according to claim 1, the printed circuit board further comprising: A first insulating portion, wherein the first wiring portion, the second-first wiring portion, and the second-second wiring portion are each disposed on and / or in the first insulating portion.

7. The printed circuit board according to claim 6, wherein: The first integrated circuit chip and the second integrated circuit chip are respectively disposed on the first insulating portion.

8. The printed circuit board according to claim 6, wherein, The first insulating portion includes a plurality of first insulating layers and a cavity penetrating at least a part of the plurality of first insulating layers, and The first integrated circuit chip is disposed in the cavity.

9. The printed circuit board according to claim 8, the printed circuit board further comprising: A connecting member, connecting the first integrated circuit chip and the second-first wiring portion to each other; And Another connecting member, connecting the first integrated circuit chip and the first wiring portion to each other.

10. The printed circuit board according to claim 6, wherein, The first insulating portion includes a core layer having a through portion, The first integrated circuit chip and the second integrated circuit chip are disposed in the through portion.

11. The printed circuit board according to claim 10, wherein, The first wiring portion includes a plurality of first vias, the plurality of first vias passing through at least a portion of the first insulating portion, and at least one of the plurality of first vias connects the plurality of first wirings to the first integrated circuit chip, and at least another first via of the plurality of first vias connects the plurality of first wirings to the second integrated circuit chip.

12. The printed circuit board according to any one of claims 1 to 11, wherein: The first integrated circuit chip includes a multiplexer circuit, and The second integrated circuit chip includes a demultiplexer circuit.

13. The printed circuit board according to any one of claims 1 to 11, further comprising: a first semiconductor chip connected to the second-first wiring portion; as well as A second semiconductor chip is connected to the second-second wiring portion.

14. The printed circuit board according to claim 13, wherein: The first semiconductor chip and the first integrated circuit chip are connected to each other through the second-first wiring portion to have a shortest path between the first semiconductor chip and the first integrated circuit chip, and The second semiconductor chip and the second integrated circuit chip are connected to each other through the second-second wiring portion to have a shortest path between the second semiconductor chip and the second integrated circuit chip.

15. A printed circuit board, comprising: A first insulating portion including a plurality of first insulating layers and a plurality of cavities respectively passing through a portion of the plurality of first insulating layers; a first integrated circuit chip mounted in one of the plurality of cavities, the first integrated circuit chip comprising a multiplexer circuit; a second integrated circuit chip mounted in another cavity of the plurality of cavities, the second integrated circuit chip comprising a demultiplexer circuit; a second insulating portion, arranged to span a portion of the first integrated circuit chip and a portion of the second integrated circuit chip; and a first wiring portion disposed on and / or in the second insulating portion, the first wiring portion connecting the first integrated circuit chip and the second integrated circuit chip to each other, wherein the first wiring portion includes a plurality of first wirings, and At least one of the multiple first wirings is open, or at least two of the multiple first wirings are short-circuited to each other, so that the open first wiring or the short-circuited first wiring is not used as a path between the first integrated circuit chip and the second integrated circuit chip.

16. The printed circuit board according to claim 15, further comprising: a first semiconductor chip arranged to straddle another portion of the first integrated circuit chip and a first portion of the first insulating portion; as well as A second semiconductor chip is provided to straddle another portion of the second integrated circuit chip and a second portion of the first insulating portion.

17. A printed circuit board, comprising: A first insulating portion including a plurality of first insulating layers and a plurality of cavities respectively passing through a portion of the plurality of first insulating layers; A first integrated circuit chip is disposed in one of the plurality of cavities; a second integrated circuit chip disposed in another cavity among the plurality of cavities; A second insulating portion, arranged to span a portion of the first integrated circuit chip and a portion of the second integrated circuit chip; as well as a wiring portion disposed on and / or in the second insulating portion, the wiring portion including a plurality of wirings connecting the first integrated circuit chip and the second integrated circuit chip to each other, The signal transmission between the first integrated circuit chip and the second integrated circuit chip is performed by bypassing a defective wiring among the plurality of wirings to a dummy wiring among the plurality of wirings by using channel switching.

18. The printed circuit board according to claim 17, wherein: Signal transmission between the first integrated circuit chip and the second integrated circuit chip is maintained through other wirings among the plurality of wirings except the defective wiring.

19. The printed circuit board according to claim 17, wherein: One or more wirings among the plurality of wirings are disposed in a region between the defective wiring and the dummy wiring.

20. The printed circuit board according to claim 17, wherein The wiring portion includes a plurality of first vias, the plurality of first vias passing through at least a portion of the first insulating portion, and at least one of the plurality of first vias connects the plurality of wirings to the first integrated circuit chip, and at least another first via of the plurality of first vias connects the plurality of wirings to the second integrated circuit chip.

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