Semiconductor structure
By adding a stress improvement layer to at least one side of the conductive wire of the semiconductor structure, the problem of deformation and stress concentration of the conductive wire material at high temperature is solved, and the electrical performance and reliability of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202411715892.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-03-04
AI Technical Summary
During the preparation of semiconductor structures, the conductive wire material is deformed due to high temperature, and bending and stress concentration problems occur, which affects the electrical performance and reliability of the process execution and the final product.
A stress improvement layer is added to at least one side of the conductive wire above the phase change storage unit, including one or more sub-layers, and the material can be selected from molybdenum, aluminum, titanium, silver, gold, etc., and the deformation and stress concentration of the conductive wire material are reduced through the stress improvement layer.
Effectively prevent bending and stress concentration of conductive wire materials, improve the problem of insufficient etching of conductive wires, reduce leakage in semiconductor structures, and improve electrical performance and reliability.
Smart Images
Figure CN119562527A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure. Background Art
[0002] Semiconductor structures, such as phase change memory, as an emerging non-volatile memory device, have great advantages over flash memory in many aspects such as read and write speed, read and write times, data retention time, unit area, and multi-value realization.
[0003] However, with the development of phase change memory, there are still many problems that need to be improved when using or forming the conductive wires included in the phase change memory unit. Summary of the invention
[0004] The present disclosure provides a semiconductor structure, comprising:
[0005] substrate;
[0006] A phase change memory unit, wherein the phase change memory unit is located on the substrate;
[0007] a first conductive line, the first conductive line being located on the phase-change memory unit and extending along a first direction, wherein the first direction is parallel to a plane of the substrate;
[0008] The first stress improvement layer is in contact with the first conductive line and at least includes a first sublayer located on a side of the first conductive line close to or far from the phase change memory unit.
[0009] In some embodiments, the first stress improvement layer further includes a second sublayer, the second sublayer is in contact with the first conductive line, and is disposed opposite to the first sublayer on a different side of the first conductive line.
[0010] In some embodiments, the thickness of the first sub-layer is the same as the thickness of the second sub-layer, and the ratio of the thickness of the first sub-layer to the thickness of the first conductive line is greater than or equal to 1 / 20 and less than or equal to 1 / 2.
[0011] In some embodiments, a size of the first sublayer and / or the second sublayer in a direction parallel to the substrate plane is the same as a size of the first conductive line in a direction parallel to the substrate plane.
[0012] In some embodiments, the first stress improvement layer further includes a third sublayer, and the third sublayer and the first sublayer are located on a same side of the first conductive line.
[0013] In some embodiments, a material of the third sub-layer is different from a material of the first sub-layer.
[0014] In some embodiments, a ratio of a size of the third sublayer in a direction perpendicular to the substrate plane to a size of the first sublayer in a direction perpendicular to the substrate plane ranges from 1 / 20 to 1 / 5.
[0015] In some embodiments, the first stress improvement layer further includes a preset structure, at least a portion of which is located in the first conductive line.
[0016] In some embodiments, the material of the first stress improvement layer includes at least one of molybdenum, aluminum, titanium, silver, gold or a combination thereof, and the material of the first conductive line is tungsten.
[0017] In some embodiments, the semiconductor structure also includes a second stress improvement layer and a second conductive line extending along a second direction, the second conductive line is located between the substrate and the phase change memory unit, the second stress improvement layer is in contact with the second conductive line, and at least includes a fourth sublayer located on one side of the second conductive line; wherein the second direction is parallel to the plane of the substrate and intersects with the first direction.
[0018] The semiconductor structure provided by the embodiment of the present disclosure includes: a substrate; a phase change memory unit, the phase change memory unit is located on the substrate; a first conductive line, the first conductive line is located on the phase change memory unit and extends along a first direction, the first direction is parallel to the plane of the substrate; a first stress improvement layer, the first stress improvement layer is in contact with the first conductive line, and at least includes a first sublayer located on one side of the first conductive line. Thus, in the embodiment of the present disclosure, by adding a stress improvement layer on at least one side of the first conductive line located above the phase change memory unit, it helps to prevent the first conductive line material from being easily deformed during the preparation and use process, resulting in bending and other phenomena, thereby helping to improve the situation of insufficient etching of the first conductive line material during the preparation process. The improvement of this situation also helps to reduce the occurrence of leakage in the manufactured semiconductor structure, thereby improving the electrical performance and reliability of the semiconductor structure.
[0019] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0021] Figure 1A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;
[0022] Figures 2 to 9 A schematic diagram of the structure of a first conductive line and a first stress improvement layer provided in different embodiments of the present disclosure;
[0023] Fig.10 A schematic diagram of the structure of a second conductive line and a second stress improvement layer provided in an embodiment of the present disclosure;
[0024] Fig.11 A flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;
[0025] Fig.12 A schematic diagram of the structure of a substrate provided in an embodiment of the present disclosure;
[0026] Figures 13 to 18 A schematic diagram of the structure of a semiconductor structure during the preparation process provided by different embodiments of the present disclosure. DETAILED DESCRIPTION
[0027] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0028] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.
[0029] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.
[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.
[0031] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0033] In semiconductor structures, such as phase change memories, the conductive wire structure is an important component. However, during the deposition process of the material constituting the conductive wire, the particles of the material contained in the conductive wire tend to grow at high temperatures (about 200°C, or even higher), which causes the material to deform easily, resulting in the conductive wire being prone to bending, stress concentration, and other problems. This in turn causes subsequent process steps to be not performed properly, resulting in serious leakage current in the conductive wire in the final semiconductor structure, reducing the performance and reliability of the semiconductor structure.
[0034] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed:
[0035] The present disclosure provides a semiconductor structure, which includes:
[0036] substrate;
[0037] A phase change memory unit, wherein the phase change memory unit is located on the substrate;
[0038] a first conductive line, the first conductive line being located on the phase-change memory unit and extending along a first direction, wherein the first direction is parallel to a plane of the substrate;
[0039] The first stress improvement layer is in contact with the first conductive line and at least includes a first sublayer located on a side of the first conductive line close to or far from the phase change memory unit.
[0040] Thus, in the embodiment of the present disclosure, by adding a stress improvement layer on at least one side of the first conductive line located above the phase change memory unit, it helps to prevent the first conductive line material from deforming itself during the preparation and use process, resulting in bending and the like, thereby helping to improve the situation where the first conductive line material is not sufficiently etched during the preparation process. The improvement of this situation also helps to reduce the occurrence of leakage in the manufactured semiconductor structure, thereby improving the electrical performance and reliability of the semiconductor structure.
[0041] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the convenience of explanation, the schematic diagram will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present disclosure.
[0042] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figures 2 to 9 A schematic diagram of the structure of a first conductive line and a first stress improvement layer provided in different embodiments of the present disclosure; Fig.10 A schematic structural diagram of a second conductive line and a second stress improvement layer provided in an embodiment of the present disclosure.
[0043] The semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0044] like Figures 1 to 9 As shown, the semiconductor structure includes:
[0045] Substrate 10;
[0046] A phase change memory unit A, wherein the phase change memory unit A is located on the substrate 10;
[0047] a first conductive line L1, wherein the first conductive line L1 is located on the phase-change memory unit A and extends along a first direction, wherein the first direction is parallel to a plane of the substrate 10;
[0048] The first stress improvement layer 11 contacts the first conductive line L1 and at least includes a first sub-layer 111 located on a side of the first conductive line L1 close to or far from the phase change memory unit A.
[0049] Here, the material of the substrate 10 can be any one of silicon (Si), silicon carbide (SiC), aluminum oxide (Al2O3), aluminum nitride (AlN), zinc oxide (ZnO), gallium oxide (Ga2O3) or lithium aluminate (LiAlO2). In a specific embodiment, the substrate 10 can be a silicon substrate that has been subjected to thermal oxidation treatment.
[0050] Continue to refer Figure 1 It can be seen that in some embodiments, the phase change memory unit A may include a storage layer 12, a gating layer 13 located between the storage layer 12 and the substrate 10, a first electrode 14 and a second electrode 15 located on both sides of the gating layer 13, a third electrode 16 and a fourth electrode 17 located on both sides of the storage layer 12, and a fifth electrode 18.
[0051] In some embodiments, the semiconductor structure also includes a second conductive line L2, which is located between the substrate 10 and the phase change memory unit A; wherein the second conductive line L2 extends along a second direction, the second direction is parallel to the plane of the substrate 10 and intersects with the first direction.
[0052] In some embodiments, the first direction and the second direction may be perpendicular to each other. However, the present invention is not limited thereto. In some other embodiments, the angle between the orthographic projections of the first direction and the second direction on the substrate 10 may be other angles, which are not specifically limited here and can be flexibly selected according to actual conditions.
[0053] In some embodiments, the materials of the first conductive line L1 and the second conductive line L2 may both be tungsten.
[0054] In some embodiments, the material of the storage layer 12 includes, but is not limited to, a chalcogenide alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy or an indium-antimony-tellurium (In-Sb-Te, IST) material, or any other appropriate phase change material. In some specific embodiments, the material of the storage layer 12 may be at least one of Ge2Sb2Te5, Ge1Sb4Te7, In2Sb2Te5, In1Sb2Te4, etc., or a combination thereof.
[0055] In some embodiments, the material of the gate layer 13 includes but is not limited to OTS (Ovonic Threshold Switch) materials, for example, GexAsySez, ZnxTey, GexTey, NbxOy, SixAsyTez, CxTey, BxTey, doped GexAsySez, etc.
[0056] In some embodiments, the materials of the first electrode 14, the second electrode 15, and the fifth electrode 18 may be the same or different. In some specific embodiments, each of the first electrode 14, the second electrode 15, and the fifth electrode 18 may include carbon, such as at least one of amorphous carbon (aC), carbon nanotubes, etc., or a combination thereof.
[0057] In some embodiments, the materials of the third electrode 16 and the fourth electrode 17 may be the same or different. In some specific embodiments, the material of each of the third electrode 16 and the fourth electrode 17 may include at least one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, etc., or a combination thereof.
[0058] In some specific embodiments, the material of the third electrode 16 and the fourth electrode 17 may be tungsten.
[0059] It can be understood that here, the formation of the third electrode 16 and the fourth electrode 17 helps to promote the close bonding between the storage layer 12 and the second electrode 15 and the fifth electrode 18 located on both sides thereof.
[0060] In the embodiment of the present disclosure, the first stress improvement layer 11 is located Figure 1 In addition to being located at the side of the first conductive line L1 away from the phase change memory unit A as shown in the figure, it can also be located at the side of the phase change memory unit A adjacent to the first conductive line L1. Specifically, it can be flexibly selected according to actual conditions and is not specifically limited here.
[0061] It can be understood that the method of introducing the first stress improvement layer 11 on one side of the first conductive line L1 is helpful to improve the preparation process of the first conductive line L1. In the deposition process of the material layer used to obtain the first conductive line, due to the high temperature, the grain growth is too large, the plasticity of the material increases, and the material layer is prone to deformation, bending, stress concentration, etc., which are not conducive to the subsequent etching process. The execution of the etching process is the process of etching the material layer used to obtain the first conductive line L1 in order to obtain the first conductive line L1. At this time, due to the deformation and bending of the above-mentioned material layer, it is easy to fail to etch, which leads to the first conductive line L1 in the semiconductor structure finally obtained. The first conductive line L1 is prone to leakage during actual application, affecting the electrical performance and reliability of the semiconductor structure.
[0062] In the embodiment of the present disclosure, by forming a first stress improvement layer 11 on at least one side of the first conductive line L1, it is helpful to reduce the deformation and stress concentration that are easy to occur in the material layer used to form the first conductive line L1, so that the first conductive line L1 obtained in the embodiment of the present disclosure can improve deformation and bending. In the etching process of forming the first conductive line L1, it is helpful to completely cut off the material layer used to obtain the first conductive line L1, thereby forming a first conductive layer L1 with significantly improved bending and leakage current, which helps to improve the electrical performance and reliability of the obtained semiconductor structure.
[0063] In the embodiment of the present disclosure, in order to improve the unfavorable conditions that occur during the preparation and use of the first conductive line L1, in addition to Figure 1 In addition to the configuration of the first stress improvement layer 11 shown, different embodiments are provided to further improve the above-mentioned situation, and these embodiments will be described below in conjunction with the accompanying drawings.
[0064] In some embodiments, Figure 2 As shown, the first stress improvement layer 11 further includes a second sub-layer 112 , which is in contact with the first conductive line L1 and is disposed opposite to the first sub-layer 111 on a different side of the first conductive line L1 .
[0065] It can be understood that, compared with the situation where the first stress improvement layer 11 only includes the first sublayer 111, the addition of the second sublayer 112 is beneficial to obtaining a first conductive layer L1 with further significantly improved bending phenomenon and significantly improved leakage current on both sides of the first conductive line L1 close to and away from the phase change memory unit A, thereby helping to improve the electrical performance and reliability of the obtained semiconductor structure.
[0066] In some embodiments, the first sub-layer 111 located on both sides of the first conductive line L1 may be symmetrical with the second sub-layer 112 in terms of position and specific structure.
[0067] In some embodiments, the first sub-layer 111 and the second sub-layer 112 have the same size.
[0068] Here, the same size of the first sublayer 111 and the second sublayer 112 can be manifested in multiple aspects, such as the same size along a first direction parallel to the plane of the substrate 10, and the same size along a second direction parallel to the plane of the substrate 10. However, it is not limited thereto, and may also include the same size along a direction perpendicular to the plane of the substrate 10, etc.
[0069] Here, arranging the first sublayer 111 and the second sublayer 112 to be symmetrical or of the same size helps to obtain a stable stress improvement effect on both sides of the first conductive line L1, which is beneficial to improving the electrical performance and reliability of the semiconductor structure finally obtained.
[0070] In some embodiments, a size of the first sub-layer 111 and / or the second sub-layer 112 in a direction parallel to the plane of the substrate 10 is the same as a size of the first conductive line L1 in a direction parallel to the plane of the substrate 10 .
[0071] Here, it can be understood that the width of the first sublayer 111 and / or the second sublayer 112 is the same as the width of the first conductive line L1, and the length of the first sublayer 111 and / or the second sublayer 112 is also the same as the length of the first conductive line L1. In this way, the first sublayer 111 and the second sublayer 112 can provide a stress improvement effect on the material included in the first conductive line L1 without generating additional occupation of the size of the substrate 10 plane.
[0072] In some other embodiments, the first stress improvement layer 11 further includes a third sublayer 113, and the third sublayer 113 and the first sublayer 111 are located on the same side of the first conductive line L1 (for details, please refer to Figure 3 ).
[0073] However, it is not limited thereto. In other embodiments, the third sublayer 113 may also be located at Figure 2 The second sub-layer 112 in the embodiment is away from the side of the first conductive line L1.
[0074] In some embodiments, the material of the third sub-layer 113 is different from the material of the first sub-layer 111 .
[0075] In this embodiment, in addition to obtaining Figure 1 and Figure 2In addition to the effect of the semiconductor structure shown in FIG. 1 , due to the addition of the third sub-layer 113, Figure 1 Compared with the embodiment shown, the first stress improvement layer 11 can further enhance the stress improvement effect of the material included in the first conductive line L1 during the preparation process, further reduce the bending and stress concentration phenomena, and is beneficial to improve the electrical performance and reliability of the semiconductor structure.
[0076] Furthermore, when the material of the third sublayer 113 is different from that of the first sublayer 111 , more options can be provided for the structural setting of the stress improvement material, and the stress improvement effect of the material layer included in the first conductive line L1 during the preparation process can be further effectively enhanced.
[0077] In some embodiments, the ratio of the size of the third sublayer 113 in a direction perpendicular to the plane of the substrate 10 to the size of the first sublayer 111 in a direction perpendicular to the plane of the substrate 10 ranges from 1 / 20 to 1 / 5 (including endpoint values), for example: 0.05, 0.08, 0.1, 0.12, 0.14, 0.16, 0.18, 0.2, etc.
[0078] It should be noted that, although in the embodiment of the present disclosure, the first stress improvement layer 11 includes the first sub-layer 111, the second sub-layer 112 and the third sub-layer 113, which is only an example of the technical solution provided in the embodiment of the present disclosure, and does not constitute a limitation on the application scenario of the embodiment of the present disclosure. In fact, the first stress improvement layer 11 can also include other sub-layers of a larger number and different types of materials, and the position of the first conductive line L1 can be set on at least one side close to or away from the phase change memory unit A. Specifically, it can be flexibly selected according to the actual situation, and no specific limitation is made here.
[0079] In some embodiments, Figures 4 to 9 As shown, the first stress improvement layer 11 further includes a preset structure Y, at least part of which is located in the first conductive line L1;
[0080] and / or,
[0081] The preset structure Y is made of a material different from that of the first sub-layer 111 .
[0082] In some embodiments, Figure 4 and Figure 5 As shown, the number of the preset structures Y includes multiple ones, and some of the preset structures Y located in the same area and arranged adjacently are defined as a combined structure Z. In the direction in which the first conductive line L1 extends, the combined structure Z is arranged at intervals in the first conductive line L1.
[0083] It can be understood that when bending and stress concentration occur in the material layer of the first conductive line L1, the presence of a gap usually occurs, which can also be confirmed by simulation results. Therefore, in the embodiment of the present disclosure, the first stress improvement layer 11 further includes a preset structure Y, which helps to improve stress on the entire surface of the first conductive line L1 parallel to the plane of the substrate 10, and also adds a preset structure Y in a targeted manner where stress is more obvious, which helps to further improve the bending and stress concentration in the material layer of the first conductive line L1.
[0084] In some embodiments, Figure 6 As shown, the combined structure Z at least includes a first preset structure Y1 and a second preset structure Y2, and the second preset structure Y2 is arranged around the first preset structure Y.
[0085] Based on the above embodiments, this embodiment further increases the flexibility of stress adjustment. The materials of the first preset structure Y1 and the second preset structure Y2 can be the same or different to meet the requirements of stress adjustment levels at different positions. For example, when the first preset structure Y1 requires a higher degree of stress adjustment than the second preset structure Y2, the first preset structure Y1 can select a material with stronger adjustment ability. Conversely, when the first preset structure Y1 requires a higher degree of stress adjustment than the second preset structure Y2, the second preset structure Y2 can select a material with stronger adjustment ability.
[0086] In some embodiments, Figures 7 to 9 As shown, in a direction perpendicular to the thickness of the first conductive line L1, the combined structure Z includes a third preset structure Y3 located in the middle area of the first conductive line L1 and a fourth preset structure Y4 located on at least one side of the third preset structure Y3; wherein at least a portion of the fourth preset structure Y4 is located in the first conductive line L1.
[0087] In this embodiment, the flexibility of stress adjustment is increased in the direction perpendicular to the thickness of the first conductive line L1. The materials of the third preset structure Y3 and the fourth preset structure Y4 can be the same or different to meet the requirements of stress adjustment levels at different positions in the direction perpendicular to the thickness of the first conductive line L1 (the direction perpendicular to the plane of the substrate 10). For example, when more stress adjustment levels are required at the middle position, the third preset structure Y3 can select a material with stronger adjustment ability. Conversely, when more stress adjustment levels are required at a position located on at least one side of the middle area, the fourth preset structure Y4 can select a material with stronger adjustment ability.
[0088] In any of the above embodiments, in the semiconductor structure including the preset structure Y, the first stress improvement layer 11 may only include the first sublayer 111, but is not limited thereto, and may further include the second sublayer 112, and may even include the third sublayer 113. For example, in addition to the first sublayer 111, it may also include at least one of the second sublayer 112 and the third sublayer 113, or a combination thereof.
[0089] It should be noted that although Figure 4 To Attachment Fig. 9 The number of the preset structures Y at the corresponding positions is shown in the figure, which is only for illustrative purposes and is not intended to limit the number setting and arrangement relationship of the preset structures Y at the corresponding positions in the first conductive line L1 provided in the embodiment of the present disclosure. The number setting and arrangement relationship setting at each position can also be flexibly adjusted according to actual conditions, for example, it can be more or less, etc., and is not specifically limited here.
[0090] It is understandable that any of the above embodiments may be combined with the embodiments of the related settings of the first stress improvement layer 11 (including but not limited to materials, positional relationships, number of layers, settings of preset structures, etc.). Specifically, it can be flexibly selected according to actual conditions and is not specifically limited here.
[0091] In some embodiments, the material of the first stress improvement layer 11 includes at least one of molybdenum, aluminum, titanium, silver, gold, or a combination thereof.
[0092] In some embodiments, the thickness of the first stress improvement layer 11 may range from 0.1 nm to 15 nm (including the end values), for example: 0.3 nm, 0.5 nm, 0.8 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, etc.
[0093] It should be noted that in the embodiment where the first stress improvement layer 11 includes multiple sub-layers, the thickness of the first stress improvement layer 11 mentioned here can be the single layer thickness of each sub-layer included therein, but is not limited thereto, and can also be the sum of the thicknesses of each sub-layer.
[0094] In addition, in the embodiment where the first stress improvement layer 11 includes a preset structure Y, the size and material type of the portion of the preset structure Y in the first conductive line L1 need to be set based on the principle of not affecting the performance of the first conductive line L1 itself. The size should not be too large or too small. If it is too large, it will affect the electrical properties or other properties of the first conductive line L1 itself. If it is too small, it may not improve the local bending or stress concentration. In addition, in terms of material selection, the parameters included in it should also be adapted to the parameters of the first conductive line L1 itself. Specifically, it can be selected according to the actual situation and is not specifically limited here.
[0095] In some embodiments, the thickness of the first conductive line L1 may range from 2 nm to 30 nm (including the end points), for example: 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, etc.
[0096] In some embodiments, the thickness of the first sub-layer 111 is the same as the thickness of the second sub-layer 112 , and the ratio of the thickness of the first sub-layer 111 to the thickness of the first conductive line L1 is greater than or equal to 1 / 20 and less than or equal to 1 / 2.
[0097] In some embodiments, the size ratio of the first sub-layer 111 to the first conductive line L1 in a plane perpendicular to the substrate 10 may be 0.05, 0.08, 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.28, 0.3, 0.35, 0.4, 0.45, 0.5, etc. The size ratio of the second sub-layer to the first conductive line in a plane perpendicular to the substrate may range from 0.05, 0.08, 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.28, 0.3, 0.35, 0.4, 0.45, 0.5, etc.
[0098] In some specific embodiments, the material of the first conductive line L1 may be tungsten, and the material of the first stress improvement layer 11 may be molybdenum (Mo).
[0099] It is understandable that the advantages of using metal Mo material are: ① Tungsten and molybdenum belong to the VIB group elements in the periodic table, and the two have more similar chemical properties; ② The combination of tungsten and molybdenum, from the stress perspective, molybdenum has a lower elastic modulus, which can reduce the deformation of the first conductive line L1 including the tungsten layer.
[0100] After adding the first stress improvement layer 11, the first conductive line L1 obtained can improve the bending and stress concentration, which can be analyzed from the following two aspects:
[0101] On the one hand, it is understandable that when the material layer includes multiple layers (such as the first conductive line L1 of the present application and the first stress improvement layer located around it), the stress situation between the multiple layers is usually closely related to the thickness of the single layer material participating in the composition of the multilayer material layer and the stress value of the single layer material itself. At the same time, when two adjacent film layers show stress changes in opposite directions (for example, when the stress direction generated by the first stress improvement layer 11 is opposite to the stress direction generated by the material layer used to form the first conductive line), there is a situation of stress cancellation, thereby reducing the stress situation in the material layer used to form the first conductive line L1, improving the bending and stress concentration situation; ② The stress situation between the interfaces of the multilayer material layers is different from that of the single film layer: (a) The reduction of defect states, the combination of multilayer materials fills the dangling bonds between the interfaces of the single film layers, reduces the defect states, reduces the atomic diffusion during the creep process, and then reduces the creep of the material, reducing its deformation degree; (b) The free energy between the interfaces of the multilayer materials is often lower than the surface free energy of the single layer material. The free energy is the ability of the system to do work externally. When the free energy is reduced, it can provide more stability for the material and reduce the internal stress caused by stress concentration or imbalance.
[0102] On the other hand: In order to better evaluate the stress of the molybdenum (Mo) layer metal deposited on the upper and lower sides of the tungsten (W) layer, a basic stress simulation is performed. The simulation structure adopts the setting relationship between the first conductive line L1 and other material layers in the semiconductor structure:
[0103] ① When there is no stress improvement layer and only tungsten (W) material, calculate the stress in its vicinity; ② Keep the thickness unchanged and deposit a thinner molybdenum (Mo) layer material on tungsten (W), calculate the stress in its vicinity; ③ Keep the thickness unchanged and deposit a thinner molybdenum (Mo) layer material on the upper and lower sides of tungsten (W), calculate the stress in its vicinity; the following results are obtained:
[0104]
[0105] From the calculation results, it can be seen that after adding molybdenum (Mo) layers on the upper and lower sides of the tungsten (W) layer, the maximum stress of the tungsten (W) layer is reduced from 366.19MPa to 323.95MPa, indicating that the addition of the molybdenum (Mo) layer will improve the maximum stress at the tungsten (W) layer. When the molybdenum (Mo) material is replaced with a material with a lower elastic modulus (including but not limited to aluminum, titanium, silver, gold and other metals), the maximum stress of the tungsten (W) layer will be further reduced.
[0106] Therefore, in the embodiment of the present disclosure, after the first stress improvement layer 11 is introduced, the bending and stress concentration phenomena of the first conductive line L1 can be greatly improved, which is beneficial to improve the situation of insufficient etching of the first conductive line material during the preparation process. The improvement of this situation also helps to reduce the occurrence of leakage in the manufactured semiconductor structure, thereby improving the electrical performance and reliability of the semiconductor structure.
[0107] In some embodiments, Fig.10 As shown, the semiconductor structure further includes a second stress improvement layer 19 , which contacts the second conductive line L2 and includes at least a fourth sublayer 191 located at one side of the second conductive line L2 .
[0108] In some embodiments, the fourth sublayer 191 included in the second stress improvement layer 19 may be disposed on a side of the second conductive line L2 that is away from or close to the substrate 10 .
[0109] In some embodiments, the second stress improvement layer 19 may be disposed in the same manner as the first improvement layer 11 provided in any of the above embodiments.
[0110] It can be understood that in the embodiment of the present disclosure, after the second stress improvement layer 19 is introduced, the bending and stress concentration phenomena of the second conductive line L2 can be greatly improved, which is beneficial to improve the situation of insufficient etching of the material layer used to form the second conductive line L2 during the preparation process. The improvement of this situation also helps to reduce the occurrence of leakage in the manufactured semiconductor structure, thereby improving the electrical performance and reliability of the semiconductor structure.
[0111] The present disclosure also provides a method for preparing a semiconductor structure. Fig.11 As shown, the method includes the following steps:
[0112] Step S101: providing a substrate;
[0113] Step S102: forming a phase change memory unit on a substrate;
[0114] Step S103: forming a first conductive line and a first stress improvement layer on the phase change memory unit, wherein the first stress improvement layer contacts the first conductive line and comprises at least a first sublayer located on a side of the first conductive line close to or away from the phase change memory unit; wherein the first conductive line extends along a first direction, and the first direction is parallel to the plane of the substrate.
[0115] It should be understood that although Fig.11The steps in the process are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Fig.11 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.
[0116] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0117] Fig.12 A schematic diagram of the structure of a substrate provided in an embodiment of the present disclosure; Figures 13 to 18 A schematic diagram of the structure of a semiconductor structure during the preparation process provided by different embodiments of the present disclosure.
[0118] First, execute step S101, such as Fig.12 As shown, a substrate 10 is provided.
[0119] Here, the material of the substrate 10 can be any one of silicon (Si), silicon carbide (SiC), aluminum oxide (Al2O3), aluminum nitride (AlN), zinc oxide (ZnO), gallium oxide (Ga2O3) or lithium aluminate (LiAlO2). In a specific embodiment, the substrate 10 can be a silicon substrate that has been subjected to thermal oxidation treatment.
[0120] Then, step S102 is performed, as shown in FIG. Fig.13 As shown, a phase change memory unit A is formed on the substrate 10 .
[0121] Here, the steps of forming the phase change memory unit A may be the same as the conventional process, and will not be described in detail here.
[0122] It should be noted that in the attached Fig.13 To Attachment Fig.18 In the figure, the detailed structure of the phase change memory unit A is not shown, and only the material layer where the phase change memory unit A is located is schematically shown. In fact, the phase change memory unit A may include multiple phase change memory units, and the multiple phase change memory units are arranged in parallel in the first direction and the second direction.
[0123] In some embodiments, before forming the phase-change memory unit A, the preparation method may further include: forming a second conductive line L2 extending along a second direction, where the second direction is parallel to the plane of the substrate 10 .
[0124] Finally, step S103 is executed. Figures 13 to 18 As shown, a first conductive line L1 and a first stress improvement layer 11 are formed on the phase change memory unit A, the first stress improvement layer 11 is in contact with the first conductive line L1, and at least includes a first sublayer 111 located on a side of the first conductive line L1 close to or away from the phase change memory unit A; wherein the first conductive line L1 extends along a first direction, the first direction is parallel to the plane of the substrate 10 and intersects with a second direction.
[0125] In some embodiments, Figures 13 to 18 As shown, forming the first conductive line L1 and the stress improvement layer 11 at least includes:
[0126] First, a conductive material layer La is formed, and the conductive material layer La covers the surface of the substrate 10;
[0127] removing a portion of the conductive material layer La to form a plurality of first grooves T1;
[0128] forming a stress improvement material layer 11a, wherein the stress improvement material layer 11a fills the first groove T1 and covers the surface of the conductive material layer La;
[0129] An etching process is performed along the first direction to remove part of the conductive material layer La and part of the stress improvement material layer 11a to form a first conductive line L and a first stress improvement layer 11; wherein, in the remaining stress improvement material layer 11a, the part filling the first groove T1 constitutes a preset structure Y, and the part covering the surface of the first conductive line L1 constitutes a first sublayer 111.
[0130] It can be understood that, depending on the location of the preset structure Y formed in this step, in different cases, the number of layers included in the conductive material layer may include various situations, which will be described below in conjunction with the accompanying drawings:
[0131] In some embodiments, Fig.13 and Fig.14 As shown, forming the first conductive line L1 and the stress improvement layer 11 includes:
[0132] A conductive material layer La is formed, wherein the conductive material layer La includes a first conductive material layer L11 and covers the surface of the substrate 10 (for details, please refer to Fig.13 );
[0133] Part of the conductive material layer La is removed to form a plurality of first grooves T1 (see Fig.13 );
[0134] A stress improvement material layer 11a is formed, and the stress improvement material layer 11a fills the first groove T1 and covers the surface of the conductive material layer La (for details, please refer to Fig.13 );
[0135] An etching process is performed along the first direction to remove part of the conductive material layer La and part of the stress improvement layer 11a to form a first conductive line L1 and a first stress improvement layer 11; wherein, in the remaining stress improvement material layer 11a, the part filling the first groove T1 constitutes a preset structure Y, and the part covering the surface of the first conductive line L1 constitutes a first sublayer 111 (for details, please refer to Fig.14 ).
[0136] In other embodiments, Fig.15 and Fig.16 As shown, forming the first conductive line L1 and the stress improvement layer 11 includes:
[0137] A first conductive material layer L11 is formed, and the first conductive material layer L11 covers the surface of the substrate 10 (for details, please refer to Fig.15 );
[0138] Part of the first conductive material layer L11 is removed to form a plurality of second grooves T2; the stress improvement material layer 11a is used to fill the second grooves T2 to form a fourth preset structure Y4 (for details, please refer to Fig.15 );
[0139] A second conductive material layer L12 is formed, and the second conductive material layer L12 covers the surface of the first conductive material layer L11. The first conductive material layer L11 and the second conductive material layer L12 constitute a conductive material layer La (for details, please refer to Fig.15 );
[0140] Next, a portion of the second conductive material layer L12 is removed to form a first groove T1 (for details, please refer to Fig.15 );
[0141] A stress improvement material layer 11a is formed, and the stress improvement material layer 11a fills the first groove T1 and covers the surface of the conductive material layer La (for details, please refer to Fig.15 );
[0142] An etching process is performed along the first direction to remove part of the conductive material layer La and part of the stress improvement layer 11a to form a first conductive line L1 and a first stress improvement layer 11; wherein, in the remaining stress improvement material layer 11a, the part filling the first groove T1 constitutes a third preset structure Y3, and the part covering the surface of the first conductive line L1 constitutes a first sublayer 111 (for details, please refer to Fig.16 ).
[0143] In this embodiment, the third preset structure Y and the fourth preset structure Y4 both belong to the preset structure Y.
[0144] In some other embodiments, Fig.17 and Fig.18 As shown, forming the first conductive line L1 and the stress improvement layer 11 includes:
[0145] A first conductive material layer L11 is formed, and the first conductive material layer L11 covers the surface of the substrate 10 (for details, please refer to Fig.17 );
[0146] Part of the first conductive material layer L11 is removed to form a plurality of second grooves T2; the stress improvement material layer 11a is used to fill the second grooves T2 to form a fourth preset structure Y4 (for details, please refer to Fig.17 );
[0147] A second conductive material layer L12 is formed, and the second conductive material layer L12 covers the surface of the first conductive material layer L11 (for details, please refer to Fig.17 );
[0148] Part of the second conductive material layer L12 is removed to form a plurality of third grooves T3; the third grooves T3 are filled with the stress improvement material layer 11a to form a third preset structure Y3 (for details, please refer to Fig.15 );
[0149] A third conductive material layer L13 is formed, and the third conductive material layer L13 covers the surface of the second conductive material layer L12; the first conductive material layer L11, the second conductive material layer L12 and the third conductive material layer L13 constitute a conductive material layer La (for details, please refer to Fig.17 );
[0150] Part of the third conductive material layer 13 is removed to form a first groove T1 (for details, please refer to Fig.17 );
[0151] A stress improvement material layer 11a is formed, and the stress improvement material layer 11a fills the first groove T1 and covers the surface of the conductive material layer La (for details, please refer to Fig.17 );
[0152] An etching process is performed along the first direction to remove part of the conductive material layer La and part of the stress improvement layer 11a to form a first conductive line L1 and a first stress improvement layer 11; wherein, in the remaining stress improvement material layer 11a, the part filling the first groove T1 constitutes a fourth preset structure Y, and the part covering the surface of the first conductive line L1 constitutes a first sublayer 111 (for details, please refer to Fig.18 ).
[0153] In this embodiment, the third preset structure Y and the fourth preset structure Y4 both belong to the preset structure Y.
[0154] In some embodiments, the materials of the first conductive line L1 and the second conductive line L2 may both be tungsten.
[0155] In some embodiments, the material of the first stress improvement layer 11 includes at least one of molybdenum, aluminum, titanium, silver, gold, or a combination thereof.
[0156] In some embodiments, the thickness of the first stress improvement layer 11 may range from 0.1 nm to 15 nm (including the end values), for example: 0.3 nm, 0.5 nm, 0.8 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, etc.
[0157] It should be noted that in the embodiment where the first stress improvement layer 11 includes multiple sub-layers, the thickness of the first stress improvement layer 11 mentioned here can be the single layer thickness of each sub-layer included therein, but is not limited thereto, and can also be the sum of the thicknesses of each sub-layer.
[0158] In addition, in the embodiment where the first stress improvement layer 11 includes a preset structure Y, the size and material type of the portion of the preset structure Y in the first conductive line L1 need to be set based on the principle of not affecting the performance of the first conductive line L1 itself. The size should not be too large or too small. If it is too large, it will affect the electrical properties or other properties of the first conductive line L1 itself. If it is too small, it may not improve the local bending or stress concentration. In addition, in terms of material selection, the parameters included in it should also be adapted to the parameters of the first conductive line L1 itself. Specifically, it can be selected according to the actual situation and is not specifically limited here.
[0159] In some embodiments, the thickness of the first conductive line L1 may range from 2 nm to 30 nm (including the end points), for example: 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, etc.
[0160] In some embodiments, the size ratio of the first sublayer 111 and the first conductive line L1 perpendicular to the plane of the substrate 10 ranges from 0.05 to 0.5 (including endpoint values), for example: 0.05, 0.08, 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.28, 0.3, 0.35, 0.4, 0.45, 0.5, etc.
[0161] In some specific embodiments, the material of the first conductive line L1 may be tungsten, and the material of the first stress improvement layer 11 may be molybdenum (Mo).
[0162] It should be noted that Figures 13 to 18 In the figure, only the situation of how to obtain the preset structure Y when the first stress improvement layer 11 includes the first sublayer 111 is shown. It can be understood that when the first stress improvement layer 11 includes multiple sublayers, or the setting position, arrangement or quantity of the preset structure Y changes, the preparation method provided in the embodiment of the present disclosure can be used to obtain it.
[0163] In the embodiment of the present disclosure, after the first stress improvement layer 11 is introduced, the bending and stress concentration phenomena of the first conductive line L1 can be greatly improved, which is beneficial to improve the situation of insufficient etching of the first conductive line material during the preparation process. The improvement of this situation also helps to reduce the occurrence of leakage in the manufactured semiconductor structure, thereby improving the electrical performance and reliability of the semiconductor structure.
[0164] It should be noted that the various technical features in the technical solutions recorded in the embodiments provided in the present disclosure can be arbitrarily combined without conflict.
[0165] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A semiconductor structure, characterized in that: The semiconductor structure comprises: substrate; A phase change memory unit, wherein the phase change memory unit is located on the substrate; a first conductive line, the first conductive line being located on the phase-change memory unit and extending along a first direction, wherein the first direction is parallel to a plane of the substrate; The first stress improvement layer is in contact with the first conductive line and at least includes a first sublayer located on a side of the first conductive line close to or far from the phase change memory unit.
2. The structure according to claim 1, characterized in that: The first stress improvement layer further includes a second sublayer, the second sublayer is in contact with the first conductive line, and is disposed opposite to the first sublayer on a different side of the first conductive line.
3. The structure according to claim 2, characterized in that: The thickness of the first sub-layer is the same as the thickness of the second sub-layer, and the ratio of the thickness of the first sub-layer to the thickness of the first conductive line is greater than or equal to 1 / 20 and less than or equal to 1 / 2.
4. The structure according to claim 2, characterized in that: A size of the first sublayer and / or the second sublayer in a direction parallel to the substrate plane is the same as a size of the first conductive line in a direction parallel to the substrate plane.
5. The structure according to claim 1, characterized in that The first stress improvement layer further includes a third sublayer, and the third sublayer and the first sublayer are located on the same side of the first conductive line.
6. The structure according to claim 5, characterized in that The material of the third sub-layer is different from that of the first sub-layer.
7. The structure according to claim 5, characterized in that The ratio of the size of the third sub-layer in a direction perpendicular to the substrate plane to the size of the first sub-layer in a direction perpendicular to the substrate plane is in a range of 1 / 20 to 1 / 5.
8. The structure according to claim 1, characterized in that The first stress improvement layer further includes a preset structure, at least a portion of which is located in the first conductive line.
9. The structure according to any one of claims 1 to 8, characterized in that: The material of the first stress improvement layer includes at least one of molybdenum, aluminum, titanium, silver, gold or a combination thereof, and the material of the first conductive line is tungsten.
10. The structure according to claim 1, characterized in that The semiconductor structure also includes a second stress improvement layer and a second conductive line extending along a second direction, wherein the second conductive line is located between the substrate and the phase change memory unit, the second stress improvement layer is in contact with the second conductive line, and at least includes a fourth sublayer located on one side of the second conductive line; wherein the second direction is parallel to the plane of the substrate and intersects with the first direction.