Semiconductor device, capacitor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor device, a capacitor structure and a manufacturing method thereof. The semiconductor device comprises an epitaxial layer, and the epitaxial layer is provided with a deep groove structure and well regions located on the two sides of the deep groove structure. The upper surface of the epitaxial layer is provided with a control gate dielectric layer and a control gate polycrystalline layer; the deep groove structure is internally provided with n first preset regions and n + 1 second preset regions which are formed through dielectric layer isolation, and each first preset region is located between the two corresponding second preset regions; the first preset region and the second preset region are filled with polycrystalline silicon; the first second preset region and the (n + 1) th second preset region are isolated from the well region through a dielectric layer; the capacitor with the capacitance value far larger than that of a planar capacitor can be manufactured under the effective chip area, the gate electrode of the device is effectively utilized, the interconnection structure of the capacitor is optimized, the chip area and the structure complexity are greatly reduced, the chip manufacturing cost is optimized, and the chip stability is improved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit manufacturing process and layout, is applicable to the development of relatively large capacitors in power management integrated circuits, and specifically relates to a semiconductor device, a capacitor structure and a manufacturing method thereof. Background Art

[0002] Currently in the field of power management circuits, whether it is AC / DC power management ICs, LED driver ICs, or high-voltage gate driver ICs, the internal oscillator function circuits, level conversion function circuits, or final current drive function circuits all require larger capacitors to isolate DC voltages or to be used as filter capacitors to increase the circuit's DC isolation capability and reduce output noise amplitude.

[0003] At present, the capacitors used in the functional circuits of all integrated circuits, whether it is the MOS capacitor between the gate and channel region of the MOS transistor, or the MIP capacitor between the metal wiring, are all planar capacitors, that is, the capacitor is a capacitor medium made between the upper and lower plates, and the size of the capacitor is directly proportional to the chip area occupied. Therefore, in actual circuit design, the larger the required capacitance value, the larger the chip area it occupies, which increases the production cost of the chip.

[0004] When a deep trench structure forms a capacitor structure, it usually refers to a deep trench capacitor (DTC), which is widely used in antenna matching, RF filtering and IC decoupling, especially in applications with height and volume restrictions. It still has very high stability and extremely low leakage current under high bias voltage. Deep trench capacitors (DTCs) have shown significant advantages in improving the capacitance per unit area, especially in high-density dynamic random access memory (DRAM) applications, but they still face several key challenges in their manufacturing and integration processes. In order to effectively transmit signals to the polysilicon layer, a reliable contact window needs to be formed at the top of the trench. However, due to space limitations, it is a difficult problem to achieve low contact resistance while maintaining good mechanical strength. The complex interconnect structure increases the process steps and also increases the probability of introducing defects. Especially in the case of high-density integration, how to ensure good connection and flatness between the layers has become a major challenge. Summary of the invention

[0005] In order to solve the problem in the background technology, the present invention provides a semiconductor device capacitor structure. The capacitor structure integrates multiple PIP capacitors and MOS capacitors, and is constructed by a polycrystalline layer located in a deep groove, a control gate polycrystalline layer of the device itself, a substrate well region, etc. as the polar plate of the capacitor. By optimizing the device capacitor structure, the present invention not only effectively improves the capacitance per unit area and reduces the chip area; but also greatly reduces the complexity of the interconnection structure and ensures the stability of the device capacitor.

[0006] The semiconductor device described in the present invention specifically refers to a device containing a trench structure, which generally includes an epitaxial layer, wherein the epitaxial layer has a deep trench structure and well regions located on both sides of the deep trench structure; the upper surface of the epitaxial layer has a control gate dielectric layer and a control gate polycrystalline layer; the deep trench structure described in the present invention has n first preset areas and n+1 second preset areas formed by isolation of the dielectric layer, and the first preset area is located between the two second preset areas; the first preset area and the second preset area are both filled with polysilicon; the first second preset area and the n+1th second preset area are isolated from the well area by the dielectric layer; n is an arbitrary positive integer.

[0007] The first preset area and the second preset area filled with polysilicon and the dielectric layer located between the first preset area and the second preset area form a first PIP capacitor; The second preset area and the well area filled with polysilicon and the dielectric layer located between the polysilicon and the well area in the second preset area form a first PIS capacitor; The well region, the control gate polycrystalline layer and the control gate dielectric layer form a second PIS capacitor; The first preset area filled with polysilicon, the control gate dielectric layer and the control gate polycrystalline layer form a second PIP capacitor; The control gate polycrystalline layer and the second preset region filled with polycrystalline silicon are connected to the positive electrode, and the first preset region filled with polycrystalline silicon and the well region are connected to the negative electrode.

[0008] Furthermore, the control gate dielectric layer and the dielectric layer located in the deep trench structure are continuous.

[0009] To achieve electrical connection, the control gate dielectric layer is provided with a first connecting groove located above the second preset area, which is used to fill the conductive medium to connect the control gate polycrystalline layer and the polysilicon in the second preset area. The control gate dielectric layer and the control gate polycrystalline layer are provided with a second connecting groove located above the first preset area, which is used to fill the conductive medium to introduce an electric potential to the polysilicon in the second preset area; the second connecting groove has an oxide layer inside. The control gate dielectric layer and the control gate polycrystalline layer are provided with a third connecting groove located above the well area, which is used to fill the conductive medium to introduce an electric potential to the well area; the third connecting groove has an oxide layer inside.

[0010] The present invention also provides a method for manufacturing the above semiconductor device capacitor structure, comprising the following steps: (1) providing a substrate, and forming a deep trench in the substrate; (2) forming an oxide layer on the surface of the deep trench and filling it with a polysilicon layer; (3) Selectively etching the polysilicon layer and filling the etched area with a dielectric layer; (4) depositing a control gate dielectric layer on the substrate, and selectively etching the control gate dielectric layer to form a first connecting groove region; (5) Depositing polysilicon to produce the control gate polycrystalline layer of the MOS transistor; (6) etching the control gate dielectric layer and the control gate polycrystalline layer to form a second connecting groove and a third connecting groove region; (7) depositing an insulating layer, and forming lead holes in the second connecting groove and the third connecting groove by pattern masking and etching; (8) A discontinuous metal layer is formed, a portion of which is connected to the substrate and the polysilicon layer through the lead hole, and another portion of which is connected to the control gate polysilicon layer.

[0011] The substrate in step (1) is generally a silicon substrate; the material of the dielectric layer is silicon oxide or silicon nitride.

[0012] The selective etching in step (3) is dry etching, and the depth can be precisely controlled.

[0013] The present invention also relates to a semiconductor device comprising the above capacitor structure, including but not limited to a high voltage buried gate N-type trench metal oxide field effect power transistor.

[0014] The beneficial effects of the present invention are that all the above process implementation methods are fully compatible with the silicon-based trench BCD process and are therefore easy to implement. Capacitors with a capacitance value far greater than that of planar capacitors can be produced under an effective chip area, the interconnection structure of the capacitors is optimized, the chip area and structural complexity are greatly reduced, the chip manufacturing cost is optimized, and the chip stability is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of an existing deep trench capacitor; Figure 2 It is a schematic diagram of the capacitor structure of the present invention; Figure 3 A simplified diagram of a semiconductor device including a deep trench structure; Figure 4 It is a three-dimensional schematic diagram of a capacitor structure based on a deep trench structure of the present invention; Figure 5 Schematic diagram of capacitance distribution of the present invention; Figure 6 This is a schematic diagram of the electrical connection of the capacitor; Figure 7This is one of the schematic diagrams of the power transistor case structure of the present invention; Figure 8 This is the second schematic diagram of the structure of the power transistor case of the present invention; Fig. 9 A top view of a power transistor example of the present invention; Fig.10 It is a schematic diagram of the distribution of discontinuous metal layers of the present invention. DETAILED DESCRIPTION

[0016] Deep Trench Structure is a special process used in semiconductor device manufacturing, mainly used to form high-density isolation or capacitance structures. This structure usually involves etching very deep and narrow trenches in the silicon substrate and filling them with oxide or other insulating materials to achieve the desired electrical properties.

[0017] Deep Trench Capacitor (DTC) is a special capacitor structure widely used in high-density integrated circuits to provide large capacitance values ​​within a limited chip area. Its main feature is to etch very deep and narrow trenches in the silicon substrate and fill these trenches through a special process to form a capacitor structure. The trench wall is usually covered with a very thin layer of silicon dioxide (SiO2) or other high dielectric constant materials as an insulating layer of the capacitor. The interior of the trench is filled with conductive materials such as doped polysilicon or metal to form one plate of the capacitor; the silicon substrate itself serves as the other plate. When a voltage is applied between the two plates, a large amount of charge storage can be achieved on a very small surface area due to the presence of the trench. This is because the capacitance value is inversely proportional to the distance between the plates, and the deep trench design effectively reduces this distance.

[0018] Figure 1 The figure shows an existing deep trench capacitor, in which an oxide layer, a polysilicon layer and a sidewall are provided in the deep trench. The polysilicon layer extends above the substrate surface to connect the interconnection structure 5; and the interconnection structure 5 has at least a four-layer structure to respectively construct the positive electrode, the positive electrode connection layer, the negative electrode and the negative electrode connection layer; thus, the capacitor has at least a 7-layer structure on the substrate surface. During preparation, after the polysilicon layer is formed, the polysilicon layer is patterned to expose part of the top surface of the oxide layer; then, the sidewall is formed along the opposite sidewalls of the polysilicon layer; then, an oxide layer is formed above the polysilicon layer and the sidewall, and the process steps described above for forming the polysilicon layer and the sidewall are repeated to form a polysilicon layer and a sidewall above the oxide layer, and a polysilicon layer and a sidewall above the oxide layer. However, this step-by-step etching method is very likely to cause leakage.

[0019] In contrast, the capacitor structure provided by the present invention is as follows Figure 2As shown, the interconnect structure above the control gate polysilicon layer of the device itself only has an electrode layout; that is, only two layers need to be set above the control gate polysilicon layer. Figure 3 and 4 , the semiconductor device capacitor structure epitaxial layer 1 of the present application, the epitaxial layer 1 has a deep trench structure 2 and well regions located on both sides of the deep trench structure; the upper surface of the epitaxial layer has a control gate dielectric layer 3 and a control gate polycrystalline layer 4; the deep trench structure 2 has n first preset areas 21 and n+1 second preset areas 22 formed by dielectric layer isolation, the first preset area 21 is located between the two second preset areas 22; the first preset area 21 and the second preset area 22 are filled with polysilicon; the first second preset area 22 and the n+1 second preset area 22 are isolated from the well area by the dielectric layer; like Figure 5 As shown, the first preset area 21 and the second preset area 22 filled with polysilicon and the dielectric layer located between the first preset area and the second preset area form a first PIP capacitor C1; the second preset area 22 filled with polysilicon and the well area and the dielectric layer located between the polysilicon and the well area in the second preset area form a first PIS capacitor C2; the well area and the control gate polycrystalline layer 4 and the control gate dielectric layer 3 form a second PIS capacitor C3; the first preset area 21 filled with polysilicon, the control gate dielectric layer 3 and the control gate polycrystalline layer 4 form a second PIP capacitor C4; the control gate polycrystalline layer 4 and the second preset area 22 filled with polysilicon are connected to the positive electrode, and the first preset area 21 filled with polysilicon and the well area are connected to the negative electrode. Thus, the above four capacitors are electrically connected in parallel through metal, so that capacitors are made on the surface and in the body of the trench-type high-voltage buried gate metal oxide field effect transistor per unit area, and the actual capacitors are distributed in a three-dimensional shape, increasing the actual capacitance value, such as Figure 6 shown.

[0020] Figure 4 It can be seen that the control gate dielectric layer 3 is continuous with the dielectric layer in the deep trench structure 2; the control gate dielectric layer 3 is provided with a first connecting groove 61 located above the second preset area 22, which is used to fill a conductive medium to connect its control gate polycrystalline layer 4 and the polysilicon in the second preset area 22. The control gate dielectric layer 3 and the control gate polycrystalline layer 4 are provided with a second connecting groove 62 located above the first preset area 21, which is used to fill a conductive medium to introduce an electric potential into the polysilicon in the second preset area 22. The control gate dielectric layer 3 and the control gate polycrystalline layer 4 are provided with a third connecting groove 63 located above the well area, which is used to fill a conductive medium to introduce an electric potential into the well area.

[0021] In order to have a specific understanding of the technical content, characteristics and functions of the present invention, a high voltage buried gate N-type trench metal oxide field effect power transistor is taken as an example, and combined with the diagram, the main manufacturing process of the present invention is described as follows: like Figure 7 As shown, the high voltage buried gate N-type trench metal oxide field effect power transistor includes a P-type substrate 101 and an N-type epitaxial layer 102 above the substrate.

[0022] N-type well region 108, deep P-type well region 103. The N-type epitaxial layer is epitaxial layer 1.

[0023] A plurality of N-type well regions 108, a deep P-type well region 103, an N+ diffusion layer 109, a P+ diffusion layer 110 and a deep silicon trench 104 are formed in the N-type epitaxial layer 102. Figure 2 The deep groove structure 2; In the deep silicon trench 104, there is a buried polysilicon layer 105, namely Figure 2 The polysilicon located in the first preset area 21; The dielectric layer 106 (ie, the dielectric layer 106 of the MOS device located above the N-type epitaxial layer 102) Figure 2 The control gate dielectric layer 3) in the deep silicon trench 104 is directly extended to form a dielectric layer in the deep silicon trench 104 as Figure 2 The dielectric layer isolating the first preset area 21 and the second preset area 22; the trench polycrystalline control gate 107 (ie, Figure 2 The control gate polycrystalline layer 4) in the deep silicon trench 104 is directly extended to form a polycrystalline layer in the deep silicon trench 104 as Figure 2 Since the control gate polycrystalline layer 4 is located above the control gate dielectric layer 3, that is, above the N-type epitaxial layer 102, and the trench polycrystalline control gate 107 is located above the dielectric layer 106, in order to allow the trench polycrystalline control gate 107 above the N-type epitaxial layer 102 to directly extend into the deep silicon trench 104, a hole can be opened in the dielectric layer 106 above the N-type epitaxial layer 102, that is, Figure 4 The first connecting groove 61 is formed in the deep silicon groove 104 and filled with homogeneous polysilicon, and the trench polycrystalline control gate 107 is introduced into the deep silicon groove 104.

[0024] The P-type substrate 101 is used as an isolation layer of the bottom plate of the three-dimensional capacitor in the circuit and is electrically connected to the lowest potential in the circuit through the P-type well region, the P+ diffusion layer, the metal layer, etc.; the N-epitaxial layer is formed on the silicon surface by epitaxy or diffusion to form an N-type doped semiconductor thin layer with a lower doping concentration than the N+ substrate layer; the deep P-type well region is formed on the N-epitaxial layer by diffusion or ion implantation to form a P-type doped silicon semiconductor thin layer, so as to be used as the common lowest potential terminal in the circuit; Thus, the buried polysilicon layer 105 and the trench polycrystalline control gate 107 located on the left / right side thereof form a first PIP capacitor C1; the trench polycrystalline control gate 107 located in the deep silicon trench 104 and the N-type well region 108 form a first PIS capacitor C2; the N-type well region 108 and the trench polycrystalline control gate 107 located above the N-type epitaxial layer 102 form a second PIS capacitor C3; the buried polysilicon layer 105 and the trench polycrystalline control gate 107 located above the N-type epitaxial layer 102 form a second PIP capacitor C4.

[0025] Since the N-type well region 108 and the buried polysilicon layer 105 are located inside, it is necessary to open holes in the dielectric layer 106 and the trench polysilicon control gate 107 above the N-type epitaxial layer 102 to introduce an electric potential. Generally, a groove is opened above the buried polysilicon layer 105 and filled with a conductive medium 111 to introduce an electric potential to the buried polysilicon layer 105, and a groove is opened above the N+ diffusion layer 109 and filled with a conductive medium 111 to introduce an electric potential to the N-type well region 108. Figure 8 The conductive medium 111 in the groove forms the interconnection structure 50 of the device, and the interconnection structure 50 is arranged in the electrical insulation layer 112 above the trench polycrystalline control gate 107, and the electrical insulation layer 112 extends downward to form a sidewall for isolating the conductive medium 111 from the trench polycrystalline control gate 107. It can be seen that the interconnection structure 50 of the device only includes the conductive medium 111 in the electrical insulation layer 112, and the structure is simple.

[0026] The top view of the device composed of multiple deep trench structures is shown in Fig. 9 shown.

[0027] When in use, the trench polycrystalline control gate 107 is connected to the positive electrode, and the conductive medium 111 is connected to the negative electrode. Thus, the above four capacitors are electrically connected in parallel through metal, so that capacitors are made on the surface and in the body of the trench type high voltage buried gate metal oxide field effect transistor per unit area, and the actual capacitors are distributed in a three-dimensional shape, thereby increasing the actual capacitance value.

[0028] In the device, the N-type well region 108 is made in the deep N-type well region by diffusion or ion implantation, and is used as the lower plate of the vertical PIS capacitor and the horizontal PIS; the buried polysilicon layer 105 is made by depositing intrinsic polycrystalline inside the silicon groove and performing N-type saturation doping or depositing in-situ N-type doped polycrystalline, and is used as the lower plate of the vertical PIP capacitor and the horizontal PIP capacitor, and is electrically connected to the N-type well region; the dielectric layer 106 of the MOS tube is grown on the surface of the buried polycrystalline silicon layer and the N+ diffusion layer by low-pressure chemical vapor deposition, and optionally, a silicon nitride layer or other insulating dielectric layer is grown on the surface of the silicon dioxide layer, as the vertical It is used as the capacitor dielectric layer of the vertical PIS capacitor, the horizontal PIS capacitor, the vertical PIP capacitor, and the horizontal PIP capacitor; the trench polycrystalline control gate 107 is directly above the buried polysilicon layer in the silicon groove, and is made by depositing intrinsic polycrystalline inside the silicon groove and performing N-type saturation doping or depositing in-situ N-type doped polycrystalline, and is used as the upper plate of the vertical PIS capacitor, the horizontal PIS capacitor, the vertical PIP capacitor, and the horizontal PIP capacitor; the N+ diffusion layer is made by ion implantation, and is used as the electrical lead-out layer of the vertical PIS capacitor and the horizontal PIS capacitor and is electrically connected to the metal layer; the P+ diffusion layer is made by ion implantation, and is used as the electrical connection layer between the isolation layer and the metal layer.

[0029] The power transistor can be constructed by the following steps: (1) Grow an N-type epitaxial layer 102 with a thickness of 4-20 μm on a P-type substrate 101, with a doping concentration of 1e14 cm -3 -1e16cm -3 (2) on the N- type epitaxial layer 102 by patterning the mask, and ion implantation BF2 or B11, to produce a deep P-type well region 103; (3) In the N-type epitaxial layer 102, phosphorus or As is ion-implanted to form an N-type well region 108 by patterning the layer; (4) A deep silicon trench 104 with a depth of 1-10 μm is produced by using a pattern mask and a dry etching method; (5) thermally oxidizing the deep silicon trench 104, then depositing polysilicon, and selectively etching the polysilicon to form a buried polysilicon layer 105; (6) depositing polysilicon and selectively dry-etching the polysilicon to produce a trench polycrystalline control gate 107 of the MOS transistor; (7) Produce the STI isolation dielectric layer of the entire circuit through thermal oxidation, selective masking, and etching methods; (8) Produce the gate dielectric layer of low-voltage CMOS circuits through low-temperature oxidation method; (9) Depositing polysilicon and producing the control gate polycrystalline layer of the MOS transistor through pattern masking and etching; (10) Through the growth and etching technology of different materials, the sidewall area of ​​self-aligned injection is produced (11) Using a pattern mask, N+ and P+ regions are produced; (12) A dielectric insulating layer is produced, and lead holes are produced through pattern masking and etching.

[0030] (13) Make a metal lead layer, such as Fig.10 As shown, it includes two discontinuous parts, one part is connected to the substrate and the polysilicon layer through the lead hole as a negative electrode, and the other part is connected to the control gate polycrystalline layer as a positive electrode.

[0031] It should be understood that many other layers may also be present, such as spacer elements and / or other suitable components, which are omitted from the illustration for simplicity.

[0032] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device capacitor structure; the semiconductor device comprises an epitaxial layer, the epitaxial layer having a deep trench structure and well regions located on both sides of the deep trench structure; characterized in that: The upper surface of the epitaxial layer has a control gate dielectric layer and a control gate polycrystalline layer; The deep trench structure has n first preset areas and n+1 second preset areas formed by isolation of a dielectric layer, wherein the first preset area is located between two second preset areas; the first preset area and the second preset area are both filled with polysilicon; the first second preset area and the n+1 second preset area are isolated from the well area by a dielectric layer; The first preset area and the second preset area filled with polysilicon and the dielectric layer located between the first preset area and the second preset area form a first PIP capacitor; The second preset area and the well area filled with polysilicon and the dielectric layer located between the polysilicon and the well area in the second preset area form a first PIS capacitor; The well region, the control gate polycrystalline layer and the control gate dielectric layer form a second PIS capacitor; The first preset area filled with polysilicon, the control gate dielectric layer and the control gate polycrystalline layer form a second PIP capacitor; The control gate polycrystalline layer and the second preset region filled with polycrystalline silicon are connected to the positive electrode, and the first preset region filled with polycrystalline silicon and the well region are connected to the negative electrode.

2. The capacitor structure according to claim 1, characterized in that: The control gate dielectric layer is continuous with the dielectric layer located in the deep trench structure.

3. The capacitor structure according to claim 1, characterized in that: The control gate dielectric layer is provided with a first connecting groove located above the second preset area, which is used to be filled with a conductive medium to connect the control gate polycrystalline layer and the polysilicon in the second preset area.

4. The capacitor structure according to claim 1, characterized in that: The control gate dielectric layer and the control gate polycrystalline layer are provided with a second connecting groove located above the first preset area, which is used to fill a conductive medium so as to introduce an electric potential to the polycrystalline silicon in the second preset area; An oxide layer is formed inside the second connecting groove.

5. The capacitor structure according to claim 1, characterized in that: The control gate dielectric layer and the control gate polycrystalline layer are provided with a third connecting groove located above the well region, which is used to fill a conductive medium to introduce an electric potential into the well region; and an oxide layer is provided inside the third connecting groove.

6. A method for manufacturing a semiconductor device capacitor structure, characterized in that: The following steps are involved: (1) providing a substrate, and forming a deep trench in the substrate; (2) forming an oxide layer on the surface of the deep trench and filling it with a polysilicon layer; (3) Selectively etching the polysilicon layer and filling the etched area with a dielectric layer; (4) depositing a control gate dielectric layer on the substrate, and selectively etching the control gate dielectric layer to form a first connecting groove region; (5) Depositing polysilicon to produce the control gate polycrystalline layer of the MOS transistor; (6) etching the control gate dielectric layer and the control gate polycrystalline layer to form a second connecting groove and a third connecting groove region; (7) depositing an insulating layer, and forming lead holes in the second connecting groove and the third connecting groove by pattern masking and etching; (8) A discontinuous metal layer is formed, a portion of which is connected to the substrate and the polysilicon layer through the lead hole, and another portion of which is connected to the control gate polysilicon layer.

7. The method for manufacturing a semiconductor device capacitor structure according to claim 6, characterized in that: The substrate in step (1) is a silicon substrate.

8. The method for manufacturing a semiconductor device capacitor structure according to claim 6, characterized in that: The selective etching in step (3) is dry etching.

9. The method for manufacturing a semiconductor device capacitor structure according to claim 6, characterized in that: The material of the dielectric layer is silicon oxide or silicon nitride. 10 . A semiconductor device comprising the capacitor structure according to claim 1 .

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