Semiconductor optical element and method for manufacturing semiconductor optical element

Abstract

The invention provides a semiconductor optical element and a manufacturing method of the semiconductor optical element, which can inhibit unexpected etching. The semiconductor optical element includes: a substrate having a silicon layer; and a semiconductor element formed of a group III-V compound semiconductor and bonded to the silicon layer, the silicon layer having a waveguide, a recessed portion, a land, and a connection portion, the recessed portion being a portion recessed from a surface of the waveguide, the land, and the connection portion, the recessed portion being provided between the waveguide and the land, the land being provided between the land and the connection portion, and the connection portion being provided between the land and the waveguide. The semiconductor element is bonded to the waveguide, the recessed portion, and the connection portion, and has a first tapered portion protruding in a direction in which the waveguide extends, and the connection portion is connected to the waveguide and the platform across the recessed portion.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor optical element and a method for manufacturing the semiconductor optical element. Background Art

[0002] A hybrid semiconductor optical element can be formed by bonding a semiconductor element having optical gain formed of a compound semiconductor to a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) having a waveguide formed thereon (for example, Non-Patent Document 1). After bonding, the semiconductor element is etched or the like to form a tapered shape.

[0003] Prior art literature

[0004] Non-patent literature

[0005] Non-patent document 1: "HIghly efficient double-taper-type coupler between III-V / silicon-on-insulator hybrid device and silicon waveguide" Junichi Suzuki etal. Japanese Journal of Applied Physics 57,094101(2018)pp.094101-1-094101-6 Summary of the invention

[0006] Problems to be solved by the invention

[0007] A groove (trench) is provided in the substrate. Sometimes an etchant enters the groove and the semiconductor element is etched from the bonding interface. There is a risk that the semiconductor element is damaged due to the undesired etching and the bonding strength is reduced. Therefore, the purpose is to provide a semiconductor optical element and a method for manufacturing a semiconductor optical element that can suppress undesired etching.

[0008] Means used to solve problems

[0009] The semiconductor optical element involved in the present disclosure comprises: a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer, the silicon layer having a waveguide, a recess, a platform and a connecting portion, the recess being a portion recessed than the surfaces of the waveguide, the platform and the connecting portion, and being arranged between the waveguide and the platform, the semiconductor element being bonded to the waveguide, the recess and the connecting portion, and having a first tapered portion protruding in the direction in which the waveguide extends, the connecting portion traversing the recess and being connected to the waveguide and the platform.

[0010] Effects of the Invention

[0011] According to the present disclosure, it is possible to provide a semiconductor optical element capable of suppressing unintended etching and a method for manufacturing the semiconductor optical element. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a perspective view showing an example of the semiconductor optical element according to the first embodiment.

[0013] Figure 2A FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0014] Figure 2B FIG. 1 is a top view showing an example of a substrate.

[0015] Figure 3A is a cross-sectional view showing an example of a semiconductor optical element.

[0016] Figure 3B is a cross-sectional view showing an example of a semiconductor optical element.

[0017] Figure 3C is a cross-sectional view showing an example of a semiconductor optical element.

[0018] Figure 4A is a cross-sectional view showing an example of a semiconductor optical element.

[0019] Figure 4B is a cross-sectional view showing an example of a semiconductor optical element.

[0020] Figure 4C is a cross-sectional view showing an example of a semiconductor optical element.

[0021] Figure 5A This is a plan view illustrating a method for manufacturing a semiconductor optical element.

[0022] Figure 5B This is a plan view illustrating a method for manufacturing a semiconductor optical element.

[0023] Figure 6 FIG. 1 is a plan view showing a semiconductor optical element according to a comparative example.

[0024] Fig. 7A is a cross-sectional view showing an example of a semiconductor optical element.

[0025] Figure 7B is a cross-sectional view showing an example of a semiconductor optical element.

[0026] Figure 7C is a cross-sectional view showing an example of a semiconductor optical element.

[0027] Fig.7D is a cross-sectional view showing an example of a semiconductor optical element.

[0028] Fig. 8A It is a plan view showing an example of a semiconductor optical element according to the second embodiment.

[0029] Figure 8B FIG. 1 is a top view showing an example of a substrate.

[0030] Fig. 9A FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0031] Fig. 9B FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0032] Fig. 10A It is a plan view showing an example of a semiconductor optical element according to the third embodiment.

[0033] Fig. 10B FIG. 1 is a top view showing an example of a substrate.

[0034] Fig.11A FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0035] Fig. 11B FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0036] Fig.12 It is a plan view showing an example of a semiconductor optical element according to a fourth embodiment.

[0037] Fig.13A FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0038] Fig. 13B FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0039] Fig. 13C FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0040] Fig.14A FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0041] Fig. 14B FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0042] Fig. 14C FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0043] Fig.15A FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0044] Fig. 15B FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0045] Fig.16AIt is a plan view showing an example of a semiconductor optical element according to the fifth embodiment.

[0046] Fig. 16B FIG. 1 is a top view showing an example of a substrate.

[0047] Fig.17A It is a plan view showing an example of a semiconductor optical element according to the sixth embodiment.

[0048] Fig. 17B FIG. 1 is a top view showing an example of a substrate.

[0049] Fig.18A FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0050] Fig.18B FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0051] Fig. 18C FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0052] Fig.19A FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0053] Fig.19B FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0054] Fig.19C FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0055] Fig. 20A FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0056] Fig. 20B FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0057] Fig. 20C FIG. 1 is a plan view showing an example of a semiconductor optical element.

[0058] Description of Reference Numerals

[0059] 10, 12: substrate;

[0060] 11: waveguide;

[0061] 13, 13a, 13b: concave parts;

[0062] 14: buried oxide layer;

[0063] 15: Platform;

[0064] 16: Si layer;

[0065] 18: Insulation film;

[0066] 20: semiconductor components;

[0067] 21: countertop;

[0068] 22, 25, 11a: conical part;

[0069] 24, 26: electrodes;

[0070] 30: connection part;

[0071] 32, 34: Noodles;

[0072] 35, 36: Partial;

[0073] 40: bonding layer;

[0074] 42, 46, 50: coating layer;

[0075] 44, 52: core layer;

[0076] 100, 110, 200, 300, 400, 500, 600: semiconductor optical components. DETAILED DESCRIPTION

[0077] [Description of Embodiments of the Present Disclosure]

[0078] First, the contents of the embodiments of the present disclosure will be listed and described.

[0079] One embodiment of the present disclosure is a semiconductor optical element, (1) the semiconductor optical element comprises: a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer, the silicon layer having a waveguide, a recess, a platform and a connecting portion, the recess being a portion recessed than the surface of the waveguide, the platform and the connecting portion, and being arranged between the waveguide and the platform, the semiconductor element being bonded to the waveguide, the recess and the connecting portion, and having a first tapered portion protruding in the direction in which the waveguide extends, the connecting portion traversing the recess and connecting to the waveguide and the platform. Since the connecting portion traverses the recess, liquid entering the recess is blocked by the connecting portion. Undesirable etching of the semiconductor element starting from the bonding interface side can be suppressed.

[0080] (2) In the above (1), the connection portion may have a tapered shape. Liquid entering the recess is blocked by the connection portion. Undesired etching of the semiconductor element can be suppressed. Since the connection portion and the semiconductor element have a tapered shape, light loss can be suppressed.

[0081] (3) In the above (1), the portion of the connection portion connected to the waveguide may have a tapered shape, the portion connected to the platform may extend in a direction different from the portion having the tapered shape, and the first tapered portion of the semiconductor element may be located above the portion of the connection portion having the tapered shape. Liquid entering the recessed portion is blocked by the connection portion. Undesired etching of the semiconductor element can be suppressed. Since the connection portion and the semiconductor element have a tapered shape, light loss can be suppressed.

[0082] (4) In any of the above (1) to (3), one surface and the other surface of the connection portion in the direction in which the waveguide extends may have a tapered shape. Since the connection portion and the semiconductor element have a tapered shape, light loss can be suppressed.

[0083] (5) In any one of the above (1) to (4), the semiconductor element may include a first semiconductor layer, a core layer, and a second semiconductor layer, the first semiconductor layer, the core layer, and the second semiconductor layer are stacked in order from the side close to the substrate, and the first tapered portion includes the first semiconductor layer, the core layer, and the second semiconductor layer. This can suppress light loss.

[0084] (6) In any one of the above (1) to (4), the semiconductor element may include a second tapered portion, the second tapered portion being located on the waveguide and opposite to the substrate in the direction in which the waveguide extends, so as to suppress light loss.

[0085] (7) In the above (6), the semiconductor element may include a first semiconductor layer, a core layer, and a second semiconductor layer, the first semiconductor layer, the core layer, and the second semiconductor layer are stacked in order from the side close to the substrate, the first tapered portion includes the first semiconductor layer, and the second tapered portion includes the core layer and the second semiconductor layer. This can suppress light loss.

[0086] (8) In any one of the above (1) to (4), the semiconductor element may include a third semiconductor layer, a core layer, and a fourth semiconductor layer, the core layer is disposed on the waveguide, and the third semiconductor layer and the fourth semiconductor layer are disposed on both sides of the core layer. Liquid entering the recess is blocked by the connecting portion. Undesired etching of the semiconductor element can be suppressed.

[0087] (9) A method for manufacturing a semiconductor optical element, the method comprising the following steps: bonding a semiconductor element formed of a III-V compound semiconductor to a silicon layer of a substrate; and wet etching the semiconductor element to form a first tapered portion on the semiconductor element, the silicon layer having a waveguide, a recess, a platform, and a connecting portion, the recess being a portion recessed from the surface of the waveguide, the platform, and the connecting portion, and being disposed between the waveguide and the platform, the first tapered portion protruding in the direction in which the waveguide extends, the connecting portion traversing the recess and connecting to the waveguide and the platform. Since the connecting portion traverses the recess, liquid entering the recess is blocked by the connecting portion. Undesirable etching of the semiconductor element starting from the bonding interface side can be suppressed.

[0088] [Details of the embodiments of the present disclosure]

[0089] Hereinafter, specific examples of semiconductor optical elements and methods for manufacturing semiconductor optical elements according to embodiments of the present disclosure will be described with reference to the accompanying drawings. In addition, the present disclosure is not limited to these examples, but is indicated by the scope of the claims, and is intended to include all changes within the meaning and scope equivalent to the scope of the claims.

[0090] <First Embodiment>

[0091] (Semiconductor Optical Components)

[0092] Figure 1 FIG. 2 is a perspective view showing an example of a semiconductor optical element 100 according to the first embodiment. Figure 1 As shown, the semiconductor optical element 100 is a hybrid element having a substrate 10 and a semiconductor element 20. The semiconductor element 20 is an element including a III-V compound semiconductor layer. The semiconductor element 20 is a modulator that modulates light by changing the refractive index according to a voltage. The substrate 10 propagates light. The Z-axis direction is the normal direction of the upper surface of the substrate 10. The X-axis direction is a direction parallel to the waveguide. The Y-axis direction is orthogonal to the X-axis direction and the Z-axis direction.

[0093] The substrate 10 is an SOI substrate including a substrate 12, a buried oxide layer 14, and a silicon (Si) layer 16 stacked in sequence in the Z-axis direction. The substrate 12 is formed of Si, for example. The buried oxide layer 14 is formed of silicon oxide (SiO2), for example. The thickness of the buried oxide layer 14 is, for example, 3 μm. The thickness of the Si layer 16 is, for example, 220 nm. The upper surface of the substrate 10 and the surface of the semiconductor element 20 are covered by an insulating film 18. The insulating film 18 is formed of SiO2 with a thickness of 1 μm, for example. The refractive index of the Si layer 16 is 3.45. The refractive index of the buried oxide layer 14 and the insulating film 18 is lower than that of the Si layer 16, which is 1.45.

[0094] The Si layer 16 of the substrate 10 has a waveguide 11, two recesses 13, two terraces 15, and a connection portion. Figure 1 The connection portion is not shown.

[0095] The waveguide 11 and the recess 13 extend in the same direction, parallel to the X-axis. The two recesses 13 are grooves located on both sides of the waveguide 11. The platform 15 is a plane of the Si layer 16, located at a position opposite to the waveguide 11 in the recess 13. The recess 13 is recessed than the upper surface of the waveguide 11 and the platform 15. The bottom surface of the recess 13 is the Si layer 16, but the bottom surface may also be the buried oxide layer 14. Optical components such as a ring resonator and a ring mirror may also be provided in the Si layer 16. For example, a ring resonator is formed by bending the waveguide 11 into a ring shape.

[0096] The semiconductor element 20 is bonded to the upper surface of the Si layer 16 of the substrate 10 and is located above the waveguide 11, the recess 13 and the terrace 15. The semiconductor element 20 has a terrace 21, an electrode 24 and an electrode 26. The terrace 21 of the semiconductor element 20 is located above the waveguide 11. The terrace 21 has a tapered portion 22 (first tapered portion) at the front end. The tapered portion 22 protrudes from the semiconductor element 20 and tapers along the waveguide 11. The insulating film 18 has openings on the terrace 21 and on the cladding layer 42.

[0097] The electrode 24 extends from the top of the table 21 to the upper surface of the insulating film 18 outside the table 21. The electrode 24 is formed of a stack of titanium (Ti), platinum (Pt) and gold (Au). The electrode 26 is separated from the electrode 24 and is provided on the upper surface of the insulating film 18, and is formed of a metal such as an alloy of gold, germanium and nickel (AuGeNi). An Au electroplating layer may also be provided on the electrode 24 and the electrode 26. The electrode 24 and the electrode 26 are electrically connected to the semiconductor element 20 through the opening of the insulating film 18.

[0098] Figure 2A 1 is a plan view showing an example of the semiconductor optical element 100, and shows the vicinity of the tapered portion 22 of the semiconductor element 20. The insulating film 18 is shown in a transparent manner. Figure 2B FIG. 1 is a top view showing an example of the substrate 10. Figure 2A as well as Figure 2B FIG. 2 shows the vicinity of one end of the semiconductor element 20. The end on the opposite side of the semiconductor element 20 also has the same structure. Figure 2A as well as Figure 2B As shown in FIG. 1 , the direction on one side of the X-axis is defined as the +X direction, and the direction opposite to the +X direction is defined as the -X direction.

[0099] like Figure 2AAs shown, the tapered portion 22 of the semiconductor element 20 protrudes in the +X axis direction from the end of the semiconductor element 20. The width of the tapered portion 22 increases as it is closer to the semiconductor element 20, and decreases as it is farther from the semiconductor element 20.

[0100] like Figure 2A as well as Figure 2B As shown, the Si layer 16 of the substrate 10 has a connection portion 30. One connection portion 30 is provided in one recess 13. The connection portion 30 crosses the recess 13 and is connected to the waveguide 11 and the platform 15. One end of the connection portion 30 is connected to the waveguide 11. The other end of the connection portion 30 is connected to the platform 15.

[0101] The recessed portion 13 is located on the +X side and the -X side of the connection portion 30. The recessed portion 13 on the +X side is referred to as a recessed portion 13a. The recessed portion 13 on the -X side is referred to as a recessed portion 13b. The connection portion 30 partitions the recessed portion 13a from the recessed portion 13b.

[0102] The connection portion 30 has a tapered shape, and similarly to the tapered portion 22 of the semiconductor element 20, extends in the extension direction of the waveguide 11 and tapers at the front end in the direction. The surface 32 of the connection portion 30 faces the +X direction. The surface 34 faces the -X direction. The surface 32 has a tapered shape along the X-axis direction. The portion of the surface 34 that is connected to the waveguide 11 is perpendicular to the waveguide 11 and parallel to the Y-axis direction. The portion of the surface 34 that is connected to the platform 15 has a tapered shape.

[0103] The tapered portion 22 of the semiconductor element 20 is located above the waveguide 11, the connection portion 30, and the platform 15. The front end of the tapered portion 22 is located above the waveguide 11. The portion (base end) opposite to the front end of the tapered portion 22 is located above the platform 15. The portion between the front end and the base end of the tapered portion 22 is located above the connection portion 30. The surface 32 of the connection portion 30 is located outside the tapered portion 22. In other words, the tapered portion 22 does not protrude toward the +X side from the surface 32 of the connection portion 30, but is located on the -X side from the surface 32.

[0104] Figure 2A The width W1 of the waveguide 11 in the Y-axis direction is, for example, 1 μm. The width W2 of the recess 13 is, for example, 4 μm. The thickness of the connection portion 30 is, for example, 0.5 μm, but may be 1 μm or less.

[0105] FIG. 3A to FIG. 4C is a cross-sectional view showing a semiconductor optical element 100 by way of example, and Figure 2A The Si layer 16 in the substrate 10 is shown, and the substrate 12 and the buried oxide layer 14 are omitted. FIG. 3A to FIG. 4CAs shown, the upper surfaces of the waveguide 11, the platform 15 and the connection portion 30 are located at the same height. The bottom surface of the recess 13 is recessed than the upper surface of the waveguide 11 and the like.

[0106] like Figure 3A As shown, the waveguide 11 is located between the two recesses 13a. FIG. 3B to FIG. 4B As shown in FIG. 1 , the connection portion 30 extends from the waveguide 11 toward the platform 15. As the connection portion 30 approaches the platform 15, the width of the recess 13a decreases. Figure 4B As shown, the connection part 30 is separated from the waveguide 11. The recess 13b is located between the connection part 30 and the waveguide 11. The recess 13a is located between the connection part 30 and the platform 15. Between the line A5 and the line A6, the connection part 30 and the platform 15 are integrated. The recess 13a disappears. Figure 4C As shown, the recess 13 b is located between the platform 15 and the waveguide 11 .

[0107] like FIG. 3B to FIG. 4C As shown, the semiconductor element 20 has a bonding layer 40, a cladding layer 42 (the above layers are the first semiconductor layer), a core layer 44 and a cladding layer 46 (the second semiconductor layer). The bonding layer 40 is in contact with the upper surface of the Si layer 16 of the substrate 10 and is bonded to the Si layer 16. The cladding layer 42, the core layer 44 and the cladding layer 46 are stacked in this order on the upper surface of the bonding layer 40. The tapered portion 22 is formed by the bonding layer 40, the cladding layer 42, the core layer 44 and the cladding layer 46.

[0108] The semiconductor element 20 has a vertical pin (positive-intrinsic-negative) junction. The bonding layer 40 is formed, for example, of indium gallium arsenic phosphide (InGaAsP). The cladding layer 42 is formed, for example, of n-type indium phosphide (n-InP). The total thickness of the bonding layer 40 and the cladding layer 42 is, for example, 0.7 μm. The cladding layer 46 is formed, for example, of p-type indium phosphide (p-InP). The thickness of the cladding layer 46 is, for example, 0.7 μm. The cladding layer 42 is electrically connected to the electrode 26. The cladding layer 46 is electrically connected to the electrode 24.

[0109] The core layer 44 has a multi-quantum well structure (MQW, Multi Quantum Well), including a plurality of well layers and barrier layers stacked alternately. The well layers and barrier layers are formed, for example, of undoped semi-insulating indium gallium arsenic phosphide (InGaAsP). The thickness of the core layer 44 is, for example, 0.4 μm. The band gap wavelength of the core layer 44 is 1.2 μm.

[0110] The insulating film 18 covers the upper surface and side surfaces of the stage 15 , the bottom surface of the recess 13 , the side surfaces and upper surface of the waveguide 11 , and the side surfaces and upper surface of the semiconductor element 20 .

[0111] The semiconductor element 20 and the substrate 10 are optically coupled by evanescent light coupling. Light is injected into the waveguide 11 of the substrate 10 . The light propagates in the waveguide 11 of the substrate 10 and is transferred to the semiconductor element 20 . FIG. 3A to FIG. 4C The dot-dash line in represents the distribution of light.

[0112] The semiconductor element 20 has a tapered portion 22. The surface 32 and the surface 34 of the connecting portion 30 also have a tapered shape. The width of the tapered portion 22 and the connecting portion 30 gradually widens along the X-axis. The refractive index changes slightly. The light gradually changes shape while migrating to the semiconductor element 20. Figure 4A As shown, the connecting portion 30 is clamped in the recess 13a. Figure 4B As shown, the recess 13b is located between the connecting portion 30 and the waveguide 11. Before the light diffuses laterally, it is gathered again near the waveguide 11. The light is not easily radiated laterally. The excitation of the multimode optical fiber is also suppressed. The loss of light can be reduced.

[0113] Light is modulated by applying a voltage to the electrodes 24 and 26 of the semiconductor element 20. The modulated light is transferred from the semiconductor element 20 to the waveguide 11 of the substrate 10.

[0114] (Manufacturing method)

[0115] The manufacturing method of the semiconductor optical element 100 is described. For example, the substrate 10 in the wafer state is dry-etched to form the recessed portion 13a and the recessed portion 13b in the Si layer 16. The portion of the Si layer 16 that is covered by a mask (not shown) and is not dry-etched is the waveguide 11, the platform 15, and the connecting portion 30. Figure 2B The substrate 10 is processed in the manner shown. After dry etching, the mask is removed.

[0116] The wafer different from the substrate 10 contains, for example, InP. For example, the wafer is subjected to metal organic chemical vapor deposition (MOCVD) to epitaxially grow the bonding layer 40, the cladding layer 42, the core layer 44, and the cladding layer 46. The wafer is cut to form the semiconductor element 20. In this process, the semiconductor element 20 is rectangular and does not have the terrace 21 or the like.

[0117] Figure 5A as well as Figure 5B 1 is a top view showing an example of a method for manufacturing a semiconductor optical element 100. Figure 5AAs shown, the semiconductor element 20 is bonded to the Si layer 16 of the substrate 10. The upper surface of the Si layer 16 and the surface of the bonding layer 40 of the semiconductor element 20 are activated by irradiating plasma. The bonding layer 40 is brought into contact with the upper surface of the Si layer 16. Annealing is performed at, for example, 150° C. to bond the semiconductor element 20 to the Si layer 16. The semiconductor element 20 is located on the waveguide 11, the terrace 15, the recessed portion 13 a and the recessed portion 13 b, and the connecting portion 30.

[0118] The InP substrate is removed from the semiconductor element 20. The mesa 21 and the tapered portion 22 are formed on the semiconductor element 20. The above process is performed by wet etching. In the InP cladding layer 42 and the cladding layer 46, for example, a mixed aqueous solution of hydrochloric acid and phosphoric acid is used as an etchant. In the InGaAsP core layer 44, for example, sulfuric acid and hydrogen peroxide are used as an etchant. A silicon oxide (SiO2) film is used as an etching mask. Buffered hydrofluoric acid is used to remove silicon oxide.

[0119] The above liquid is immersed in Figure 5B The concave portion 13a of the Si layer 16 is indicated by the diagonal lines. The connecting portion 30 of the Si layer 16 crosses the concave portion 13 and separates the concave portion 13a from the concave portion 13b, functioning as a dam to block the liquid. Since the connecting portion 30 blocks, the infiltration of the liquid into the concave portion 13b is suppressed. Etching from the bonding interface side of the semiconductor element 20 is suppressed. Figure 2A As shown, the semiconductor element 20 is formed with a tapered portion 22 and the like.

[0120] After etching of the semiconductor element 20, the insulating film 18 is provided. The electrode 24 and the electrode 26 are provided by vacuum deposition or the like. By cutting the wafer, a plurality of semiconductor optical elements 100 are formed from the wafer.

[0121] (Comparative Example)

[0122] Figure 6 FIG. 1 is a top view of a semiconductor optical element 110 according to a comparative example. No connection portion 30 is provided on the Si layer 16. The semiconductor element 20 is located above the waveguide 11 and the recess 13. The semiconductor element 20 has a tapered portion 22 and a tapered portion 25. The tapered portion 22 and the tapered portion 25 are located at the front end of the semiconductor element 20. The tapered portion 25 is located inside the tapered portion 22. Figure 6 Located on the -X side.

[0123] 7A to 7D is a cross-sectional view showing a semiconductor optical element 110 by way of example, and Figure 6 The cross section along line B2, line B3, line B4 and line B5. The cross section along line B1 is Figure 3A same.

[0124] like 7A to 7D As shown in FIG. 1 , the recess 13 extends from the outside of the semiconductor element 20 to below the semiconductor element 20. Figure 7B as well as Figure 7C As shown, the tapered portion 22 of the semiconductor element 20 is formed by the bonding layer 40 and the cladding layer 42. Figure 7C As shown, the tapered portion 25 is formed by a core layer 44 and a cladding layer 46. Light migrates from the waveguide 11 to the semiconductor element 20.

[0125] like 7A to 7D As shown, the semiconductor element 20 is covered with the insulating film 18. It is difficult to form the insulating film 18 on the lower surface of the semiconductor element 20 and the portion of the recess 13 overlapping with the semiconductor element 20. The surface of the semiconductor element 20 is protected by the insulating film 18, but the lower surface of the semiconductor element 20 is difficult to be protected by the insulating film 18. In the wet etching process, the etchant penetrates into the recess 13 and also flows under the semiconductor element 20. The semiconductor element 20 is etched from the lower surface. The semiconductor element 20 is damaged, and the semiconductor element 20 is easily detached from the substrate 10.

[0126] According to the first embodiment, the silicon layer 16 of the substrate 10 has the waveguide 11, the recess 13, the terrace 15, and the connection portion 30. Figure 2A as well as Figure 2B As shown, the connection portion 30 is provided between the waveguide 11 and the platform 15, and crosses the recess 13. The semiconductor element 20 is bonded to the silicon layer 16. Wet etching is performed to form the tapered portion 22 on the semiconductor element 20. The liquid such as the etchant is blocked by the connection portion 30 and is difficult to penetrate into the recess 13b on the -X side of the connection portion 30. Undesired etching of the semiconductor element 20 starting from the bonding interface can be suppressed. The semiconductor element 20 is not easily damaged, and peeling can also be suppressed.

[0127] In the manufacturing process, liquids such as hydrochloric acid-based etchants, buffered hydrofluoric acid, sulfuric acid and hydrogen peroxide are used. These liquids are blocked by the connecting portion 30, and the intrusion into the recess 13b is suppressed. Undesired etching of the semiconductor element 20 can be suppressed. Sometimes other liquids are used depending on the material of the semiconductor element 20. Liquids are also used in the cleaning process. These liquids can be blocked by the connecting portion 30.

[0128] The connection portion 30 has a tapered shape from the position connected to the waveguide 11 to the position connected to the platform 15. The connection portion 30 approaches the platform 15 from the waveguide 11 along the extension direction of the waveguide 11. The light propagating in the waveguide 11 gradually changes its shape and migrates to the semiconductor element 20. The light is not easily radiated in the lateral direction. The excitation of the multimode optical fiber is suppressed. The loss of light can be suppressed.

[0129] The surface 32 and the surface 34 of the connection part 30 have a tapered shape. The waveguide 11 extends from the connection part 30 in the +X direction and the -X direction. The light is distributed in the waveguide 11, diffused in the lateral direction in the connection part 30, and gathered again in the center. The light changes adiabatically, so the loss can be suppressed.

[0130] The semiconductor element 20 has a tapered portion 22. The tapered portion 22 includes a bonding layer 40, a cladding layer 42, a core layer 44, and a cladding layer 46. Light gradually changes shape in the tapered connection portion 30 and the tapered portion 22 of the semiconductor element 20, and is transferred to the semiconductor element 20. The loss of light can be suppressed. As described later, the semiconductor element 20 may also have two tapered portions, the tapered portion 22 and the tapered portion 25.

[0131] <Second Embodiment>

[0132] Fig. 8A FIG. 1 is a plan view showing an example of a semiconductor optical element 200 according to the second embodiment. Figure 8B 1 is a plan view showing an example of the substrate 10. Description of the same structure as that of the first embodiment will be omitted.

[0133] The substrate 10 has a connection portion 30. A portion of the connection portion 30 is tapered. Figure 8B As shown, part 35 of the connection part 30 is located at the front end of the connection part 30, has a tapered shape, and is connected to the waveguide 11. The length L1 of part 35 is, for example, 20 μm or more. Part 36 of the connection part 30 is closer to the -X side than part 35. Part 36 extends in a direction different from that of part 35. Part 36 is, for example, perpendicular to the waveguide 11 and parallel to the Y-axis direction. The length L2 of part 36 is smaller than the length L1, for example, 3 μm or less. The surface 32 has a tapered shape along the part 35, and extends perpendicularly to the waveguide 11 along the part 36. The surface 34 has a tapered shape.

[0134] Fig. 9A as well as Fig. 9B 2 is a top view showing an example of a semiconductor optical element 200, and shows a cross section at the position of line C4 and a cross section at the position of line C5. Figure 3A The cross-sectional view along line C2 is the same as Figure 3B The cross-sectional view along line C3 is the same as Figure 3C The cross-sectional view along line C6 is the same as Figure 4C same.

[0135] like Fig. 9A As shown, there is no concave portion 13 at the position of line C4. The waveguide 11, the platform 15 and the connecting portion 30 are integrated. Fig. 9B As shown, at the position of line C5 , the recess 13 b is located between the waveguide 11 and the connecting portion 30 .

[0136] According to the second embodiment, the liquid such as an etchant is blocked by the connection portion 30 and is less likely to enter the recessed portion 13b on the -X side of the connection portion 30. Unintended etching of the semiconductor element 20 starting from the bonding interface can be suppressed.

[0137] Light migrates from the waveguide 11 to the semiconductor element 20. The tapered portion 22 of the semiconductor element 20 is located above the portion 35 and above the portion 36. Light propagating in the waveguide 11 is transferred to the semiconductor element 20 at the portion 35. Since the portion 35 has a tapered shape, light loss is suppressed. The portion 36 of the connection portion 30 is connected to the waveguide 11 and the platform 15.

[0138] Since the length L2 of the portion 36 is, for example, 3 μm, the diffusion of light is suppressed, and the light is gathered near the waveguide 11. The lateral radiation of light is suppressed, and it is also difficult to excite the multimode optical fiber. The loss of light can be suppressed. If the portion 36 is long, the light is radiated laterally. If the portion 36 is too short, there is a risk that the etchant will seep out of the portion 36 and penetrate into the recess 13b. The length L2 of the portion 36 is, for example, 3 μm, and is set to be less than 10 μm. The radiation of light can be suppressed, and the penetration of the etchant can be suppressed.

[0139] The surface 32 and the surface 34 of the connection portion 30 have a tapered shape. Since light changes adiabatically, loss can be suppressed.

[0140] <Third Embodiment>

[0141] Fig. 10A FIG. 1 is a plan view showing an example of a semiconductor optical element 300 according to the third embodiment. Fig. 10B 1 is a top view showing an example of the substrate 10. The description of the same structure as that of the first embodiment or the second embodiment is omitted. Fig. 10B As shown, the portion 36 of the connecting portion 30 in the third embodiment is longer than that in the second embodiment. The length L3 of the portion 36 is longer than that in the second embodiment. Figure 8B The length L2 in the embodiment is large, for example, 20 μm. The other structures are the same as those in the second embodiment.

[0142] Fig.11A as well as Fig. 11B is a top view showing an example of a semiconductor optical element 300, and Fig. 10A The cross-sectional view along line D1 is the same as the cross-sectional view along line D4 and line D5. Figure 3A The cross-sectional view along line D2 is the same as Figure 3B The cross-sectional view along line D3 is the same as Figure 3C The cross-sectional view along line D6 is the same as Figure 4C Same. Fig.11A as well as Fig. 11BAs shown, at the positions of line D4 and line D5, the waveguide 11, the platform 15 and the connecting portion 30 are integrated.

[0143] According to the third embodiment, since the connection portion 30 blocks the etchant, the etchant is unlikely to enter the recessed portion 13 b , thereby suppressing unintended etching of the semiconductor element 20 .

[0144] Light migrates from the waveguide 11 to the semiconductor element 20. The portion 36 of the connection portion 30 is long. Therefore, light propagating in the waveguide 11 diffuses laterally after reaching the portion 36. Between the line D5 and the line D6, the shape of the Si layer 16 changes from the portion 36 to the waveguide 11. Since the refractive index changes sharply, light is radiated. Compared with the second embodiment, the loss of light is large.

[0145] <Fourth Embodiment>

[0146] Fig.12 1 is a plan view showing an example of a semiconductor optical device 400 according to the fourth embodiment. The semiconductor device 20 has a tapered portion 22 (first tapered portion) and a tapered portion 25 (second tapered portion). The other structures are the same as those of the second embodiment.

[0147] FIG. 13A to FIG. 15B 4 is a top view showing a semiconductor optical element 400. Fig.12 The cross-sectional view along line E1 is similar to the cross-sectional view along line E2 to line E9. Figure 3A same.

[0148] like FIG. 13A to FIG. 14A As shown, the tapered portion 22 includes a bonding layer 40 and a cladding layer 42, but does not include a core layer 44 and a cladding layer 46. Fig. 14B As shown in FIG. 2 , a bonding layer 40 and a coating layer 42 are provided between the tapered portion 22 and the tapered portion 25 in the semiconductor element 20. Fig. 14C as well as Fig.15A As shown, the tapered portion 25 is located on the upper surface of the cladding layer 42, including a core layer 44 and a cladding layer 46. Fig. 15B As shown, a bonding layer 40 , a cladding layer 42 , a core layer 44 , and a cladding layer 46 are provided on the −X side of the tapered portion 25 .

[0149] According to the fourth embodiment, the liquid such as an etchant is blocked by the connection portion 30 and is less likely to enter the recessed portion 13b on the -X side of the connection portion 30. Unintended etching of the semiconductor element 20 starting from the bonding interface can be suppressed.

[0150] The portion 35 connected to the waveguide 11 in the connection portion 30 has a tapered shape. The semiconductor element 20 has a tapered portion 22 and a tapered portion 25. The tapered portion 22 is located above the portion 35 and above the portion 36. The tapered portion 25 is located closer to the -X direction than the tapered portion 22 and is located above the waveguide 11. Light propagates in the waveguide 11 and migrates to the tapered portion 22 of the semiconductor element 20. The light distributed in the center is further transferred to the semiconductor element 20 at the tapered portion 25. The semiconductor element 20 has two tapered portions, thereby suppressing the loss of light.

[0151] The tapered portion 22 includes a bonding layer 40 and a cladding layer 42. The tapered portion 25 is located on the upper surface of the cladding layer 42 and includes a core layer 44 and a cladding layer 46. The light propagating in the waveguide 11 is transferred to the semiconductor element 20 in the tapered portion 22. The light is concentrated to the center on the -X side of the connecting portion 30. In the tapered portion 25, the light is further transferred to the semiconductor element 20. It is possible to transfer the light from the waveguide 11 to the semiconductor element 20 while suppressing the loss of light.

[0152] <Fifth Embodiment>

[0153] Fig.16A FIG. 1 is a plan view showing an example of a semiconductor optical element 500 according to the fifth embodiment. Fig. 16B 1 is a top view showing an example of the substrate 10. The description of the same structure as any one of the first to fourth embodiments will be omitted. Fig.16A as well as Fig. 16B As shown, the connection portion 30 does not have a tapered shape and is parallel to the Y-axis direction. The other structures are the same as those of the first embodiment.

[0154] According to the fifth embodiment, the liquid such as the etching agent is blocked by the connection portion 30 and is not easily penetrated into the recessed portion 13b on the -X side of the connection portion 30. Undesirable etching of the semiconductor element 20 starting from the bonding interface can be suppressed. Fig. 16B As shown, the connection portion 30 is not tapered but extends along the Y-axis direction, so that light can be easily diffused in the lateral direction.

[0155] <Sixth Implementation Method>

[0156] Fig.17A FIG. 1 is a plan view showing an example of a semiconductor optical element 600 according to the sixth embodiment. Fig. 17B 1 is a plan view showing an example of the substrate 10. Description of the same structure as that of any one of the first to fifth embodiments will be omitted.

[0157] The connecting portion 30 has Fig. 8A as well as Figure 8BThe waveguide 11 has a tapered portion 11a. The tapered portion 11a is located below the semiconductor element 20 and tapers toward the -X direction. The tapered portion 11a is the tip of the -X side of the waveguide 11. That is, the waveguide 11 is interrupted in the tapered portion 11a, and a concave portion 13b is located on the -X side of the tapered portion 11a.

[0158] FIG. 18A to FIG. 20C is a top view showing an example of a semiconductor optical element 600, and Fig.17A The cross section along line F2 to line F10. Figure 3A same.

[0159] like FIG. 18A to FIG. 19A As shown, the semiconductor element 20 has a lateral nin (negative-intrinsic-negative: negative-intrinsic-negative) junction. The semiconductor element 20 has a bonding layer 40, a cladding layer 50 and a core layer 52. The cladding layer 50 is formed of, for example, n-type indium gallium arsenic phosphide (n-InGaAsP) and is located on the bonding layer 40. The core layer 52 is formed of, for example, semi-insulating InGaAsP.

[0160] like 18A to 18C As shown, the tapered portion 22 of the semiconductor element 20 is formed by the cladding layer 50 and is located above the waveguide 11 and the connecting portion 30. Fig.19B As shown in FIG. 1 , a coating layer 50 is provided between the tapered portion 22 and the tapered portion 25. Fig.19C As shown in FIG. 1 , the tapered portion 25 is formed by a cladding layer 50 and a core layer 52. The portion of the cladding layer 50 close to the waveguide 11 is thicker than the other portions and is divided into two portions (a third semiconductor layer and a fourth semiconductor layer) in the Y-axis direction. The core layer 52 is provided between the two cladding layers 50. The tapered portion 25 is located above the waveguide 11. FIG. 20A to FIG. 20C As shown, the waveguide 11 becomes thinner and disappears along the -X direction. The concave portion 13b is located below the tapered portion 25.

[0161] According to the sixth embodiment, the liquid such as an etchant is blocked by the connection portion 30 and is less likely to enter the recessed portion 13b on the -X side of the connection portion 30. Unintended etching of the semiconductor element 20 starting from the bonding interface can be suppressed.

[0162] like Fig.17A As shown in FIG. 1 , the tapered portion 25 is located above the waveguide 11 and the recess 13b, and is not disposed on the platform 15. That is, the tapered portion 25 may be made thinner to about 400 μm. This allows light to be focused at the center. The waveguide 11 may be removed at the position of line F10. This allows Figure 1 The positions of the electrodes 24 and 26 are close to the semiconductor element 20 in the Y direction. The semiconductor optical element 600 can be miniaturized.

[0163] As shown in the first to fifth embodiments, the semiconductor element 20 may be a vertical element including semiconductor layers stacked in the longitudinal direction (Z-axis direction), or a horizontal element including semiconductor layers stacked in the transverse direction (Y-axis direction) as shown in the sixth embodiment.

[0164] As mentioned above, although the embodiment of this disclosure was described in detail, this disclosure is not limited to the said specific embodiment, Various deformation|transformation and change are possible within the range of the summary of this disclosure described in a claim.

Claims

1. A semiconductor optical element, wherein: The semiconductor optical element comprises: a substrate having a silicon layer; and A semiconductor element, formed of a III-V compound semiconductor, is bonded to the silicon layer. The silicon layer has a waveguide, a recess, a platform and a connecting portion, The recessed portion is a portion recessed from the surface of the waveguide, the platform, and the connecting portion, and is disposed between the waveguide and the platform. The semiconductor element is bonded to the waveguide, the recess, and the connection portion, and has a first tapered portion protruding in the direction in which the waveguide extends. The connecting portion crosses the recess and is connected to the waveguide and the platform.

2. The semiconductor optical element according to claim 1, wherein The connecting portion has a tapered shape.

3. The semiconductor optical element according to claim 1, wherein A portion of the connection portion connected to the waveguide has a tapered shape, and a portion connected to the platform extends in a direction different from the direction of the portion having the tapered shape. The first tapered portion of the semiconductor element is located above a portion of the connection portion having the tapered shape.

4. The semiconductor optical element according to any one of claims 1 to 3, wherein One surface and the other surface of the connection portion in the direction in which the waveguide extends have a tapered shape.

5. The semiconductor optical element according to any one of claims 1 to 3, wherein The semiconductor element comprises a first semiconductor layer, a core layer and a second semiconductor layer. The first semiconductor layer, the core layer and the second semiconductor layer are stacked in sequence from a side close to the substrate, The first tapered portion includes the first semiconductor layer, the core layer, and the second semiconductor layer.

6. The semiconductor optical element according to any one of claims 1 to 3, wherein: The semiconductor element has a second tapered portion, The second tapered portion is above the waveguide and is located at a position of the first tapered portion opposite to the substrate in the extending direction of the waveguide.

7. The semiconductor optical element according to claim 6, wherein: The semiconductor element comprises a first semiconductor layer, a core layer and a second semiconductor layer. The first semiconductor layer, the core layer and the second semiconductor layer are stacked in sequence from a side close to the substrate, The first tapered portion includes the first semiconductor layer, The second tapered portion includes the core layer and the second semiconductor layer.

8. The semiconductor optical element according to any one of claims 1 to 3, wherein: The semiconductor element comprises a third semiconductor layer, a core layer and a fourth semiconductor layer. The core layer is arranged on the waveguide, The third semiconductor layer and the fourth semiconductor layer are arranged on both sides of the core layer.

9. A method for manufacturing a semiconductor optical element, wherein: The method for manufacturing the semiconductor optical element comprises the following steps: A semiconductor element formed of a III-V compound semiconductor is bonded to a silicon layer of a substrate; as well as wet-etching the semiconductor element to form a first tapered portion in the semiconductor element, The silicon layer has a waveguide, a recess, a platform and a connecting portion, The recessed portion is a portion recessed from the surface of the waveguide, the platform, and the connecting portion, and is disposed between the waveguide and the platform. The first tapered portion protrudes in the direction in which the waveguide extends, The connecting portion crosses the recess and is connected to the waveguide and the platform.

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