Data prefetching method and device, computer equipment and storage medium

Abstract

The invention provides a data prefetching method and device, computer equipment and a storage medium, and is applied to a processor, the method comprises the following steps: after an nth-level storage structure of the processor receives a prefetching mode and a prefetching distance of a first-level storage structure, determining a target data address from a plurality of initial data addresses contained in the prefetching mode according to the prefetching distance, wherein n is an integer greater than or equal to 1, and the prefetching distance is used for indicating the number of initial data addresses of the nth-level storage structure which does not perform data prefetching; and the nth-level storage structure sends a prefetching request corresponding to each target data address to the (n + 1) th-level storage structure. By implementing the method disclosed by the invention, the timeliness of prefetching can be effectively improved, and the pollution of prefetching to the cache is reduced, so that the overall performance of the processor is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of processor technology, and in particular to a data pre-fetching method, device, computer equipment and storage medium. Background Art

[0002] The development of processor storage speed is far behind the development of processor computing speed. The increasingly severe "memory wall" problem seriously restricts the further improvement of processor performance. Cache is a storage mechanism designed based on the principle of program access locality. Its purpose is to make up for the huge gap between processor computing speed and storage access speed as much as possible. The "memory wall" problem makes cache develop in the direction of large capacity and multi-level. The multi-level structure of cache can reduce the average delay of data access with good locality, but it cannot reduce the delay of the first memory access, that is, the computational miss.

[0003] Prefetching technology is the key to improving the processor's memory access performance. An important way to improve memory access performance is to reduce the miss rate of cache access. Prefetching is a way to reduce the compulsive miss by taking the cache lines that the processor may need to each level of storage in advance. Prefetching is essentially a guessing mechanism for program memory access addresses, so it is necessary to analyze program behavior. The core is to utilize the spatial locality and temporal locality that exist during program execution. Its performance improvement also shows a great correlation with the characteristics of the executed program. If the prefetched data block has not been returned when the required data block is used, the prefetching will be untimely, which will reduce the effect of prefetching on the processor performance. Prefetching will occupy the processor's memory bandwidth and generate additional power consumption. In addition, if the wrong cache line is fetched and the prefetching timing is wrong, it may also cause cache pollution. Prefetching needs to be implemented with caution. Prefetching problems will not only not improve the overall performance of the processor, but will reduce the performance of the processor.

[0004] In the related art, it is not possible to effectively solve the problem of untimely prefetching and cache pollution caused by prefetching. Summary of the invention

[0005] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0006] To this end, the purpose of the present disclosure is to propose a data prefetching method, apparatus, computer device and storage medium, which can effectively improve the timeliness of prefetching, reduce the pollution of prefetching to the cache, and thus improve the overall performance of the processor.

[0007] To achieve the above-mentioned purpose, a data prefetching method proposed in an embodiment of the first aspect of the present disclosure is applied to a processor, comprising: After receiving the prefetch mode and prefetch distance of the first-level storage structure, the n-th level storage structure of the processor determines the target data address from the multiple initial data addresses included in the prefetch mode according to the prefetch distance, wherein n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of the initial data addresses for which the n-th level storage structure does not perform data prefetching; The n-th level storage structure sends a pre-fetch request corresponding to each of the target data addresses to the n+1-th level storage structure.

[0008] To achieve the above-mentioned purpose, a data pre-fetching device provided in a second aspect of the present disclosure is applied to a processor, including: a determination module, for the nth level storage structure of the processor, after receiving the prefetch mode and prefetch distance of the first level storage structure, determining the target data address from a plurality of initial data addresses included in the prefetch mode according to the prefetch distance, wherein n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of the initial data addresses for which the nth level storage structure does not perform data prefetching; A sending module is used for the n-th level storage structure to send a pre-fetch request corresponding to each of the target data addresses to the (n+1)-th level storage structure.

[0009] The computer device proposed in the third aspect embodiment of the present disclosure includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the program, the data prefetching method proposed in the first aspect embodiment of the present disclosure is implemented.

[0010] The fourth aspect embodiment of the present disclosure proposes a non-temporary computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the data prefetching method proposed in the first aspect embodiment of the present disclosure is implemented.

[0011] The fifth aspect embodiment of the present disclosure proposes a computer program product. When the instructions in the computer program product are executed by a processor, the data prefetching method proposed in the first aspect embodiment of the present disclosure is executed.

[0012] The data prefetching method, device, computer equipment and storage medium provided by the present disclosure include: after receiving the prefetching mode and prefetching distance of the first-level storage structure, the n-th level storage structure of the processor determines the target data address from the multiple initial data addresses contained in the prefetching mode according to the prefetching distance, wherein n is an integer greater than or equal to 1, and the prefetching distance is used to indicate the number of initial data addresses for which the n-th level storage structure does not perform data prefetching; the n-th level storage structure sends a prefetching request corresponding to each target data address to the n+1-th level storage structure. Thus, the timeliness of prefetching can be effectively improved, the pollution of prefetching to the cache can be reduced, and the overall performance of the processor can be improved.

[0013] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which: Figure 1 is a flowchart of a data pre-fetching method proposed in an embodiment of the present disclosure; Figure 2 is a flow chart of a data pre-fetching method proposed in another embodiment of the present disclosure; Figure 3 is a flow chart of a data pre-fetching method proposed in another embodiment of the present disclosure; Figure 4 is a schematic diagram of a memory hierarchy structure proposed according to the present disclosure; Figure 5 is a diagram of a multi-level timely prefetching architecture proposed in the present disclosure; Figure 6 is a diagram of pre-fetch components of caches at various levels proposed in the present disclosure; Figure 7 is a schematic diagram of hardware implementation of the spatial storage stream prefetching strategy proposed in the present disclosure; Figure 8 is a structural schematic diagram of a data pre-fetching device proposed in an embodiment of the present disclosure; Fig. 9 A block diagram of an exemplary computer device suitable for implementing embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0015] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and are not to be construed as limitations of the present disclosure. On the contrary, the embodiments of the present disclosure include all changes, modifications, and equivalents that fall within the spirit and connotation of the appended claims.

[0016] Figure 1 It is a flowchart of a data pre-fetching method proposed in an embodiment of the present disclosure.

[0017] It should be noted that the executor of the data pre-fetching method of this embodiment is a data pre-fetching device, which can be implemented by software and / or hardware. The device can be configured in a computer device, and the computer device can include but is not limited to a terminal, a server, etc. For example, the terminal can be a mobile phone, a handheld computer, etc.

[0018] like Figure 1 As shown, the data pre-fetching method comprises: S101: After receiving the prefetch mode and prefetch distance of the first-level storage structure, the n-th level storage structure of the processor determines the target data address from the multiple initial data addresses included in the prefetch mode according to the prefetch distance, where n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of initial data addresses for which the n-th level storage structure does not perform data prefetching.

[0019] The storage structure of the processor may refer to a structure configured in the processor for storing data, for example, an N-level cache on the processor chip.

[0020] The first-level storage structure may refer to a first-level cache L1 Cache which is closest to the processor core among the N-level caches.

[0021] The prefetch mode may be used to indicate the address of the data to be prefetched.

[0022] The prefetch distance refers to the number of initial data addresses for which the n-th level storage structure does not perform data prefetching.

[0023] The initial data address refers to the data address included in the pre-fetch mode, and the target data address refers to the address of the data that the n-th level storage structure needs to pre-fetch from the (n+1)-th level storage structure.

[0024] It can be understood that the multiple initial data addresses included in the prefetch pattern are arranged in sequence. When the embodiment of the present disclosure determines the target data address from the multiple initial data addresses included in the prefetch pattern according to the prefetch distance, it can ignore a specified number of initial data addresses that are ranked at the front based on the prefetch distance and use the initial data addresses that are ranked at the back as the target data address.

[0025] S102: The nth level storage structure sends a pre-fetch request corresponding to each target data address to the (n+1)th level storage structure.

[0026] The pre-fetch request refers to a request sent by the n-th level storage structure to the n+1-th level storage structure for pre-fetching data corresponding to a target data address.

[0027] It can be understood that the pre-fetch request sent by the n-th level storage structure to the (n+1)-th level storage structure can be regarded as a data access request.

[0028] Optionally, in some embodiments, when the n-level storage structure sends a prefetch request corresponding to each target data address to the n+1-level storage structure, it may be to determine the first matching result between the prefetch request and the historical prefetch record table, wherein the historical prefetch record table is used to record the prefetch request that the n-level storage structure has sent to the n+1-level storage structure; when the first matching result indicates that the n-level storage structure has not sent a prefetch request to the n+1-level storage structure, the n-level storage structure sends a prefetch request to the n+1-level storage structure. In this way, the bandwidth and power consumption loss caused by the n-level storage structure sending prefetch requests to the same data address multiple times can be effectively avoided.

[0029] The historical pre-fetch record table refers to a pre-configured table for recording pre-fetch requests sent from the n-th level storage structure to the n+1-th level storage structure.

[0030] The first matching result may be used to indicate whether the historical pre-fetch record table contains the pre-fetch request.

[0031] That is, in the embodiment of the present disclosure, when the first matching result indicates that the n-th level storage structure has sent a pre-fetch request to the (n+1)-th level storage structure, the n-th level storage structure may ignore the corresponding pre-fetch request.

[0032] In this embodiment, after receiving the prefetch mode and prefetch distance of the first-level storage structure, the n-th level storage structure of the processor determines the target data address from the multiple initial data addresses included in the prefetch mode according to the prefetch distance, wherein n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of initial data addresses for which the n-th level storage structure does not perform data prefetching; the n-th level storage structure sends a prefetch request corresponding to each target data address to the n+1-th level storage structure. Thus, the timeliness of prefetching can be effectively improved, and the pollution of prefetching to the cache can be reduced, thereby improving the overall performance of the processor.

[0033] Figure 2 It is a flowchart of a data pre-fetching method proposed in another embodiment of the present disclosure.

[0034] like Figure 2 As shown, the data pre-fetching method comprises: S201: After receiving a first access request corresponding to an upper-level storage structure, the n-level storage structure determines a second matching result between the first access request and a historical prefetch record table, wherein the historical prefetch record table is used to record the prefetch request sent by the n-level storage structure to the n+1-level storage structure, and the upper-level storage structure corresponding to the 1st-level storage structure is a processor core of a processor.

[0035] The previous level storage structure may refer to a storage structure that is closer to the processor core than the nth level storage structure.

[0036] The first access request refers to a request for data access sent by the upper level storage structure to the nth level storage structure. In the disclosed embodiment, the first access request includes a pre-fetch request sent by the upper level storage structure to the nth level storage structure.

[0037] The second matching result may be used to indicate whether the n-th level storage structure has sent a pre-fetch request having the same target data address as the first access request to the (n+1)-th level storage structure.

[0038] That is to say, after the n-level storage structure in the embodiment of the present disclosure receives the first access request corresponding to the previous-level storage structure, it can first match the first access request based on the historical prefetch record table to determine whether the n-level storage structure has sent a prefetch request with the same target data address as the first access request to the n+1-level storage structure.

[0039] S202: When the n-level storage structure meets the preset conditions, the n-level storage structure updates the prefetch distance, wherein the preset conditions include: the second matching result indicates that the n-level storage structure has sent a prefetch request with the same target data address as the first access request to the n+1-level storage structure, and there is no data corresponding to the first access request in the n-level storage structure.

[0040] The preset condition refers to the condition configured for whether the n-th level storage structure needs to update the pre-fetch distance in the embodiment of the present disclosure. The specific content of the preset condition can be flexibly configured according to the application scenario, and there is no limitation on this.

[0041] Optionally, in some embodiments, when updating the prefetch distance, a prefetch performance index of the n-th level storage structure may be determined, and the prefetch distance may be updated according to the prefetch performance index. Thus, the practicality and effectiveness of the updated prefetch distance may be guaranteed in combination with the prefetch performance index of the n-th level storage structure.

[0042] Among them, the prefetch performance index can be used to measure the data prefetch capability of the n-th level storage structure.

[0043] Optionally, in some embodiments, the prefetch performance indicator includes at least one of the following: a prefetch hit rate of the n-th level storage structure; and the number of times the n-th level storage structure continuously meets a preset condition. Thus, the prefetch performance indicator can ensure the indication effect of the n-th level storage structure data prefetch capability.

[0044] The prefetch hit rate may be used to indicate the number of successful times in multiple data prefetching processes.

[0045] In this embodiment, after receiving the first access request corresponding to the previous level storage structure, the n-level storage structure determines the second matching result of the first access request and the historical pre-fetch record table, wherein the historical pre-fetch record table is used to record the pre-fetch request sent by the n-level storage structure to the n+1-level storage structure, and the previous level storage structure corresponding to the 1-level storage structure is the processor core of the processor; the n-level storage structure updates the pre-fetch distance when the preset conditions are met, wherein the preset conditions include: the second matching result indicates that the n-level storage structure has sent a pre-fetch request with the same target data address as the first access request to the n+1-level storage structure, and there is no data corresponding to the first access request in the n-level storage structure. In this way, the pre-fetch distance can be flexibly adjusted to ensure that the updated pre-fetch distance can be applied to a variety of application scenarios.

[0046] Optionally, in some embodiments, when determining the target data address from multiple initial data addresses included in the prefetch pattern according to the prefetch distance, the target data address may be determined from multiple initial data addresses included in the prefetch pattern according to the updated prefetch distance. Thus, the practicality of the obtained target data address can be effectively improved based on the updated prefetch distance.

[0047] Figure 3 It is a flowchart of a data pre-fetching method proposed in another embodiment of the present disclosure.

[0048] like Figure 3 As shown, the data pre-fetching method comprises: S301: The first-level storage structure of the processor receives a second access request from a processor core, and generates a prefetch pattern according to the second access request.

[0049] That is, the first-level storage structure of the processor in the embodiment of the present disclosure can receive the second access request of the processor core and generate a prefetch mode according to the second access request, thereby providing a reliable execution basis for the prefetch process of subsequent levels of storage structures.

[0050] Optionally, in some embodiments, when generating a prefetch pattern according to the second access request, a target event identifier corresponding to the second access request may be determined; a historical event identifier matching the target event identifier is determined from a pattern history table, wherein the pattern history table includes multiple historical event identifiers and a historical pattern corresponding to each historical event identifier; and the historical pattern corresponding to the matching historical event identifier is used as the prefetch pattern. In this way, an adapted prefetch pattern can be quickly and accurately determined in combination with the historical data access situation of the processor, and the practicability of the obtained prefetch pattern is guaranteed.

[0051] S302: The first-level storage structure determines a prefetch distance corresponding to the n-th-level storage structure, and sends a prefetch mode and a prefetch distance to the n-th-level storage structure.

[0052] In the embodiment of the present disclosure, when determining the prefetch distance corresponding to the n-th level storage structure, it can be based on a preset relationship table, which contains the prefetch distance corresponding to each storage structure, or it can be based on a data combination method to determine the prefetch distance corresponding to the n-th level storage structure, and there is no limitation on this.

[0053] Optionally, in some embodiments, when determining the pre-fetch distance corresponding to the n-th level storage structure, the number of storage structure layers between the first-level storage structure and the n-th level storage structure may be determined; based on the number of storage structure layers, the initial distance corresponding to the n-th level storage structure is determined; based on the initial distance, the pre-fetch distance corresponding to the n-th level storage structure is determined. Thus, the applicability of the obtained pre-fetch distance can be guaranteed by combining the location information of different storage structures.

[0054] The number of storage structure layers can be used to indicate the number of storage structure layers between the first-level storage structure and the nth-level storage structure. For example, the number of storage structure layers between the first-level storage structure and the seventh-level storage structure is 6.

[0055] The initial distance may refer to a pre-fetch distance in an initial state configured for the n-th level storage structure according to the number of storage structure layers.

[0056] For example, in the embodiments of the present disclosure, when determining the initial distance corresponding to the n-th level storage structure according to the number of storage structure layers, it can be based on a pre-configured relationship table, which contains the initial distances corresponding to the above-mentioned number of storage structure layers. Alternatively, it can be based on statistics or intelligent learning methods to determine the initial distance corresponding to the n-th level storage structure according to the number of storage structure layers, and there is no limitation on this.

[0057] Optionally, in some embodiments, when determining the initial distance corresponding to the n-th level storage structure according to the number of storage structure layers, the product value of the preset distance value and the number of storage structure layers may be determined as the initial distance. Thus, the initial distances corresponding to different levels of storage structures can be quickly configured based on the preset distance value.

[0058] The preset distance value can be flexibly configured according to the application scenario, and there is no restriction on this. For example, when the pre-fetch distance value is configured as 2, the initial distance corresponding to the fifth-level storage structure is .

[0059] In the embodiment of the present disclosure, when determining the pre-fetch distance corresponding to the n-th level storage structure based on the initial distance, the initial distance can be directly used as the pre-fetch distance corresponding to the n-th level storage structure, or the initial distance can be adjusted by a third-party device to obtain the pre-fetch distance corresponding to the n-th level storage structure, and there is no limitation on this.

[0060] Optionally, in some embodiments, when determining the prefetch distance corresponding to the n-th level storage structure based on the initial distance, the prefetch performance index of the n-th level storage structure during multiple data prefetching processes may be determined; the initial distance may be adjusted based on the multiple prefetch performance indexes to obtain the prefetch distance corresponding to the n-th level storage structure. Thus, the data prefetching capability of the n-th level storage structure may be evaluated in combination with the prefetch performance index of the n-th level storage structure during multiple data prefetching processes, and then the initial distance may be adaptively adjusted to ensure that the obtained preset distance can effectively improve the data prefetching capability of the n-th level storage structure.

[0061] For example, in the embodiment of the present disclosure, when determining the pre-fetch distance corresponding to the n-th level storage structure according to the number of storage structure layers, the specific value of the pre-fetch distance may be configured to be in direct proportion to the number of storage structure layers.

[0062] In this embodiment, the first-level storage structure of the processor receives the second access request of the processor core, and generates a prefetch pattern according to the second access request; the first-level storage structure determines the prefetch distance corresponding to the n-th-level storage structure, and sends the prefetch pattern and the prefetch distance to the n-th-level storage structure. Thus, the reliability of the prefetch pattern and the prefetch distance obtained by the n-th-level storage structure can be guaranteed.

[0063] In combination with the above embodiments, the present disclosure aims to improve the timeliness of prefetching and reduce the cache pollution caused by prefetching, thereby improving the overall performance of the processor by setting the prefetching distance and fetching the prefetching blocks to different storage levels at different times.

[0064] like Figure 4 As shown, Figure 4 This is a schematic diagram of the memory hierarchy proposed in the present disclosure, in which a processor includes multiple levels of memory hierarchy. It includes N-level cache (Cache) on the processor chip and off-chip memory. Cache (Cache) is usually composed of static memory (SRAM, Static Random Access Memory), and the cache includes a first-level cache L1Cache, a second-level cache L2 Cache, a third-level cache L3 Cache, and up to an N-level cache LN Cache (also called the last-level cache Last Level Cache, LLC). Off-chip memory is usually composed of dynamic memory (DRAM, Dynamic Random Access Memory). From the first-level cache L1 Cache, the second-level cache L2 Cache, the third-level cache L3 Cache to the last-level cache LLC and off-chip memory, each level of storage hierarchy is farther and farther away from the processor core, the capacity is gradually increasing, and the access delay is also gradually increasing.

[0065] like Figure 5 As shown, Figure 5 It is a multi-level timely prefetching architecture diagram proposed in the present disclosure. The present disclosure provides a multi-level timely prefetching method and device, including: a prefetching component, a processor core, an on-chip N-level cache (Cache) and an off-chip memory.

[0066] In order to solve the problem that the prefetching component prefetches too late and the prefetching is not timely, the present disclosure sets the prefetching distance, skips a section of the prefetching pattern in the head, and performs prefetching. The present disclosure determines that the sign of prefetching too late is that when a normal memory access request accesses the cache, the prefetching request has been issued, but the data has not been returned, that is, the normal access request hits the prefetched block, but the data of the prefetched block has not been returned. In this case, by increasing the prefetching distance and sending a later pattern for prefetching, the problem of prefetching not being timely caused by the prefetching being issued too late is solved.

[0067] The training of the pre-fetch mode disclosed in the present invention is trained by the access request sent by the processor core to the first-level cache. The pre-fetch request is sent to the caches at all levels. The pre-fetch of the caches at all levels does not affect each other. The pre-fetch mode will be sent to the caches at all levels for pre-fetching. The pre-fetching will be performed separately at the caches at all levels, and finally the first-level cache closest to the processor core will be pre-fetched. The processor's pre-fetching of the caches at the following levels can achieve the purpose of making the pre-fetch of the previous level cache hit the cache at the next level, saving more pre-fetching time. Each level of pre-fetch request is a normal access request for the cache at the next level. If the pre-fetch is too late, the pre-fetch distance is dynamically adjusted, thereby achieving timely pre-fetching of caches at all levels.

[0068] The pre-fetch pattern generation disclosed in the present invention is all performed in the first-level cache, and the access request issued by the processor core is used to train the pre-fetch pattern generation, so the pre-fetch pattern generation component is only in the first-level cache. The generated pre-fetch pattern is sent to the caches at various levels for pre-fetching, and the pre-fetch distance sent to each level of cache is different.

[0069] like Figure 6 As shown, Figure 6 It is a pre-fetch component diagram of each level of cache proposed in the present disclosure, and each level of cache includes the pre-fetch component of this level. The multi-level timely pre-fetch of the present disclosure includes a pre-fetch access mode receiving component, a pre-fetch filtering component and a pre-fetch issuing component.

[0070] The prefetch access pattern receiving component is responsible for receiving the prefetch access pattern sent by the prefetch generating component of the first-level cache.

[0071] The pre-fetch issuing component issues a pre-fetch request to the next level storage system according to the pre-fetch distance.

[0072] The pre-fetch filter component records the pre-fetch requests that have been issued. When there is a new pre-fetch request, the pre-fetch filter component is checked first. If the pre-fetch request has been issued, the same pre-fetch request is not issued repeatedly, thereby saving memory access bandwidth.

[0073] After receiving the access request from the previous level cache (including the prefetch request from the previous level cache), each level cache will check the prefetch filter component of this level to determine whether the prefetch request has been issued but the data has not been returned. If the prefetch request has been issued but the data has not been returned, it means that the prefetch of this level is not timely and the prefetch distance needs to be adjusted. The next prefetch will skip a prefetch distance and issue the next prefetch mode.

[0074] The prefetch pattern generation of the first-level cache disclosed in the present invention is applicable to various prefetch strategies, and the commonly used spatial memory streaming (Spatial Memory Streaming, SMS) strategy is used as an embodiment of the prefetch pattern generation.

[0075] Spatial Memory Streaming (SMS) is proposed and evaluated in the context of servers and scientific applications. The SMS hardware prefetcher exploits spatial correlation. Whenever a spatial region is requested for the first time, SMS uses information about misses to look up previously observed patterns in a table. SMS starts observing and recording accesses to the spatial region as long as the application is using it. Whenever the spatial region is no longer in use (i.e., response blocks for the spatial region start to be evicted from the cache), the access information observed by SMS is stored in a Pattern History Table (PHT).

[0076] The information in the pattern history table PHT is in the form of <event, pattern> (<event,pattern> ). Event event can be Program Counter (PC) + Address, Program Counter (PC) + Offset, Address, Offset, i.e. PC+Address / PC+Offset / Address / Offset, etc., which is a piece of information associated with the observed access pattern. That is, if the event occurs again in the future, the corresponding storage access pattern will be used. For example, SMS selects Program Counter (PC) + Offset that triggers the access, i.e., the PC of the instruction that first accesses the spatial region plus the distance between the first requested cache block and the beginning of the spatial region, as the event related to the access pattern. In this way, whenever PC+Offset reappears, the relevant access pattern history will be used to issue a prefetch request. The pattern is the history of accesses that occurred in each spatial region. SMS encodes the access pattern as a bit vector. In this way, for each cache block in the spatial region, a bit is stored to indicate whether the block has been used in the spatial region in the last time, and it is marked as "1" if it is used, and "0" if it is not. Therefore, whenever a pattern is used, prefetch requests are only issued for blocks whose corresponding bits in the storage pattern are "1". Figure 7 It is a schematic diagram of the hardware implementation of the spatial storage stream prefetching strategy proposed in the present disclosure.

[0077] The present invention issues a spatial region prefetch request pattern to each level of cache, i.e., 0x24D8, ..., 0X24F7. When the prefetch request is sent to the next level storage system, it is found that the prefetch request of the next level storage system is sent but the data is not returned, so the distance of sending the prefetch request to the next level storage system is adjusted, such as sending a request to the secondary cache from 0x24F7 instead of 0x24D8. The adjustment of sending the prefetch request can be moved back one mode request each time, or multiple mode requests can be moved back each time, and it can be dynamically adjusted according to the timeliness evaluation of the prefetch.

[0078] The timeliness of prefetching can be evaluated based on the timeliness of prefetching. For example, if prefetching is not timely for the first time, the prefetching request is moved back by one mode request. If prefetching is not timely again, the prefetching distance is adjusted more aggressively, such as the prefetching request can be moved back by two mode requests. The prefetching distance can also be adjusted based on other performance indicators such as the hit rate of the cache at this level.

[0079] In the multi-level cache, a larger prefetch distance is set for the cache that is far from the processor. The prefetch unit skips a prefetch distance to send to the next level cache for prefetching. For example, it skips a larger prefetch distance to prefetch at the second level cache. In this way, when the first level cache prefetches again, it can hit the second level cache, which speeds up the prefetching speed of the first level cache. The specific amount of prefetch distance to skip to send to the next level cache for prefetching can be generated through training. For example, initially, for each level of cache prefetching, two mode requests are shifted backwards. Later, adjustments are made dynamically based on the evaluation of untimely prefetching or the hit rate of caches at each level.

[0080] Figure 8 It is a structural schematic diagram of a data pre-fetching device proposed in an embodiment of the present disclosure.

[0081] like Figure 8 As shown, the data pre-fetching device 80 is applied to a processor, and the device includes: A determination module 801, configured for the nth level storage structure of the processor to determine a target data address from a plurality of initial data addresses included in the prefetch pattern according to the prefetch distance after receiving the prefetch pattern and the prefetch distance of the first level storage structure, wherein n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of initial data addresses for which the nth level storage structure does not perform data prefetching; The sending module 802 is used for the n-th level storage structure to send a pre-fetch request corresponding to each target data address to the (n+1)-th level storage structure.

[0082] It should be noted that the above explanation of the data pre-fetching method is also applicable to the data pre-fetching device of this embodiment and will not be repeated here.

[0083] In this embodiment, after receiving the prefetch mode and prefetch distance of the first-level storage structure, the n-th level storage structure of the processor determines the target data address from the multiple initial data addresses included in the prefetch mode according to the prefetch distance, wherein n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of initial data addresses for which the n-th level storage structure does not perform data prefetching; the n-th level storage structure sends a prefetch request corresponding to each target data address to the n+1-th level storage structure. Thus, the timeliness of prefetching can be effectively improved, and the pollution of prefetching to the cache can be reduced, thereby improving the overall performance of the processor.

[0084] Fig. 9 A block diagram of an exemplary computer device suitable for implementing embodiments of the present disclosure is shown. Fig. 9 The computer device 12 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0085] like Fig. 9 As shown, the computer device 12 is in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that connects various system components (including the system memory 28 and the processing unit 16).

[0086] The bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (hereinafter referred to as: ISA) bus, Micro Channel Architecture (hereinafter referred to as: MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (hereinafter referred to as: VESA) local bus and Peripheral Component Interconnection (hereinafter referred to as: PCI) bus.

[0087] The computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0088] The memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media ( Fig. 9 Not shown, usually called a "hard drive").

[0089] although Fig. 9Not shown in the figure, a disk drive for reading and writing a removable non-volatile disk (such as a "floppy disk"), and an optical disk drive for reading and writing a removable non-volatile optical disk (such as a compact disc read only memory (hereinafter referred to as: CD-ROM), a digital versatile disc read only memory (hereinafter referred to as: DVD-ROM) or other optical media) can be provided. In these cases, each drive can be connected to the bus 18 through one or more data medium interfaces. The memory 28 may include at least one program product, which has a set (for example, at least one) of program modules, which are configured to perform the functions of the various embodiments of the present disclosure.

[0090] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination thereof may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described in the present disclosure.

[0091] The computer device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), one or more devices that enable a human body to interact with the computer device 12, and / or any device that enables the computer device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed through an input / output (I / O) interface 22. In addition, the computer device 12 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 20. As shown, the network adapter 20 communicates with other modules of the computer device 12 through a bus 18. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the computer device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0092] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the data pre-fetching method mentioned in the above embodiment.

[0093] In order to implement the above embodiments, the present disclosure further proposes a non-temporary computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the data prefetching method proposed in the above embodiments of the present disclosure is implemented.

[0094] In order to implement the above embodiments, the present disclosure further proposes a computer program product. When an instruction processor in the computer program product is executed, the data prefetching method proposed in the above embodiments of the present disclosure is executed.

[0095] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0096] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0097] It should be noted that, in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "plurality" is two or more.

[0098] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0099] It should be understood that the various parts of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof may be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0100] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0101] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0102] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0103] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0104] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A data pre-fetching method, characterized in that: Applied to a processor, the method comprises: After receiving the prefetch mode and prefetch distance of the first-level storage structure, the n-th level storage structure of the processor determines the target data address from the multiple initial data addresses included in the prefetch mode according to the prefetch distance, wherein n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of the initial data addresses for which the n-th level storage structure does not perform data prefetching; The n-th level storage structure sends a pre-fetch request corresponding to each of the target data addresses to the n+1-th level storage structure.

2. The method according to claim 1, characterized in that The sending a pre-fetch request corresponding to each of the target data addresses to the n+1th level storage structure includes: Determine a first matching result between the prefetch request and a historical prefetch record table, wherein the historical prefetch record table is used to record the prefetch request that the n-th level storage structure has sent to the n+1-th level storage structure; When the first matching result indicates that the n-th level storage structure has not sent the pre-fetch request to the n+1-th level storage structure, the n-th level storage structure sends the pre-fetch request to the n+1-th level storage structure.

3. The method according to claim 1, characterized in that The method further comprises: After receiving a first access request corresponding to an upper level storage structure, the nth level storage structure determines a second matching result between the first access request and a historical prefetch record table, wherein the historical prefetch record table is used to record the prefetch request sent by the nth level storage structure to the n+1th level storage structure, and the upper level storage structure corresponding to the first level storage structure is a processor core of the processor; The n-level storage structure updates the prefetch distance when a preset condition is met, wherein the preset condition includes: the second matching result indicates that the n-level storage structure has sent the prefetch request with the same target data address as the first access request to the n+1-level storage structure, and there is no data corresponding to the first access request in the n-level storage structure.

4. The method according to claim 3, characterized in that The determining the target data address from a plurality of initial data addresses included in the prefetch mode according to the prefetch distance comprises: The target data address is determined from the multiple initial data addresses included in the prefetch pattern according to the updated prefetch distance.

5. The method according to claim 3, characterized in that The updating of the pre-fetch distance comprises: Determining a prefetch performance indicator of the nth level storage structure; The prefetch distance is updated according to the prefetch performance indicator.

6. The method according to claim 5, characterized in that The pre-fetch performance indicator includes at least one of the following: A prefetch hit rate of the n-th level storage structure; The number of times the n-th level storage structure continuously satisfies the preset condition.

7. The method according to claim 6, characterized in that The method further comprises: The first level storage structure of the processor receives a second access request from the processor core, and generates the pre-fetch pattern according to the second access request; The first level storage structure determines the pre-fetch distance corresponding to the n-th level storage structure, and sends the pre-fetch mode and the pre-fetch distance to the n-th level storage structure.

8. The method according to claim 7, characterized in that Generating the prefetch mode according to the second access request includes: determining a target event identifier corresponding to the second access request; Determining a historical event identifier that matches the target event identifier from a pattern history table, wherein the pattern history table includes a plurality of the historical event identifiers and a historical pattern corresponding to each of the historical event identifiers; The historical pattern corresponding to the matched historical event identifier is used as the pre-fetch pattern.

9. The method according to claim 7, characterized in that The determining the pre-fetch distance corresponding to the n-th level storage structure comprises: Determine the number of storage structure layers between the first-level storage structure and the n-th-level storage structure; Determining an initial distance corresponding to the n-th level storage structure according to the number of layers of the storage structure; The pre-fetch distance corresponding to the n-th level storage structure is determined according to the initial distance.

10. The method according to claim 9, characterized in that The determining, according to the number of layers of the storage structure, an initial distance corresponding to the n-th level storage structure comprises: A product value of a preset distance value and the number of layers of the storage structure is determined as the initial distance.

11. The method according to claim 9, characterized in that The step of determining the pre-fetch distance corresponding to the n-th level storage structure according to the initial distance includes: Determining the prefetching performance index of the n-th level storage structure during multiple data prefetching processes; The initial distance is adjusted according to the plurality of pre-fetch performance indicators to obtain the pre-fetch distance corresponding to the n-th level storage structure.

12. A data pre-fetching device, characterized in that: Applied to a processor, the device comprises: a determination module, for the nth level storage structure of the processor, after receiving the prefetch mode and prefetch distance of the first level storage structure, determining the target data address from a plurality of initial data addresses included in the prefetch mode according to the prefetch distance, wherein n is an integer greater than or equal to 1, and the prefetch distance is used to indicate the number of the initial data addresses for which the nth level storage structure does not perform data prefetching; A sending module is used for the n-th level storage structure to send a pre-fetch request corresponding to each of the target data addresses to the (n+1)-th level storage structure.

13. A computer device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 11.

14. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: in, The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 11.

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