Digital-analog hybrid circuit with frequency controlled by voltage and control method of digital-analog hybrid circuit

Abstract

The invention discloses a digital-analog hybrid circuit with frequency controlled by voltage, which realizes switching of different modulation modes by adjusting threshold voltage Vlow, and realizes cluster switch operation by outputting a BM control signal burst through a threshold voltage modulation circuit in a BM modulation mode. The digital-analog hybrid circuit provided by the invention has the advantages that the oscillator frequency and the load can realize higher linearity, the frequency nonlinearity is reduced, the switching loss of a BM modulation mode is favorably reduced, the efficiency is improved and the like.

Description

Technical Field

[0001] The invention relates to the technical field of charging, and in particular to a digital-analog hybrid circuit for controlling frequency by voltage. Background Art

[0002] The existing multi-mode flyback converter frequency modulation technology controls the frequency output by changing the charging current of the oscillator capacitor. The oscillator capacitor charging time is The charging current I2 is adjustable, and the oscillator capacitor discharge time is Under heavy load conditions, by controlling the charging current I2 to the maximum value, the oscillator outputs the maximum fixed frequency, realizing the pulse width modulation mode (Pulse Width Modulation, PWM); under medium and light load conditions, by controlling the charging current I2 to decrease as the load decreases, the oscillator frequency decreases accordingly, realizing the pulse frequency modulation mode (Pulse Frequency Modulation, PFM); under extremely light load conditions, by controlling the charging current I2 to the minimum value, the oscillator outputs the minimum fixed frequency, realizing the burst modulation mode (Burst Mode, BM). However, in the existing multi-mode flyback converter modulation technology, the oscillator capacitor charge and discharge cycle is It can be seen that in PFM modulation mode, if only the charging current I2 is changed, the period T of the oscillator will not change linearly with the load, and the frequency of the oscillator will not change linearly with the load. That is, when the charging current I2 changes, frequency nonlinearity will occur, and the frequency error will be large when the charging current is used to control the frequency. Moreover, in extremely light load or standby state, if the BM modulation mode uses fixed frequency switching, the converter efficiency will be reduced, and the standby power consumption and switching loss will be high. Summary of the invention

[0003] In view of the above-mentioned deficiencies of the prior art, the technical problem to be solved by the present invention is: how to provide a digital-analog hybrid circuit that can achieve higher linearity between the oscillator frequency and the load, reduce frequency nonlinearity, and help reduce the switching loss of the BM modulation mode and improve efficiency.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0005] A voltage-controlled frequency digital-analog hybrid circuit, comprising a charging current source I1, a discharging current source I2, an NMOS tube N1, a PMOS tube P1, a capacitor C, a comparator comp4, a comparator comp5, an RS trigger, a NOT gate N1 and an AND gate AND; the input end of the charging current source I1 is connected to a power supply voltage V DD1, the source and drain of the PMOS tube P1 are respectively connected to the output end of the charging current source I1 and the input end of the discharging current source I2, the output end of the discharging current source I2 is connected to the source of the NMOS tube N1, one end of the capacitor C is connected to the drain of the PMOS tube P1, and the other end of the capacitor C and the drain of the NMOS tube N1 are both grounded; the non-inverting input end of the comparator comp4 and the inverting input end of the comparator comp5 are both connected to the drain of the PMOS tube P1, the output end of the comparator comp4 and the output end of the comparator comp5 are respectively connected to the A end and the B end of the RS trigger, and the output end of the RS trigger is connected to the input end of the NOT gate N1; the non-inverting input end of the comparator comp5 is connected to the reference voltage V high The inverting input terminal of the comparator comp4 is connected to a reference voltage V low A threshold voltage modulation circuit is provided, wherein the output terminal burst of the threshold voltage modulation circuit and the output terminal of the NOT gate N1 are respectively connected to the first input terminal and the second input terminal of the AND gate AND; the gate of the NMOS tube N1, the gate of the PMOS tube P1 and the output terminal of the AND gate AND are all connected to the frequency output terminal OSC.

[0006] Furthermore, the threshold voltage modulation circuit includes a voltage dividing resistor R1, a voltage dividing resistor R2, a comparator comp1, a comparator comp2, a comparator comp3, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, a NOT gate N2, an XNOR gate XNOR, a transmission gate TG1 and a transmission gate TG2; the input end of the voltage dividing resistor R1, the non-inverting input end of the comparator comp1 and the inverting input end of the comparator comp2 are all connected to the feedback voltage V FB The input end of the voltage divider resistor R2 is connected to the output end of the voltage divider resistor R1 and the non-inverting input end of the comparator comp3 respectively, and the output end of the voltage divider resistor R2 is grounded; the inverting input end of the comparator comp1 is connected to the reference voltage V REF2 , the output terminal V of the comparator comp1 comp1 The first input terminal of the XNOR gate and the gate of the NMOS tube M2 are connected respectively; the same-direction input terminal of the comparator comp2 is connected to the reference voltage V REF1 , the output terminal V of the comparator comp2 comp2 The second input terminal of the XNOR gate XNOR and the gate of the NMOS tube M3 are respectively connected, and the output terminal of the XNOR gate XNOR is connected to the gate of the NMOS tube M1; the drains of the NMOS tubes M1, M2 and M3 are respectively connected to the feedback voltage V FB , bias voltage V low(max) and bias voltage V low(min), the sources of the NMOS tubes M1, M2 and M3 are all connected to the inverting input terminal of the comparator comp4;

[0007] The output ends of the transmission gate TG1 and the transmission gate TG2 are both connected to the inverting input end of the comparator comp3, the output end of the comparator comp3 is connected to the BM control signal burst, the BM control signal burst is respectively connected to the input end of the NOT gate N2, the positive phase control end of the transmission gate TG1 and the inverting control end of the transmission gate TG2; the output end of the NOT gate N2 is respectively connected to the inverting control end of the transmission gate TG1 and the positive phase control end of the transmission gate TG2;

[0008] The positive input terminal of the comparator comp2, the negative input terminal of the comparison stage comp1, the input terminals of the transmission gate TG1 and the transmission gate TG2 are respectively connected to the reference voltage V REF1 、V REF2 、V REF3 and V REF4 .

[0009] As another optimization, the threshold voltage modulation circuit includes a voltage divider resistor R1, a voltage divider resistor R2, a comparator comp1, a comparator comp2, a comparator comp3, a NOT gate N2 to N5, an XNOR gate XNOR and a transmission gate TG1 to TG5; the input end of the voltage divider resistor R1, the non-inverting input end of the comparator comp1 and the inverting input end of the comparator comp2 are all connected to the feedback voltage V FB The input end of the voltage divider resistor R2 is connected to the output end of the voltage divider resistor R1 and the non-inverting input end of the comparator comp3 respectively, and the output end of the voltage divider resistor R2 is grounded; the inverting input end of the comparator comp1 is connected to the reference voltage V REF2 , the output terminal V of the comparator comp1 comp1 The first input terminal of the XNOR gate, the positive phase control terminal of the transmission gate TG3 and the input terminal of the NOT gate N3 are respectively connected, and the output terminal of the NOT gate N3 is connected to the positive phase control terminal of the transmission gate TG3; the non-inverting input terminal of the comparator comp2 is connected to the reference voltage VREF1, the output terminal Vcomp2 of the comparator comp2 is respectively connected to the second input terminal of the XNOR gate XNOR, the positive phase control terminal of the transmission gate TG5 and the input terminal of the NOT gate N5, and the output terminal of the NOT gate N4 is connected to the positive phase control terminal of the transmission gate TG4; the output terminal Q of the XNOR gate XNOR is connected to the positive phase control terminal of the transmission gate TG4 and the input terminal of the NOT gate N4, and the output terminal of the NOT gate N5 is connected to the positive phase control terminal of the transmission gate TG5; the input terminals of the transmission gates TG3 to TG5 are respectively connected to the bias voltage V low(max) , feedback voltage V FBand bias voltage V low(min) The output ends of the transmission gates TG3 to TG5 are all connected to the inverting input end of the comparator comp4;

[0010] The output ends of the transmission gate TG1 and the transmission gate TG2 are both connected to the inverting input end of the comparator comp3, the output end of the comparator comp3 is connected to the BM control signal burst, the BM control signal burst is respectively connected to the input end of the NOT gate N2, the positive phase control end of the transmission gate TG1 and the inverting control end of the transmission gate TG2; the output end of the NOT gate N2 is respectively connected to the inverting control end of the transmission gate TG1 and the positive phase control end of the transmission gate TG2;

[0011] The positive input terminal of the comparator comp2, the negative input terminal of the comparison stage comp1, the input terminals of the transmission gate TG1 and the transmission gate TG2 are respectively connected to the reference voltage V REF1 、V REF2 、V REF3 and V REF4 .

[0012] Furthermore, the reference voltage V REF1 、V REF2 、V REF3 and V REF4 Satisfies the following relationship: V REF3 <V REF4 <V REF1 <V REF2 .

[0013] Furthermore, the bias voltage V low(max) and bias voltage V low(min) Satisfies the following relationship: V low(max) >V low(min) .

[0014] A control method for a voltage-controlled frequency digital-analog hybrid circuit as described above, when the load is extremely light, the threshold voltage modulation circuit inputs a minimum reference voltage V low , switch the modulation mode to BM.

[0015] In the above structure, the voltage-controlled frequency digital-analog hybrid circuit of the present invention can modulate the threshold voltage V low By changing the charge and discharge time T of the capacitor C, the switching frequency f is changed. When the load is heavy, the threshold voltage V is controlled. low is the minimum value, so that the charging and discharging time of capacitor C is the shortest, the switching frequency is the largest, and PWM is realized; when the load is medium or light, the threshold voltage V is controlled low As the feedback voltage V FBAs the load decreases, the charge and discharge time of the capacitor C decreases linearly, and the switching frequency changes linearly with the change of the load to achieve PFM; when the load is extremely light, the control threshold voltage V low is the maximum value, so that the charging and discharging time of capacitor C is the longest, the switching frequency is the minimum, and the switching operation is performed according to the cluster to achieve BM.

[0016] Compared with the prior art, the present invention has the following advantages:

[0017] 1. The use of mixed digital-analog circuits can achieve low power consumption, especially in extremely light load mode.

[0018] 2. Better reflect the advantages of multi-mode flyback converter modulation technology. The frequency is controlled by threshold voltage, which makes the oscillator frequency and load feedback voltage achieve higher linearity, reduce frequency nonlinearity, and thus achieve multiple mode switching with higher efficiency. The figure is a schematic diagram of the threshold voltage modulation circuit and frequency waveform of this patent. It can be seen from the waveform diagram that under heavy load conditions, the threshold voltage V low Output maximum value, the oscillator outputs the maximum operating frequency; under medium and light load conditions, the threshold voltage V low With the load feedback voltage V FB The oscillator frequency increases linearly with the decrease of load. Under extremely light load conditions, the threshold voltage V low Output minimum value, the oscillator outputs minimum operating frequency, and performs cluster switching operation.

[0019] 3. Under long-term standby conditions, BM switching operations according to clusters can significantly reduce switching losses and improve converter efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the voltage-controlled frequency digital-analog hybrid circuit in Example 1.

[0021] Figure 2 Schematic diagram of the threshold voltage modulation circuit in Example 1.

[0022] Figure 3 Schematic diagram of threshold voltage modulation circuit and frequency waveform.

[0023] Figure 4 Schematic diagram of the voltage-controlled frequency digital-analog hybrid circuit in Example 2. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below in conjunction with embodiments.

[0025] Example 1: Figure 1 and Figure 2As shown, a voltage-controlled frequency digital-analog hybrid circuit includes a voltage-controlled frequency oscillating circuit and a threshold voltage modulation circuit. The voltage-controlled frequency oscillating circuit includes a power supply voltage V DD1 , charging current source I1, discharging current source I2, NMOS tube N1, PMOS tube P1, capacitor C, threshold voltage modulation circuit and output reference voltage V low , BM control signal burst, reference voltage V high , comparator comp4, comparator comp5, RS flip-flop, NOT gate N1 and AND gate AND.

[0026] Supply voltage V DD1 The input end of the charging current source I1 is connected, the source of the PMOS tube P1 is connected to the output end of I1, the gate of the PMOS tube P1 is connected to the frequency output end OSC, and the drain of the PMOS tube P1 is respectively connected to the input end of the discharge current source I2, one end of the capacitor C, the non-inverting input end of the comparator comp4, and the inverting input end of the comparator comp5; the source of the NMOS tube N1 is connected to the output end of I2, the gate of the NMOS tube N1 is connected to the frequency output end OSC, and the drain of the NMOS tube N1 and the other end of the capacitor C are grounded; the inverting input end of the comparator comp4 is connected to the output end V low , the non-inverting input terminal of comparator comp5 is connected to the reference voltage V high , the output end of the comparator comp4 is connected to the A end of the RS trigger, the output end of the comparator comp5 is connected to the B end of the RS trigger; the output end of the RS trigger is connected to the input end of the inverter N1, the output end of the inverter N1 is connected to the second input end of the AND gate AND, the output end of the threshold voltage modulation circuit burst is connected to the first input end of the AND gate AND, and the output end of the AND gate AND is connected to the frequency output OSC; wherein the charging current source I1 and the discharging current source I2 are both constants, and the voltage V low Modulated by a threshold voltage modulation circuit.

[0027] The threshold voltage modulation circuit includes a feedback voltage V FB , voltage divider resistors R1, R2, reference voltage V REF1 , reference voltage V REF2 , reference voltage V REF3 , reference voltage V REF4 , comparator comp1, comparator comp2, comparator comp3, XNOR gate, bias voltage V low(max) , bias voltage V low(min) , NOT gate N2, NOT gate N3, NOT gate N4, NOT gate N5, transmission gate TG1, transmission gate TG2, transmission gate TG3, transmission gate TG4, transmission gate TG5, output BM control signal burst and output voltage V low .

[0028] Feedback voltage V FB One end of the voltage divider resistor R1 is connected to the input end, and the output end of the voltage divider resistor R1 is connected to the non-inverting input end V FB_1 , the input end of the voltage divider resistor R2, and the output end of the voltage divider resistor R2 is grounded; the inverting input end of the comparator comp3 is respectively connected to the output end of the transmission gate TG1 and the output end of the transmission gate TG2, and the output end of the comparator comp3 is connected to the BM control signal burst; the BM control signal burst is respectively connected to the input end of the NOT gate N2, the positive phase control end of the transmission gate TG1, and the inverting control end of the transmission gate TG2; the output end of the NOT gate N2 is respectively connected to the inverting control end of the transmission gate TG1 and the positive phase control end of the transmission gate TG2; the feedback voltage V FB The other end is connected to the same-direction input of comparator comp1 and the inverting input of comparator comp2 respectively. The inverting input of comparator comp1 is connected to the reference voltage V REF2 , the non-inverting input terminal of comparator comp2 is connected to the reference voltage V REF1 , the output terminal V of comparator comp1 comp1 The first input terminal of the XNOR gate, the positive phase control terminal of the transmission gate TG3 and the input terminal of the NOT gate N3 are connected respectively, and the output terminal V comp2 The second input terminal of the XNOR gate, the positive phase control terminal of the transmission gate TG5 and the input terminal of the NOT gate N5 are respectively connected; the input terminal of the transmission gate TG3 is connected to the bias voltage V low(max) The inverting control terminal of the transmission gate TG3 is connected to the output terminal of the NOT gate N3, and the output terminal of the transmission gate TG3 is connected to the threshold voltage V low ; The input of transmission gate TG4 is connected to the feedback voltage V FB The positive control terminal of the transmission gate TG4 and the input terminal of the NOT gate N4 are connected to the output terminal Q of the XNOR gate XNOR, the negative control terminal of the transmission gate TG4 is connected to the output terminal of the NOT gate N4, and the output terminal of the transmission gate TG4 is connected to the threshold voltage V low ; The input of transmission gate TG5 is connected to bias voltage V low(min) The inverting control terminal of the transmission gate TG5 is connected to the output terminal of the NOT gate N5, and the output terminal of the transmission gate TG5 is connected to the threshold voltage V low ; where the bias voltage V is set low(max) Maximum frequency control can be achieved by setting the bias voltage V low(min) The minimum frequency control can be achieved; the feedback voltage V FB Reflects the size of the load. The larger the load, the higher the feedback voltage V FB Similarly, the smaller the load, the larger the feedback voltage V FB The smaller.

[0029] In the voltage-controlled frequency oscillator circuit of this embodiment, I1 and I2 are current sources, which are constants; V low 、V high is the reference voltage, where V low The voltage is controlled by the threshold voltage modulation circuit, V high is a constant, V low <V high In the threshold voltage modulation circuit, V FB is the load feedback voltage, which increases with the increase of load and decreases with the decrease of load; R1 and R2 are voltage divider resistors. V REF1 、V REF2 、V REF3 、V REF4 is the reference voltage, V REF3 <V REF4 <V REF1 <V REF2 ; V low(max) 、V low(min) is the bias voltage, V low(max) >V low(min) .

[0030] like Figure 1 As shown, V high >V low , then the charging time of capacitor C is The discharge time is The switching frequency is In this embodiment, the charging current source I1 and the discharging current source I2 are kept unchanged, and the load feedback voltage V FB Adaptive modulation threshold voltage V low , the switching of three modulation modes can be realized.

[0031] The specific implementation principle is: when the load is within the heavy load range, the threshold voltage modulation circuit controls V low Output maximum voltage, V low(max) , the charging time is Discharge time The charge and discharge time is the shortest, the frequency is the highest, and the modulation mode is PWM.

[0032] When the load is medium or light, the threshold voltage modulation circuit controls V low The output decreases as the load decreases, that is, as the feedback voltage V FB The charging time decreases linearly with the decrease of Discharge time The charge and discharge time varies with the load feedback voltage V FB decreases and becomes longer linearly, that is, the frequency increases with the feedback voltage V FB Decreases and increases linearly, and the modulation mode is PFM.

[0033] When the load is extremely light, the threshold voltage modulation circuit controls V low The output is the lowest voltage, that is, V low(min) , the charging time is Discharge time The charge and discharge time is the longest, the control frequency is the smallest, and the cluster switch operation can be realized by outputting the burst signal through the threshold voltage modulation circuit. The modulation mode is BM.

[0034] like Figure 2 As shown, the threshold voltage modulation circuit analysis: V REF3 <V REF1 <V REF2

[0035] When the load is within the heavy load range, the load feedback voltage V FB Reaching the reference voltage V REF2 , at this time V REF1 <V REF2 <V FB ; The output burst of comparator comp3 is high level, and the reference voltage of comparator comp3 is V REF3 ; Comparator comp1 output V comp1 is high, transmission gate TG3 is turned on; comparator comp2 output terminal V comp2 is low level, transmission gate TG5 is not conducting; comp1 =1, V comp2 =0, the XNOR gate output Q is 0, and the transmission gate TG4 is not conducting. At this time, the threshold voltage V low Equal to the bias voltage V low(max) , set the bias voltage V low(max) The maximum frequency can be adjusted to achieve PWM.

[0036] When the load is medium or light, V REF1 <V FB <V REF2 , the comparator comp3 output burst is high level, and the reference voltage of comparator comp3 is still V REF3 ; Comparator comp1 output V comp1 is low level, transmission gate TG3 is not conducting; comparator comp2 output terminal V comp2 is low level, transmission gate TG5 is not conducting; comp1 =0, V comp2 =0, the XNOR gate XNOR output Q is 1, and the transmission gate TG4 is turned on. At this time, the threshold voltage decreases linearly with the decrease of the load feedback voltage VFB, realizing PFM.

[0037] When the load is extremely light, the feedback voltage VFB Reaching the reference voltage V REF1 , V REF2 >V REF1 >V FB , comparator comp1 output V comp1 is low level, transmission gate TG3 is not conducting; comparator comp2 output terminal V comp2 is high, transmission gate TG5 is turned on; due to V comp1 =0, V comp2 =1, the output of XNOR gate is 0, and transmission gate TG4 is not conducting. At this time, the threshold voltage V low Equal to the bias voltage V low(min) , set the bias voltage V low(min) The minimum switching frequency can be adjusted. FB_1 <V REF3 , the comparator comp3 output burst is low level, and the reference voltage of comparator comp3 becomes V REF4 , since the frequency signal OSC is low, no switching operation is performed, so the load gradually increases. When the load feedback voltage V FB_1 >V REF4 , the output terminal burst of the comparator comp3 is high level, and the frequency signal OSC outputs the minimum frequency, and this cycle is repeated to realize the switching operation of BM according to the cluster.

[0038] It can be seen that this embodiment has the following advantages:

[0039] 1. The use of mixed digital-analog circuits can achieve low power consumption, especially in extremely light load mode.

[0040] 2. Better reflect the advantages of multi-mode flyback converter modulation technology. By controlling the frequency through the threshold voltage, the oscillator frequency and the load feedback voltage can achieve higher linearity, reduce frequency nonlinearity, and thus achieve more efficient switching of multiple modes, such as Figure 3 As shown in the waveform diagram, it can be seen that under heavy load conditions, the threshold voltage V low Output maximum value, the oscillator outputs the maximum operating frequency; under medium and light load conditions, the threshold voltage V low With the load feedback voltage V FB The oscillator frequency increases linearly with the decrease of load. Under extremely light load conditions, the threshold voltage V low Output minimum value, the oscillator outputs minimum operating frequency, and performs cluster switching operation. The frequency is controlled by threshold voltage to reduce frequency nonlinearity, thereby realizing the switching of multiple modes of the flyback converter, reducing switching losses and improving switching conversion efficiency.

[0041] 3. In the long-term standby state, the BM modulation mode performs switching operations according to clusters and automatically adjusts the cluster spacing according to the load size, which can reduce the switching loss of the converter and improve efficiency.

[0042] Embodiment 2: The main difference between this embodiment and embodiment 1 is that Figure 4 As shown, the threshold voltage modulation circuit includes a feedback voltage V FB , voltage divider resistors R1, R2, reference voltage V REF1 , reference voltage V REF2 , reference voltage V REF3 , reference voltage V REF4 , comparator comp1, comparator comp2, comparator comp3, bias voltage V low(max) , bias voltage V low(min) , NMOS tube M1, NMOS tube M2, NMOS tube M3, NOT gate N2, transmission gate TG1, transmission gate TG2, output BM control signal burst and output voltage V low .

[0043] Feedback voltage V FB One end of the voltage divider resistor R1 is connected to the input end, and the output end of the voltage divider resistor R1 is connected to the non-inverting input end V FB_1 , the input end of the voltage divider resistor R2, and the output end of the voltage divider resistor R2 is grounded; the inverting input end of the comparator comp3 is respectively connected to the output end of the transmission gate TG1 and the output end of the transmission gate TG2, and the output end of the comparator comp3 is connected to the BM control signal burst; the BM control signal burst is respectively connected to the input end of the NOT gate N2, the positive phase control end of the transmission gate TG1, and the inverting control end of the transmission gate TG2; the output end of the NOT gate N2 is respectively connected to the inverting control end of the transmission gate TG1 and the positive phase control end of the transmission gate TG2; the feedback voltage V FB The other end is connected to the same-direction input of comparator comp1 and the inverting input of comparator comp2 respectively. The inverting input of comparator comp1 is connected to the reference voltage V REF2 , the non-inverting input terminal of comparator comp2 is connected to the reference voltage V REF1 , the output terminal V of comparator comp1 comp1 The first input terminal of the XNOR gate, the gate of the NMOS tube M2, and the output terminal V comp2 The drain of NMOS tube M2 is connected to the bias voltage V low(max) , the source of NMOS tube M2 is connected to the threshold voltage V low ; The drain of NMOS tube M1 is connected to the feedback voltage V FBThe gate of NMOS tube M1 is connected to the output end of XNOR gate XNOR, and the source of NMOS tube M1 is connected to the threshold voltage V low ; The drain of NMOS tube M3 is connected to the bias voltage V low(min) , the source of NMOS tube M3 is connected to the threshold voltage V low ; where the bias voltage V is set low(max) Maximum frequency control can be achieved by setting the bias voltage V low(min) The minimum frequency control can be achieved; the feedback voltage V FB Reflects the size of the load. The larger the load, the higher the feedback voltage V FB Similarly, the smaller the load, the larger the feedback voltage V FB The smaller.

[0044] When the load is within the heavy load range, the load feedback voltage V FB Reaching the reference voltage V REF2 , at this time V REF1 <V REF2 <V FB ; The output burst of comparator comp3 is high level, and the reference voltage of comparator comp3 is V REF3 ; Comparator comp1 output V comp1 is high level, NMOS tube M2 is turned on; comparator comp2 output terminal V comp2 is low level, NMOS tube M3 is turned off; due to V comp1 =1, V comp2 =0, the output of XNOR gate is 0, and NMOS tube M1 is turned off. At this time, the threshold voltage V low Equal to the bias voltage V low(max) , set the bias voltage V low(max) The maximum frequency can be adjusted to achieve PWM.

[0045] When the load is medium or light, V REF1 <V FB <V REF2 , the comparator comp3 output burst is high level, and the reference voltage of comparator comp3 is still V REF3 ; Comparator comp1 output V comp1 is low level, NMOS tube M2 is turned off; comparator comp2 output terminal V comp2 is low level, NMOS tube M3 is turned off; due to V comp1 =0, V comp2 =0, the output of the XNOR gate is 1, and the NMOS tube M1 is turned on. At this time, the threshold voltage decreases linearly with the decrease of the load feedback voltage VFB, realizing PFM.

[0046] When the load is extremely light, the feedback voltage VFB Reaching the reference voltage V REF1 , V REF2 >V REF1 >V FB , comparator comp1 output V comp1 is low level, NMOS tube M2 is turned off; comparator comp2 output terminal V comp2 is high level, NMOS tube M3 is turned on; due to V comp1 =0, V comp2 =1, the output of XNOR gate is 0, and NMOS tube M1 is turned off. At this time, the threshold voltage V low Equal to the bias voltage V low(min) , set the bias voltage V low(min) The minimum switching frequency can be adjusted. FB_1 <V REF3 , the comparator comp3 output burst is low level, and the reference voltage of comparator comp3 becomes V REF4 , since the frequency signal OSC is low, no switching operation is performed, so the load gradually increases. When the load feedback voltage V FB_1 >V REF4 , the output terminal burst of the comparator comp3 is high level, and the frequency signal OSC outputs the minimum frequency, and this cycle is repeated to realize the switching operation of BM according to the cluster.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A voltage-controlled frequency digital-analog hybrid circuit, characterized in that: The device comprises a charging current source I1, a discharging current source I2, an NMOS tube N1, a PMOS tube P1, a capacitor C, a comparator comp4, a comparator comp5, an RS trigger, a NOT gate N1 and an AND gate AND; the input end of the charging current source I1 is connected to a power supply voltage V DD1 , the source and drain of the PMOS tube P1 are respectively connected to the output end of the charging current source I1 and the input end of the discharging current source I2, the output end of the discharging current source I2 is connected to the source of the NMOS tube N1, one end of the capacitor C is connected to the drain of the PMOS tube P1, and the other end of the capacitor C and the drain of the NMOS tube N1 are both grounded; the non-inverting input end of the comparator comp4 and the inverting input end of the comparator comp5 are both connected to the drain of the PMOS tube P1, the output end of the comparator comp4 and the output end of the comparator comp5 are respectively connected to the A end and the B end of the RS trigger, and the output end of the RS trigger is connected to the input end of the NOT gate N1; the non-inverting input end of the comparator comp5 is connected to the reference voltage V high The inverting input terminal of the comparator comp4 is connected to a reference voltage V low A threshold voltage modulation circuit is provided, wherein the output terminal burst of the threshold voltage modulation circuit and the output terminal of the NOT gate N1 are respectively connected to the first input terminal and the second input terminal of the AND gate AND; the gate of the NMOS tube N1, the gate of the PMOS tube P1 and the output terminal of the AND gate AND are all connected to the frequency output terminal OSC.

2. The voltage-controlled frequency digital-analog hybrid circuit according to claim 1, characterized in that: The threshold voltage modulation circuit includes a voltage dividing resistor R1, a voltage dividing resistor R2, a comparator comp1, a comparator comp2, a comparator comp3, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, a NOT gate N2, an XNOR gate XNOR, a transmission gate TG1 and a transmission gate TG2; the input end of the voltage dividing resistor R1, the in-phase input end of the comparator comp1 and the inverting input end of the comparator comp2 are all connected to the feedback voltage V FB The input end of the voltage divider resistor R2 is connected to the output end of the voltage divider resistor R1 and the non-inverting input end of the comparator comp3 respectively, and the output end of the voltage divider resistor R2 is grounded; the inverting input end of the comparator comp1 is connected to the reference voltage V REF2 , the output terminal V of the comparator comp1 comp1 The first input terminal of the XNOR gate and the gate of the NMOS tube M2 are connected respectively; the same-direction input terminal of the comparator comp2 is connected to the reference voltage V REF1 , the output terminal V of the comparator comp2 comp2 The second input terminal of the XNOR gate XNOR and the gate of the NMOS tube M3 are respectively connected, and the output terminal of the XNOR gate XNOR is connected to the gate of the NMOS tube M1; the drains of the NMOS tubes M1, M2 and M3 are respectively connected to the feedback voltage V FB , bias voltage V low(max) and bias voltage V low(min) , the sources of the NMOS tubes M1, M2 and M3 are all connected to the inverting input terminal of the comparator comp4; The output ends of the transmission gate TG1 and the transmission gate TG2 are both connected to the inverting input end of the comparator comp3, the output end of the comparator comp3 is connected to the BM control signal burst, the BM control signal burst is respectively connected to the input end of the NOT gate N2, the positive phase control end of the transmission gate TG1 and the inverting control end of the transmission gate TG2; the output end of the NOT gate N2 is respectively connected to the inverting control end of the transmission gate TG1 and the positive phase control end of the transmission gate TG2; The positive input terminal of the comparator comp2, the negative input terminal of the comparison stage comp1, the input terminals of the transmission gate TG1 and the transmission gate TG2 are respectively connected to the reference voltage V REF1 、V REF2 、V REF3 and V REF4 .

3. The voltage-controlled frequency digital-analog hybrid circuit according to claim 1, characterized in that: The threshold voltage modulation circuit includes a voltage dividing resistor R1, a voltage dividing resistor R2, a comparator comp1, a comparator comp2, a comparator comp3, NOT gates N2 to N5, an XNOR gate XNOR and transmission gates TG1 to TG5; the input end of the voltage dividing resistor R1, the in-phase input end of the comparator comp1 and the inverting input end of the comparator comp2 are all connected to the feedback voltage V FB The input end of the voltage divider resistor R2 is connected to the output end of the voltage divider resistor R1 and the non-inverting input end of the comparator comp3 respectively, and the output end of the voltage divider resistor R2 is grounded; the inverting input end of the comparator comp1 is connected to the reference voltage V REF2 , the output terminal V of the comparator comp1 comp1 The first input terminal of the XNOR gate, the positive phase control terminal of the transmission gate TG3 and the input terminal of the NOT gate N3 are respectively connected, and the output terminal of the NOT gate N3 is connected to the positive phase control terminal of the transmission gate TG3; the non-inverting input terminal of the comparator comp2 is connected to the reference voltage VREF1, the output terminal Vcomp2 of the comparator comp2 is respectively connected to the second input terminal of the XNOR gate XNOR, the positive phase control terminal of the transmission gate TG5 and the input terminal of the NOT gate N5, and the output terminal of the NOT gate N4 is connected to the positive phase control terminal of the transmission gate TG4; the output terminal Q of the XNOR gate XNOR is connected to the positive phase control terminal of the transmission gate TG4 and the input terminal of the NOT gate N4, and the output terminal of the NOT gate N5 is connected to the positive phase control terminal of the transmission gate TG5; the input terminals of the transmission gates TG3 to TG5 are respectively connected to the bias voltage V low(max) , feedback voltage V FB and bias voltage V low(min) The output ends of the transmission gates TG3 to TG5 are all connected to the inverting input end of the comparator comp4; The output ends of the transmission gate TG1 and the transmission gate TG2 are both connected to the inverting input end of the comparator comp3, the output end of the comparator comp3 is connected to the BM control signal burst, the BM control signal burst is respectively connected to the input end of the NOT gate N2, the positive phase control end of the transmission gate TG1 and the inverting control end of the transmission gate TG2; the output end of the NOT gate N2 is respectively connected to the inverting control end of the transmission gate TG1 and the positive phase control end of the transmission gate TG2; The positive input terminal of the comparator comp2, the negative input terminal of the comparison stage comp1, the input terminals of the transmission gate TG1 and the transmission gate TG2 are respectively connected to the reference voltage V REF1 、V REF2 、V REF3 and V REF4 .

4. The voltage-controlled frequency digital-analog hybrid circuit according to claim 2 or 3, characterized in that: The reference voltage V REF1 、V REF2 、V REF3 and V REF4 Satisfies the following relationship: V REF3 <V REF4 <V REF1 <V REF2 .

5. The voltage-controlled frequency digital-analog hybrid circuit according to claim 2 or 3, characterized in that: The bias voltage V low(max) and bias voltage V low(min) Satisfies the following relationship: V low(max) >V low(min) .

6. A control method for a voltage-controlled frequency digital-analog hybrid circuit according to any one of claims 1 to 5, characterized in that: When the load is extremely light, the threshold voltage modulation circuit inputs the minimum reference voltage V low , switch the modulation mode to BM.

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