High-voltage sampling circuit
By designing a high-voltage sampling circuit containing series resistors and switching elements, using capacitors to achieve fast charging and correct output offset, the existing high-voltage sampling circuit has solved the problem of difficulty in sampling and slow response speed in high-voltage environments, and efficient high-voltage sampling is achieved.
Patent Information
- Application Number
- CN202411689126.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-03-07
AI Technical Summary
It is difficult for existing high-voltage sampling circuits to achieve effective sampling in high-voltage environments, and the response speed is slow, which cannot meet high requirements.
A high-voltage sampling circuit is designed to connect the first resistor, the first switching element and the second resistor in series, and to achieve fast charging in the sampling stage using the first capacitor and the second capacitor, and correct the output voltage offset through the second resistor.
This circuit takes into account both sampling speed and accuracy when sampling high voltages, reduces power consumption, and improves the sampling upper limit and scope of application by optimizing the matching accuracy of resistors and capacitors.
Smart Images
Figure CN119582848A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of high-voltage sampling, and in particular to a high-voltage sampling circuit. Background Art
[0002] With the development of power electronics technology, high-voltage signal links are increasingly used in power systems, electric vehicles, industrial control and other fields. As a key component of high-voltage signal links, the performance of high-voltage sampling circuits directly affects the stability and reliability of the entire system.
[0003] Figure 1a FIG. 1 shows a schematic circuit diagram of a pre-charged capacitor sampling circuit. Figure 1a As shown, by controlling the switch elements S1 and S2, the input signal Vin can be pre-charged to the capacitor C1 and the capacitor C1 can be quickly discharged to the capacitor C2, which is beneficial to improve the response speed of the sampling circuit. However, since transistors are usually selected as the switch elements S1 / S2, it is impossible to provide a control voltage of a corresponding voltage to the transistor in a high-voltage environment to control the on and off of the transistor, so the pre-charge type capacitor sampling circuit is difficult to be used in a high-voltage sampling circuit.
[0004] Figure 1b The schematic circuit diagram of the resistor voltage divider sampling circuit is shown in FIG. Figure 1b As shown, through the series voltage divider resistor (in Figure 1b Taking R1 and R2 as an example, the high-voltage input signal Vin can be converted into a low-voltage output signal Vout. However, since the resistor itself has a certain amount of leakage current, it will cause the input impedance to decrease and the power consumption to increase. It is not suitable for high-voltage sampling and is not conducive to improving the input impedance of the sampling circuit. In addition, the response speed of the resistor voltage divider sampling circuit is relatively slow, and it cannot be used in scenarios with high requirements for circuit response speed.
[0005] Therefore, a new high voltage sampling circuit is still needed. Summary of the invention
[0006] In view of the above problems, the purpose of the present application is to provide a high-voltage sampling circuit that can take into account both sampling speed and sampling accuracy.
[0007] According to one aspect of the present application, a high-voltage sampling circuit is provided, wherein the high-voltage sampling circuit includes: a first resistor, a first switch element, and a second resistor connected in series between an input voltage and a first reference voltage, wherein an intermediate node between the first resistor and the first switch element is a first node, and an intermediate node between the first switch element and the second resistor is a second node; a first capacitor connected between the first node and the first reference voltage; and a second capacitor connected between the second node and the second reference voltage, for providing an output voltage of the high-voltage sampling circuit, wherein the first switch element is used to disconnect the first node and the second node in a pre-charging phase, and connect the first node and the second node in a sampling phase.
[0008] Optionally, a resistance value of the first resistor is at least half of a resistance value of the second resistor.
[0009] Optionally, a time constant of the first resistor and the first capacitor is equal to a time constant of the second resistor and the second capacitor.
[0010] Optionally, the second capacitor is reused as a sampling capacitor of an analog-to-digital converter, and the high-voltage sampling circuit further includes: a second switching element connected between the second node and the first reference voltage, and the second switching element is used to be turned on in the pre-charging stage to reset the output voltage.
[0011] Optionally, the analog-to-digital converter further includes: a first sampling switch connected between the second node and the second capacitor; and a second sampling switch connected between the second capacitor and the second reference voltage, the first sampling switch and the second sampling switch being configured to be turned on before the start of the sampling phase to reset the output voltage in the pre-charging phase and to provide a charging path for the second capacitor in the sampling phase; and the first sampling switch and the second sampling switch being configured to be turned off before the end of the sampling phase to isolate the output voltage.
[0012] Optionally, the analog-to-digital converter includes a successive approximation analog-to-digital converter or a delta-sigma analog-to-digital converter.
[0013] Optionally, the high-voltage sampling circuit further includes: a third capacitor connected between the input voltage and the second capacitor, the intermediate node between the third capacitor and the second capacitor being a third node; and a third switch element connected between the second node and the third node, the third switch element being turned on before the start of the sampling phase to reset the output voltage, and providing a charging path for the third node during the sampling phase, and the third switch element being used to be disconnected before the end of the sampling phase to isolate the output voltage.
[0014] Optionally, the high-voltage sampling circuit further includes: a fourth switch element connected between the second node and the first reference potential, the fourth switch element being configured to be turned on before the sampling phase starts to reset the output voltage.
[0015] Optionally, the high-voltage sampling circuit further includes: a buffer, an input end of the buffer is connected to the third node, and an output end of the buffer provides the output voltage.
[0016] Optionally, the first reference voltage is the same as / different from the second reference voltage.
[0017] According to the high-voltage sampling circuit provided by the present application, the high-voltage sampling circuit of the present application can be used to sample a high voltage higher than the power supply voltage by setting the first resistor, and fast charging can be achieved in the sampling stage by the first capacitor and the second capacitor, and the output voltage offset caused by the mismatch between the first capacitor and the second capacitor can be corrected by setting the second resistor. Therefore, the high-voltage sampling circuit provided by the present application can take into account both the sampling speed and the sampling accuracy when sampling high voltage. At the same time, in the pre-charging stage, since the first switching element is disconnected, the high-voltage sampling circuit has no leakage, which is conducive to reducing power consumption.
[0018] Furthermore, by controlling the resistance of the first resistor to be at least half of the resistance of the second resistor, high-ratio voltage division and high-impedance input can be achieved, thereby increasing the sampling upper limit of the high-voltage sampling circuit of the present application and facilitating the expansion of the scope of application of the high-voltage sampling circuit of the present application.
[0019] Furthermore, by improving the matching accuracy of the first capacitor and the second capacitor, the power consumption of the high-voltage sampling circuit of the present application is greatly reduced, which is beneficial to energy saving. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0021] Figure 1a A schematic circuit diagram of a pre-charge type capacitor sampling circuit is shown;
[0022] Figure 1b A schematic circuit diagram of a resistor voltage divider type sampling circuit is shown;
[0023] Figure 2 A schematic circuit diagram showing a high voltage sampling circuit according to a first embodiment of the present application is shown;
[0024] Figure 3 The working waveform diagram of the high voltage sampling circuit of the first embodiment of the present application is shown;
[0025] Figure 4 A schematic circuit diagram showing a high voltage sampling circuit according to a second embodiment of the present application is shown;
[0026] Figure 5 A timing diagram of a high voltage sampling circuit according to a second embodiment of the present application is shown;
[0027] Figure 6 A schematic circuit diagram showing a high voltage sampling circuit according to a third embodiment of the present application;
[0028] Figure 7 FIG. 1 shows a timing diagram of a high voltage sampling circuit according to a third embodiment of the present application. DETAILED DESCRIPTION
[0029] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.
[0030] At the same time, certain words are used in this specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.
[0031] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.
[0032] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.
[0033] It should be noted that the high-voltage sampling circuit provided in each embodiment of the present application is suitable for a high-voltage signal chain system, and the input voltage of the high-voltage sampling circuit is higher than the supply voltage of the high-voltage sampling circuit.
[0034] Figure 2 FIG. 1 is a schematic circuit diagram of a sampling circuit according to a first embodiment of the present application. Figure 2 , the high voltage sampling circuit 100 of the first embodiment of the present application includes:
[0035] A first resistor R1, a first switch element S1, and a second resistor R2 are connected in series between an input voltage HVin and a first reference voltage. An intermediate node between the first resistor R1 and the first switch element S1 is a first node N1, and an intermediate node between the first switch element S1 and the second resistor R2 is a second node N2. A first capacitor C1 is connected between the first node N1 and the first reference voltage, and a second capacitor C2 is connected between the second node N2 and the second reference voltage. The second capacitor C2 is used to provide an output voltage of the high voltage sampling circuit 100.
[0036] It should be noted that, in each embodiment of the present application, the first reference voltage is the same as or different from the second reference voltage. For ease of description, in the following, the first reference voltage and the second reference voltage are both described by taking the ground voltage as an example.
[0037] The working process of the high-voltage sampling circuit 100 provided in the present application includes a pre-charging stage and a sampling stage. The first switch element S1 is used to disconnect the first node N1 from the second node N2 (i.e., disconnect the first resistor R1 from the second resistor R2) during the pre-charging stage of the high-voltage sampling circuit 100, and connect the first node N1 to the second node N2 (i.e., connect the first resistor R1 to the second resistor R2) during the sampling stage of the high-voltage sampling circuit 100.
[0038] The first switch element S1, the first resistor R1 and the first capacitor C1 operate in the first voltage domain, and the second resistor R2 and the second capacitor C2 operate in the second voltage domain. Specifically, in the high voltage sampling circuit 100, the first voltage domain is a high voltage domain, and the second voltage domain is a low voltage domain.
[0039] In the embodiment of the present application, an NMOS transistor is used as the first switch element S1. Further, the high-voltage sampling circuit 100 can also receive a negative input voltage HVin, and the ability of the high-voltage sampling circuit 100 of the present application to receive a negative input voltage can be adjusted by selecting the first switch element S1 and adjusting the control voltage.
[0040] In some embodiments, the resistance of the first resistor R1 is at least half of the resistance of the second resistor R2. The high-voltage sampling circuit can have a higher impedance and a wider voltage division range, which increases the sampling upper limit of the high-voltage sampling circuit of the present application and expands the applicable scenarios of the high-voltage sampling circuit. In addition, the large-proportional voltage division of the second resistor R2 can realize direct sampling of the input voltage HVin, reducing the restriction on the input voltage, so that the high-voltage sampling circuit of the present application can be compatible with working scenarios where the input voltage is close to zero voltage or the input voltage is negative voltage in addition to sampling high voltage, expanding the use scenarios of the high-voltage sampling circuit of the present application. At the same time, there is no need to connect a buffer in the circuit for buffering and isolation, and the circuit design is simple, which is conducive to reducing circuit power consumption and saving circuit area.
[0041] Figure 3 The working waveform diagram of the high voltage sampling circuit of the first embodiment of the present application is shown below. Figure 2 and Figure 3 The high voltage sampling circuit 100 of the first embodiment of the present application is further described.
[0042] exist Figure 3 In the example, the first switch element S1 is an NMOS transistor, that is, the first switch element S1 is turned on when the control voltage is a high level H, and is turned off when the control voltage is a low level L. Accordingly, the working process of the high-voltage sampling circuit 100 is divided into a pre-charging stage (the first switch element S1 is turned off) and a sampling stage (the first switch element S1 is turned on) according to the on-off state of the first switch element S1. By controlling the intermittent sampling of the high-voltage sampling circuit by the on-off of the first switch element, power consumption can be reduced.
[0043] refer to Figure 3 In the pre-charging stage, since the first switch element S1 is disconnected, the input voltage HVin charges the first capacitor C1 through the first resistor R1, and the first capacitor C1 (i.e., the voltage of the first node N1) is charged to the input voltage HVin. Since the first switch element S1 is disconnected, the high-voltage sampling circuit has no leakage in the pre-charging stage, which is conducive to further reducing power consumption.
[0044] It should be understood that in Figure 2 In the embodiment shown, one end of the first capacitor C1 is connected to the input voltage HVin, and the other end is connected to the first reference voltage. Therefore, in the pre-charging stage, the first capacitor C1 is charged by HVin. However, in some other embodiments, in the pre-charging stage, the two ends of the first capacitor C1 can also be connected to the original signal and the inverted signal in a pair of differential signals, respectively, and this application does not make too many restrictions on this.
[0045] At time t1, the first switch element S1 is turned on, and the high voltage sampling circuit 100 operates in the sampling phase. Further, the sampling phase is divided into a fast charging sub-phase (from time t1 to time t2) and a slow charging sub-phase (from time t2 to time t3).
[0046] In the fast charging sub-stage, since the first switch element S1 is turned on, the first capacitor C1 charges the second capacitor C2, so that the second capacitor C2 is charged to the voltage at point A. At this time, the output voltage LVout (i.e., the voltage at the second node N2) is the voltage at point A. By redistributing the charge between the first capacitor C1 and the second capacitor C2, the second capacitor C2 can be charged without other circuit designs, which can simplify the circuit and facilitate the development of highly integrated circuits. At the same time, the second capacitor C2 can usually be charged to the voltage at point A in a few nanoseconds (ns), and the charging speed is faster, which is conducive to increasing the sampling frequency.
[0047] However, due to capacitor mismatch, there is a deviation ΔV between the voltage at point A and the ideal value Vid of the output voltage LVout (i.e., the voltage divided by the second resistor R2). Therefore, the high-voltage sampling circuit 100 enters the slow charging sub-stage at time t2. Through the voltage division relationship between the first resistor R1 and the second resistor R2, the voltage of the second node N2 is clamped to Vid at time t3, completing the slow charging sub-stage.
[0048] It should be understood that the deviation ΔV between the voltage at point A and the ideal value Vid of the input voltage can be positive or negative (i.e., the voltage at point A can be higher or lower than the ideal value Vid). Figure 3 The voltage at point A is lower than the ideal value as an example.
[0049] Specifically,
[0050] (1)
[0051] Wherein, Vid is the ideal value of the output voltage LVout, R1 is the resistance value of the first resistor, R2 is the resistance value of the second resistor, and HVin is the input voltage of the high-voltage sampling circuit.
[0052] When the second node voltage N2 is clamped to Vid, the first switch element S1 is turned off. The high-voltage sampling circuit 100 enters the next pre-charging stage, and the first capacitor C1 (i.e., the voltage of the first node N1) is recharged to the input voltage HVin. The second capacitor C2 (i.e., the output voltage LVout) is discharged through the second resistor R2. The high-voltage sampling circuit 100 waits for the next sampling stage.
[0053] Furthermore, ignoring the power consumption generated by driving the first switch element S1, the power consumption of the high-voltage sampling circuit 100 in the pre-charging stage is shown in the following formula (2):
[0054] (2)
[0055] Wherein, P1 is the power consumption in the pre-charging stage, HVin is the input voltage of the high-voltage sampling circuit, and C1 is the capacitance of the first capacitor.
[0056] The power consumption of the high voltage sampling circuit 100 during the sampling phase is shown in the following formula (3):
[0057] (3)
[0058] Wherein, P2 is the power consumption in the sampling stage, HVin is the input voltage of the high-voltage sampling circuit, R1 is the resistance value of the first resistor, R2 is the resistance value of the second resistor, and T is the conduction time of the first switch element.
[0059] The power consumption in the pre-charging stage is only related to the capacitance of the first capacitor C1, which is difficult to optimize. In addition to being related to the input voltage HVin, the first resistor R1, and the second resistor R2, the power consumption in the sampling stage is also related to the on-time of the first switch element S1. Therefore, the power consumption of the high-voltage sampling circuit 100 can be optimized by optimizing the on-time of the first switch element S1.
[0060] The difference ΔV between the voltage at point A and the ideal voltage Vid can be reduced by reducing the mismatch between the first capacitor C1 and the second capacitor C2, thereby reducing the duration of the slow charging sub-stage (i.e., from time t2 to time t3), thereby reducing the on-time of the first switching element S1.
[0061] Specifically, in some embodiments, the mismatch between the first capacitor C1 and the second capacitor C2 is reduced by making the time constant of the first resistor R1 and the first capacitor C1 equal to the time constant of the second resistor R2 and the second capacitor C2. That is, there is:
[0062] (4)
[0063] According to the high-voltage sampling circuit provided by the present application, the high-voltage sampling circuit of the present application can be used to sample a high voltage higher than the power supply voltage by setting the first resistor, and the first capacitor and the second capacitor can realize fast charging in the sampling stage, and the output voltage offset caused by the mismatch between the first capacitor and the second capacitor can be corrected by setting the second resistor. Therefore, the present application provides a high-voltage sampling circuit that can take into account both sampling speed and sampling accuracy when sampling high voltage. At the same time, the intermittent sampling of the high-voltage sampling circuit can be controlled by the on-off control of the first switching element, which can reduce power consumption. And in the pre-charging stage, since the first switching element is disconnected, the high-voltage sampling circuit has no leakage, which is conducive to further reducing power consumption.
[0064] It should be understood that by reducing the mismatch between the first capacitor C1 and the second capacitor C2, the impact of the nonlinear on-resistance of the first switch element S1 on the sampling phase can be reduced, further reducing the difference between the voltage at point A and the ideal voltage, thereby further reducing the power consumption of the circuit.
[0065] Furthermore, the second capacitor C2 in the high-voltage sampling circuit of the first embodiment of the present application can be equivalent to a load. For example, it can be reused as a sampling capacitor in an analog-to-digital converter (ADC). Specifically, Figure 4 A schematic circuit diagram of a high-voltage sampling circuit according to a second embodiment of the present application is shown, that is, a schematic circuit diagram in which the second capacitor C2 is reused as a sampling capacitor in an ADC.
[0066] refer to Figure 4 , the high voltage sampling circuit 200 of the second embodiment of the present application includes:
[0067] A first resistor R1, a first switch element S1, and a second resistor R2 are connected in series between an input voltage HVin and a first reference voltage. An intermediate node between the first resistor R1 and the first switch element S1 is a first node N1, and an intermediate node between the first switch element S1 and the second resistor R2 is a second node N2. A first capacitor C1 is connected between the first node N1 and the first reference voltage. A second capacitor C2 is connected between the second node N2 and the second reference voltage. The second capacitor C2 is used to provide an output voltage of the high voltage sampling circuit 100.
[0068] The working process of the high-voltage sampling circuit 100 provided in the present application includes a pre-charging stage and a sampling stage. The first switch element S1 is used to disconnect the first node N1 from the second node N2 (i.e., disconnect the first resistor R1 from the second resistor R2) during the pre-charging stage of the high-voltage sampling circuit 100, and connect the first node N1 to the second node N2 (i.e., connect the first resistor R1 to the second resistor R2) during the sampling stage of the high-voltage sampling circuit 100.
[0069] The difference from the high-voltage sampling circuit 100 of the first embodiment of the present application is that the second capacitor C2 in the high-voltage sampling circuit 200 of the second embodiment of the present application is also reused as a sampling capacitor in the analog-to-digital converter (ADC) 10. At this time, the second capacitor C2 is connected between the second node N2 and the first reference voltage of the ADC 10. For example, it is a successive approximation register ADC (SAR-ADC) or a delta-sigma analog-to-digital converter (Σ-Δ ADC).
[0070] refer to Figure 4 The high voltage sampling circuit 200 of the second embodiment of the present application further includes a second switch element S2. The second switch element S2 is connected between the second node N2 and the first reference voltage, and is used to reset the voltage of the second node N2 (ie, the output voltage) before the sampling phase begins.
[0071] Furthermore, the ADC10 further includes a first sampling switch S10a and a second sampling switch S10b. The first sampling switch S10a is connected between the second capacitor C2 and the second node N2, and the second sampling switch S10b is connected between the second capacitor C2 and the second reference voltage. The first sampling switch S10a and the second sampling switch S10b are used to be turned on before the sampling phase starts, so as to provide a discharge path for the second capacitor C2 in the pre-charging phase and a charging path for the second capacitor C2 in the sampling phase. The first sampling switch S10a and the second sampling switch S10b are also used to be disconnected before the end of the sampling phase to isolate the second capacitor C2 and prevent the sampling voltage from leaking.
[0072] The first switch element S1, the first resistor R1 and the first capacitor C1 operate in the first voltage domain, and the second resistor R2, the second switch element S2 and the ADC10 operate in the second voltage domain. Specifically, in the high voltage sampling circuit 200, the first voltage domain is the high voltage domain, and the second voltage domain is the low voltage domain.
[0073] In the embodiment of the present application, an NMOS transistor is used as the first switch element S1. Further, the high-voltage sampling circuit 100 can also receive a negative input voltage HVin, and the ability of the high-voltage sampling circuit 100 of the present application to receive a negative input voltage can be adjusted by selecting the first switch element S1 and adjusting the control voltage.
[0074] In some embodiments, the resistance of the first resistor R1 is at least half of the resistance of the second resistor R2. The high-voltage sampling circuit can have a higher impedance and a wider voltage division range, thereby increasing the sampling upper limit of the high-voltage sampling circuit of the present application and broadening the applicable scenarios of the high-voltage sampling circuit. In addition, the large-proportional voltage division of the second resistor R2 can realize direct sampling of the input voltage HVin, and there is no need to connect a buffer in the circuit for buffering and isolation. The circuit design is simple, which is conducive to reducing circuit power consumption and saving circuit area.
[0075] Figure 5 FIG. 2 shows a timing diagram of a high voltage sampling circuit according to a second embodiment of the present application. Figure 5 In the example, a high level indicates that the switch element is turned on, and a low level indicates that the switch element is turned off. Figure 5The working process of the high-voltage sampling circuit 200 shown is divided into a pre-charging stage and a sampling stage. By controlling the on-off of the first switch element to intermittently sample the high-voltage sampling circuit, power consumption can be reduced. Figure 5 The high voltage sampling circuit 200 according to the second embodiment of the present application is further described.
[0076] refer to Figure 5 At time t1, the first switch element is disconnected, and the high-voltage sampling circuit 200 works in the pre-charging stage. The input voltage HVin charges the first capacitor C1 through the resistor R1. At this time, the second switch element S2, the first sampling switch S10a, and the second sampling switch S10b are turned on to reset the second node N2 and the second capacitor C2. Since the first switch element S1 is disconnected, the high-voltage sampling circuit has no leakage in the pre-charging stage, which is conducive to further reducing power consumption.
[0077] At time t2, the first switch element is turned on, and the high-voltage sampling circuit 200 enters the sampling phase. The turned-on first sampling switch S10a and the second sampling switch S10b provide a charging path for the second capacitor C2. Specifically, the first capacitor C1 first quickly charges the second capacitor C2, and then the voltage of the second capacitor C2 is clamped and corrected according to the voltage division of the second resistor R2.
[0078] After the second capacitor C2 is fully charged, the first sampling switch S10a and the second sampling switch S10b are disconnected, thereby isolating the second capacitor C2 and preventing leakage of the sampling voltage. In a preferred embodiment, the disconnection time t3 of the second sampling switch S10b is slightly earlier than the disconnection time t4 of the first sampling switch S10a, which can further improve the sampling accuracy.
[0079] At time t5, the first switch element S1 is turned off, and the high-voltage sampling circuit 200 enters the next pre-charging stage, and the first node N1 is gradually charged to the input voltage HVin. At time t6, the second switch element S2 is turned on, the second node N2 is reset, and the next sampling stage is awaited. At this time, the first sampling switch S10a and the second sampling switch S10b are controlled to be turned on and off according to the data processing status of ADC10, and this application does not impose too many restrictions.
[0080] Furthermore, since the first embodiment and the second embodiment of the present application have similar circuit structures, they also have the beneficial effects of any of the above items, which will not be described in detail here. And referring to the relevant calculation of power consumption in the first embodiment of the present application, for the second embodiment of the present application, the mismatch between the first capacitor C1 and the second capacitor C2 can be reduced by making the time constant of the first resistor R1 and the first capacitor C1 equal to the time constant of the second resistor R2 and the second capacitor C2, so as to achieve power consumption control.
[0081] In addition, the present application also provides a high-voltage sampling circuit of a third embodiment to further reduce power consumption.
[0082] Figure 6 FIG. 2 is a schematic circuit diagram of a high voltage sampling circuit according to a third embodiment of the present application. Figure 6 , the high voltage sampling circuit 300 of the third embodiment of the present application includes:
[0083] A first resistor R1, a first switch element S1, and a second resistor R2 are connected in series between an input voltage HVin and a first reference voltage. An intermediate node between the first resistor R1 and the first switch element S1 is a first node N1, and an intermediate node between the first switch element S1 and the second resistor R2 is a second node N2. A first capacitor C1 is connected between the first node N1 and the first reference voltage. A second capacitor C2 is connected between the first node N1 and the second reference voltage. The second capacitor C2 is used to provide an output voltage of the high voltage sampling circuit 100.
[0084] The working process of the high-voltage sampling circuit 300 provided in the present application includes a pre-charging stage and a sampling stage. The first switch element S1 is used to disconnect the first node N1 from the second node N2 (i.e., disconnect the first resistor R1 from the second resistor R2) during the pre-charging stage of the high-voltage sampling circuit 300, and connect the first node N1 to the second node N2 (i.e., connect the first resistor R1 to the second resistor R2) during the sampling stage of the high-voltage sampling circuit 300.
[0085] The difference from the high-voltage sampling circuit 100 of the first embodiment of the present application is that the high-voltage sampling circuit 300 of the third embodiment of the present application further includes a third capacitor C3 and a third switch element S3. The third capacitor C3 is connected between the input voltage HVin and the second capacitor C2, and the middle node between the third capacitor C3 and the second capacitor C2 is the third node N3. The third switch element S3 is connected between the second node N2 and the third node N3. The third switch element S3 is used to turn on before the sampling phase starts to reset the output voltage (i.e., reset the voltage of the third node N3), and provide a charging path for the third node N3 during the sampling phase. The third switch element S3 is also used to turn off before the end of the sampling phase to isolate the output voltage.
[0086] The high voltage sampling circuit 300 further includes a fourth switch element S4. The fourth switch element S4 is connected between the second node N2 and the first reference voltage, and is used to be turned on before the sampling phase starts to reset the output voltage. The fourth switch element S4 is also turned off at the beginning of the sampling phase to prevent the output voltage from discharging during the sampling phase.
[0087] In addition, in order to achieve continuous output of the output voltage, the high voltage sampling circuit 300 further includes a buffer BUF. The input end of the buffer BUF is connected to the third node N3, and the output end provides the output voltage LVout.
[0088] Figure 7 FIG. 2 shows a timing diagram of a high voltage sampling circuit according to a third embodiment of the present application. Figure 7 In the example, a high level indicates that the switch element is turned on, and a low level indicates that the switch element is turned off. Figure 7 The working process of the high-voltage sampling circuit 300 shown is divided into a pre-charging stage and a sampling stage. By controlling the on-off of the first switch element to intermittently sample the high-voltage sampling circuit, power consumption can be reduced. Figure 7 The high voltage sampling circuit 200 according to the second embodiment of the present application is further described.
[0089] refer to Figure 7 At time t1, the first switch element S1 is turned off, and the high-voltage sampling circuit 300 works in the pre-charging stage. The input voltage HVin charges the first capacitor C1 through the resistor R1. Since the first switch element S1 is turned off, the high-voltage sampling circuit has no leakage in the pre-charging stage, which is conducive to further reducing power consumption. At the same time, the third switch element S3 and the fourth switch element S4 are turned on to quickly discharge the third node N3.
[0090] At time t2, the first switch element S1 is turned on, and the high-voltage sampling circuit 300 works in the sampling phase. At the same time, the fourth switch element S4 is turned off to prevent the third node N3 from being discharged in the sampling phase. At this time, the first capacitor C1 is quickly charged to the third node N3 (i.e., to the second capacitor C2 and the third capacitor C3) through the first switch element S1 and the third switch element S3.
[0091] Thereafter, the voltage of the third node is clamped and corrected according to the voltage division of the second resistor R2, and an ideal output voltage is obtained at time t3. At this time, the third switch element S3 is disconnected. The third node N3 is in a high-resistance state. Since the charging of the third node N3 is completed at time t3 (i.e., the voltage refresh of the third node N3 is completed), it is beneficial to improve the refresh bandwidth of the high-voltage sampling circuit 300. At the same time, since the third node N3 is isolated, the input voltage HVin does not generate a charging current, so the circuit power consumption is 0, which achieves a significant reduction in the circuit power consumption.
[0092] At time t4, S1 is disconnected, and the high-voltage sampling circuit 300 resumes operation in the pre-charging phase. Then, at time t5, the fourth switch element S4 is closed, waiting for the next sampling phase.
[0093] Since after time t3, the third node N3 is isolated and the output voltage LVout is continuously output through the buffer BUF without being limited by the RC time constant, and even after the pre-charging stage is restored at time t4, the high-voltage sampling circuit 300 can maintain continuous output until the third switch element S3 is turned on before the next sampling stage to reset the third node N3.
[0094] According to the high-voltage sampling circuit provided by the present application, the high-voltage sampling circuit of the present application can be used to sample a high voltage higher than the power supply voltage by setting the first resistor, and the first capacitor and the second capacitor can realize fast charging in the sampling stage, and the output voltage offset caused by the mismatch between the first capacitor and the second capacitor can be corrected by setting the second resistor. Therefore, the present application provides a high-voltage sampling circuit that can take into account both sampling speed and sampling accuracy when sampling high voltage. At the same time, the intermittent sampling of the high-voltage sampling circuit can be controlled by the on-off control of the first switching element, which can reduce power consumption. And in the pre-charging stage, since the first switching element is disconnected, the high-voltage sampling circuit has no leakage, which is conducive to further reducing power consumption.
[0095] Furthermore, by controlling the resistance of the first resistor to be at least half of the resistance of the second resistor, high-ratio voltage division and high-impedance input can be achieved, thereby increasing the sampling upper limit of the high-voltage sampling circuit of the present application and facilitating the expansion of the scope of application of the high-voltage sampling circuit of the present application.
[0096] Furthermore, by improving the matching accuracy of the first capacitor and the second capacitor, the power consumption of the high-voltage sampling circuit of the present application is greatly reduced, which is beneficial to energy saving.
[0097] According to the embodiments of the present application as above, these embodiments do not describe all the details in detail, nor do they limit the present application to specific embodiments. Obviously, according to the above description, many modifications and changes can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that technicians in the relevant technical field can use the present application and the modifications based on the present application. The scope of protection of the present application shall be based on the scope defined by the claims of the present application.
Claims
1. A high voltage sampling circuit, wherein: The high voltage sampling circuit comprises: A first resistor, a first switch element, and a second resistor connected in series between an input voltage and a first reference voltage, wherein an intermediate node between the first resistor and the first switch element is a first node, and an intermediate node between the first switch element and the second resistor is a second node; A first capacitor connected between the first node and the first reference voltage; and a second capacitor connected between the second node and a second reference voltage, and configured to provide an output voltage of the high voltage sampling circuit; The first switch element is used to disconnect the first node and the second node in a pre-charging phase, and to connect the first node and the second node in a sampling phase.
2. The high voltage sampling circuit according to claim 1, wherein: The resistance of the first resistor is at least half of the resistance of the second resistor.
3. The high voltage sampling circuit according to claim 2, wherein: A time constant of the first resistor and the first capacitor is equal to a time constant of the second resistor and the second capacitor.
4. The high voltage sampling circuit according to claim 3, wherein: The second capacitor is reused as a sampling capacitor of the analog-to-digital converter. The high-voltage sampling circuit further includes: a second switch element connected between the second node and the first reference voltage, the second switch element being configured to be turned on during the pre-charging phase to reset the output voltage.
5. The high voltage sampling circuit according to claim 4, wherein: The analog-to-digital converter further comprises: A first sampling switch connected between the second node and the second capacitor; and a second sampling switch connected between the second capacitor and the second reference voltage, The first sampling switch and the second sampling switch are used to be turned on before the sampling phase starts, so as to reset the output voltage in the pre-charging phase and provide a charging path for the second capacitor in the sampling phase; and The first sampling switch and the second sampling switch are further configured to be disconnected before the sampling phase ends to isolate the output voltage.
6. The high voltage sampling circuit according to claim 4, wherein: The analog-to-digital converter includes a successive approximation analog-to-digital converter or a delta-sigma analog-to-digital converter.
7. The high voltage sampling circuit according to claim 3, wherein: The high voltage sampling circuit also includes: A third capacitor is connected between the input voltage and the second capacitor, and an intermediate node between the third capacitor and the second capacitor is a third node; and A third switch element is connected between the second node and the third node. The third switch element is turned on before the sampling phase starts to reset the output voltage and provides a charging path for the third node during the sampling phase. The third switch element is also used to be turned off before the sampling phase ends to isolate the output voltage.
8. The high voltage sampling circuit according to claim 7, wherein: The high voltage sampling circuit also includes: A fourth switch element is connected between the second node and the first reference potential, and is used to be turned on before the sampling phase starts to reset the output voltage.
9. The high voltage sampling circuit according to claim 8, wherein: The high voltage sampling circuit also includes: A buffer, wherein an input terminal of the buffer is connected to the third node, and an output terminal of the buffer provides the output voltage.
10. The high voltage sampling circuit according to claim 1, wherein: The first reference voltage is the same as / different from the second reference voltage.