Frame rate control jitter method and device for optimizing chip area

Abstract

The invention provides a frame rate control jitter method and device for optimizing a chip area. The method comprises the following steps: determining a color depth difference value between a color depth to be displayed and a color depth of a display screen; wherein the to-be-displayed color depth is higher than the color depth; according to the color depth difference value, determining the size and the type of the color-imitated pattern, and screening out a key type from the types; according to the color depth difference value, the color-imitating pattern corresponding to each key type is divided, and a plurality of basic patterns are obtained; determining a reference pattern according to the basic pattern, and transforming and splicing the reference pattern to obtain a color-imitated pattern; wherein the number of the reference patterns is the same as that of the key types. According to the scheme, the visual effect of the picture is ensured, and meanwhile, the chip area occupied by storing the color-imitating pattern is reduced.

Description

Technical Field

[0001] The present invention relates to the field of image processing technology, and in particular to a frame rate control jitter method and device for optimizing chip area. Background Art

[0002] Each digital image is composed of many pixels. The light source behind each sub-pixel can show different brightness levels, which are called grayscale. The more grayscales there are between the darkest and the brightest, the more delicate the image effect can be.

[0003] The pixel width of the source driver chip of the existing display system is usually 6 bits or 8 bits. In order to reduce costs, the frame rate control dithering (FRC-Dither) method is usually used to display more grayscales with fewer grayscales, for example, using a 6-bit screen to display 8-bit image data. However, when using the FRC-Dither method, it is necessary to store the dithering patterns used in the processing process, and storing all the dithering patterns will use more storage units, which will also occupy more chip area; at the same time, as the chip functions increase and the size decreases, how to reduce the chip area occupied by storing the dithering patterns becomes particularly important. Therefore, it is urgent to provide a frame rate control dithering method and device that optimizes the chip area. Summary of the invention

[0004] The present invention provides a frame rate control jitter method and device for optimizing chip area, which reduces the chip area occupied by storing dithering patterns while ensuring the visual effect of the picture by storing part of the dithering patterns.

[0005] In a first aspect, the present invention provides a frame rate control jitter method for optimizing chip area, the method comprising:

[0006] Determining a color depth difference between a color depth to be displayed and a color depth of a display screen; wherein the color depth to be displayed is higher than the color depth;

[0007] Determining the size and type of the dither pattern according to the color depth difference, and selecting key types from the types;

[0008] Dividing the dither pattern corresponding to each of the key categories according to the color depth difference to obtain a plurality of basic patterns;

[0009] A reference pattern is determined according to the basic pattern, so as to obtain a dithered pattern by transforming and splicing the reference pattern; wherein the number of the reference patterns is the same as the number of the key types.

[0010] Optionally, determining the size and type of the dither pattern according to the color depth difference includes:

[0011] The size of the dither pattern is determined according to the color depth difference; wherein the size is n 2 *n 2 ; n is the color depth difference;

[0012] The type and number of the dither pattern are determined according to the size; wherein the ratio of the number of carry pixels to the number of non-carry pixels in different types is different, and the number of types is n. 2 -1.

[0013] Optionally, a two-dimensional binary matrix is ​​used to represent the dithering pattern; wherein the size of the two-dimensional binary matrix is ​​the same as the size; when the matrix element value of the two-dimensional binary matrix is ​​1, it represents a carry pixel, and when the matrix element value is 0, it represents a non-carry pixel;

[0014] The key categories are screened out from the categories, including:

[0015] Using binary code to represent the number of carry pixels in the two-dimensional binary matrix;

[0016] The actual values ​​corresponding to the binary codes whose least significant bits are even are sorted from small to large or from large to small, and the types of dither patterns represented by the two-dimensional binary matrices corresponding to the first n binary codes are used as the key types; n is the color depth difference;

[0017] The two-dimensional binary matrix of the dither pattern corresponding to the key category is inverted using a logical NOT operator to obtain a two-dimensional binary matrix of the dither pattern corresponding to the first category; the dither pattern corresponding to the binary code whose least significant bit is an even number is alternately displayed between frames to obtain a dither pattern corresponding to the binary code whose least significant bit is an odd number corresponding to the second category; wherein the categories consist of the key category, the first category, and the second category.

[0018] Optionally, the dither patterns corresponding to each of the key categories are divided according to the color depth difference to obtain a number of basic patterns, including:

[0019] According to the color depth difference, determine the size of the basic pattern; wherein the size of the basic pattern is n*n; n is the color depth difference;

[0020] According to the size of the basic pattern, the dither pattern corresponding to the key type is divided in order from left to right and from top to bottom to obtain n 2 The basic pattern.

[0021] Optionally, determining a reference pattern according to the basic pattern includes:

[0022] Any basic pattern in a symmetrical shape is used as the reference pattern.

[0023] Optionally, when the color depth difference is 4, the dither pattern is obtained by splicing 4 rows and 4 columns of the basic patterns; and obtaining the dither pattern by transforming and splicing the reference pattern includes:

[0024] Using the reference pattern as the initial pattern of the first row and the first column, transforming the initial pattern according to a preset transformation rule to obtain patterns of each row and column;

[0025] The initial pattern and the transformed pattern are spliced ​​according to row and column positions to obtain the dithered pattern.

[0026] Optionally, when the color depth difference is 4, the dither pattern is obtained by splicing 4 rows and 4 columns of the basic patterns; and obtaining the dither pattern by transforming and splicing the reference pattern includes:

[0027] Using a logical NOT operator to perform an inversion operation on the reference pattern to obtain an initial pattern of the first row and the first column, and transforming the initial pattern according to a preset transformation rule to obtain patterns of each row and column;

[0028] The initial pattern and the transformed pattern are spliced ​​according to row and column positions to obtain the dithered pattern.

[0029] Optionally, the preset transformation rule is:

[0030] Transforming the initial pattern according to a preset row transformation rule to obtain a pattern of the first row and second column, a pattern of the first row and third column, and a pattern of the first row and fourth column respectively;

[0031] Performing a third matrix transformation on the initial pattern to obtain a pattern in the second row and first column, and transforming the pattern in the second row and first column according to the preset row transformation rule to obtain a pattern in the second row and second column, a pattern in the second row and third column, and a pattern in the second row and fourth column, respectively;

[0032] Performing a second matrix transformation or a fourth matrix transformation on the pattern in the second row and first column to obtain a pattern in the third row and first column, and transforming the pattern in the third row and first column according to the preset row transformation rule to obtain a pattern in the third row and second column, a pattern in the third row and third column, and a pattern in the third row and fourth column, respectively;

[0033] Performing a third matrix transformation on the pattern in the third row and first column to obtain a pattern in the fourth row and first column, and transforming the pattern in the fourth row and first column according to the preset row transformation rule to obtain a pattern in the fourth row and second column, a pattern in the fourth row and third column, and a pattern in the fourth row and fourth column, respectively;

[0034] splicing the initial pattern and the transformed pattern according to row and column positions to obtain the dithered pattern;

[0035] Among them, the preset row transformation rule is to perform the first matrix transformation, the second matrix transformation, and the first matrix transformation in sequence; the first matrix transformation is to exchange the two adjacent rows in the matrix; the second matrix transformation is to exchange the upper two rows and the lower two rows of the matrix; the third matrix transformation is to exchange the two adjacent columns in the matrix; the fourth matrix transformation is to exchange the left two columns and the right two columns of the matrix.

[0036] In a second aspect, the present invention further provides a frame rate control jitter device for optimizing chip area, comprising:

[0037] A color depth difference determination module, used to determine the color depth difference between the color depth to be displayed and the color depth of the display screen; wherein the color depth to be displayed is higher than the color depth;

[0038] a dither pattern determination module, configured to determine the size and type of the dither pattern according to the color depth difference, and select key types from the types;

[0039] A processing module is used to divide the dither pattern corresponding to each of the key categories according to the color depth difference to obtain a plurality of basic patterns; and determine a reference pattern according to the basic pattern to obtain the dither pattern by transforming and splicing the reference pattern; wherein the number of the reference patterns is the same as the number of the key categories.

[0040] In a third aspect, the present invention further provides a computing device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it implements any of the above-mentioned frame rate control jitter methods for optimizing chip area.

[0041] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute any of the above-mentioned frame rate control jitter methods for optimizing chip area.

[0042] In a fifth aspect, an embodiment of the present invention further provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the steps of the method described in any first aspect of this specification.

[0043] The present invention provides a frame rate control dithering method and device for optimizing chip area. After determining the color depth difference between the color depth to be displayed and the color depth of the display screen, the method determines the size and type of the dither pattern based on the color depth difference, and then reduces the dither pattern to be stored by screening key types; divides the dither pattern corresponding to the key type to obtain a number of basic patterns, and then further screens the reference pattern to be stored from the basic pattern, and finally obtains the dither pattern by transforming and splicing the reference pattern. In this way, the final reference pattern to be stored is obtained through two screenings, and it is not necessary to store all the dither patterns used in the frame rate control dithering algorithm, and multiple different dither patterns can be generated through the stored reference patterns, which not only ensures the visual effect of the picture, but also reduces the area required for the chip to store the dither pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 It is a 4*4 dithering pattern provided by the present invention;

[0046] Figure 2 is a flow chart of a frame rate control jitter method for optimizing chip area provided by an embodiment of the present invention;

[0047] Figure 3 is a schematic diagram of a basic pattern obtained by dividing a dither pattern provided by an embodiment of the present invention;

[0048] Figure 4 is a schematic diagram of a transformation using a first matrix transformation provided by an embodiment of the present invention;

[0049] Figure 5 is a schematic diagram of a transformation using a second matrix transformation provided by an embodiment of the present invention;

[0050] Figure 6 is a schematic diagram of a transformation using a third matrix transformation provided by an embodiment of the present invention;

[0051] Figure 7 is a schematic diagram of a transformation using a fourth matrix transformation provided by an embodiment of the present invention;

[0052] Figure 8 A transformation flow chart of a dithered pattern obtained by transforming and splicing a reference pattern provided by an embodiment of the present invention;

[0053] Fig. 9 A dither pattern in which the ratio of the number of carry pixels to the number of non-carry pixels is 4 / 16 is provided by an embodiment of the present invention;

[0054] Fig.10 is a hardware architecture diagram of a computing device provided by an embodiment of the present invention;

[0055] Fig.11 1 is a structural diagram of a frame rate control jitter device for optimizing chip area provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0057] For the traditional FRC-Dither principle. For example, for 8-bit input data, a 6-bit screen is usually used for display, so the color depth to be displayed is 8-bit, and the color depth of the display screen is 6-bit. Although the 6-bit screen can only display 64 grayscales, for the 256 grayscales of 8-bit to be displayed; among them, the 0th, 4th, 8th, 4m and other grayscales are displayed directly, while the grayscales 4m+1, 4m+2, 4m+3 are realized by the spatial-temporal averaging of FRC-Dither.

[0058] Dither refers to the intra-frame averaging in the spatial domain. For example, to display the 129th order (32.25th order of 6bit), it is necessary to display a 132th order (33rd order of 6bit) and three 128th orders (32nd order of 6bit) in each 2*2 unit in the entire image, and achieve an average grayscale of 129th order through spatial averaging, that is, (132+128*3) / 4=129. Similarly, other grayscale levels can be achieved. The above-mentioned 2*2 unit can also select other sizes, such as 4*4, 8*8, etc., as long as the ratio of 132th order (4n+4) and 128th order (4n) is 1:3, 2:2, 3:1, the corresponding 4n+1, 4n+2, 4n+3 can be achieved. For each pixel in each unit, whether it is displayed as 4n or 4n+4 is achieved by searching the dither pattern (Dither Pattern) according to the row and column positions; Figure 1 Shown is a 4*4 dither pattern showing 4n+1 steps.

[0059] FRC refers to the inter-frame average in the time domain. Taking the display of 129 levels as an example, in the adjacent 4 frames, for each pixel, the ratio of 128 levels to 132 levels is still maintained at 3:1, so that the average grayscale of the pixel is 129 levels. This requires that the dithering pattern of each frame is different.

[0060] Please refer to Figure 2 , an embodiment of the present invention provides a frame rate control jitter method for optimizing chip area, comprising:

[0061] Step 200, determining a color depth difference between a color depth to be displayed and a color depth of a display screen; wherein the color depth to be displayed is higher than the color depth;

[0062] Step 202, determining the size and type of the dither pattern according to the color depth difference, and selecting key types from the types;

[0063] Step 204, dividing the dither pattern corresponding to each key category according to the color depth difference to obtain a plurality of basic patterns;

[0064] Step 206, determining reference patterns according to the basic patterns, so as to obtain dithered patterns by transforming and splicing the reference patterns; wherein the number of reference patterns is the same as the number of key types.

[0065] In the present invention, after determining the color depth difference between the color depth to be displayed and the color depth of the display screen, the size and type of the dither pattern are determined based on the color depth difference, and then the dither patterns to be stored are reduced by screening key types; a number of basic patterns are obtained by dividing the dither patterns corresponding to the key types, and then the reference patterns to be stored are further screened from the basic patterns, and finally the dither pattern is obtained by transforming and splicing the reference patterns. In this way, the final reference pattern to be stored is obtained through two screenings, and it is not necessary to store all the dither patterns used in the frame rate control dithering algorithm, and multiple different dither patterns can be generated through the stored reference patterns, so that more grayscales can be displayed with fewer grayscales, thereby further reducing the area required for the chip to store the dither pattern while ensuring the visual effect of the picture.

[0066] Described below Figure 2 How the various steps are performed.

[0067] In step 200, the color depth is represented by the number of bits. The more bits there are, the more grayscales there are, the more colors there are available, and the more delicate the colors are. The number of grayscales is equal to 2 raised to the power of the number of color depth bits. In addition, the frame rate control dithering (FRC-Dither) method can display more grayscales with fewer grayscales, so it is necessary to satisfy that the color depth to be displayed is higher than the color depth.

[0068] In a preferred embodiment, the color depth difference is ≤4, and can be 4, 3, 2 or 1.

[0069] In step 202, the size and type of the dither pattern are determined according to the color depth difference, including:

[0070] The size of the dither pattern is determined according to the color depth difference; wherein the size is n 2 *n 2 ; n is the color depth difference;

[0071] The type and number of dither patterns are determined according to the size; the ratio of the number of carry pixels to the number of non-carry pixels in different types is different, and the number of types is n. 2 -1.

[0072] Specifically, taking a 6-bit screen displaying a 10-bit (color depth to be displayed) grayscale as an example, that is, the color depth difference is 4, and grayscales 16m+1, 16m+2, ... 16m+15 need to be realized by FRC-Dither on an average basis. According to the principle of the traditional FRC-Dither method, the size of the dither pattern (Dither_Pattern) is required to be at least 4*4 units, so that the ratio of the number of carry pixels to the number of non-carry pixels in the dither pattern can meet the ratio of 0:16, 1:15, 2:14, 3:13, 4:12, 5:11, 6:10, 7:9, 8:8, 9:7, 10:6, 11:5, 12:4, 13:3, 14:2, 15:1 and 16:0, and grayscales from 16m to 16m+16 can be displayed. In the present invention, by requiring that the above ratio can also be satisfied within the adjacent minimum 16*1 units in the row and column directions of the screen, the size of the dither pattern is limited to 16*16 (i.e., n 2 *n 2 ), can further improve spatial averaging and enhance visual display effects.

[0073] In the present invention, as described in the previous example, since the ratio of the number of carry pixels to the number of non-carry pixels in the dither pattern is 0:16 and 16:0, the gray scale of 16m and the gray scale of 16m+16 are displayed respectively, the color depth of the display screen can be directly displayed. Therefore, there are only 15 types of actual dither patterns, including the ratios of the number of carry pixels to the number of non-carry pixels of 1:15, 2:14, 3:13, 4:12, 5:11, 6:10, 7:9, 8:8, 9:7, 10:6, 11:5, 12:4, 13:3, 14:2, and 15:1 respectively.

[0074] In a preferred embodiment, a two-dimensional binary matrix is ​​used to represent the dither pattern; wherein the size of the two-dimensional binary matrix is ​​the same as the dimension; when the matrix element value of the two-dimensional binary matrix is ​​1, it represents a carry pixel, and when the matrix element value is 0, it represents a non-carry pixel;

[0075] Filter out key categories from the categories, including:

[0076] A binary code is used to represent the number of carry pixels in a two-dimensional binary matrix;

[0077] The actual values ​​corresponding to the binary codes whose least significant bits are even are sorted from small to large or from large to small, and the types of dithering patterns represented by the two-dimensional binary matrices corresponding to the first n binary codes are used as key types; n is the color depth difference;

[0078] The two-dimensional binary matrix of the dither pattern corresponding to the key category is inverted by using a logical NOT operator to obtain a two-dimensional binary matrix of the dither pattern corresponding to the first category; the dither pattern corresponding to the binary code whose least significant bit is an even number is alternately displayed between frames to obtain a dither pattern corresponding to the binary code whose least significant bit is an odd number corresponding to the second category; wherein the category consists of the key category, the first category and the second category.

[0079] It should be noted that the dither pattern used in the current frame can be represented as a two-dimensional binary matrix: Dither_Pattern[i,j], i∈(0,n 2 -1), j∈(0,n 2 -1); n is the color depth difference. Among them, i, j represent the row and column position coordinates of the matrix, that is, corresponding to the i-th row and j-th column. The actual FRC-Dither process is to find the corresponding matrix element value of the pixel in the matrix. When the corresponding matrix element value is 1, the pixel is a carry pixel, and the higher order of the two adjacent grayscales needs to be displayed, that is, the grayscale output at the pixel position is 16m+16; when the corresponding matrix element value is 0, the pixel is a non-carry pixel, and the lower order of the two adjacent grayscales needs to be displayed, that is, the grayscale output at the pixel position is 16m.

[0080] Specifically, taking a 6-bit screen displaying a 10-bit grayscale as an example, the number of categories is 15. As described in the previous example, the binary codes used to represent the number of carry pixels in the two-dimensional binary matrix of the 15 categories of dither patterns are 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111. In the first case, the actual values ​​corresponding to the binary codes whose least significant bits are even are sorted from small to large, and the resulting sequence is 0010, 0100, 0110, 1000, 1010, 1100, 1110. The top four binary codes are 0010, 0100, 0110, 1000, respectively. The key category is the type of dither pattern represented by the two-dimensional binary matrix corresponding to the four binary codes. At this time, the two-dimensional binary matrices with binary codes of 1110, 1100, and 1010 can be obtained by inverting the two-dimensional binary matrices with binary codes of 0010, 0100, and 0110. The two-dimensional binary matrices with the least significant bits of the binary codes 0001, 0011, 0101, 0111, 1001, 1011, 1101, and 1111, which are odd numbers, can be obtained by alternating the dithering patterns corresponding to the binary codes with the least significant bits adjacent to them being even numbers according to the principle similar to FRC; for example, the two-dimensional binary matrix of the binary code 0011 can be realized by alternating the two-dimensional binary matrices with the binary codes 0010 and 0100 between frames. The second case: the actual values ​​corresponding to the binary codes whose least significant bits are even are sorted from large to small, and the resulting sequence is 1110, 1100, 1010, 1000, 0110, 0100, 0010. The top four binary codes are 1110, 1100, 1010, 1000, respectively. The key type is the type of dither pattern represented by the two-dimensional binary matrix corresponding to these four binary codes. At this time, the two-dimensional binary matrices with binary codes of 0010, 0100, and 0110 can be obtained by performing the inversion operation on the two-dimensional binary matrices with binary codes of 1110, 1100, and 1010, respectively. For the two-dimensional binary matrix of the binary codes 0001, 0011, 0101, 0111, 1001, 1011, 1101, 1111 whose least significant bits are odd, the dithered patterns corresponding to the adjacent binary codes whose least significant bits are even can be obtained by alternating between frames based on the FRC principle.

[0081] Therefore, in the present invention, all dither patterns required in the dither algorithm can be obtained by processing n key types of dither patterns, and because only n types of dither patterns are stored, the chip area occupied by storing the dither patterns is further reduced, thereby achieving chip area optimization.

[0082] In step 204, the dither pattern corresponding to each key category is divided according to the color depth difference to obtain several basic patterns, including:

[0083] According to the color depth difference, the size of the basic pattern is determined; wherein the size of the basic pattern is n*n; n is the color depth difference;

[0084] According to the size of the basic pattern, the dither pattern corresponding to the key category is divided in order from left to right and from top to bottom to obtain n 2 A basic pattern.

[0085] Specifically, following the previous example, taking a 6-bit screen displaying a 10-bit grayscale as an example, the size of the dither pattern is 16*16, and the dither pattern is divided into the following Figure 3 The 16 4*4 basic patterns shown are called sub_pat00, sub_pat01, sub_pat02, sub_pat03, sub_pat10, sub_pat11, sub_pat12, sub_pat13, sub_pat20...sub_pat33 in sequence.

[0086] In step 206, when the color depth difference is 4, the dither pattern is obtained by splicing 4 rows and 4 columns of basic patterns; the dither pattern is obtained by transforming and splicing the reference pattern, including the following three methods:

[0087] The first method: taking the reference pattern as the initial pattern of the first row and the first column, transforming the initial pattern according to a preset transformation rule to obtain patterns of each row and column;

[0088] The initial pattern and the transformed pattern are spliced ​​according to the row and column positions to obtain the dithered pattern corresponding to the key category.

[0089] The second method: using a logical NOT operator to perform an inversion operation on the reference pattern to obtain an initial pattern of the first row and first column, and transforming the initial pattern according to a preset transformation rule to obtain patterns of each row and column;

[0090] The initial pattern and the transformed pattern are spliced ​​according to row and column positions to obtain a dithered pattern corresponding to the first category.

[0091] A third method is to alternate the dither pattern corresponding to the key category and / or the dither pattern corresponding to the first category between frames to obtain the dither pattern corresponding to the second category.

[0092] In a preferred embodiment, the preset transformation rule is:

[0093] The initial pattern is transformed according to a preset row transformation rule to obtain a pattern of the first row and second column, a pattern of the first row and third column, and a pattern of the first row and fourth column respectively;

[0094] Performing a third matrix transformation on the initial pattern to obtain a pattern in the second row and first column, and transforming the pattern in the second row and first column according to a preset row transformation rule to obtain a pattern in the second row and second column, a pattern in the second row and third column, and a pattern in the second row and fourth column, respectively;

[0095] Performing a second matrix transformation or a fourth matrix transformation on the pattern in the second row and first column to obtain a pattern in the third row and first column, and transforming the pattern in the third row and first column according to a preset row transformation rule to obtain a pattern in the third row and second column, a pattern in the third row and third column, and a pattern in the third row and fourth column, respectively;

[0096] Performing a third matrix transformation on the pattern in the third row and first column to obtain a pattern in the fourth row and first column, and transforming the pattern in the fourth row and first column according to a preset row transformation rule to obtain a pattern in the fourth row and second column, a pattern in the fourth row and third column, and a pattern in the fourth row and fourth column, respectively;

[0097] The initial pattern and the transformed pattern are spliced ​​according to row and column positions to obtain a dithered pattern;

[0098] Among them, the preset row transformation rule is to perform the first matrix transformation, the second matrix transformation, and the first matrix transformation in sequence; the first matrix transformation is to exchange the two adjacent rows in the matrix; the second matrix transformation is to exchange the upper two rows and the lower two rows of the matrix; the third matrix transformation is to exchange the two adjacent columns in the matrix; the fourth matrix transformation is to exchange the left two columns and the right two columns of the matrix.

[0099] Specifically, the first matrix transformation is as follows Figure 4 As shown, the 0th row is swapped with the 1st row, and the 2nd row is swapped with the 3rd row; the second matrix transformation is as follows Figure 5 As shown, the 0th and 1st rows are swapped with the 2nd and 3rd rows; the third matrix transformation is as follows Figure 6 As shown, swap the 0th column with the 1st column, and swap the 2nd column with the 3rd column; the fourth matrix transformation is as follows Figure 7 As shown, swap columns 0 and 1 with columns 2 and 3. Figure 3 As shown, the preset transformation rules are as follows Figure 8 As shown, the first matrix transformation is represented as mode1, the second matrix transformation is represented as mode2, the third matrix transformation is represented as mode3, and the fourth matrix transformation is represented as mode4. It should be noted that, Figures 4 to 7 In the figure, the left figures are schematic diagrams before transformation, and the right figures are schematic diagrams after transformation.

[0100] In a preferred embodiment, any basic pattern in a symmetrical shape is used as a reference pattern.

[0101] In the present invention, a symmetrical reference pattern is selected, and after transformation according to the above transformation method, the carry pixels in the reference pattern are traversed in the row direction and the column direction respectively. Therefore, for a dither pattern with a size of 16*16, the proportion of the carry pixels in the units of 16*16, 4*4, 16*1, and 1*16 are the same, which can further improve the visual effect and achieve a better dithering effect. Specifically, Fig. 9 As shown, the ratio of the number of carry pixels to the number of non-carry pixels in the dither pattern is 4 / 16, and the ratio of the 1 value in the four units of 16*16, 4*4, 16*1, and 1*16 all reaches 4 / 16, which can more evenly display the grayscale of 16m+4.

[0102] In order to achieve the average between frames, the conventional FRC stores multiple dither patterns and performs periodic transformation in units of frames. The present invention does not need to store multiple dither patterns, but can generate multiple dither patterns based on n stored reference patterns. Therefore, different dither patterns can be generated by only changing the reference pattern between frames, thereby reducing the chip area required for storing all dither patterns.

[0103] like Fig.10 , Fig.11 As shown, the embodiment of the present invention provides a frame rate control jitter device that optimizes the chip area. The device embodiment can be implemented by software, or by hardware or a combination of software and hardware. From the hardware level, Fig.10 As shown, it is a hardware architecture diagram of a computing device where a frame rate control jitter device for optimizing chip area provided by an embodiment of the present invention is located. Fig.10 In addition to the processor, memory, network interface, and non-volatile memory shown in the figure, the computing device in which the device is located in the embodiment may also generally include other hardware, such as a forwarding chip responsible for processing messages, etc. Taking software implementation as an example, Fig.11 As shown, as a device in a logical sense, the CPU of the computing device in which it is located reads the corresponding computer program in the non-volatile memory into the memory and runs it. This embodiment provides a frame rate control jitter device for optimizing chip area, including:

[0104] A color depth difference determination module 110, for determining a color depth difference between a color depth to be displayed and a color depth of a display screen; wherein the color depth to be displayed is higher than the color depth;

[0105] A dither pattern determination module 112, for determining the size and type of the dither pattern according to the color depth difference, and filtering out key types from the types;

[0106] The processing module 114 is used to divide the dither pattern corresponding to each key category according to the color depth difference to obtain a plurality of basic patterns; and determine the reference pattern according to the basic pattern to obtain the dither pattern by transforming and splicing the reference pattern; wherein the number of the reference patterns is the same as the number of the key categories.

[0107] In some specific implementations, the color depth difference determination module 110 may be used to perform the above step 200 , the dither pattern determination module 112 may be used to perform the above step 202 ; and the processing module 114 may be used to perform the above steps 204 and 206 .

[0108] In some specific implementations, the dither pattern determination module 112 is further configured to perform the following operations:

[0109] The size of the dither pattern is determined according to the color depth difference; wherein the size is n 2 *n 2 ; n is the color depth difference;

[0110] The type and number of dither patterns are determined according to the size; the ratio of the number of carry pixels to the number of non-carry pixels in different types is different, and the number of types is n. 2 -1.

[0111] In some specific implementations, the dither pattern determination module 112 is further configured to perform the following operations:

[0112] A two-dimensional binary matrix is ​​used to represent the dithering pattern; wherein the size of the two-dimensional binary matrix is ​​the same as the size; when the matrix element value of the two-dimensional binary matrix is ​​1, it represents a carry pixel, and when the matrix element value is 0, it represents a non-carry pixel;

[0113] Filter out key categories from the categories, including:

[0114] A binary code is used to represent the number of carry pixels in a two-dimensional binary matrix;

[0115] The actual values ​​corresponding to the binary codes whose least significant bits are even are sorted from small to large or from large to small, and the types of dithering patterns represented by the two-dimensional binary matrices corresponding to the first n binary codes are used as key types; n is the color depth difference;

[0116] The two-dimensional binary matrix of the dither pattern corresponding to the key category is inverted by using a logical NOT operator to obtain a two-dimensional binary matrix of the dither pattern corresponding to the first category; the dither pattern corresponding to the binary code whose least significant bit is an even number is alternately displayed between frames to obtain a dither pattern corresponding to the binary code whose least significant bit is an odd number corresponding to the second category; wherein the category consists of the key category, the first category and the second category.

[0117] In some specific implementations, the processing module 114 is further configured to perform the following operations:

[0118] According to the color depth difference, the size of the basic pattern is determined; wherein the size of the basic pattern is n*n; n is the color depth difference;

[0119] According to the size of the basic pattern, the dither pattern corresponding to the key category is divided in order from left to right and from top to bottom to obtain n 2 A basic pattern.

[0120] In some specific embodiments, any basic pattern in a symmetrical shape is used as a reference pattern.

[0121] In some specific implementations, the processing module 114 is further configured to perform the following operations:

[0122] When the color depth difference is 4, the dither pattern is obtained by splicing 4 rows and 4 columns of the basic pattern; the dither pattern is obtained by transforming and splicing the reference pattern, including:

[0123] Using the reference pattern as the initial pattern of the first row and the first column, transforming the initial pattern according to a preset transformation rule to obtain patterns of each row and column;

[0124] The initial pattern and the transformed pattern are spliced ​​according to row and column positions to obtain a dithered pattern;

[0125] and / or,

[0126] Using a logical NOT operator to perform an inversion operation on the reference pattern to obtain an initial pattern of the first row and the first column, and transforming the initial pattern according to a preset transformation rule to obtain patterns of each row and column;

[0127] The initial pattern and the transformed pattern are spliced ​​according to row and column positions to obtain a dithered pattern.

[0128] In some specific implementations, the preset transformation rule is:

[0129] The initial pattern is transformed according to a preset row transformation rule to obtain a pattern of the first row and second column, a pattern of the first row and third column, and a pattern of the first row and fourth column respectively;

[0130] Performing a third matrix transformation on the initial pattern to obtain a pattern in the second row and first column, and transforming the pattern in the second row and first column according to a preset row transformation rule to obtain a pattern in the second row and second column, a pattern in the second row and third column, and a pattern in the second row and fourth column, respectively;

[0131] Performing a second matrix transformation or a fourth matrix transformation on the pattern in the second row and first column to obtain a pattern in the third row and first column, and transforming the pattern in the third row and first column according to a preset row transformation rule to obtain a pattern in the third row and second column, a pattern in the third row and third column, and a pattern in the third row and fourth column, respectively;

[0132] Performing a third matrix transformation on the pattern in the third row and first column to obtain a pattern in the fourth row and first column, and transforming the pattern in the fourth row and first column according to a preset row transformation rule to obtain a pattern in the fourth row and second column, a pattern in the fourth row and third column, and a pattern in the fourth row and fourth column, respectively;

[0133] The initial pattern and the transformed pattern are spliced ​​according to row and column positions to obtain a dithered pattern;

[0134] Among them, the preset row transformation rule is to perform the first matrix transformation, the second matrix transformation, and the first matrix transformation in sequence; the first matrix transformation is to exchange the two adjacent rows in the matrix; the second matrix transformation is to exchange the upper two rows and the lower two rows of the matrix; the third matrix transformation is to exchange the two adjacent columns in the matrix; the fourth matrix transformation is to exchange the left two columns and the right two columns of the matrix.

[0135] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on a frame rate control jitter device for optimizing chip area. In other embodiments of the present invention, a frame rate control jitter device for optimizing chip area may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0136] The information interaction, execution process and other contents between the modules in the above-mentioned device are based on the same concept as the embodiment of the method of the present invention. For the specific contents, please refer to the description in the embodiment of the method of the present invention, and no further description is given here.

[0137] An embodiment of the present invention further provides a computing device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, a frame rate control jitter method for optimizing chip area in any embodiment of the present invention is implemented.

[0138] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the processor executes a frame rate control jitter method for optimizing chip area in any embodiment of the present invention.

[0139] An embodiment of the present application also provides a computer program product, which includes a computer program. A processor of a computer device reads the computer program from a computer-readable storage medium, and the processor executes the computer program, so that the computer device executes a frame rate control jitter method for optimizing chip area as described in any of the above embodiments.

[0140] Specifically, a system or device equipped with a storage medium can be provided, on which software program code that implements the functions of any of the above-mentioned embodiments is stored, and a computer (or CPU or MPU) of the system or device can be enabled to read and execute the program code stored in the storage medium.

[0141] In this case, the program code itself read from the storage medium can realize the function of any one of the above-mentioned embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.

[0142] The storage medium embodiments for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer by a communication network.

[0143] In addition, it should be clear that the functions of any of the above embodiments can be implemented not only by executing the program code read by the computer, but also by enabling an operating system operating on the computer to complete part or all of the actual operations based on instructions from the program code.

[0144] In addition, it can be understood that the program code read from the storage medium is written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion module connected to the computer, and then based on the instructions of the program code, a CPU installed on the expansion board or expansion module is enabled to perform part or all of the actual operations, thereby realizing the functions of any of the above-mentioned embodiments.

[0145] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical factors in the process, method, article or device including the elements.

[0146] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A frame rate control jitter method for optimizing chip area, characterized in that: include: Determining a color depth difference between a color depth to be displayed and a color depth of a display screen; wherein the color depth to be displayed is higher than the color depth; Determining the size and type of the dither pattern according to the color depth difference, and selecting key types from the types; Dividing the dither pattern corresponding to each of the key categories according to the color depth difference to obtain a plurality of basic patterns; A reference pattern is determined according to the basic pattern, so as to obtain a dithered pattern by transforming and splicing the reference pattern; wherein the number of the reference patterns is the same as the number of the key types.

2. The method according to claim 1, characterized in that The step of determining the size and type of the dither pattern according to the color depth difference includes: The size of the dither pattern is determined according to the color depth difference; wherein the size is n 2 *n 2 ; n is the color depth difference; The type and number of the dither pattern are determined according to the size; wherein the ratio of the number of carry pixels to the number of non-carry pixels in different types is different, and the number of types is n. 2 -1.

3. The method according to claim 1, characterized in that The dither pattern is represented by a two-dimensional binary matrix; wherein the size of the two-dimensional binary matrix is ​​the same as the size; when the matrix element value of the two-dimensional binary matrix is ​​1, it represents a carry pixel, and when the matrix element value is 0, it represents a non-carry pixel; The key categories are screened out from the categories, including: Using binary code to represent the number of carry pixels in the two-dimensional binary matrix; The actual values ​​corresponding to the binary codes whose least significant bits are even are sorted from small to large or from large to small, and the types of dither patterns represented by the two-dimensional binary matrices corresponding to the first n binary codes are used as the key types; n is the color depth difference; The two-dimensional binary matrix of the dither pattern corresponding to the key category is inverted using a logical NOT operator to obtain a two-dimensional binary matrix of the dither pattern corresponding to the first category; the dither pattern corresponding to the binary code whose least significant bit is an even number is alternately displayed between frames to obtain a dither pattern corresponding to the binary code whose least significant bit is an odd number corresponding to the second category; wherein the categories consist of the key category, the first category, and the second category.

4. The method according to claim 1, characterized in that: Divide the dither pattern corresponding to each key category according to the color depth difference to obtain several basic patterns, including: According to the color depth difference, determine the size of the basic pattern; wherein the size of the basic pattern is n*n; n is the color depth difference; According to the size of the basic pattern, the dither pattern corresponding to the key type is divided in order from left to right and from top to bottom to obtain n 2 The basic pattern.

5. The method according to claim 1, characterized in that The determining of the reference pattern according to the basic pattern comprises: Any basic pattern in a symmetrical shape is used as the reference pattern.

6. The method according to any one of claims 3 to 5, characterized in that: When the color depth difference is 4, the dither pattern is obtained by splicing 4 rows and 4 columns of the basic patterns; the dither pattern is obtained by transforming and splicing the reference pattern, including: Using the reference pattern as the initial pattern of the first row and the first column, transforming the initial pattern according to a preset transformation rule to obtain patterns of each row and column; splicing the initial pattern and the transformed pattern according to row and column positions to obtain the dithered pattern; and / or, Using a logical NOT operator to perform an inversion operation on the reference pattern to obtain an initial pattern of the first row and the first column, and transforming the initial pattern according to a preset transformation rule to obtain patterns of each row and column; The initial pattern and the transformed pattern are spliced ​​according to row and column positions to obtain the dithered pattern.

7. The method according to claim 6, characterized in that The preset transformation rule is: Transforming the initial pattern according to a preset row transformation rule to obtain a pattern of the first row and second column, a pattern of the first row and third column, and a pattern of the first row and fourth column respectively; Performing a third matrix transformation on the initial pattern to obtain a pattern in the second row and first column, and transforming the pattern in the second row and first column according to the preset row transformation rule to obtain a pattern in the second row and second column, a pattern in the second row and third column, and a pattern in the second row and fourth column, respectively; Performing a second matrix transformation or a fourth matrix transformation on the pattern in the second row and first column to obtain a pattern in the third row and first column, and transforming the pattern in the third row and first column according to the preset row transformation rule to obtain a pattern in the third row and second column, a pattern in the third row and third column, and a pattern in the third row and fourth column, respectively; Performing a third matrix transformation on the pattern in the third row and first column to obtain a pattern in the fourth row and first column, and transforming the pattern in the fourth row and first column according to the preset row transformation rule to obtain a pattern in the fourth row and second column, a pattern in the fourth row and third column, and a pattern in the fourth row and fourth column, respectively; splicing the initial pattern and the transformed pattern according to row and column positions to obtain the dithered pattern; Among them, the preset row transformation rule is to perform the first matrix transformation, the second matrix transformation, and the first matrix transformation in sequence; the first matrix transformation is to exchange the two adjacent rows in the matrix; the second matrix transformation is to exchange the upper two rows and the lower two rows of the matrix; the third matrix transformation is to exchange the two adjacent columns in the matrix; the fourth matrix transformation is to exchange the left two columns and the right two columns of the matrix.

8. A frame rate control jitter device for optimizing chip area, characterized in that: include: A color depth difference determination module, used to determine the color depth difference between the color depth to be displayed and the color depth of the display screen; wherein the color depth to be displayed is higher than the color depth; a dither pattern determination module, configured to determine the size and type of the dither pattern according to the color depth difference, and select key types from the types; A processing module is used to divide the dither pattern corresponding to each of the key categories according to the color depth difference to obtain a plurality of basic patterns; and determine a reference pattern according to the basic pattern to obtain the dither pattern by transforming and splicing the reference pattern; wherein the number of the reference patterns is the same as the number of the key categories.

9. A computing device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute the method according to any one of claims 1 to 7.

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