Hafnium-zirconium-oxygen-doped multi-bit ferroelectric storage unit and preparation method thereof

Abstract

The invention discloses a hafnium-zirconium-oxygen-doped multi-bit ferroelectric storage unit and a preparation method thereof. The storage unit comprises a first electrode, a second electrode and a multi-state ferroelectric layer arranged between the first electrode and the second electrode, the polymorphic ferroelectric layer comprises a hafnium-zirconium-oxygen solid solution and doping elements. And carrying out high-temperature annealing treatment on the device, and enabling the material of the multi-state ferroelectric layer to be subjected to phase transformation under the combined action of doped elements and electrode stress so as to form a mixed crystal of a ferroelectric phase, an anti-ferroelectric phase and a non-ferroelectric phase, thereby realizing multi-bit information storage. The polymorphic ferroelectric layer has stable polymorphisms for storing multi-bit data, and can be quickly switched among different storage states. The electrode layer is used for providing electric field driving force and regulating stress and oxygen vacancy space distribution of the electrode-ferroelectric interface layer at the same time; and the distribution between the material phase components and the oxygen vacancies in the ferroelectric layer is adjusted by controlling the distribution and the concentration of the elements by doping the elements and under the combined action of the electrodes.

Description

Technical Field

[0001] The present invention relates to the field of novel storage materials and microelectronic devices, and in particular to a hafnium-zirconium-oxygen-doped multi-bit ferroelectric storage unit and a preparation method thereof. Background Art

[0002] Ferroelectric random access memory (FeRAM) is a non-volatile storage material with the characteristics of high-speed read and write capabilities, low operating voltage, high integration and low power consumption. It is regarded as one of the effective solutions to replace DRAM in the future.

[0003] Compared with the current DRAM that uses the charge storage principle, non-ferroelectric memory has a broader application prospect because it does not need to use voltage to maintain the storage state and does not need to refresh the storage content periodically. However, due to the limitations of current material technology, the mainstream non-volatile memory on the market generally has disadvantages such as slow reading and writing speeds and high writing power consumption, making it difficult to replace or even surpass the current DRAM.

[0004] By using ferroelectric thin films to replace traditional DRAM dielectric materials, multiple stable states (such as "00", "01", "10", "11") can be achieved by using different polarization directions of ferroelectric materials. Increasing the number of stable storage states from two to multiple allows FeRAM to have both the fast response speed of DRAM and the high storage density of NAND. Since the ferroelectric polarization strength can change with voltage, incompletely polarized multi-state storage can be achieved using a voltage lower than the complete polarization flip.

[0005] At the same time, it needs to meet the requirements of DRAM's low-voltage reading and writing and the durability equivalent to DRAM. However, due to the defects and instability in the hafnium-based ferroelectric film, the polarization amount of the ferroelectric film with continuous polarization at a fixed voltage will decay as the number of flips increases due to the instability and randomness of the defects, making it difficult to form a high-durability multi-stable polarization.

[0006] Therefore, it is an urgent goal to introduce a method to control the phase composition (ferroelectric phase O-phase, antiferroelectric phase T-phase) of hafnium zirconium oxide thin films so that ferroelectric capacitors can form multiple steady-state polarization current peaks to achieve multi-stable storage. Summary of the invention

[0007] In view of the above defects and shortcomings of the prior art, the present invention aims to provide a novel ultra-low power consumption multi-state lossless reading ferroelectric memcapacitor and a preparation method thereof to solve the above technical problems.

[0008] To achieve the above objectives, the present invention provides a hafnium-zirconium-oxygen-doped multi-bit ferroelectric memory cell, comprising:

[0009] A first electrode and a second electrode, with a multi-state ferroelectric layer disposed therebetween;

[0010] The multi-state ferroelectric layer includes a hafnium-zirconium-oxygen solid solution and a doping element.

[0011] A further improvement of the present invention is that the doping element in the polymorphic ferroelectric layer is group II element calcium (Ca), strontium (Sr) or barium (Ba); or group III element scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga) and indium (In); or doped lanthanide elements lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu). In the doped hafnium zirconium oxygen solid solution, the ratio of hafnium oxide to zirconium oxide is 0.1 to 10; the concentration of the doping element is 0.1% to 20%.

[0012] A further improvement of the present invention is that the thickness of the first electrode and the second electrode is 2-50 nm.

[0013] A further improvement of the present invention is that the material of the first electrode and the second electrode is any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, chromium, or any one of the alloys, nitride oxides, and metal oxide semiconductors of the above materials.

[0014] A further improvement of the present invention is that the thickness of the multi-state ferroelectric layer is 1.5-30 nm.

[0015] The present invention also provides a method for preparing a hafnium zirconium oxygen doped multi-bit ferroelectric memory cell, which is used to prepare the hafnium zirconium oxygen doped multi-bit ferroelectric memory cell mentioned above, and comprises the following steps:

[0016] S1: growing an insulating material on the surface of the semiconductor as an insulating dielectric layer. In this step, the insulating material can be grown by sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy.

[0017] S2: preparing a first electrode on the surface of the insulating dielectric layer; in this step, a conductive medium is deposited as the first electrode by spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation.

[0018] S3: preparing a polymorphic ferroelectric layer on the surface of the first electrode; in this step, the polymorphic ferroelectric layer is prepared by sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy.

[0019] S4: preparing a second electrode on the polymorphic ferroelectric layer; in this method, the conductive medium can be deposited as the second electrode by spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation.

[0020] S5: performing high temperature annealing treatment on the device, so that the material of the polymorphic ferroelectric layer undergoes a phase transformation under the combined action of the doping elements and the electrode stress to form a mixed crystal of a ferroelectric phase, an antiferroelectric phase, and a non-ferroelectric phase.

[0021] A further improvement of the present invention is that in step S5, the temperature of the high temperature annealing treatment is 350-650°C.

[0022] The combined effects of doping ratio, electrode stress, and temperature regulation can adjust the stability of polymorphism and the memory write voltage point to meet the needs of the driving circuit. The method has more uniform spatial positions of phase mixing and less defect aggregation, thereby effectively reducing the operating voltage and improving the durability of the memory.

[0023] The advantages of the present invention are as follows:

[0024] (1) The polymorphic memory of the present invention includes an electrode layer and a polymorphic ferroelectric layer. The polymorphic ferroelectric layer has a stable polymorphism for storing multi-bit data and can quickly switch between different storage states; the electrode layer is used to provide an electric field driving force and simultaneously regulate stress and the oxygen vacancy spatial distribution of the electrode-ferroelectric interface layer; the distribution and concentration of the elements are controlled by the doping elements and the electrodes are used to adjust the distribution between the material phase composition and the oxygen vacancies in the ferroelectric layer; and the stability of the polarization state and the driving electric field strength of each bit polarization state are optimized at the same time. This control method can optimize the lattice stability and polarization stability, and improve the rewrite performance and long-term stability of the memory.

[0025] (2) Data durability can reach 1E11, which is close to the durability index of current DRAM.

[0026] (3) The uniformity of the device can meet the needs of the array and can be applied to large-scale storage.

[0027] (4) It is fully compatible with the current CMOS process and does not require the introduction of additional doping elements and process equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic structural diagram of a ferroelectric storage capacitor provided in an embodiment of the present application;

[0029] Figure 2 It is a schematic diagram of the current continuous polarization multi-state problem;

[0030] Figure 3 A schematic structural diagram of a ferroelectric memory cell provided in an embodiment of the present application;

[0031] Figure 4 The schematic principle of the ferroelectric memory cell provided in the embodiment of the present application;

[0032] Figure 5 Schematic polarization current and polarization state of the ferroelectric memory cell provided in the embodiment of the present application;

[0033] Figure 6 The following are illustrative results of the ferroelectric memory cell provided in the embodiments of the present application.

[0034] Wherein, the accompanying drawings are marked as follows:

[0035] 1-first electrode, 2-second electrode, 3-multistate ferroelectric layer. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0037] While some exemplary embodiments of the present invention have been described for the purpose of illustration, it should be understood that the present invention may be implemented in other ways not specifically shown in the drawings.

[0038] like Figure 1 As shown, the device structure of the hafnium zirconium oxide doped multi-bit ferroelectric memory cell provided in this embodiment includes: a sandwich structure formed by a first electrode 1, a second electrode 2, and a polymorphic ferroelectric layer 3. The above-mentioned sandwich structure can be a metal electrode-ferroelectric film-metal electrode (MFM) structure but is not limited thereto. In some embodiments, the electrode 1 and the electrode 2 can also be made of materials other than metals, such as metal oxide semiconductors. In this embodiment, the materials of the two electrodes are not limited.

[0039] The ferroelectric material of the ferroelectric layer of the present application is a solid solution of hafnium oxide (HfO2) and zirconium oxide (ZrO2) doped with a single element or multiple elements, thereby ensuring the compatibility of the ferroelectric device with the CMOS process and the scalability of the size.

[0040] Since polymorphic storage plays a positive role in reducing memory power consumption and improving integration, the remnant polarization (Pr) of most hafnium oxide-based ferroelectric materials increases linearly with the increase of the electric field when the applied electric field is greater than the coercive field (reference Figure 2-01), this phenomenon can be polarized in multiple states. However, due to the bottom electrode and post-annealing treatment, the metal electrode takes away the oxygen of the ferroelectric film (oxygen scavenging), thus generating a certain number of oxygen vacancies at the metal-ferroelectric layer interface, causing a built-in electric field, which initially pins part of the ferroelectric dipole (ferroelectric dipole), and even causes the opposite polarization direction. Due to the instability of oxygen vacancy pinning and the characteristics of oxygen vacancies being easy to move under electric fields, and oxygen vacancies also play a role in stabilizing the ferroelectric phase. When oxygen vacancies begin to diffuse and transfer to the ferroelectric film bulk phase, they can transform part of the non-ferroelectric phase (M-phase) into the ferroelectric phase (O-phase), further increasing Pr (reference Figure 2 -02). As the electric field continues to circulate, oxygen continues to be lost in the ferroelectric film, the electrode interface is continuously oxidized, more defects and oxygen vacancies begin to form, and the interface begins to divide the applied electric field, causing the electric field on the ferroelectric layer to decrease. At the same time, the charges and vacancies captured by the defects also begin to pin some ferroelectric dipoles to prevent them from flipping, causing Pr to decrease. This is "fatigue" (reference Figure 2 -02). Therefore, using linear incomplete polarization to perform polymorphic storage will cause polymorphic logic ambiguity during the cycle due to the above reasons (refer to Figure 2 -02).

[0041] In contrast, the present application (reference Figure 3 ) The embodiment provides a ferroelectric device, in which one or more doping elements are added to the polymorphic ferroelectric layer 3 and the hafnium-zirconium-oxygen solid solution with a non-fixed ratio. Figure 3 The doping configuration is only used as an example, and the actual doping can be layered or uniformly mixed.

[0042] Under the action of the doping elements and the electrodes, this configuration can generate a structure in which the O-phase and the antiferroelectric phase T-phase are uniformly mixed in the ferroelectric layer 3 after annealing.

[0043] The O / T-phase with a suitable ratio will have a single peak behavior different from the dominant O-phase ferroelectric polarization during the reversal process, so that the ferroelectric memory cell of the application will have multiple stable polarization current peaks (reference Figure 5 -01), so that the polarization state maintains a stable polarization window during the long-term flipping process.

[0044] The stable multi-bit state of this arrangement is to use the O-phase in the stack to first generate a first polarization current peak (semi-polarization state) with a relatively small polarization voltage. When the electric field continues to increase and reaches the polarization condition of the T-phase in the stack, another polarization current peak will appear. At this time, the state of the multi-state ferroelectric layer 3 can be regarded as a full polarization state. The semi-polarization state and the full polarization state in both positive and negative directions are placed in the memory to generate four stable dual-bit states.

[0045] It should be noted that the difference between the two polarization electric field magnitudes is caused by the polarization electric field strength required by the O / T-phase itself. Therefore, the O / T-phase mixed ferroelectric layer 3 will naturally split into two polarization states in different electric field phases.

[0046] It is understood by those skilled in the art that the polarization state of the antiferroelectric layer cannot be maintained when the electric field is removed. Therefore, a pure antiferroelectric layer is not used for nonvolatile storage. Figure 4 As shown in the present configuration, when full polarization is completed, semi-polarization in the O-phase will generate charge pinning in the electrode. Even after the external electric field is removed, part of the polarization electric field generated by the O-phase polarization can still be maintained in the capacitor. When the electric field of the O-phase is greater than the depolarization field of the T-phase, the polarization charge in the fully polarized state can still be maintained when the electric field is 0, thereby realizing two storage states in the positive and negative directions.

[0047] It should be understood that changing the proportions of various elements can achieve the regulation of phase composition and stability, thereby meeting the device parameter adjustment requirements in practical applications.

[0048] On the other hand, electrode stress also plays a great role in the proportion and durability of phase components. The stacking ratio, thickness and sequence of the polymorphic ferroelectric layer 3 in the configuration will be adjusted accordingly according to the electrode.

[0049] It should be noted that this setting has more outstanding advantages than other methods of regulating O / T phase composition, such as being fully compatible with current CMOS processes and not requiring the introduction of additional doping elements and process equipment.

[0050] On the other hand, this configuration can be thinned to 5nm and still maintain higher Pr and lower operating voltage, which can achieve the characteristics of high integration and low power consumption.

[0051] On the other hand, Figure 6 As shown, the endurance of this configuration can reach 1E11, which is close to the endurance index of current DRAM.

[0052] On the other hand, the device uniformity of this configuration can meet the requirements of the array.

[0053] In a specific embodiment:

[0054] like Figure 3 As shown, this embodiment provides a hafnium zirconium oxygen doped multi-bit ferroelectric memory cell, which includes: a first electrode 1, a second electrode 2, and a multi-state ferroelectric layer 3 arranged between the two. The material of the first electrode is indium, and the thickness is 10nm; the material of the second electrode is chromium, and the thickness of the second electrode is 20nm.

[0055] The method for preparing the device comprises the following steps:

[0056] S1: growing insulating material as an insulating dielectric layer on the surface of the semiconductor by chemical vapor deposition;

[0057] S2: preparing a first electrode on the surface of the insulating dielectric layer by magnetron sputtering;

[0058] S3: preparing a multi-state ferroelectric layer on the surface of the first electrode by chemical vapor deposition;

[0059] S4: preparing a second electrode on the multi-state ferroelectric layer by magnetron sputtering;

[0060] S5: Perform high temperature annealing on the device, so that the material of the polymorphic ferroelectric layer undergoes phase transformation to form a mixed crystal of ferroelectric phase, antiferroelectric phase and non-ferroelectric phase under the combined action of doping elements and electrode stress. In step S5, the temperature of high temperature annealing is 350-650°C.

[0061] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A hafnium-zirconium-oxygen-doped multi-bit ferroelectric memory cell, characterized in that include: A first electrode and a second electrode, with a multi-state ferroelectric layer disposed therebetween; The multi-state ferroelectric layer includes a hafnium-zirconium-oxygen solid solution and a doping element.

2. The hafnium-zirconium-oxygen doped multi-bit ferroelectric memory cell according to claim 1, characterized in that: The doped elements in the polymorphic ferroelectric layer include: Group II elements calcium, strontium or barium; or Group III elements scandium, yttrium, aluminum, gallium and indium; or doped lanthanide elements lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium and lutetium.

3. The hafnium-zirconium-oxygen-doped multi-bit ferroelectric memory cell according to claim 2, characterized in that: In the polymorphic ferroelectric layer, the ratio of hafnium oxide to zirconium oxide in the hafnium zirconium oxygen solid solution is 0.1-10; and the concentration of doping elements is 0.1%-20%.

4. The hafnium-zirconium-oxygen doped multi-bit ferroelectric memory cell according to claim 1, characterized in that: The thickness of the first electrode and the second electrode is 2-50 nm.

5. The hafnium-zirconium-oxygen doped multi-bit ferroelectric memory cell according to claim 1, characterized in that: The material of the first electrode and the second electrode is any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, and chromium, or any one of alloys, nitride oxides, and metal oxide semiconductors of the above materials.

6. The HfZrO-doped multi-bit ferroelectric memory cell according to claim 1, characterized in that: The thickness of the multi-state ferroelectric layer is 1.5-30 nm.

7. A method for preparing a hafnium zirconium oxide doped multi-bit ferroelectric memory cell, used for preparing the hafnium zirconium oxide doped multi-bit ferroelectric memory cell as claimed in any one of claims 1 to 6, characterized in that The following steps are involved: S1: growing insulating material on the surface of the semiconductor as an insulating dielectric layer; S2: preparing a first electrode on the surface of the insulating dielectric layer; S3: preparing a multi-state ferroelectric layer on the surface of the first electrode; S4: preparing a second electrode on the multi-state ferroelectric layer; S5: performing high temperature annealing treatment on the device, so that the material of the polymorphic ferroelectric layer undergoes a phase transformation under the combined action of the doping elements and the electrode stress to form a mixed crystal of a ferroelectric phase, an antiferroelectric phase, and a non-ferroelectric phase.

8. The method for preparing a hafnium-zirconium-oxygen doped multi-bit ferroelectric memory cell according to claim 7, characterized in that: In step S5, the temperature of the high temperature annealing treatment is 350-650°C.

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