Preparation method for improving mobility of indium gallium zinc oxide thin film transistor

Abstract

The invention relates to the technical field of display panels, in particular to a preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor, and the method comprises the steps: forming a gate metal thin film on a target substrate, and carrying out the imaging, so as to obtain a back gate; generating a metal oxide on the back gate, and etching the metal oxide on the gate of the target transistor by using inductively coupled plasma to form a gate oxide layer; growing indium gallium zinc oxide on the gate oxide layer as an active layer; evaporating a source-drain metal film on the active layer, and patterning to obtain drain-source metal; defining a channel region of the indium gallium zinc oxide through photoetching, and isolating the channel region; and growing yttrium metal on the drain-source metal by using a magnetron sputtering process, and carrying out annealing treatment on the yttrium metal at a preset temperature to obtain a covering layer, thereby preparing the target transistor. Therefore, the problems that an existing method for improving the IGZO mobility affects the original performance of the transistor and is not suitable for the display field and the subsequent process are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of display panels, and in particular to a preparation method for improving the mobility of indium gallium zinc oxide thin film transistors. Background Art

[0002] Thin Film Transistor (TFT) is a field effect transistor. The basic manufacturing method is to deposit various thin films on a substrate, such as a semiconductor active layer, a dielectric layer, and a metal electrode layer. According to the different materials of the TFT active layer, TFT technology is mainly divided into the following four types: hydrogenated amorphous silicon (a-Si:H) TFT, low temperature polycrystalline silicon (LTPS) TFT, amorphous metal oxide TFT, and organic semiconductor TFT. Among them, metal oxide TFT, represented by indium gallium zinc oxide (IGZO), has been widely favored for its advantages such as high uniformity over a large area and low temperature preparation process.

[0003] IGZO is a transparent oxide semiconductor composed of indium (In), gallium (Ga), zinc (Zn) and oxygen (O). It has become a hot topic in research and industry in recent years due to its many excellent electrical and optical properties. At present, IGZO is mainly used in the field of display technology: the mobility of IGZO is much higher than that of traditional a-Si, which makes the pixel refresh speed faster, thereby achieving a higher screen refresh rate; its low leakage characteristics allow the screen to maintain the pixel state without current refresh, thereby greatly reducing power consumption. In addition to the field of display technology, IGZO also shows great potential in new storage technologies. For example, the new memory 2T0C DRAM structure uses the low leakage characteristics of IGZO to reduce process complexity and improve retention time.

[0004] The mobility of IGZO has been an important topic of common concern in the scientific research and industry in recent years. For display technology, high mobility can bring higher refresh rate, resolution and color saturation, which is conducive to the production of high-end screens; for storage technology, high mobility can bring lower power consumption, faster speed, and can broaden its application.

[0005] At present, the main methods to improve the mobility of IGZO are: (1) adjusting the proportion of each component in IGZO, but this method requires a compromise between mobility and stability, and it is difficult to significantly improve the mobility while meeting the normal performance of the transistor; (2) post-processing method: the mobility of IGZO can be improved through post-processing methods such as annealing, but the device will subsequently experience performance degradation; (3) crystallization: the temperature for crystallization is relatively high (>600°C), which is not suitable for the display field and post-processing. The scope of use is relatively limited, and after the transition from amorphous state to polycrystalline state, the mobility may even decrease due to the influence of grain boundaries. Summary of the invention

[0006] The present invention provides a preparation method for improving the mobility of indium gallium zinc oxide thin film transistors, so as to solve the problems that the existing method for improving the mobility of IGZO is not suitable for the display field and the back-end process, it is difficult to significantly improve the mobility while satisfying the normal performance of the transistor, and the device will subsequently experience performance degradation.

[0007] The first aspect of the present invention provides a preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor, comprising the following steps: forming a gate metal film on a target substrate, and patterning the gate metal film to obtain a patterned gate metal as a back gate of a target transistor; generating a metal oxide on the back gate, and etching the metal oxide on the gate of the target transistor by inductively coupled plasma to form a gate oxide layer of the target transistor; growing indium gallium zinc oxide on the gate oxide layer with the gate metal to use the indium gallium zinc oxide as an active layer of the target transistor; evaporating a source and drain metal film on the active layer, and patterning the source and drain metal film to obtain a patterned source and drain metal as a drain and source metal of the target transistor; defining a channel region of the indium gallium zinc oxide by photolithography, and etching the indium gallium zinc oxide outside the channel region by a wet method or a dry method to isolate the channel region; growing yttrium metal on the drain and source metal by a magnetron sputtering process, and annealing the yttrium metal at a preset temperature to obtain a covering layer of the target transistor.

[0008] Optionally, forming a gate metal film on a target substrate and patterning the gate metal film to obtain a patterned gate metal as a back gate of a target transistor includes:

[0009] Depositing a gate metal, or a gate metal and an adhesion layer, or a gate metal and an adhesion layer of a gate and gate oxide, or a gate metal, an adhesion layer, and an adhesion layer of a gate and gate oxide on the target substrate by photolithography and electron beam to form the gate metal film;

[0010] The gate metal film is peeled off to form the patterned gate metal, and the patterned gate metal is used as the back gate of the target transistor; or

[0011] Generating a gate metal, or a gate metal and an adhesion layer, or a gate metal and an adhesion layer of a gate and a gate oxide, or a gate metal, an adhesion layer, and an adhesion layer of a gate and a gate oxide on the target substrate to form the gate metal film;

[0012] The gate metal film is photolithographically processed and etched to form the patterned gate metal, and the patterned gate metal is used as the back gate of the target transistor.

[0013] Optionally, the gate metal is any one of palladium, molybdenum, titanium nitride and platinum.

[0014] Optionally, the generating a metal oxide on the back gate comprises:

[0015] The metal oxide is generated on the back gate by using an atomic layer deposition method, a plasma enhanced chemical vapor deposition method or a plasma enhanced atomic layer deposition method, wherein the metal oxide is at least one of hafnium dioxide and aluminum oxide.

[0016] Optionally, the indium gallium zinc oxide is grown on the gate oxide layer with the gate metal by atomic layer deposition, so as to use the indium gallium zinc oxide as the active layer of the target transistor; or

[0017] The indium gallium zinc oxide is grown on the gate oxide layer with the gate metal by plasma enhanced atomic layer deposition and sputtering, so as to use the indium gallium zinc oxide as the active layer of the target transistor.

[0018] Optionally, the source-drain metal and the protective metal are evaporated on the active layer by photolithography and electron beam to form the source-drain metal film;

[0019] The source-drain metal film is stripped to form the patterned source-drain metal, and the patterned source-drain metal is used as the drain-source metal of the target transistor; or

[0020] Generating evaporated source-drain metal and protective metal on the active layer to form the source-drain metal film;

[0021] The source-drain metal film is photolithographically processed and etched to form the patterned source-drain metal, and the patterned source-drain metal is used as the drain-source metal of the target transistor.

[0022] Optionally, the preset temperature is 100°C-250°C.

[0023] A second aspect of the present invention provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the preparation method for improving the mobility of indium gallium zinc oxide thin film transistors as described in the above embodiment.

[0024] A third aspect of the present invention provides a computer program product. When the computer program / instructions are executed by a processor, the above-mentioned preparation method for improving the mobility of indium gallium zinc oxide thin film transistors is implemented.

[0025] A fourth aspect of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-mentioned preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor.

[0026] The preparation method for improving the mobility of indium gallium zinc oxide thin film transistors proposed in the embodiment of the present invention first grows a layer of metal by physical vapor deposition PVD (evaporation or sputtering), and then performs appropriate annealing. During the annealing, the covered metal absorbs oxygen from the IGZO channel and injects electrons, thereby increasing the carrier concentration in the channel, thereby improving the effective mobility of the transistor. Not only is the process complexity low, large-area preparation is possible, and the mobility of IGZO TFTs can be greatly improved at low temperatures (<200°C), the original characteristics of the transistor are maintained, and the application scenarios are wider.

[0027] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 A flow chart of a preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor provided by an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of a preparation process for improving the mobility of an indium gallium zinc oxide thin film transistor provided by an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of the back-gate IGZO TFT structure provided by an embodiment of the present invention;

[0032] Figure 4A schematic diagram comparing the transfer characteristics of a Baseline (device without a cover layer) and an IGZO TFT device with a Y cover layer provided in an embodiment of the present invention;

[0033] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0035] The following describes a method for improving the mobility of an indium gallium zinc oxide thin film transistor according to an embodiment of the present invention with reference to the accompanying drawings.

[0036] Figure 1 A schematic flow chart of a method for improving the mobility of an indium gallium zinc oxide thin film transistor provided in an embodiment of the present invention.

[0037] like Figure 1 As shown, the preparation method for improving the mobility of indium gallium zinc oxide thin film transistors includes the following steps:

[0038] In step S101, a gate metal film is formed on a target substrate, and the gate metal film is patterned to obtain a patterned gate metal as a back gate of a target transistor.

[0039] In some embodiments, forming a gate metal film on a target substrate and patterning the gate metal film to obtain a patterned gate metal as a back gate of a target transistor includes:

[0040] By photolithography and electron beam evaporation, a gate metal, or a gate metal and an adhesion layer, or a gate metal and an adhesion layer of a gate and gate oxide, or a gate metal, an adhesion layer, and an adhesion layer of a gate and gate oxide are formed on a target substrate to form a gate metal film;

[0041] The gate metal film is stripped to form a patterned gate metal, and the patterned gate metal is used as the back gate of the target transistor; or

[0042] Generating a gate metal, or a gate metal and an adhesion layer, or a gate metal and an adhesion layer of a gate and a gate oxide, or a gate metal, an adhesion layer, and an adhesion layer of a gate and a gate oxide on a target substrate to form a gate metal film;

[0043] The gate metal film is photolithographically processed and etched to form a patterned gate metal, and the patterned gate metal is used as the back gate of the target transistor.

[0044] like Figure 2 As shown, in the actual implementation process, 15nmPd / 10nmTi / 1nmTi ​​is evaporated on the target substrate by photolithography and electron beam to form a gate metal film, and then the gate metal film is peeled off to form a patterned gate metal as the back gate of the target transistor. Among them, 15nmPd is the gate metal, which must be included and can be other thicknesses. In addition to Pd, it can also be other materials, such as Ti, Mo, TiN, Pt, etc. 10nmTi is an adhesion layer, which can be absent or of other thicknesses. The material can be Ti or TaN and other adhesion layer materials. 1nmTi ​​is the adhesion layer between the gate and the gate oxide, which can be absent or of other thicknesses. The material can be Ti or other materials such as Al.

[0045] In addition, in addition to the above-mentioned photolithography-stripping process, the patterning of the gate metal film can also adopt a growth-etching process, that is, first grow the gate metal embodied by the above-mentioned material, then photolithography, and then use etching (including plasma etching, etc.) to form a patterned gate metal as the back gate of the target transistor.

[0046] In step S102, a metal oxide is generated on the back gate, and the metal oxide on the gate of the target transistor is etched using inductively coupled plasma to form a gate oxide layer of the target transistor.

[0047] In some embodiments, forming a metal oxide on a back gate includes:

[0048] Atomic layer deposition, plasma enhanced chemical vapor deposition or plasma enhanced atomic layer deposition is used to generate metal oxide on the back gate, wherein the metal oxide is at least one of hafnium dioxide and aluminum oxide.

[0049] like Figure 2 As shown, in the actual implementation process, the atomic layer deposition method ALD is used to grow 10nm HfO2 as the gate oxide layer of the target transistor, and the HfO2 on the gate of the target transistor is etched away using the inductively coupled plasma method ICP etching to expose the gate metal for subsequent interconnection and form the gate oxide layer of the target transistor.

[0050] Among them, the metal oxide of the back gate can be 10nm HfO2, other thicknesses, other materials, such as Al2O3, etc., or their combinations, such as 10nm Al2O3+5nm HfO2, and the growth method can be ALD, plasma enhanced chemical vapor deposition method PECVD, plasma enhanced atomic layer deposition method PEALD, etc.

[0051] In step S103, indium gallium zinc oxide is grown on the gate oxide layer with the gate metal, so that the indium gallium zinc oxide is used as an active layer of the target transistor.

[0052] In some embodiments, growing indium gallium zinc oxide on a gate oxide layer with a gate metal so as to use the indium gallium zinc oxide as an active layer of a target transistor includes:

[0053] Growing indium gallium zinc oxide on a gate oxide layer with a gate metal by atomic layer deposition to use the indium gallium zinc oxide as an active layer of a target transistor; or

[0054] Indium gallium zinc oxide is grown on a gate oxide layer with a gate metal by plasma enhanced atomic layer deposition and sputtering, so as to use the indium gallium zinc oxide as an active layer of a target transistor.

[0055] like Figure 2 As shown, in the actual implementation process, the ALD method can be used to grow 10nm IGZO on the gate oxide layer with gate metal as the active layer of the target transistor; the PEALD method and sputtering technology can also be used to grow 10nm IGZO on the gate oxide layer with gate metal, or other thicknesses can be used as the active layer of the target transistor.

[0056] It should be noted that, in addition to IGZO materials, other materials such as indium gallium zinc oxide such as IGO, or material combinations, such as 5nm IGZO+2nm InO+5nm IGZO, may also be used.

[0057] In step S104, a source-drain metal film is evaporated on the active layer, and the source-drain metal film is patterned to obtain patterned source-drain metals as drain-source metals of the target transistor.

[0058] In some embodiments, a source-drain metal film is evaporated on the active layer, and the source-drain metal film is patterned to obtain a patterned source-drain metal as a drain-source metal of a target transistor, including:

[0059] By using photolithography and electron beam to evaporate source and drain metal and protective metal on the active layer, a source and drain metal film is formed;

[0060] Stripping the source-drain metal film to form a patterned source-drain metal, and using the patterned source-drain metal as the drain-source metal of the target transistor; or

[0061] Generating evaporated source-drain metal and protective metal on the active layer to form a source-drain metal film;

[0062] The source-drain metal film is photolithographically processed and etched to form patterned source-drain metal, and the patterned source-drain metal is used as the drain-source metal of the target transistor.

[0063] In the actual implementation process, Figure 2 As shown, 20nm Ti / 45nm Pd is evaporated on the active layer by photolithography and electron beam to form a source-drain metal film, and then the source-drain metal film is stripped to form a pattern as the source and drain of the target transistor. Among them, 20nm Ti is used as the source-drain contact metal of IGZO, and other thicknesses can be used, and the material can be replaced by Mo, TiN, ITO, etc., and 45nm Pd is used as a protective metal, and other thicknesses can be used, and the material can be replaced by Pt, etc.

[0064] In addition, in addition to the above-mentioned photolithography-stripping process, the patterning of the source and drain metal can also adopt a growth-etching process, that is, first grow the source and drain metal embodied by the above-mentioned material, then photolithography, and then use etching (including plasma etching, etc.) to form a patterned source and drain metal as the drain source metal of the target transistor.

[0065] In step S105 , a channel region of the indium gallium zinc oxide is defined by photolithography, and the indium gallium zinc oxide outside the channel region is etched by a wet method or a dry method to isolate the channel region.

[0066] In the actual implementation process, Figure 2 As shown, the channel region of IGZO is defined by photolithography, and the IGZO outside the channel region is etched by wet or dry method to achieve channel isolation.

[0067] In step S106, a yttrium metal is grown on the drain-source metal by using a magnetron sputtering process, and the yttrium metal is annealed at a preset temperature to obtain a capping layer of the target transistor.

[0068] In some embodiments, the preset temperature is 100°C-250°C.

[0069] In the actual implementation process, Figure 2 and 3 As shown, 2 nm of yttrium (Y) is grown by magnetron sputtering process, and then annealed at 200°C in air for 5 minutes to obtain the covering layer of the target transistor, thereby preparing a back-gate field effect transistor composed of a metal layer / insulating layer / semiconductor layer stacked in the vertical direction, i.e., the target transistor.

[0070] It should be noted that in addition to the magnetron sputtering process, other PVD methods such as evaporation can also be used for the growth method. The 2nm Y can have other thicknesses, the material can be replaced with Al, etc., the annealing conditions can use other temperatures and other durations, and the temperature can be lower than 200°C.

[0071] Furthermore, if Figure 4As shown, the transfer characteristics test of the target transistor prepared in the embodiment of the present invention is carried out. It can be seen from the figure that the mobility of the IGZO TFT device with the Y covering layer is improved by 7 times compared with the device baseline without the covering layer.

[0072] In summary, according to the preparation method for improving the mobility of indium gallium zinc oxide thin film transistors proposed in an embodiment of the present invention, a layer of metal is first grown by physical vapor deposition PVD (evaporation or sputtering), and then appropriate annealing is performed. During the annealing, the covered metal absorbs oxygen from the IGZO channel and injects electrons, thereby increasing the carrier concentration in the channel, thereby improving the effective mobility of the transistor. Not only is the process complexity low, large-area preparation is possible, and a significant improvement in the mobility of IGZO TFTs can be achieved at low temperatures (<200°C), the original characteristics of the transistor are maintained, and the application scenarios are wider.

[0073] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. The electronic device may include:

[0074] A memory 501 , a processor 502 , and a computer program stored in the memory 501 and executable on the processor 502 .

[0075] When the processor 502 executes the program, the preparation method for improving the mobility of the indium gallium zinc oxide thin film transistor provided in the above embodiment is implemented.

[0076] Furthermore, the electronic device further comprises:

[0077] The communication interface 503 is used for communication between the memory 501 and the processor 502 .

[0078] The memory 501 is used to store computer programs that can be executed on the processor 502 .

[0079] The memory 501 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0080] If the memory 501, the processor 502 and the communication interface 503 are implemented independently, the communication interface 503, the memory 501 and the processor 502 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0081] Optionally, in a specific implementation, if the memory 501, the processor 502 and the communication interface 503 are integrated on a chip, the memory 501, the processor 502 and the communication interface 503 can communicate with each other through an internal interface.

[0082] The processor 502 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0083] An embodiment of the present invention further provides a computer program product, which implements the above-mentioned preparation method for improving the mobility of indium gallium zinc oxide thin film transistors when the computer program / instructions are executed by a processor.

[0084] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor.

[0085] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0086] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0087] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present invention belong.

[0088] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or N wirings (electronic devices), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways as necessary and then storing it in a computer memory.

[0089] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0090] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0091] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A preparation method for improving the mobility of indium gallium zinc oxide thin film transistors, characterized in that: The following steps are involved: Forming a gate metal film on a target substrate, and patterning the gate metal film to obtain a patterned gate metal as a back gate of a target transistor; Generating a metal oxide on the back gate, and etching the metal oxide on the gate of the target transistor by using an inductively coupled plasma to form a gate oxide layer of the target transistor; Growing indium gallium zinc oxide on the gate oxide layer with gate metal, so as to use the indium gallium zinc oxide as the active layer of the target transistor; Depositing a source-drain metal film on the active layer, and patterning the source-drain metal film to obtain patterned source-drain metal as the drain-source metal of the target transistor; Defining the channel region of the indium gallium zinc oxide by photolithography, and etching the indium gallium zinc oxide outside the channel region by wet or dry etching to isolate the channel region; Yttrium metal is grown on the drain-source metal by using a magnetron sputtering process, and the yttrium metal is annealed at a preset temperature to obtain a covering layer of the target transistor.

2. The method for improving the mobility of an indium gallium zinc oxide thin film transistor according to claim 1, characterized in that: The step of forming a gate metal film on a target substrate and patterning the gate metal film to obtain a patterned gate metal as a back gate of a target transistor comprises: Depositing a gate metal, or a gate metal and an adhesion layer, or a gate metal and an adhesion layer of a gate and gate oxide, or a gate metal, an adhesion layer, and an adhesion layer of a gate and gate oxide on the target substrate by photolithography and electron beam to form the gate metal film; The gate metal film is peeled off to form the patterned gate metal, and the patterned gate metal is used as the back gate of the target transistor; or Generating a gate metal, or a gate metal and an adhesion layer, or a gate metal and an adhesion layer of a gate and a gate oxide, or a gate metal, an adhesion layer, and an adhesion layer of a gate and a gate oxide on the target substrate to form the gate metal film; The gate metal film is photolithographically processed and etched to form the patterned gate metal, and the patterned gate metal is used as the back gate of the target transistor.

3. The method for improving the mobility of an indium gallium zinc oxide thin film transistor according to claim 1, characterized in that: The gate metal is any one of palladium, molybdenum, titanium nitride and platinum.

4. The method for improving the mobility of an indium gallium zinc oxide thin film transistor according to claim 1, characterized in that: The step of generating a metal oxide on the back gate comprises: The metal oxide is generated on the back gate by using an atomic layer deposition method, a plasma enhanced chemical vapor deposition method or a plasma enhanced atomic layer deposition method, wherein the metal oxide is at least one of hafnium dioxide and aluminum oxide.

5. The method for improving the mobility of an indium gallium zinc oxide thin film transistor according to claim 1, characterized in that: The step of growing indium gallium zinc oxide on the gate oxide layer with gate metal so as to use the indium gallium zinc oxide as the active layer of the target transistor comprises: Growing the indium gallium zinc oxide on the gate oxide layer with gate metal by atomic layer deposition to use the indium gallium zinc oxide as the active layer of the target transistor; or The indium gallium zinc oxide is grown on the gate oxide layer with the gate metal by plasma enhanced atomic layer deposition and sputtering, so as to use the indium gallium zinc oxide as the active layer of the target transistor.

6. The method for improving the mobility of an indium gallium zinc oxide thin film transistor according to claim 1, characterized in that: The step of evaporating a source-drain metal film on the active layer and patterning the source-drain metal film to obtain a patterned source-drain metal as a drain-source metal of the target transistor includes: Depositing source-drain metal and protective metal on the active layer by photolithography and electron beam to form the source-drain metal film; The source-drain metal film is stripped to form the patterned source-drain metal, and the patterned source-drain metal is used as the drain-source metal of the target transistor; or Generating evaporated source-drain metal and protective metal on the active layer to form the source-drain metal film; The source-drain metal film is photolithographically processed and etched to form the patterned source-drain metal, and the patterned source-drain metal is used as the drain-source metal of the target transistor.

7. The method for improving the mobility of an indium gallium zinc oxide thin film transistor according to claim 1, characterized in that: The preset temperature is 100°C-250°C.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor as described in any one of claims 1 to 6.

9. A computer program product, characterized in that When the computer program / instruction is executed by a processor, the preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor as described in any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the preparation method for improving the mobility of an indium gallium zinc oxide thin film transistor as described in any one of claims 1 to 6.

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