Discrete device multimode drive circuit integrated device

Abstract

The invention provides a discrete device multimode driving circuit integrated device, which comprises a discrete device area and a driving circuit area, and the discrete device area is composed of a cellular area II and a terminal area I. The whole driving circuit area is located in a floating basin structure III manufactured in the discrete device cellular area. The floating basin is integrally integrated in a second conductive type well region of the discrete device and comprises a buried oxide layer located at the bottom and an oxidation medium groove located between the boundary of the floating basin and an internal high-voltage and low-voltage region. Devices such as a BJT, a DMOS, a CMOS and the like can be integrated in the floating basin to build a driving circuit. Isolation between the floating basin and the discrete device and isolation between the high-voltage area and the low-voltage area in the floating basin are achieved through the oxide layer, normal work of the drive circuit is guaranteed, and integration of the discrete device and the drive circuit is achieved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor power devices and relates to a discrete device multi-mode drive circuit integrated device. Background Art

[0002] Since its invention, power devices have been widely used in the field of electronic power, such as consumer electronics, automotive electronics, industrial automation and other fields. In the application of power devices, drive circuits are often required to control the devices. When using discrete power devices, the separate use of devices and control circuits often occupies a large circuit board area, which is not conducive to the miniaturization of equipment. Therefore, directly integrating the drive circuit in the cell area of ​​the discrete device can reduce the chip area and improve the integration. But at the same time, because the drive circuit is integrated in the cell area of ​​the discrete device, when the discrete device is forward withstand voltage, the expansion of the depletion region will affect the normal operation of the drive circuit, and even cause the breakdown of the device in the drive circuit. Moreover, for the drive circuit, it is generally a high-voltage integrated circuit (HVIC), which is divided into a high-voltage area and a low-voltage area. These two areas also need to be isolated to ensure the normal operation of the device. Summary of the invention

[0003] In view of the shortcomings of the background technology, the present invention proposes a discrete device multi-mode drive circuit integrated device, which isolates the influence of the discrete device cell area on the drive circuit area by forming an oxide medium groove between the cell area and the floating basin and injecting a buried oxide layer under the drive circuit; and the entire floating basin structure is placed in the P-well of the discrete device to avoid premature breakdown of the bottom of the oxide medium groove at the edge of the floating basin. Inside the floating basin, the oxide medium groove is used to isolate the circuit area on the high-voltage side and the low-voltage side to ensure the normal operation of the high and low voltage areas in working states such as level conversion. The present invention solves the influence of discrete devices on the drive circuit area when the drive circuit is integrated. And the present invention can be applied to various discrete device structures such as VDMOS, IGBT, etc.

[0004] To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0005] A discrete device multi-mode drive circuit integrated device comprises a discrete device area and a drive circuit area.

[0006] The discrete device area consists of the cell area II and the terminal area I.

[0007] The driving circuit area is located as a whole in the floating basin structure III made in the cell area of ​​the discrete device; the floating basin structure III is integrated as a whole in the second conductive type semiconductor well area A201 of the discrete device, which includes a buried oxide layer 403 at the bottom and an oxide medium groove 402 located between the boundary of the floating basin structure and the internal high and low voltage areas; BJT, CMOS, or DMOS devices are integrated in the floating basin for building a driving circuit.

[0008] As a preferred embodiment, AA' is a cross section of a discrete device including a floating basin structure; line AA' is a section line pointing from the second conductive type semiconductor field limiting ring 203 structure to the oxide dielectric groove 402 at the edge of the floating basin structure; the device cross section along line AA' includes:

[0009] The discrete device cell region VDMOS includes a first conductive type semiconductor substrate 101, a first conductive type semiconductor drift region A102, a first conductive type semiconductor contact A103, a first conductive type semiconductor drift region B104, a first conductive type semiconductor contact B105, a first conductive type semiconductor well region A106, a first conductive type semiconductor contact region A107, a first conductive type semiconductor well region B108, a first conductive type semiconductor contact region B109, a second conductive type semiconductor well region A201, and a second conductive type Semiconductor contact region A202, second conductivity type semiconductor field limiting ring structure 203, second conductivity type semiconductor well region B204, second conductivity type semiconductor contact region B205, second conductivity type semiconductor well region C206, second conductivity type semiconductor well region D207, second conductivity type semiconductor buried layer A208, second conductivity type semiconductor region 209, VDMOS polysilicon gate 301, DMOS polysilicon gate 302, CMOS polysilicon gate 303, field oxide layer 401, oxide dielectric groove 402, buried oxide layer 403;

[0010] Among them, the first conductive type semiconductor substrate 101, the first conductive type semiconductor drift region A102, the first conductive type semiconductor contact A103, the second conductive type semiconductor well region A201, the second conductive type semiconductor contact region A202, the VDMOS polysilicon gate 301, and the field oxide layer 401 constitute the cell region II of the discrete device, and the second conductive type semiconductor field limiting ring structure 203 is the terminal region I of the discrete device; the first conductive type drift region B104, the first conductive type semiconductor contact B105, the first conductive type semiconductor well region A106, the first conductive type contact A107, the first conductive type well region B108, the first conductive type contact B109, the second conductive type well region B204, the second conductive type contact region B205, the second conductive type well region C206, the second conductive type well region D207, the DMOS polysilicon gate 302, the CMOS polysilicon gate 303, the oxidation dielectric groove 402, and the buried oxide layer 403 constitute the floating basin structure III;

[0011] Among them, the first conductive type semiconductor drift region A102 is located above the first conductive type semiconductor substrate 101, and the second conductive type semiconductor well region A201 is located above the first conductive type semiconductor drift region A102; the first conductive type semiconductor contact A103 and the second conductive type semiconductor contact A202 are located in the second conductive type semiconductor well region A201, and the second conductive type semiconductor 203 is located outside the device cell region to form a terminal structure; the VDMOS polysilicon gate 301 is located above the first conductive type semiconductor drift region A102,

[0012] The floating basin structure III is entirely located in the second conductivity type semiconductor well region A201, and is composed of:

[0013] The buried oxide layer 403 is located at the bottom of the second conductive type semiconductor well region B204, the oxidizing medium groove 402 is located between the edge of the floating basin structure and different devices inside the floating basin structure, the first conductive type semiconductor drift region B104 is located on the right side of the second conductive type semiconductor well region B204, the second conductive type semiconductor B205 is located in the second conductive type semiconductor well region B204, the first conductive type semiconductor well region A106 is located on the right side of the first conductive type semiconductor drift region B104, the first conductive type semiconductor contact B105 is located in the second conductive type semiconductor well region B204 and the first conductive type semiconductor well region A106, the polysilicon gate 302 covers the semiconductor surface adjacent to the second conductive type semiconductor well region B204 and the first conductive type semiconductor drift region B104, the first conductive type semiconductor drift region B104, the first conductive type semiconductor contact B105, the first conductive type semiconductor The body well region A106, the second conductive type semiconductor well region B204, the second conductive type semiconductor contact region B205 and the DMOS polysilicon gate 302 constitute a DMOS; the first conductive type semiconductor contact A107 is located in the second conductive type semiconductor well region C206, the polysilicon gate 303 is located on the silicon surface between the two first conductive type semiconductor contacts A107, the first conductive type semiconductor contact A107, the second conductive type semiconductor C206 and the CMOS polysilicon gate 303 constitute a CMOS tube; the second conductive type semiconductor well region D207 is located in the first conductive type semiconductor well region B108, the first conductive type semiconductor contact B109 is located on the surface of the second conductive type semiconductor well region D207, the first conductive type semiconductor well region B108, the first conductive type semiconductor contact B109 and the second conductive type semiconductor D207 constitute a BJT tube;

[0014] The devices in the floating basin structure described above are isolated laterally by the oxide dielectric trench 402 between the DMOS and the BJT, the DMOS and the CMOS, and the CMOS and the BJT.

[0015] As a preferred embodiment, the buried oxide layer 403 at the bottom of the floating basin structure is replaced by a second conductive type semiconductor buried layer 208 formed by implantation.

[0016] As a preferred embodiment, the oxidizing medium groove 402 in the floating basin structure is replaced with a second conductive type semiconductor region 209 .

[0017] As a preferred method, the edge of the second conductive type semiconductor well region A201 close to the edge of the floating basin structure is terminated at the cut-off oxidation medium groove 402, and the second conductive type semiconductor buried layer B210 is formed by groove bottom implantation.

[0018] As a preferred method, the width of the oxidation medium groove 402 and the size formed by the groove bottom injection are enlarged so that the second conductive type semiconductor buried layer B210 is directly connected below the CMOS and BJT devices to form isolation.

[0019] As a preferred embodiment, the oxidized dielectric groove 402 at the edge of the floating basin structure is replaced with a semiconductor region 209 of the second conductivity type.

[0020] As a preferred embodiment, the terminal region I is replaced by a field plate structure and a junction terminal extension structure.

[0021] As a preferred embodiment, the discrete device cell region II is replaced by VDMOS and IGBT.

[0022] The beneficial effects of the present invention are:

[0023] Integrating the driving circuit in the discrete device can greatly improve the integration of the circuit and further reduce the circuit area. The method of connecting the oxide medium groove between the discrete device cell area and the driving circuit and the oxide medium buried layer formed by injection under the integrated circuit, and making the floating basin structure in the second conductive type semiconductor well area of ​​the discrete device, can well isolate the influence of the depletion area or leakage current on the integrated circuit when the discrete device is under voltage or turned on. And in the floating basin, the method of connecting the oxide medium groove with the oxide medium buried layer formed by injection under the driving circuit can well achieve the isolation between the high-voltage area and the low-voltage area in the driving circuit, isolate the influence of the high potential or leakage current of the high-voltage area on the low-voltage area, and ensure the normal operation of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A top view of a schematic diagram of a discrete device integrated floating basin isolation structure of the present invention;

[0025] Figure 2 For along Figure 1 The device cross-section diagram along line AA';

[0026] Figure 3 It is a cross-sectional view of the discrete device integrated floating basin isolation structure of Example 2;

[0027] Figure 4 It is a cross-sectional view of a discrete device integrated floating basin isolation structure of Example 3;

[0028] Figure 5 It is a cross-sectional view of a discrete device integrated floating basin isolation structure of Example 4;

[0029] Figure 6 It is a cross-sectional view of the discrete device integrated floating basin isolation structure of Example 5;

[0030] Figure 7 A top view of a schematic diagram of a floating basin isolation structure for discrete device integration in Example 6;

[0031] 101-a first conductive type semiconductor substrate, 102-a first conductive type semiconductor drift region A, 103-a first conductive type semiconductor contact A, 104-a first conductive type semiconductor drift region B, 105-a first conductive type semiconductor contact B, 106-a first conductive type semiconductor well region A, 107-a first conductive type semiconductor contact region A, 108-a first conductive type semiconductor well region B, 109-a first conductive type semiconductor contact region B,

[0032] 201-second conductive type semiconductor well region A, 202-second conductive type semiconductor contact region A, 203-second conductive type semiconductor field limiting ring structure, 204-second conductive type semiconductor well region B, 205-second conductive type semiconductor contact region B, 206-second conductive type semiconductor well region C, 207-second conductive type semiconductor well region D, 208-second conductive type semiconductor buried layer A, 209-second conductive type semiconductor region, 210-second conductive type semiconductor buried layer B,

[0033] 301-VDMOS polysilicon gate, 302-DMOS polysilicon gate, 303-CMOS polysilicon gate, 401-field oxide layer, 402-oxidation dielectric groove, 403-buried oxide layer. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Example 1

[0036] A top view of a discrete device multi-mode drive circuit integration technology described in Example 1 is shown in FIG. Figure 1 As shown, Figure 1 The overall diagram is a top view of a discrete device integrated floating basin isolation structure, where reference numeral Ⅰ is the terminal region of the discrete device, reference numeral Ⅱ is the cell region of the discrete device, and reference numeral Ⅲ is the floating basin isolation structure.

[0037] Including discrete device area and drive circuit area,

[0038] The discrete device area consists of the cell area II and the terminal area I.

[0039] The driving circuit area is located as a whole in the floating basin structure III made in the cell area of ​​the discrete device; the floating basin structure III is integrated as a whole in the second conductive type semiconductor well area A201 of the discrete device, which includes a buried oxide layer 403 at the bottom and an oxide medium groove 402 located between the boundary of the floating basin structure and the internal high and low voltage areas; BJT, CMOS, or DMOS devices are integrated in the floating basin for building a driving circuit.

[0040] AA' is a cross section of a discrete device including a floating basin structure; line AA' is a section line from the second conductive type semiconductor field limiting ring 203 structure to the oxide dielectric groove 402 at the edge of the floating basin structure; the device cross section along line AA' includes:

[0041] The discrete device cell region VDMOS includes a first conductive type semiconductor substrate 101, a first conductive type semiconductor drift region A102, a first conductive type semiconductor contact A103, a first conductive type semiconductor drift region B104, a first conductive type semiconductor contact B105, a first conductive type semiconductor well region A106, a first conductive type semiconductor contact region A107, a first conductive type semiconductor well region B108, a first conductive type semiconductor contact region B109, a second conductive type semiconductor well region A201, and a second conductive type Semiconductor contact region A202, second conductivity type semiconductor field limiting ring structure 203, second conductivity type semiconductor well region B204, second conductivity type semiconductor contact region B205, second conductivity type semiconductor well region C206, second conductivity type semiconductor well region D207, second conductivity type semiconductor buried layer A208, second conductivity type semiconductor region 209, VDMOS polysilicon gate 301, DMOS polysilicon gate 302, CMOS polysilicon gate 303, field oxide layer 401, oxide dielectric groove 402, buried oxide layer 403;

[0042] Among them, the first conductive type semiconductor substrate 101, the first conductive type semiconductor drift region A102, the first conductive type semiconductor contact A103, the second conductive type semiconductor well region A201, the second conductive type semiconductor contact region A202, the VDMOS polysilicon gate 301, and the field oxide layer 401 constitute the cell region II of the discrete device, and the second conductive type semiconductor field limiting ring structure 203 is the terminal region I of the discrete device; the first conductive type drift region B104, the first conductive type semiconductor contact B105, the first conductive type semiconductor well region A106, the first conductive type contact A107, the first conductive type well region B108, the first conductive type contact B109, the second conductive type well region B204, the second conductive type contact region B205, the second conductive type well region C206, the second conductive type well region D207, the DMOS polysilicon gate 302, the CMOS polysilicon gate 303, the oxidation dielectric groove 402, and the buried oxide layer 403 constitute the floating basin structure III;

[0043] Among them, the first conductive type semiconductor drift region A102 is located above the first conductive type semiconductor substrate 101, and the second conductive type semiconductor well region A201 is located above the first conductive type semiconductor drift region A102; the first conductive type semiconductor contact A103 and the second conductive type semiconductor contact A202 are located in the second conductive type semiconductor well region A201, and the second conductive type semiconductor 203 is located outside the device cell region to form a terminal structure; the VDMOS polysilicon gate 301 is located above the first conductive type semiconductor drift region A102,

[0044] The floating basin structure III is entirely located in the second conductivity type semiconductor well region A201, and is composed of:

[0045] The buried oxide layer 403 is located at the bottom of the second conductive type semiconductor well region B204, the oxidizing medium groove 402 is located between the edge of the floating basin structure and different devices inside the floating basin structure, the first conductive type semiconductor drift region B104 is located on the right side of the second conductive type semiconductor well region B204, the second conductive type semiconductor B205 is located in the second conductive type semiconductor well region B204, the first conductive type semiconductor well region A106 is located on the right side of the first conductive type semiconductor drift region B104, the first conductive type semiconductor contact B105 is located in the second conductive type semiconductor well region B204 and the first conductive type semiconductor well region A106, the polysilicon gate 302 covers the semiconductor surface adjacent to the second conductive type semiconductor well region B204 and the first conductive type semiconductor drift region B104, the first conductive type semiconductor drift region B104, the first conductive type semiconductor contact B105, the first conductive type semiconductor The body well region A106, the second conductive type semiconductor well region B204, the second conductive type semiconductor contact region B205 and the DMOS polysilicon gate 302 constitute a DMOS; the first conductive type semiconductor contact A107 is located in the second conductive type semiconductor well region C206, the polysilicon gate 303 is located on the silicon surface between the two first conductive type semiconductor contacts A107, the first conductive type semiconductor contact A107, the second conductive type semiconductor C206 and the CMOS polysilicon gate 303 constitute a CMOS tube; the second conductive type semiconductor well region D207 is located in the first conductive type semiconductor well region B108, the first conductive type semiconductor contact B109 is located on the surface of the second conductive type semiconductor well region D207, the first conductive type semiconductor well region B108, the first conductive type semiconductor contact B109 and the second conductive type semiconductor D207 constitute a BJT tube;

[0046] The devices in the floating basin structure described above are isolated laterally by the oxide dielectric trench 402 between the DMOS and the BJT, the DMOS and the CMOS, and the CMOS and the BJT.

[0047] Its basic working principle is as follows. Taking the first conductive type semiconductor material as N-type and the discrete device cell region structure as VDMOS as an example, when VDMOS is in forward withstand voltage, the first conductive type semiconductor substrate 101 is at a high potential, and the depletion region will expand in the first conductive type semiconductor drift region 102. When the floating basin structure is not used to isolate the drive circuit, the depletion region will expand into the drive circuit region, and the potential distribution brought by it will also affect the normal operation of the drive circuit. However, at this time, the oxide medium buried layer 403 has a high dielectric constant. The floating basin structure composed of the oxide medium groove 402 and the buried oxide layer 403 can achieve high withstand voltage inside and outside the basin. At the same time, the high-voltage side and the low-voltage side in the floating basin are also isolated by the oxide medium groove, which can also achieve high withstand voltage between the high-voltage side and the low-voltage side.

[0048] Example 2

[0049] like Figure 3 As shown, a discrete device multi-mode drive circuit integration technology of Example 2 is shown. The structure of this example is different from that of Example 1 in that the buried oxide layer 403 near the bottom of the floating basin is replaced with a second conductive type semiconductor buried layer 208 formed by injection.

[0050] Taking the case where the first conductive type semiconductor material is N-type and the discrete device cell region structure is VDMOS as an example, when the VDMOS withstands forward voltage, the first conductive type semiconductor drift region 102 will float to a high potential along with the first conductive type semiconductor substrate 101. At this time, the reverse PN junction formed by the second conductive type semiconductor buried layer 208 and the first conductive type semiconductor drift region 102 will bear the high voltage difference from the inside of the floating basin to the outside of the floating basin, thereby achieving the isolation of the floating basin. Laterally, the oxide dielectric groove is still used to isolate the high voltage area and the low voltage area circuit.

[0051] Example 3

[0052] like Figure 4 As shown, it is a cross-sectional view of a discrete device multi-mode drive circuit integration technology of Example 3. The structure of this example is different from that of Example 1 in that the oxide medium groove 402 at the edge and inside of the floating basin structure is replaced with a second conductive type semiconductor region 209, and the buried oxide layer 403 at the bottom of the floating basin is replaced with a second conductive type semiconductor buried layer A208 formed by injection.

[0053] Taking the case where the first conductive type semiconductor material is N-type and the discrete device cell region structure is VDMOS as an example, when the VDMOS withstands forward voltage, the first conductive type semiconductor drift region A102 will float to a high potential along with the first conductive type semiconductor substrate 101. At this time, the reverse PN junction formed by the second conductive type semiconductor buried layer A208 and the first conductive type semiconductor drift region A102 will bear the high voltage difference from inside the floating basin to outside the floating basin, thereby achieving isolation of the floating basin. Laterally, the PN junction formed by the P-type semiconductor region 209 and the N-type semiconductor region of the device integrated in the floating basin is used to withstand voltage, thereby achieving isolation of the device in the floating basin.

[0054] Example 4

[0055] like Figure 5 As shown, it is a cross-sectional view of a discrete device multi-mode drive circuit integration technology of Example 4. The structure of this example is different from that of Example 1 in that the edge of the second conductive type semiconductor well region A201 near the edge of the floating basin structure is terminated at the cut-off oxide medium groove 402, and the second conductive type semiconductor buried layer B210 is formed by groove bottom injection.

[0056] Taking the first conductive type semiconductor material as N type and the discrete device cell region structure as VDMOS as an example, when VDMOS withstands forward voltage, the first conductive type semiconductor drift region A102 will float to a high potential along with the first conductive type semiconductor substrate 101. At this time, the P-type buried layer B210 injected into the bottom of the groove and the first conductive type semiconductor drift region A102 will form a reverse PN junction. At this time, the depletion region of the PN junction will expand and connect to the depletion region of the PN junction formed by the P-type buried layer B210 on its right or left side and the first conductive type semiconductor drift region A102, thereby realizing the isolation of the floating basin and the first conductive type semiconductor drift region A102. Laterally, the oxide medium groove is still used to isolate the high-voltage area and the low-voltage area circuit.

[0057] Example 5

[0058] like Figure 6 As shown, it is a cross-sectional view of a discrete device multi-mode drive circuit integration technology of Example 5. The structure of this example is different from that of Example 3 in that the width of the oxidation medium groove 402 is enlarged, and the size formed by the injection at the bottom of the groove is increased so that the second conductive type semiconductor buried layer B210 is connected to form isolation under smaller devices such as CMOS and BJT.

[0059] The difference between its working principle and that of the third embodiment is that the second conductive type semiconductor buried layer B210 under the CMOS and BJT devices can be directly connected to achieve isolation, and the rest of the working principle is basically the same as that of the third embodiment.

[0060] Example 6

[0061] like Figure 7 , which is a top view of a discrete device multi-mode drive circuit integration technology of Example 6. The structure of this example is different from that of Example 1 in that the edge of the floating basin is changed from a dielectric groove 402 to a second conductive type semiconductor region 209.

[0062] The difference between its working principle and that of the first embodiment is that the PN junction formed by the second conductive type semi-conducting region and the N-type region of the device in the floating basin is used to realize junction isolation in the lateral direction.

[0063] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A discrete device multi-mode drive circuit integrated device, characterized in that: Including discrete device area and drive circuit area, The discrete device area consists of the cell area II and the terminal area I. The driving circuit area is entirely located in a floating basin structure III fabricated in a discrete device cell area; the floating basin structure III is entirely integrated in a second conductive type semiconductor well area A (201) of the discrete device, and includes a buried oxide layer (403) at the bottom, and an oxide medium groove (402) located between the floating basin structure boundary and the internal high and low voltage areas; a BJT, CMOS, or DMOS device is integrated in the floating basin to build a driving circuit.

2. The discrete device multi-mode drive circuit integration technology according to claim 1, characterized in that: AA' is a cross section of a discrete device including a floating basin structure; line AA' is a section line pointing from the second conductive type semiconductor field limiting ring (203) structure to the oxide dielectric groove (402) at the edge of the floating basin structure; The device cross section along the AA' section line includes: The discrete device cell region VDMOS includes a first conductive type semiconductor substrate (101), a first conductive type semiconductor drift region A (102), a first conductive type semiconductor contact A (103), a first conductive type semiconductor drift region B (104), a first conductive type semiconductor contact B (105), a first conductive type semiconductor well region A (106), a first conductive type semiconductor contact region A (107), a first conductive type semiconductor well region B (108), a first conductive type semiconductor contact region B (109), a second conductive type semiconductor well region A (201), and a second conductive type semiconductor contact region B (101). Contact region A (202), second conductive type semiconductor field limiting ring structure (203), second conductive type semiconductor well region B (204), second conductive type semiconductor contact region B (205), second conductive type semiconductor well region C (206), second conductive type semiconductor well region D (207), second conductive type semiconductor buried layer A (208), second conductive type semiconductor region (209), VDMOS polysilicon gate (301), DMOS polysilicon gate (302), CMOS polysilicon gate (303), field oxide layer (401), oxidation dielectric groove (402), buried oxide layer (403); The first conductive type semiconductor substrate (101), the first conductive type semiconductor drift region A (102), the first conductive type semiconductor contact A (103), the second conductive type semiconductor well region A (201), the second conductive type semiconductor contact region A (202), the VDMOS polysilicon gate (301), and the field oxide layer (401) constitute a cell region II of the discrete device, and the second conductive type semiconductor field limiting ring structure (203) is a terminal region I of the discrete device; the first conductive type drift region B (104), the first conductive type semiconductor contact B (105), a first conductive type semiconductor well region A (106), a first conductive type contact A (107), a first conductive type well region B (108), a first conductive type contact B (109), a second conductive type well region B (204), a second conductive type contact region B (205), a second conductive type well region C (206), a second conductive type well region D (207), a DMOS polysilicon gate (302), a CMOS polysilicon gate (303), an oxidizing dielectric groove (402), and a buried oxide layer (403) constitute a floating basin structure III; The first conductive type semiconductor drift region A (102) is located above the first conductive type semiconductor substrate (101), and the second conductive type semiconductor well region A (201) is located above the first conductive type semiconductor drift region A (102); the first conductive type semiconductor contact A (103) and the second conductive type semiconductor contact A (202) are located in the second conductive type semiconductor well region A (201), and the second conductive type semiconductor (203) is located outside the device cell region to form a terminal structure; the VDMOS polysilicon gate (301) is located above the first conductive type semiconductor drift region A (102), The floating basin structure III is entirely located in the second conductivity type semiconductor well region A (201), and is composed of: The buried oxide layer (403) is located at the bottom of the second conductive type semiconductor well region B (204), the oxidizing medium groove (402) is located between the edge of the floating basin structure and different devices inside the floating basin structure, the first conductive type semiconductor drift region B (104) is located on the right side of the second conductive type semiconductor well region B (204), the second conductive type semiconductor B (205) is located in the second conductive type semiconductor well region B (204), the first conductive type semiconductor well region A (106) is located on the right side of the first conductive type semiconductor drift region B (104), the first conductive type semiconductor contact B (105) is located in the second conductive type semiconductor well region B (204) and the first conductive type semiconductor well region A (106), the polysilicon gate (302) covers the semiconductor surface adjacent to the second conductive type semiconductor well region B (204) and the first conductive type semiconductor drift region B (104), the first conductive type semiconductor drift region B (104), the first conductive type semiconductor contact B (105), and the first conductive type semiconductor The well region A (106), the second conductive type semiconductor well region B (204), the second conductive type semiconductor contact region B (205) and the DMOS polysilicon gate (302) form a DMOS; the first conductive type semiconductor contact A (107) is located in the second conductive type semiconductor well region C (206), the polysilicon gate (303) is located on the silicon surface between the two first conductive type semiconductor contacts A (107), the first conductive type semiconductor contact A (107), the second conductive type semiconductor C (206) and the CMOS polysilicon gate (303) form a CMOS tube; the second conductive type semiconductor well region D (207) is located in the first conductive type semiconductor well region B (108), the first conductive type semiconductor contact B (109) is located on the surface of the second conductive type semiconductor well region D (207), the first conductive type semiconductor well region B (108), the first conductive type semiconductor contact B (109) and the second conductive type semiconductor D (207) form a BJT tube; In the above-mentioned devices located in the floating basin structure, DMOS and BJT, DMOS and CMOS, and CMOS and BJT are all isolated laterally by an oxide dielectric groove (402).

3. The discrete device multi-mode driving circuit integrated device according to claim 2, characterized in that: The buried oxide layer (403) at the bottom of the floating basin structure is replaced by a second conductive type semiconductor buried layer (208) formed by implantation.

4. The discrete device multi-mode driving circuit integrated device according to claim 3, characterized in that: The oxidizing medium groove (402) in the floating basin structure is replaced with a second conductive type semiconductor region (209).

5. The discrete device multi-mode driving circuit integrated device according to claim 2, characterized in that: The edge of the second conductive type semiconductor well region A (201) near the edge of the floating basin structure is terminated at the termination oxide dielectric groove (402), and a second conductive type semiconductor buried layer B (210) is formed by groove bottom implantation.

6. The discrete device multi-mode driving circuit integrated device according to claim 5, characterized in that: The width of the oxidation medium groove (402) and the size formed by the groove bottom injection are enlarged, so that the second conductive type semiconductor buried layer B (210) is directly connected below the CMOS and BJT devices to form isolation.

7. The discrete device multi-mode driving circuit integrated device according to claim 1, characterized in that: The oxidized dielectric groove (402) at the edge of the floating basin structure is replaced with a second conductive type semiconductor region (209).

8. The discrete device multi-mode driving circuit integrated device according to claim 2, characterized in that: The terminal region I is replaced by a field plate structure and a junction terminal extension structure.

9. The discrete device multi-mode driving circuit integrated device according to claim 2, characterized in that: The discrete device cell area II is replaced by VDMOS and IGBT.

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