Chip test circuit, chip test method and equipment

Abstract

The invention provides a chip test circuit, a chip test method and equipment, and the circuit comprises a test configuration module which is connected with a test power supply through a test line; the test configuration module comprises at least two fixed polarity test ends and at least one variable polarity test end; wherein the polarity of at least one fixed polarity test end is opposite to the polarity of the other fixed polarity test ends; and the test configuration module is used for enabling the fixed polarity test end and the variable polarity test end according to the number of the electrodes of the chip to be tested and the corresponding electrode polarities so as to execute an electrical test on the chip to be tested. According to the invention, when the two fixed polarity test ends are independently enabled, the test of the single crystal chip can be realized; when one of the fixed polarity test end and the variable polarity test end is enabled, the test of the single crystal chip can also be realized; and when all the fixed polarity test ends and the variable polarity test ends are enabled, the electrical test when at least two chips are integrated can be realized. Therefore, the coexistence test of single crystal and polycrystal test circuits is realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip testing circuit, a chip testing method and a chip testing device. Background Art

[0002] In the current mainstream LED (Light-Emitting Diode, LED for short) chip testing process, there are mainly two types of testers: single crystal testers and polycrystalline testers; for example, single crystal testers for large-grain LED chips, Mini LED chips, PN non-common-pole Micro LED chips, and polycrystalline testers for common-N-pole MIP (Micro Light-Emitting Diode in Package, packaged micro-light-emitting diodes, MIP for short) chips, non-common-pole MIP chips, etc. Since the two types of testers cannot be mixed with each other for testing, they can only be tested correctly by complex modifications or replacement with single crystal testers and polycrystalline testers to test single crystal chips and polycrystalline chips.

[0003] However, frequent modification or replacement of test machines will not only increase the testing cost, but also the process of modifying or replacing the test machine involves uncontrollable factors that may cause damage to the test machine equipment. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip testing circuit, a chip testing method and a device for solving the technical problems existing in the prior art.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a chip testing circuit, comprising:

[0006] Test the power supply;

[0007] A test configuration module connected to the test power supply via a test line;

[0008] The test configuration module includes at least two fixed polarity test terminals and at least one variable polarity test terminal; wherein the polarity of at least one fixed polarity test terminal is opposite to the polarity of the other fixed polarity test terminals;

[0009] The test configuration module is used to enable the fixed polarity test terminal and the variable polarity test terminal according to the number of electrodes of the chip to be tested and the corresponding electrode polarities so as to perform electrical testing on the chip to be tested.

[0010] Optionally, the test configuration module includes three fixed polarity test terminals and one variable polarity test terminal; wherein, the polarities of two of the three fixed polarity test terminals are the same, and the polarity of the variable polarity test terminal after being enabled is the same as the polarity of the two fixed polarity test terminals.

[0011] Optionally, the test configuration module further includes a polarity switching unit, a first shunt unit, and a second shunt unit;

[0012] The input end of the first shunt unit is connected to the positive electrode of the test power supply, and is used to divide the positive electrode line of the test power supply into at least two positive sub-lines. The input end of the second shunt unit is connected to the negative electrode of the test power supply, and is used to divide the negative electrode line of the test power supply into two negative sub-lines.

[0013] The first input end of the polarity switching unit is connected to the output end of the positive sub-circuit, the second input end is connected to the output end of the negative sub-circuit, the output end of the polarity switching unit is the variable polarity test end, and the output ends of the remaining positive sub-circuit and the negative sub-circuit are the fixed polarity test ends.

[0014] Optionally, the test configuration module further includes: a first switch unit, a second switch unit and a third shunt unit;

[0015] The input end of the third shunt unit is connected to the positive electrode of the test power supply, and is used to divide the positive electrode line of the test power supply into two positive sub-lines, the two positive sub-lines are respectively connected to the two input ends of the first switch unit, an output end of the first switch unit is connected to an input end of the second switch unit, and the remaining three output ends of the first switch unit are all connected to the input end of the first shunt unit, the other input end of the second switch unit is connected to an output end of the first shunt unit, and the output end of the second switch unit is one of the fixed polarity test ends.

[0016] Optionally, at least three test probes are further included, and one of the test probes is correspondingly connected to one of the fixed polarity test terminals or one of the variable polarity test terminals.

[0017] Optionally, a connection module is further included, the connection module includes at least three connectors, the connector is connected between the fixed polarity test end and the test probe, and the connector is connected between the variable polarity test end and the test probe.

[0018] The present application also provides a chip testing method, based on a chip testing circuit, the chip testing circuit includes a test power supply and a test configuration module connected thereto, the test configuration module includes three fixed polarity test terminals and one variable polarity test terminal, the polarity of a fixed polarity test terminal is opposite to the polarity of the other fixed polarity test terminals; the method includes the following steps:

[0019] Confirm the number of electrodes and the corresponding electrode polarity of the chip to be tested;

[0020] The fixed polarity test terminal and the variable polarity test terminal are enabled according to the number of electrodes of the chip under test and the corresponding electrode polarities to perform an electrical test on the chip under test.

[0021] Optionally, if the chip to be tested has two electrodes, and the polarity of one electrode is positive and the polarity of the other electrode is negative, performing an electrical test on the chip to be tested includes:

[0022] Enabling all fixed polarity test terminals and variable polarity test terminals in the test configuration module; wherein the polarity of the enabled variable polarity test terminal is the same as the polarity of the fixed polarity test terminal with a smaller polarity ratio among the fixed polarity test terminals;

[0023] The two electrodes of the chip to be tested are respectively connected to two fixed polarity test terminals with opposite polarities; or the two electrodes of the chip to be tested are respectively connected to one of the fixed polarity test terminals and the variable polarity test terminal.

[0024] Optionally, if the chip to be tested has four electrodes, and the polarity of one of the electrodes is opposite to the polarities of the other three electrodes; performing an electrical test on the chip to be tested includes:

[0025] Enabling all fixed polarity test terminals and one variable polarity test terminal in the test configuration module; wherein the polarity of the variable polarity test terminal after being enabled is the same as the polarity of the fixed polarity test terminal with a larger polarity ratio among the fixed polarity test terminals;

[0026] Connecting three electrodes with the same polarity in the chip to be tested to two fixed polarity test terminals and a variable polarity test terminal with the same polarity in the test configuration module respectively; and

[0027] Connect another electrode of the chip to be tested to another fixed polarity test terminal.

[0028] The present application also provides a chip testing device, comprising a chip testing circuit and a control circuit as described in any one of the above; wherein the chip testing circuit is electrically connected to the control circuit.

[0029] As described above, the present invention provides a chip testing circuit, a chip testing method and a device, which have the following beneficial effects: the present invention can realize the testing of single crystal chips by enabling two fixed polarity test terminals separately; can also realize the testing of single crystal chips by enabling one of the fixed polarity test terminals and the variable polarity test terminal; can realize the electrical testing of at least two chips when integrated by enabling all the fixed polarity test terminals and the variable polarity test terminals. Therefore, the present invention can realize the mutual switching between single crystal chip testing and polycrystalline chip testing by switching to enable the fixed polarity test terminal and the variable polarity test terminal, without the need to realize the testing of single crystal chips and polycrystalline chips by modifying the machine or replacing other types of test machines, perfectly solving the equipment cost and human uncontrollable factors caused by frequent modification or replacement of the test machine due to switching between single crystal chip testing and polycrystalline chip testing, reducing the risk of damage to the equipment, and realizing the coexistence test of single crystal chip test circuits and polycrystalline chip test circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a chip testing circuit provided by an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of a chip testing circuit provided in another embodiment of the present invention;

[0032] Figure 3 A schematic diagram of a chip testing circuit provided in yet another embodiment of the present invention;

[0033] Figure 4 A schematic diagram of a chip testing circuit provided in another embodiment of the present invention;

[0034] Figure 5 A schematic diagram of chip test circuit connections for testing a single crystal chip or a polycrystalline chip provided by an embodiment of the present invention;

[0035] Figure 6 A schematic diagram of a chip testing method according to an embodiment of the present invention;

[0036] Figure 7 A schematic diagram of a chip testing method according to an embodiment of the present invention.

[0037] Figure 8 A schematic diagram of a flow chart of a single crystal chip testing method provided in an embodiment of the present invention.

[0038] Fig. 9 The present invention is a flowchart of a method for testing a polycrystalline chip according to an embodiment of the present invention.

[0039] Reference numerals:

[0040] 100-P pole test line; 20-second series-parallel switch module; 30-first test connection line; 40-second test connection line; 50-P pole test area; 60-chip to be tested; 7-test probe; 8-N pole test area; 9-third test connection line; 10-fourth test connection line; 11-third series-parallel switch module; 12-series-parallel shunt module; 13-first series-parallel switch module; 14-current source; 15-N pole test line; 16- Connection module; 17-connector; 300-test power supply; 310-test configuration module; 320-test line; 311a-fixed polarity test terminal; 311b-fixed polarity test terminal; 311c-fixed polarity test terminal; 312-variable polarity test terminal; 313-polarity switching unit; 314-first shunt unit; 315-second shunt unit; 316-first switch unit; 317-second switch unit; 318-third shunt unit. DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0042] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0043] In one embodiment of the present invention, Figure 1 As shown, this embodiment provides a chip testing circuit, including:

[0044] Test power supply 300;

[0045] A test configuration module 310 connected to a test power supply 300 via a test line 320;

[0046] The test configuration module 310 includes at least two fixed polarity test terminals and at least one variable polarity test terminal 312; wherein the polarity of at least one fixed polarity test terminal is opposite to the polarity of the remaining fixed polarity test terminals; as an example, in Figure 1 In the embodiment, the polarity of the fixed polarity test terminal 311a is opposite to the polarity of the fixed polarity test terminal 311b.

[0047] The test configuration module 310 is used to enable the fixed polarity test terminal and the variable polarity test terminal 312 according to the number of electrodes of the chip under test 60 and the corresponding electrode polarity to perform electrical testing on the chip under test 60. As an example, the test configuration module 310 can enable the fixed polarity test terminal 311a, the fixed polarity test terminal 311b, and the variable polarity test terminal 312 according to the number of electrodes of the chip under test 60 and the corresponding electrode polarity to perform electrical testing on the chip under test 60.

[0048] It can be seen that in this embodiment, by enabling two fixed polarity test terminals separately, the test of single crystal chips can be realized; by enabling one of the fixed polarity test terminals and the variable polarity test terminal, the test of single crystal chips can also be realized; by enabling all fixed polarity test terminals and variable polarity test terminals, the electrical test of at least two chips when integrated can be realized. Therefore, in this embodiment, by switching to enable the fixed polarity test terminal and the variable polarity test terminal, the mutual switching between single crystal chip testing and polycrystalline chip testing can be realized, without the need to realize single crystal chip testing and polycrystalline chip testing by modifying the machine or replacing other types of test machines, which perfectly solves the equipment cost and human uncontrollable factors caused by frequent modification or replacement of the test machine due to switching between single crystal chip testing and polycrystalline chip testing, reduces the risk of damage to the equipment, and realizes the coexistence test of single crystal chip test circuits and polycrystalline chip test circuits. As an example, the test power supply in this embodiment can be a current source; the chip to be tested can be a polycrystalline chip or a single crystal chip.

[0049] According to the above records, in one embodiment, if Figure 2 As shown, the test configuration module 310 includes three fixed polarity test terminals and one variable polarity test terminal 312; wherein, the polarities of two of the three fixed polarity test terminals are the same, and the polarity of the variable polarity test terminal after being enabled is the same as the polarity of the two fixed polarity test terminals. Specifically, Figure 2 In the embodiment, the polarity of the fixed polarity test terminal 311a is opposite to the polarity of the fixed polarity test terminal 311b and the fixed polarity test terminal 311c, the polarity of the fixed polarity test terminal 311b and the fixed polarity test terminal 311c is the same, and the polarity of the variable polarity test terminal 312 after being enabled is the same as the polarity of the fixed polarity test terminal 311b and the fixed polarity test terminal 311c. It can be seen that the present embodiment provides three fixed polarity test terminals and one variable polarity test terminal through the test configuration module, and the polarity of two of the three fixed polarity test terminals is the same, and the polarity of the variable polarity test terminal after being enabled is the same as the polarity of the two fixed polarity test terminals, so that the polycrystalline chip can be tested. For example, a common N-pole electrical test of 3 N poles and 1 P can be performed on the polycrystalline chip, and a common P-pole electrical test of 1 N pole and 3 P can also be performed on the polycrystalline chip.

[0050] According to the above records, in one embodiment, if Figure 3 As shown, the test configuration module 310 also includes a polarity switching unit 313, a first shunt unit 314 and a second shunt unit 315; the input end of the first shunt unit 314 is connected to the positive electrode of the test power supply, and is used to divide the positive line of the test power supply 300 into at least two positive sub-lines, and the input end of the second shunt unit 315 is connected to the negative electrode of the test power supply 300, and is used to divide the negative line of the test power supply 300 into two negative sub-lines; the first input end of the polarity switching unit 313 is connected to the output end of a positive sub-line, and the second input end is connected to the output end of a negative sub-line, the output end of the polarity switching unit 313 is a variable polarity test end 312, and the output ends of the remaining positive sub-lines and negative sub-lines are fixed polarity test ends. Specifically, in Figure 3 In the embodiment, the polarity of the fixed polarity test terminal 311a is opposite to the polarity of the fixed polarity test terminal 311b and the fixed polarity test terminal 311c, the polarity of the fixed polarity test terminal 311b and the fixed polarity test terminal 311c are the same, and the polarity of the variable polarity test terminal 312 after being enabled is the same as the polarity of the fixed polarity test terminal 311b and the fixed polarity test terminal 311c. In this embodiment, the polarity switching unit 313 can be a single-pole double-throw switch. It can be seen that this embodiment can realize the electrical test of polycrystalline chips and single crystal chips. When this embodiment performs electrical test on polycrystalline chips and single crystal chips, the corresponding connection relationship is series connection.

[0051] According to the above records, in one embodiment, if Figure 4 As shown, the test configuration module 310 also includes: a first switch unit 316, a second switch unit 317 and a third shunt unit 318; the input end of the third shunt unit 318 is connected to the positive electrode of the test power supply 300, and is used to divide the positive electrode line of the test power supply 300 into two positive sub-lines, and the two positive sub-lines are respectively connected to the two input ends of the first switch unit 316, an output end of the first switch unit 316 is connected to an input end of the second switch unit 317, and the remaining three output ends of the first switch unit 316 are all connected to the input end of the first shunt unit 314, and the other input end of the second switch unit 317 is connected to an output end of the first shunt unit 314, and the output end of the second switch unit 317 is one of the fixed polarity test ends. Specifically, in Figure 4In the embodiment, the polarity of the fixed polarity test terminal 311a is opposite to the polarity of the fixed polarity test terminal 311b and the fixed polarity test terminal 311c, the polarity of the fixed polarity test terminal 311b and the fixed polarity test terminal 311c is the same, and the polarity of the variable polarity test terminal 312 after being enabled is the same as the polarity of the fixed polarity test terminal 311b and the fixed polarity test terminal 311c. In this embodiment, the first switch unit 316 can be a double-pole double-throw switch, and the second switch unit 317 can be a single-pole double-throw switch. It can be seen that the electrical test of the polycrystalline chip and the single crystal chip can be realized by the coordinated connection of the first switch unit 316, the second switch unit 317 and the third shunt unit 318 in this embodiment; that is, when the electrical test of the polycrystalline chip is performed in this embodiment, the connection relationship of the corresponding chip to be tested is parallel; and after the parallel connection, the chips constituting the polycrystalline chip do not interfere with each other, and at the same time, the parameters of each chip can be obtained separately in this embodiment.

[0052] According to the above records, in one embodiment, the chip test circuit further includes at least three test probes 7, and one test probe 7 is correspondingly connected to a fixed polarity test terminal or a variable polarity test terminal 312. According to the above records, in one embodiment, the chip test circuit further includes a connection module 16, and the connection module 16 includes at least three connectors 17, and the connector 17 is connected between the fixed polarity test terminal and the test probe 7, and the connector 17 is connected between the variable polarity test terminal 312 and the test probe 7.

[0053] According to the above records, in a specific embodiment, the embodiment provides a chip test circuit that can test single crystal chips and polycrystalline chips at the same time. The circuit connection of the chip test circuit is as follows: Figure 5 As shown. Specifically, the chip test circuit includes a current source 14 as a test power supply, and the current source 14 outputs current through a P-pole test line 100 and an N-pole test line 15; the chip test circuit also includes: a first series-parallel switch module 13, a second series-parallel switch module 20, a third series-parallel switch module 11, a series-parallel shunt module 12, a first test connection line 30, a second test connection line 40, a third test connection line 9, a fourth test connection line 10, a chip to be tested 60 and a test probe 7. Among them, the current source 14 is connected to other circuit components through the P-pole test line 100 and the N-pole test line 15 to form a test loop for a single crystal chip or a polycrystalline chip, and outputs a test current at the same time. In this embodiment, the first series-parallel switch module 13 can be a double-pole double-throw switch, and the second series-parallel switch module 20 and the third series-parallel switch module 11 can be single-pole double-throw switches.

[0054] Specifically, the positive and negative electrodes of the current source 14 are connected to the P-pole test line 100 and the N-pole test line 15, respectively, and the P-pole test line 100 is connected to the first series-parallel switch module 13. The first series-parallel switch module 13 is provided with 7 switch terminals numbered 0-6, wherein the switch terminal 0 in the first series-parallel switch module 13 is in contact with the P-pole test line 100, the switch terminal 1 in the first series-parallel switch module 13 can be in contact with the switch terminal 3 in the first series-parallel switch module 13 or the switch terminal 4 in the first series-parallel switch module 13, the switch terminal 2 in the first series-parallel switch module 13 can be in contact with the switch terminal 5 in the first series-parallel switch module 13 or the switch terminal 6 in the first series-parallel switch module 13, and the switch terminal 3 in the first series-parallel switch module 13 is also connected with the switch terminal 3 in the second series-parallel switch module 20. And the switch terminal 4 in the first series-parallel switch module 13, the switch terminal 5 in the first series-parallel switch module 13, and the switch terminal 6 in the first series-parallel switch module 13 are all connected in series with the switch terminal 1 in the series-parallel shunt module 12. The switch terminal 1 in the second series-parallel switch module 20 can be connected to the switch terminal 2 in the second series-parallel switch module 20 or the switch terminal 3 in the second series-parallel switch module 20, and the switch terminal 2 in the second series-parallel switch module 20 is also connected to the switch terminal 1 in the series-parallel shunt module 12. The switch terminal 1 in the third series-parallel switch module 11 can be connected to the switch terminal 3 in the third series-parallel switch module 11 or the switch terminal 2 in the third series-parallel switch module 11, and the switch terminal 2 in the third series-parallel switch module 11 is connected to the N-pole test line 15, and the switch terminal 3 in the third series-parallel switch module 11 is also connected to the switch terminal 1 in the series-parallel shunt module 12. The switch terminal 1 in the second series-parallel switch module 20 is connected to the connector 17 in the connection module 16 through the first test connection line 30, and after the first test connection line 30 is connected to the connector 17, it is connected to the test probe 7, and a polarity test terminal can be output; the switch terminal 1 in the series-parallel shunt module 12 is connected to the connector 17 in the connection module 16 through the second test connection line 40, and after the second test connection line 40 is connected to the connector 17, it is connected to the test probe 7, and a polarity test terminal can be output. Polarity test terminal; the switch point 1 in the third series-parallel switch module 11 is connected to the connector 17 in the connection module 16 through the fourth test connection line 10, and after the fourth test connection line 10 is connected to the connector 17, it is connected to the test probe 7, and a polarity test terminal can be output; the N-pole test line 15 is connected to the connector 17 in the connection module 16 through the third test connection line 9, and after the third test connection line 9 is connected to the connector 17, it is connected to the test probe 7, and a polarity test terminal can be output.

[0055] In this embodiment, the first series-parallel switch module 13 can constitute the polarity switching unit 313 described in one or some of the above embodiments, the second series-parallel switch module 20 can constitute the second switch unit 317 described in one or some of the above embodiments, the third series-parallel switch module 11 can constitute the first switch unit 316 described in one or some of the above embodiments, the series-parallel shunt module 12 can constitute the first shunt unit 314 described in one or some of the above embodiments, the shunt loop corresponding to the switch terminal 0 at the N-pole test line 15 can constitute the second shunt unit 315 described in one or some of the above embodiments, and the shunt loop corresponding to the switch terminal 0 at the P-pole test line 100 can constitute the third shunt unit 318 described in one or some of the above embodiments. The polarity test terminal output after the first test connection line 30 is connected to the test probe 7, the polarity test terminal output after the second test connection line 40 is connected to the test probe 7, the polarity test terminal output after the third test connection line 9 is connected to the test probe 7, and the polarity test terminal output after the fourth test connection line 10 is connected to the test probe 7 can constitute the fixed polarity test terminal and the variable polarity test terminal 312 described in one or some of the above-mentioned embodiments.

[0056] exist Figure 5 In, if Figure 5The chip to be tested 60 is a polycrystalline chip, such as an MIP chip; the P-pole test area 50 of the chip to be tested 60 is the positive test area corresponding to the MIP chip, and the N-pole test area 8 of the chip to be tested 60 is the negative test area corresponding to the MIP chip. At this time, the positive test area of ​​the MIP chip can be in contact with the switch terminal 1 in the second series-parallel switch module 20, the switch terminal 1 in the third series-parallel switch module 11, and the switch terminal 1 in the series-parallel shunt module 12; and the switch terminal 1 in the second series-parallel switch module 20 is connected to the switch terminal 2 in the second series-parallel switch module 20, the switch terminal 1 in the third series-parallel switch module 11 is connected to the switch terminal 3 in the third series-parallel switch module 11, and the N-pole test area of ​​the MIP chip is connected to the N-pole test line 15. At the same time, the P-pole test line 100 is connected to the switch terminal 0 in the first series-parallel switch module 13, the switch terminal 1 in the first series-parallel switch module 13 contacts the switch terminal 4 in the first series-parallel switch module 13, and the switch terminal 2 in the first series-parallel switch module 13 contacts the switch terminal 6 in the first series-parallel switch module 13. The switch terminal 1 in the second series-parallel switch module 20 contacts the switch terminal 2 in the second series-parallel switch module 20, and the switch terminal 1 in the third series-parallel switch module 11 contacts the switch terminal 3 in the third series-parallel switch module 11, so that the P-pole of the current source 14 is connected in parallel to the first test connection line 30, the second test connection line 40 and the fourth test connection line 10, and the N-pole test area 8 of the MIP chip is connected to the N-pole test line 15 through the third test connection line 9, and the entire circuit can form a MIP chip test loop.

[0057] exist Figure 5 In, if Figure 5If the chip to be tested is a single crystal chip, such as a Mini LED chip, then the P-pole test area 50 of the chip to be tested 60 is the positive electrode test area corresponding to the Mini LED chip, and the N-pole test area 8 of the chip to be tested 60 is the negative electrode test area corresponding to the Mini LED chip. At this time, the positive electrode test area of ​​the Mini LED chip can be in contact with the switch terminal 1 in the second series-parallel switch module 20, the switch terminal 1 in the third series-parallel switch module 11, and the switch terminal 1 in the series-parallel shunt module 12; and the switch terminal 1 in the second series-parallel switch module 20 is connected to the switch terminal 3 in the second series-parallel switch module 20, the switch terminal 1 in the third series-parallel switch module 11 is connected to the switch terminal 2 in the third series-parallel switch module 11, and the N-pole test area of ​​the Mini LED chip is connected to the N-pole test line 15. At the same time, the P-pole test line 100 is connected to the switch terminal 0 in the first series-parallel switch module 13, the switch terminal 1 in the first series-parallel switch module 13 contacts the switch terminal 3 in the first series-parallel switch module 13, and the switch terminal 2 in the first series-parallel switch module 13 contacts the switch terminal 5 in the first series-parallel switch module 13. The switch terminal 1 in the second series-parallel switch module 20 contacts the switch terminal 3 in the second series-parallel switch module 20, and the switch terminal 1 in the third series-parallel switch module 11 contacts the switch terminal 2 in the third series-parallel switch module 11, so that the P-pole of the current source 14 is connected to the first test connection line 30, the third test connection line 9 and the fourth test connection line 10, and the N-pole test area 8 of the Mini LED chip is connected to the N-pole test line 15 through the third test connection line 9, and the entire circuit can form a Mini LED chip test loop.

[0058] In summary, the present invention provides a chip test circuit, which can realize the test of single crystal chips by enabling two fixed polarity test terminals separately; can also realize the test of single crystal chips by enabling one of the fixed polarity test terminals and the variable polarity test terminal; can realize the electrical test of at least two chips when integrated by enabling all the fixed polarity test terminals and the variable polarity test terminals. Therefore, the chip test circuit can realize the mutual switching between single crystal chip test and polycrystalline chip test by switching the fixed polarity test terminal and the variable polarity test terminal, without the need to realize the single crystal chip test and polycrystalline chip test by modifying the machine or replacing other types of test machines, which perfectly solves the equipment cost and human uncontrollable factors caused by frequent modification or replacement of the test machine due to switching between single crystal chip test and polycrystalline chip test, reduces the risk of damage to the equipment, and realizes the coexistence test of single crystal chip test circuit and polycrystalline chip test circuit. In addition, the chip test circuit can also perfectly solve the compatibility testing difficulties of MIP chips (polycrystalline chips) and conventional LED chips (single crystal chips), avoiding the cost of purchasing new equipment and uncontrollable human factors caused by frequent changes or replacements of test machines due to switching between single crystal and polycrystalline tests, thereby reducing the risk of damage to the equipment.

[0059] In one embodiment of the present invention, Figure 6 As shown, the embodiment also provides a chip testing method, based on a chip testing circuit, the chip testing circuit includes a test power supply and a test configuration module connected thereto, the test configuration module includes three fixed polarity test terminals and one variable polarity test terminal, the polarity of a fixed polarity test terminal is opposite to the polarity of the other fixed polarity test terminals; the chip testing method includes the following steps:

[0060] Confirm the number of electrodes and the corresponding electrode polarity of the chip to be tested;

[0061] According to the number of electrodes of the chip to be tested and the corresponding electrode polarities, the fixed polarity test terminal and the variable polarity test terminal are enabled to perform electrical tests on the chip to be tested.

[0062] In this embodiment, reference may be made to the above-mentioned embodiment, and this embodiment will not be described in detail here.

[0063] According to the above records, if Figure 7As shown, in an exemplary embodiment, if the number of electrodes of the chip to be tested is two, and the polarity of one electrode is positive and the polarity of the other electrode is negative; then performing an electrical test on the chip to be tested includes: enabling all fixed polarity test terminals and variable polarity test terminals in the test configuration module; wherein the polarity of the enabled variable polarity test terminal is the same as the polarity of the fixed polarity test terminal with a smaller polarity ratio in the fixed polarity test terminal; connecting the two electrodes of the chip to be tested to two fixed polarity test terminals with opposite polarities respectively; or connecting the two electrodes of the chip to be tested to one of the fixed polarity test terminals and the variable polarity test terminal respectively. It can be seen that the chip to be tested in this embodiment can be a single crystal chip, such as a Mini LED chip. Wherein, when performing an electrical test on a single crystal chip in this embodiment, the circuit connections inside the chip test circuit and the circuit connections inside the test configuration module can refer to the description of the above embodiment, and this embodiment will not be repeated here.

[0064] According to the above records, if Figure 8 As shown, in another exemplary embodiment, if the number of electrodes of the chip to be tested is four, and the polarity of one of the electrodes is opposite to the polarity of the other three electrodes; then performing an electrical test on the chip to be tested includes: enabling all fixed polarity test terminals and one variable polarity test terminal in the test configuration module; wherein the polarity of the enabled variable polarity test terminal is the same as the polarity of the fixed polarity test terminal with a larger polarity proportion in the fixed polarity test terminal; connecting the three electrodes with the same polarity in the chip to be tested to the two fixed polarity test terminals and the variable polarity test terminal with the same polarity in the test configuration module respectively; and connecting another electrode of the chip to be tested to another fixed polarity test terminal. It can be seen that the chip to be tested in this embodiment can be a polycrystalline chip, such as a MIP chip. Wherein, when performing an electrical test on a polycrystalline chip in this embodiment, the circuit connections inside the chip test circuit and the circuit connections inside the test configuration module can refer to the description of the above embodiment, and this embodiment will not be repeated here.

[0065] As an example, in a specific embodiment, the embodiment is based on Figure 5 Taking the chip test loop shown in FIG. 1 as an example, a method for testing a MIP chip is provided. The implementation process of the method is shown in FIG. Fig. 9The process part of S10 in the above. Specifically, at this time, the positive electrode test area of ​​the MIP chip can be in contact with the switch terminal 1 in the second series-parallel switch module 20, the switch terminal 1 in the third series-parallel switch module 11, and the switch terminal 1 in the series-parallel shunt module 12; and the switch terminal 1 in the second series-parallel switch module 20 is connected to the switch terminal 2 in the second series-parallel switch module 20, the switch terminal 1 in the third series-parallel switch module 11 is connected to the switch terminal 3 in the third series-parallel switch module 11, and the N-pole test area of ​​the MIP chip is connected to the N-pole test line 15. At the same time, the P-pole test line 100 is connected to the switch terminal 0 in the first series-parallel switch module 13, the switch terminal 1 in the first series-parallel switch module 13 is in contact with the switch terminal 4 in the first series-parallel switch module 13, and the switch terminal 2 in the first series-parallel switch module 13 is in contact with the switch terminal 6 in the first series-parallel switch module 13. The switch terminal 1 in the second series-parallel switch module 20 contacts the switch terminal 2 in the second series-parallel switch module 20, and the switch terminal 1 in the third series-parallel switch module 11 contacts the switch terminal 3 in the third series-parallel switch module 11, so that the P pole of the current source 14 is connected in parallel to the first test connection line 30, the second test connection line 40 and the fourth test connection line 10, and the N pole test area 8 of the MIP chip is then connected to the N pole test line 15 through the third test connection line 9, and the entire circuit can form a MIP chip test loop. It can be seen that this embodiment can realize the common N pole characteristic test of the MIP chip through the above-mentioned chip test loop, that is, realize the one N pole three P pole characteristic test. It is equivalent to that this embodiment can design the switch terminal connection in the series-parallel switch module and the switch terminal connection in the series-parallel shunt module through the above-mentioned chip test loop, so as to realize the test of the conventional MIP chip.

[0066] According to the above records, in another specific embodiment, the embodiment is Figure 5 Taking the chip test circuit shown in FIG. 1 as an example, a method for testing a Mini LED chip is provided. The implementation process of the method is as follows: Fig. 9The process part of S20 in the process. Specifically, at this time, the positive electrode test area of ​​the Mini LED chip can be in contact with the switch terminal 1 in the second series-parallel switch module 20, the switch terminal 1 in the third series-parallel switch module 11, and the switch terminal 1 in the series-parallel shunt module 12; and the switch terminal 1 in the second series-parallel switch module 20 is connected to the switch terminal 3 in the second series-parallel switch module 20, the switch terminal 1 in the third series-parallel switch module 11 is connected to the switch terminal 2 in the third series-parallel switch module 11, and the N-pole test area of ​​the Mini LED chip is connected to the N-pole test line 15. At the same time, the P-pole test line 100 is connected to the switch terminal 0 in the first series-parallel switch module 13, the switch terminal 1 in the first series-parallel switch module 13 is in contact with the switch terminal 3 in the first series-parallel switch module 13, and the switch terminal 2 in the first series-parallel switch module 13 is in contact with the switch terminal 5 in the first series-parallel switch module 13. The switch terminal 1 in the second series-parallel switch module 20 contacts the switch terminal 3 in the second series-parallel switch module 20, and the switch terminal 1 in the third series-parallel switch module 11 contacts the switch terminal 2 in the third series-parallel switch module 11, so that the P pole of the current source 14 is connected to the first test connection line 30, the third test connection line 9 and the fourth test connection line 10, and the N pole test area 8 of the MiniLED chip is connected to the N pole test line 15 through the third test connection line 9, and the entire circuit can form a MiniLED chip test loop. It can be seen that this embodiment can realize conventional LED chip testing through the above-mentioned chip test loop, that is, this embodiment can design and connect the switch terminals in the series-parallel switch module and the switch terminals in the series-parallel shunt module through the above-mentioned chip test loop, so as to realize the test of conventional LED chips.

[0067] Therefore, the present invention provides a chip testing method, which can realize the testing of single crystal chips by enabling two fixed polarity test terminals separately; can also realize the testing of single crystal chips by enabling one of the fixed polarity test terminals and the variable polarity test terminal; can realize the electrical testing of at least two chips when integrated by enabling all the fixed polarity test terminals and the variable polarity test terminals. Therefore, the chip testing circuit can realize the mutual switching between single crystal chip testing and polycrystalline chip testing by switching to enable the fixed polarity test terminal and the variable polarity test terminal, without the need to realize the testing of single crystal chips and polycrystalline chips by modifying the machine or replacing other types of test machines, which perfectly solves the equipment cost and human uncontrollable factors caused by frequent modification or replacement of the test machine due to switching between single crystal chip testing and polycrystalline chip testing, reduces the risk of damage to the equipment, and realizes the coexistence test of single crystal chip test circuit and polycrystalline chip test circuit. In addition, the chip test circuit can also perfectly solve the compatibility testing difficulties of MIP chips (polycrystalline chips) and conventional LED chips (single crystal chips), avoiding the cost of purchasing new equipment and uncontrollable human factors caused by frequent changes or replacements of test machines due to switching between single crystal and polycrystalline tests, thereby reducing the risk of damage to the equipment.

[0068] In another exemplary embodiment of the present application, the embodiment further provides a chip testing device, comprising a chip testing circuit and a control circuit as described in any of the above embodiments; wherein the chip testing circuit is electrically connected to the control circuit. As an example, the chip testing device provided by this embodiment may include Figures 1 to 5 The chip test circuit described in the corresponding embodiment. It should be noted that the chip test device provided in the above embodiment and the chip test circuit provided in the above embodiment belong to the same concept, wherein the specific circuit connection method of each module of the chip test circuit has been described in detail in the above embodiment and will not be repeated here. In actual applications, the chip test device provided in the above embodiment can distribute the above functions to different functional modules as needed, that is, divide the internal structure of the chip test device into different functional modules to complete all or part of the functions described above, and this is not limited here.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

[0070] The structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0071] It should be understood that, although the terms first, second, third, etc. may be used to describe preset ranges, etc. in the embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are only used to distinguish preset ranges from each other. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

Claims

1. A chip testing circuit, characterized in that: The test circuit comprises: Test the power supply; A test configuration module connected to the test power supply via a test line; The test configuration module includes at least two fixed polarity test terminals and at least one variable polarity test terminal; wherein the polarity of at least one fixed polarity test terminal is opposite to the polarity of the other fixed polarity test terminals; The test configuration module is used to enable the fixed polarity test terminal and the variable polarity test terminal according to the number of electrodes of the chip to be tested and the corresponding electrode polarities so as to perform electrical testing on the chip to be tested.

2. The chip testing circuit according to claim 1, characterized in that: The test configuration module includes three fixed polarity test terminals and one variable polarity test terminal; wherein, two of the three fixed polarity test terminals have the same polarity, and the polarity of the variable polarity test terminal after being enabled is the same as the polarity of the two fixed polarity test terminals.

3. The chip testing circuit according to claim 2, characterized in that: The test configuration module also includes a polarity switching unit, a first shunt unit, and a second shunt unit; The input end of the first shunt unit is connected to the positive electrode of the test power supply, and is used to divide the positive electrode line of the test power supply into at least two positive sub-lines. The input end of the second shunt unit is connected to the negative electrode of the test power supply, and is used to divide the negative electrode line of the test power supply into two negative sub-lines. The first input end of the polarity switching unit is connected to the output end of the positive sub-circuit, the second input end is connected to the output end of the negative sub-circuit, the output end of the polarity switching unit is the variable polarity test end, and the output ends of the remaining positive sub-circuit and the negative sub-circuit are the fixed polarity test ends.

4. The chip testing circuit according to claim 3, characterized in that: The test configuration module further includes: a first switch unit, a second switch unit and a third shunt unit; The input end of the third shunt unit is connected to the positive electrode of the test power supply, and is used to divide the positive electrode line of the test power supply into two positive sub-lines, the two positive sub-lines are respectively connected to the two input ends of the first switch unit, an output end of the first switch unit is connected to an input end of the second switch unit, and the remaining three output ends of the first switch unit are all connected to the input end of the first shunt unit, the other input end of the second switch unit is connected to an output end of the first shunt unit, and the output end of the second switch unit is one of the fixed polarity test ends.

5. The chip testing circuit according to claim 1, characterized in that: It also includes at least three test probes, one of which is correspondingly connected to one of the fixed polarity test terminals or one of the variable polarity test terminals.

6. The chip testing circuit according to claim 5, characterized in that: It also includes a connection module, which includes at least three connectors. The connector is connected between the fixed polarity test end and the test probe, and the connector is connected between the variable polarity test end and the test probe.

7. A chip testing method, characterized in that: Based on a chip test circuit, the chip test circuit includes a test power supply and a test configuration module connected thereto, the test configuration module includes three fixed polarity test terminals and one variable polarity test terminal, and the polarity of a fixed polarity test terminal is opposite to the polarity of the other fixed polarity test terminals; the method includes the following steps: Confirm the number of electrodes and the corresponding electrode polarity of the chip to be tested; The fixed polarity test terminal and the variable polarity test terminal are enabled according to the number of electrodes of the chip under test and the corresponding electrode polarities to perform an electrical test on the chip under test.

8. The chip testing method according to claim 7, characterized in that: If the chip to be tested has two electrodes, and the polarity of one electrode is positive and the polarity of the other electrode is negative, then performing an electrical test on the chip to be tested includes: Enabling all fixed polarity test terminals and variable polarity test terminals in the test configuration module; wherein the polarity of the enabled variable polarity test terminal is the same as the polarity of the fixed polarity test terminal with a smaller polarity ratio among the fixed polarity test terminals; The two electrodes of the chip to be tested are respectively connected to two fixed polarity test terminals with opposite polarities; or the two electrodes of the chip to be tested are respectively connected to one of the fixed polarity test terminals and the variable polarity test terminal.

9. The chip testing method according to claim 7, characterized in that: If the chip to be tested has four electrodes, and the polarity of one of the electrodes is opposite to the polarities of the other three electrodes, performing an electrical test on the chip to be tested includes: Enabling all fixed polarity test terminals and one variable polarity test terminal in the test configuration module; wherein the polarity of the variable polarity test terminal after being enabled is the same as the polarity of the fixed polarity test terminal with a larger polarity ratio among the fixed polarity test terminals; Connecting three electrodes with the same polarity in the chip to be tested to two fixed polarity test terminals and a variable polarity test terminal with the same polarity in the test configuration module respectively; and Connect another electrode of the chip to be tested to another fixed polarity test terminal.

10. A chip testing device, characterized in that: The invention comprises a chip testing circuit and a control circuit as claimed in any one of claims 1 to 6; wherein the chip testing circuit is electrically connected to the control circuit.

Images