Integrated circuit chip test system, method, equipment and medium

Abstract

The invention discloses an integrated circuit chip test system, method and device and a medium, mainly relates to the technical field of integrated circuit chips, and aims to solve the problems that according to an existing integrated circuit chip fault detection scheme, only current and other single-link tests are concerned, qualification is determined only through preliminary tests, and the test efficiency is low. And potential risks of the chip in operation cannot be found. Comprising a set obtaining module used for carrying out clustering processing on a data set to obtain a plurality of clustering sets; the probability determination module is used for determining the actual fault probability corresponding to the current clustering set; the data adding module is used for determining a corresponding data set based on the chip model of the integrated circuit chip to be tested and a specific actual measurement link; adding the measured data of the integrated circuit chip to be tested into the data set; and the anomaly detection module is used for carrying out clustering processing on the current data set so as to obtain a corresponding actual fault probability.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit chips, and in particular to an integrated circuit chip testing system, method, equipment and medium. Background Art

[0002] ‌An integrated circuit chip is a miniature electronic device that contains a variety of electronic components. It is a miniature electronic device that integrates a large number of microelectronic components (such as transistors, resistors, capacitors, etc.) through a specific process and encapsulates them on a small piece or several small pieces of semiconductor wafers or dielectric substrates. Integrated circuit chips have a wide range of applications, from simple signal amplification or timing functions to complex computing task processing. Especially in electronic devices that require advanced computing, such as computers and smart phones, integrated circuit chips play an indispensable role. ‌

[0003] The existing integrated circuit chip fault detection scheme involves the following: actual testing, which mainly divides the test into several links, collects the test results corresponding to each link (for example, in the current test link, the test current value), and determines whether the measured data meets the preset qualified range. When it is within the preset qualified range, the preliminary test is completed and the integrated circuit chip is determined to be qualified.

[0004] However, existing solutions for fault detection of integrated circuit chips only focus on testing a single link such as current, which may ignore other key parameters such as voltage, timing, and function, and cannot fully evaluate chip performance. In addition, only preliminary testing to determine whether the chip is qualified may fail to discover potential problems in chip operation. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present application provides an integrated circuit chip testing system, method, device and medium to solve the existing solutions related to fault detection of integrated circuit chips: only focusing on the test of a single link such as current, while ignoring other key parameters; in addition, only preliminary testing is performed to determine whether the chip is qualified, resulting in the problem of being unable to discover potential risks of the chip during operation.

[0006] In a first aspect, the present application provides an integrated circuit chip testing system, the system comprising: The sample acquisition module is used to obtain the chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; the set acquisition module is used to take the sample data belonging to the same chip model and the same actual measurement link as a data set, and then cluster the data set to obtain a number of cluster sets; the feedback acquisition module is used to obtain the actual fault feedback result corresponding to the sample data; wherein the actual fault feedback result is divided into: fault existence and no fault; the probability determination module is used to determine the actual fault probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the component of sample data with faults; the data addition module is used to obtain the chip model of the integrated circuit chip to be tested, the specific actual measurement link and the actual measurement data corresponding to each actual measurement link; based on the chip model of the integrated circuit chip to be tested and the specific actual measurement link, determine the corresponding data set; add the actual measurement data of the integrated circuit chip to be tested to the data set; the abnormality detection module is used to cluster the current data set to determine the cluster set corresponding to the actual measurement data of the current integrated circuit chip; and then obtain the corresponding actual fault probability; when the actual fault probability is greater than the preset probability threshold, generate an abnormal alarm to the preset maintenance terminal.

[0007] The integrated circuit chip test system provided by the embodiment of the present application organizes the sample data of the same chip model and measured link into a data set through the set acquisition module, and performs clustering processing; through the probability determination module, the actual fault probability corresponding to each cluster set is calculated and determined (the fault probability is determined because the chip data of the same type and measured link are more comparable, which improves the accuracy of fault detection), which will help to determine which cluster the new data point (such as the data of the chip to be tested) belongs to; and then the actual fault probability of the current chip data can be predicted according to the actual fault probability of the specific cluster. In addition, it can process data of different chip models and measured links. For a new chip to be tested, it only needs to obtain its model and measured data through the data addition module, and it can be included in the corresponding data set for analysis. The above implementation process involves the measured data corresponding to each measured link, which reduces the risk of only focusing on the test of a single link such as current, and may ignore other key parameters such as voltage, timing, function, etc., and cannot fully evaluate the chip performance. In addition, the present application uses an aggregation algorithm to perform correlation analysis on the measured data corresponding to each measured link, reducing the risk that only preliminary tests are used to determine that it is qualified, and the risk of not being able to discover potential problems in the operation of the chip may not be discovered.

[0008] In one implementation of the present application, the system also includes a data set correction module; after generating an abnormal alarm to a preset maintenance terminal, the module is used to obtain actual fault feedback results of the newly added integrated circuit chip data to be tested in the data set through the preset maintenance terminal.

[0009] The integrated circuit chip testing system provided in the embodiment of the present application obtains the actual fault feedback results of the newly added integrated circuit chip data to be tested in the data set through the data set correction module. This module can effectively expand the data set, and the number of data sets is continuously increased, providing more reliable data support for the fault prediction and diagnosis of integrated circuit chips.

[0010] In one implementation of the present application, the sample acquisition module includes a first acquisition unit and a second acquisition unit; the first acquisition unit is used to obtain the chip model of the integrated circuit chip and the measurement link of the integrated circuit chip through a preset data upload interface; the second acquisition unit is used to obtain the measured data corresponding to each measurement link according to the measurement terminal corresponding to each measurement link.

[0011] In one implementation of the present application, the set acquisition module includes a clustering unit, which is used to obtain the type K of actual faults; randomly select M sample data from the data set as initial cluster centers; wherein M K; use K-Means clustering algorithm to obtain M clustering sets.

[0012] In one implementation of the present application, the probability determination module includes a calculation unit, which is used to calculate the probability of the following: , calculate and obtain the actual failure probability corresponding to the current cluster set.

[0013] In a second aspect, the present application provides an integrated circuit chip testing method, the method comprising: Obtain the chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; take the sample data belonging to the same chip model and the same actual measurement link as a data set, and then cluster the data set to obtain several cluster sets; obtain the actual fault feedback result corresponding to the sample data; wherein the actual fault feedback result is divided into: fault existence and no fault; based on the total amount of sample data in the cluster set and the component of sample data with faults, determine the actual fault probability corresponding to the current cluster set; obtain the chip model of the integrated circuit chip to be tested, the specific actual measurement link and the actual measurement data corresponding to each actual measurement link; based on the chip model of the integrated circuit chip to be tested and the specific actual measurement link, determine the corresponding data set; add the actual measurement data of the integrated circuit chip to be tested to the data set; cluster the current data set to determine the cluster set corresponding to the actual measurement data of the current integrated circuit chip; and then obtain the corresponding actual fault probability; when the actual fault probability is greater than the preset probability threshold, generate an abnormal alarm to the preset maintenance terminal.

[0014] In one implementation of the present application, the chip model of the integrated circuit chip, the measurement link of the integrated circuit chip, and the measured data corresponding to each measurement link are obtained as sample data, specifically including: The chip model of the integrated circuit chip and the actual measurement link of the integrated circuit chip are obtained through the preset data upload interface; and the actual measurement data corresponding to each actual measurement link are obtained according to the actual measurement terminal corresponding to each actual measurement link.

[0015] In one implementation of the present application, clustering is performed on the data set to obtain several cluster sets, specifically including: Get the actual fault type K; randomly select M sample data from the data set as the initial cluster center; where M K; use K-Means clustering algorithm to obtain M clustering sets.

[0016] In a third aspect, the present application provides an integrated circuit chip testing device, the device comprising: processor; and a memory storing executable codes, which, when executed, enable the processor to execute any one of the above-mentioned integrated circuit chip testing methods.

[0017] In a fourth aspect, the present application provides a non-volatile computer storage medium having computer instructions stored thereon, which when executed implement an integrated circuit chip testing method as described above.

[0018] Those skilled in the art can understand that the present application has at least the following beneficial effects: The present application discloses an integrated circuit chip testing system, method, device and medium. Through a collection acquisition module, sample data of the same chip model and actual measurement link are organized into a data set, and then the data set is clustered to obtain several cluster sets; through a probability determination module, the actual fault probability corresponding to each cluster set is calculated and determined (the determination of the fault probability is performed because the chip data of the same type and actual measurement link are more comparable, which improves the accuracy of fault detection), which will help to determine which cluster the new data point (such as the data of the chip to be tested) belongs to; and then the actual fault probability of the current chip data can be predicted based on the actual fault probability of the specific cluster. In addition, it can process data of different chip models and actual measurement links. For a new chip to be tested, it only needs to obtain its model and actual measurement data through a data addition module, and it can be included in the corresponding data set for analysis. The above implementation process involves the actual measurement data corresponding to each actual measurement link, not only focusing on the test of a single link such as current, but also solving the risk of ignoring other key parameters such as voltage, timing, function, etc., and failing to fully evaluate the chip performance. In addition, the present application uses an aggregation algorithm to perform correlation analysis on the measured data corresponding to each measured link, thereby reducing the risk of failing to discover potential problems in the operation of the chip by only determining its qualification through preliminary testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Some embodiments of the present disclosure are described below with reference to the accompanying drawings, in which: Figure 1 It is a schematic diagram of the internal structure of an integrated circuit chip testing system provided in an embodiment of the present application.

[0020] Figure 2 It is a flow chart of an integrated circuit chip testing method provided in an embodiment of the present application.

[0021] Figure 3 It is a schematic diagram of the internal structure of an integrated circuit chip testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] It should be understood by those skilled in the art that the embodiments described below are only preferred embodiments of the present disclosure, and do not mean that the present disclosure can only be implemented through the preferred embodiments. The preferred embodiments are only used to explain the technical principles of the present disclosure, and are not used to limit the protection scope of the present disclosure. Based on the preferred embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work should still fall within the protection scope of the present disclosure.

[0023] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0024] The technical solution proposed in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0025] This application Figure 1 An integrated circuit chip testing system is provided in an embodiment of the present application. Figure 1 As shown, the system provided in the embodiment of the present application mainly includes: The sample acquisition module 110 is used to acquire the chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data.

[0026] It should be noted that the actual measurement link may be a voltage actual measurement link, a timing actual measurement link, a function actual measurement link, etc. The sample acquisition module 110 is software or hardware capable of acquiring data.

[0027] Those skilled in the art can understand that, in the present application, by collecting data of different chip models and different actual measurement links, a data set containing test data of multiple links can be constructed.

[0028] As an example, the sample acquisition module 110 includes a first acquisition unit and a second acquisition unit; the first acquisition unit is used to obtain the chip model of the integrated circuit chip and the actual measurement link of the integrated circuit chip through a preset data upload interface; the second acquisition unit is used to obtain the actual measurement data corresponding to each actual measurement link according to the actual measurement terminal corresponding to each actual measurement link.

[0029] The set acquisition module 120 is used to take the sample data belonging to the same chip model and the same actual measurement link as a data set, and then perform clustering processing on the data set to obtain a plurality of cluster sets.

[0030] It should be noted that the set acquisition module 120 is connected to the sample acquisition module 110 and can perform clustering processing on the data obtained by the sample acquisition module 110 .

[0031] Among them, the clustering processing process can be: implemented through an existing algorithm that can automatically cluster data, for example, through the clustering unit embedded in the set acquisition module 120, to obtain the actual fault type K; randomly select M sample data from the data set as the initial clustering center; where M>K; use the K-Means clustering algorithm to obtain M clustering sets.

[0032] It should be noted that, since the data presentation methods of different specific actual faults are different in this application, in order to make the clustering accurate, M is at least K+1; K means that the specific actual faults are classified into the same category (so there are K categories), and 1 means that the data without faults are classified into one category (1 category).

[0033] The feedback acquisition module 130 is used to obtain the actual fault feedback result corresponding to the sample data.

[0034] It should be noted that the feedback acquisition module 130 is a device that can obtain the actual fault feedback results of the above data from the outside. The feedback acquisition module 130 can be a server, including an upload interface, through which the actual fault feedback results returned by the technician are obtained. Among them, the actual fault feedback results are divided into: fault exists and no fault.

[0035] The probability determination module 140 is used to determine the actual fault probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the proportion of sample data with faults.

[0036] As an example, the probability determination module 140 includes a calculation unit for determining the probability of: , calculate and obtain the actual failure probability corresponding to the current cluster set.

[0037] Those skilled in the art will appreciate that the probability determination module 140 can obtain a more reliable fault probability estimate by considering the total number of samples in the cluster set and the sample component with faults.

[0038] The data adding module 150 is used to obtain the chip model of the integrated circuit chip to be tested, the specific measurement links and the measured data corresponding to each measurement link; determine the corresponding data set based on the chip model of the integrated circuit chip to be tested and the specific measurement links; and add the measured data of the integrated circuit chip to be tested to the data set.

[0039] It should be noted that the present application matches the model of the chip to be tested and the actual measurement link to find the corresponding data set through the data adding module 150. Comparing and analyzing the data of the chip to be tested with the existing sample data helps to improve the accuracy of fault prediction.

[0040] The anomaly detection module 160 is used to perform clustering processing on the current data set to determine the cluster set corresponding to the measured data of the current integrated circuit chip; and then obtain the corresponding actual fault probability; when the actual fault probability is greater than the preset probability threshold, an abnormal alarm is generated to the preset maintenance terminal.

[0041] It should be noted that the present application performs clustering processing through the abnormality detection module 160 to find the cluster set to which the measured data of the chip under test belongs. The data of the chip under test is matched with the existing cluster set, so that its failure risk (actual failure probability) can be more accurately assessed.

[0042] In addition, the present application can increase the data capacity through the subsequent addition of actual fault feedback results, thereby updating and optimizing the data set, so that the clustering algorithm can continuously learn and adapt to new data, thereby improving the accuracy of clustering.

[0043] The specific implementation process can be: Through the data set correction module included in the system; after generating an abnormal alarm to a preset maintenance terminal, the actual fault feedback result of the newly added integrated circuit chip data to be tested in the data set is obtained through the preset maintenance terminal.

[0044] In addition, the embodiment provides an integrated circuit chip testing method, such as Figure 2 As shown, the method provided in the embodiment of the present application mainly includes the following steps: Step 210: Obtain the chip model of the integrated circuit chip, the actual measurement links of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data.

[0045] This step specifically includes: The chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link are obtained as sample data, specifically including: Obtain the chip model of the integrated circuit chip and the actual measurement link of the integrated circuit chip through the preset data upload interface; According to the measuring terminals corresponding to each measuring link, the measuring data corresponding to each measuring link is obtained.

[0046] Step 220: Take the sample data belonging to the same chip model and the same measurement link as a data set, and then perform clustering processing on the data set to obtain a plurality of cluster sets.

[0047] The data set is clustered to obtain several cluster sets, which can be: Get the actual fault type K; randomly select M sample data from the data set as the initial cluster center; where M K; use K-Means clustering algorithm to obtain M clustering sets.

[0048] Step 230: Obtain actual fault feedback results corresponding to the sample data; wherein the actual fault feedback results are divided into: fault presence and no fault.

[0049] Step 240: Determine the actual fault probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the proportion of sample data with faults.

[0050] Step 250, obtain the chip model of the integrated circuit chip to be tested, the specific measurement steps and the measured data corresponding to each measurement step; determine the corresponding data set based on the chip model of the integrated circuit chip to be tested and the specific measurement steps; add the measured data of the integrated circuit chip to be tested to the data set.

[0051] Step 260: cluster the current data set to determine the cluster set corresponding to the measured data of the current integrated circuit chip; then obtain the corresponding actual fault probability; when the actual fault probability is greater than a preset probability threshold, generate an abnormal alarm to a preset maintenance terminal.

[0052] The above is a method embodiment of the present application. Based on the same inventive concept, the present application embodiment also provides an integrated circuit chip testing device. Figure 3 As shown, the device includes: a processor; and a memory on which executable codes are stored. When the executable codes are executed, the processor executes an integrated circuit chip testing method as described in the above embodiment.

[0053] Specifically, the server obtains the chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; takes the sample data belonging to the same chip model and the same actual measurement link as a data set, and then clusters the data set to obtain several cluster sets; obtains the actual fault feedback result corresponding to the sample data; wherein the actual fault feedback result is divided into: fault existence and no fault; based on the total amount of sample data in the cluster set and the component of sample data with faults, determines the actual fault probability corresponding to the current cluster set; obtains the chip model of the integrated circuit chip to be tested, the specific actual measurement link and the actual measurement data corresponding to each actual measurement link; determines the corresponding data set based on the chip model of the integrated circuit chip to be tested and the specific actual measurement link; adds the actual measurement data of the integrated circuit chip to be tested to the data set; clusters the current data set to determine the cluster set corresponding to the actual measurement data of the current integrated circuit chip; and then obtains the corresponding actual fault probability; when the actual fault probability is greater than the preset probability threshold, generates an abnormal alarm to the preset maintenance terminal.

[0054] In addition, an embodiment of the present application further provides a non-volatile computer storage medium on which executable instructions are stored. When the executable instructions are executed, an integrated circuit chip testing method as described above is implemented.

[0055] So far, the technical solutions of the present disclosure have been described in combination with the above multiple embodiments, but it is easy for those skilled in the art to understand that the protection scope of the present disclosure is not limited to these specific embodiments. Without departing from the technical principles of the present disclosure, those skilled in the art can split and combine the technical solutions in the above-mentioned various embodiments, and can also make equivalent changes or replacements to the relevant technical features. Any changes, equivalent replacements, improvements, etc. made within the technical concept and / or technical principle of the present disclosure will fall within the protection scope of the present disclosure.

Claims

1. An integrated circuit chip testing system, characterized in that: The system comprises: A sample acquisition module is used to acquire the chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; A set acquisition module is used to take the sample data belonging to the same chip model and the same actual measurement link as a data set, and then perform clustering processing on the data set to obtain several cluster sets; The feedback acquisition module is used to obtain the actual fault feedback results corresponding to the sample data; wherein the actual fault feedback results are divided into: fault existence and no fault; A probability determination module, used to determine the actual fault probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the proportion of sample data with faults; The data adding module is used to obtain the chip model of the integrated circuit chip to be tested, the specific measurement links and the measured data corresponding to each measurement link; based on the chip model of the integrated circuit chip to be tested and the specific measurement links, determine the corresponding data set; add the measured data of the integrated circuit chip to be tested to the data set; The anomaly detection module is used to perform clustering processing on the current data set to determine the cluster set corresponding to the measured data of the current integrated circuit chip; and then obtain the corresponding actual fault probability; when the actual fault probability is greater than the preset probability threshold, an abnormal alarm is generated to the preset maintenance terminal.

2. The integrated circuit chip testing system according to claim 1, characterized in that: The system also includes a data set correction module; It is used to obtain the actual fault feedback results of the newly added integrated circuit chip data to be tested in the data set through the preset maintenance terminal after generating an abnormal alarm to the preset maintenance terminal.

3. The integrated circuit chip testing system according to claim 1, characterized in that: The sample acquisition module includes a first acquisition unit and a second acquisition unit; A first acquisition unit is used to acquire the chip model of the integrated circuit chip and the actual measurement link of the integrated circuit chip through a preset data upload interface; The second acquisition unit is used to obtain the measured data corresponding to each measurement link according to the measurement terminal corresponding to each measurement link.

4. The integrated circuit chip testing system according to claim 1, characterized in that: The collection acquisition module includes a clustering unit, Used to obtain the actual fault type K; Randomly select M sample data from the data set as the initial clustering center; where M>K; Using the K-Means clustering algorithm, we can obtain M clustering sets.

5. The integrated circuit chip testing system according to claim 1, characterized in that: The probability determination module includes a calculation unit, Used by the formula: , calculate and obtain the actual failure probability corresponding to the current cluster set.

6. A method for testing an integrated circuit chip, characterized in that: The method comprises: Obtaining the chip model of the integrated circuit chip, the actual measurement links of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; The sample data belonging to the same chip model and the same measurement link are taken as a data set, and then the data set is clustered to obtain several cluster sets; Obtaining actual fault feedback results corresponding to the sample data; wherein the actual fault feedback results are divided into: fault presence and no fault; Determine the actual failure probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the portion of sample data with failures; Obtaining the chip model of the integrated circuit chip to be tested, the specific measurement links and the measured data corresponding to each measurement link; determining the corresponding data set based on the chip model of the integrated circuit chip to be tested and the specific measurement links; adding the measured data of the integrated circuit chip to be tested to the data set; The current data set is clustered to determine the cluster set corresponding to the measured data of the current integrated circuit chip; then the corresponding actual fault probability is obtained; when the actual fault probability is greater than the preset probability threshold, an abnormal alarm is generated to the preset maintenance terminal.

7. The integrated circuit chip testing method according to claim 6, characterized in that: The chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link are obtained as sample data, specifically including: Obtain the chip model of the integrated circuit chip and the actual measurement link of the integrated circuit chip through the preset data upload interface; According to the measuring terminals corresponding to each measuring link, the measuring data corresponding to each measuring link is obtained.

8. The integrated circuit chip testing method according to claim 6, characterized in that: Cluster the data set to obtain several cluster sets, including: Get the actual fault type K; Randomly select M sample data from the data set as the initial clustering center; where M K; Using the K-Means clustering algorithm, we can obtain M clustering sets.

9. An integrated circuit chip testing device, characterized in that: The device comprises: processor; and a memory storing executable codes thereon, which, when the executable codes are executed, enable the processor to execute an integrated circuit chip testing method as claimed in any one of claims 6 to 8.

10. A non-volatile computer storage medium, characterized in that: Computer instructions are stored thereon, and when the computer instructions are executed, an integrated circuit chip testing method as described in any one of claims 6-8 is implemented.

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