PTAT reference current source, chip and electronic equipment

Abstract

The invention discloses a PTAT reference current source, a chip and electronic equipment, and belongs to the technical field of electronic circuits, and the PTAT reference current source is characterized in that a current mirror is used for mirroring PTAT current to output mirroring current and first output current; the amplifier transmits PTAT current and image current, and virtually shortens a first input end and a second input end; a collector electrode of the first triode is connected with a first input end of the amplifier, a collector electrode of the second triode is connected with a second input end of the amplifier, a source electrode of the first NMOS tube is connected with a base electrode of the first triode and a base electrode of the second triode, a grid electrode of the first NMOS tube is connected with the current mirror and the amplifier, and a drain electrode of the first NMOS tube is connected with a power supply. The emitter of the second triode is connected with the first end of the first resistor, and the emitter of the first triode and the second end of the first resistor are jointly connected to the power ground; therefore, the precision of the PTAT reference current source is improved.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuit technology, and in particular, relates to a PTAT reference current source, a chip, and an electronic device. Background Art

[0002] Proportional to absolute temperature (PTAT) current refers to current that changes in direct proportion to temperature. PTAT reference current sources are often used in bandgap references, operational amplifiers, and low-dropout linear regulators to provide a stable bias current to compensate for the effect of temperature on circuit performance. The PTAT current source that provides a reference for the entire circuit needs to have the characteristics of low error and high precision. In addition to providing PTAT current for the bandgap reference, the circuit can also be used as a common current mirror to provide bias current for the operational amplifier.

[0003] The generation of PTAT current is usually achieved by using the base-emitter voltage difference between two transistors of different sizes. However, due to the Early effect, the collector currents of the two transistors will be affected by the collector-emitter voltage, and the difference in the collector currents of the two affects the temperature characteristics and accuracy of the PTAT current. Therefore, the temperature linearity and accuracy of the related PTAT reference current source are poor, that is, the accuracy is poor. Summary of the invention

[0004] The purpose of the present application is to provide a PTAT reference current source, a chip, and an electronic device, aiming to solve the problem of poor accuracy of the related PTAT reference current source.

[0005] The embodiment of the present application provides a PTAT reference current source, including:

[0006] A current mirror configured to access the PTAT current and mirror the PTAT current to output a mirror current and a first output current;

[0007] an amplifier connected to the current mirror, having a first input terminal and a second input terminal, configured to transmit the PTAT current and the mirror current, and to virtually short the first input terminal and the second input terminal;

[0008] The PTAT reference current source also includes a first NMOS transistor, a first transistor, a second transistor and a first resistor;

[0009] The collector of the first transistor is connected to the first input terminal of the amplifier, the collector of the second transistor is connected to the second input terminal of the amplifier, the source of the first NMOS transistor is connected to the base of the first transistor and the base of the second transistor, the gate of the first NMOS transistor is connected to the current mirror and the amplifier, the drain of the first NMOS transistor is connected to a power supply, the emitter of the second transistor is connected to the first end of the first resistor, and the emitter of the first transistor and the second end of the first resistor are connected to a power ground.

[0010] In one embodiment, the amplifier includes a second NMOS tube and a third NMOS tube;

[0011] The drain of the second NMOS tube, the gate of the second NMOS tube and the gate of the third NMOS tube serve together as the first output end of the amplifier, and are connected to the current mirror and the gate of the first NMOS tube to access the mirror current;

[0012] The source of the second NMOS tube serves as the first input terminal of the amplifier and is connected to the collector of the first transistor to transmit the mirror current;

[0013] The drain of the third NMOS tube serves as the second output terminal of the amplifier and is connected to the current mirror to transmit the PTAT current;

[0014] The source of the third NMOS transistor serves as the second input terminal of the amplifier and is connected to the collector of the second transistor to access the PTAT current.

[0015] In one embodiment, the amplifier includes an operational amplifier and a fourth NMOS tube;

[0016] The non-inverting input terminal of the operational amplifier serves as the first output terminal of the amplifier and the first input terminal of the amplifier, and is connected to the current mirror, the gate of the first NMOS tube and the collector of the first transistor;

[0017] The drain of the fourth NMOS tube serves as the second output terminal of the amplifier and is connected to the current mirror to output the PTAT current;

[0018] The inverting input terminal of the operational amplifier and the source of the fourth NMOS transistor serve together as the second input terminal of the amplifier, and are connected to the collector of the second transistor;

[0019] The output end of the operational amplifier is connected to the gate of the fourth NMOS tube.

[0020] In one embodiment, a second resistor is also included;

[0021] The first end of the second resistor is connected to the source of the first NMOS transistor, the base of the first transistor and the base of the second transistor.

[0022] In one of the embodiments, it further includes a third triode;

[0023] The base of the third transistor is connected to the source of the first NMOS transistor, the base of the first transistor and the base of the second transistor, and the emitter of the third transistor is connected to the power ground;

[0024] The collector of the third transistor serves as an auxiliary output terminal of the PTAT reference current source to output a second output current.

[0025] In one embodiment, the current mirror includes a first PMOS tube, a second PMOS tube and a third PMOS tube;

[0026] The source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected to a power supply;

[0027] The drain of the second PMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube and the gate of the third PMOS tube serve together as the PTAT current input terminal of the current mirror, and are connected to the amplifier to access the PTAT current;

[0028] The drain of the first PMOS tube serves as a mirror current output terminal of the current mirror and is connected to the gate of the first NMOS tube and the amplifier;

[0029] The drain of the third PMOS tube serves as an output current output terminal of the current mirror to output the first output current.

[0030] In one embodiment, the current mirror includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube and a third resistor;

[0031] The source of the fourth PMOS tube, the source of the fifth PMOS tube and the source of the sixth PMOS tube are connected to a power supply;

[0032] The drain of the fourth PMOS tube is connected to the source of the seventh PMOS tube, the drain of the fifth PMOS tube is connected to the source of the eighth PMOS tube, and the drain of the sixth PMOS tube is connected to the source of the ninth PMOS tube;

[0033] The drain of the eighth PMOS tube is connected to the first end of the third resistor, the gate of the fourth PMOS tube, the gate of the fifth PMOS tube and the gate of the sixth PMOS tube;

[0034] The gate of the seventh PMOS tube, the gate of the eighth PMOS tube, the gate of the ninth PMOS tube and the second end of the third resistor serve together as the PTAT current input end of the current mirror, and are connected to the amplifier to access the PTAT current;

[0035] The drain of the seventh PMOS tube serves as the output end of the mirror circuit of the current mirror, and is connected to the gate of the first NMOS tube and the amplifier to output the mirror current;

[0036] The drain of the ninth PMOS tube serves as an output current output terminal of the current mirror to output the first output current.

[0037] In one embodiment, a tenth PMOS tube is further included; the source of the tenth PMOS tube is connected to a power supply, and the drain of the tenth PMOS tube is connected to the current mirror, the amplifier and the gate of the first NMOS tube;

[0038] The gate of the tenth PMOS tube serves as an inverting enable signal input terminal of the PTAT reference current source to receive an inverting enable signal.

[0039] An embodiment of the present invention further provides a chip, wherein the chip includes the above-mentioned PTAT reference current source.

[0040] An embodiment of the present invention further provides an electronic device, wherein the electronic device includes the above-mentioned PTAT reference current source.

[0041] Compared with the prior art, the embodiment of the present invention has the following beneficial effects: by utilizing the deep negative feedback characteristics of the amplifier, the voltages of the first input terminal and the second input terminal tend to be close, i.e., "virtual short". In this way, the difference in collector currents between the first triode and the second triode generated by the collector-emitter voltage difference is suppressed, thereby reducing the influence of the Early effect on the base-emitter voltage difference and even the PTAT current, and improving the accuracy of the PTAT reference current source. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 A schematic diagram of the structure of a PTAT reference current source provided in an embodiment of the present application;

[0044] Figure 2 Another structural schematic diagram of a PTAT reference current source provided in an embodiment of the present application;

[0045] Figure 3 Another structural schematic diagram of a PTAT reference current source provided in an embodiment of the present application;

[0046] Figure 4 Another structural schematic diagram of a PTAT reference current source provided in an embodiment of the present application;

[0047] Figure 5 A partial exemplary circuit schematic diagram of a current output circuit in a PTAT reference current source provided in an embodiment of the present application;

[0048] Figure 6 A partial exemplary circuit schematic diagram of a current output circuit in a PTAT reference current source provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0051] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0053] Figure 1 The structure diagram of the PTAT reference current source provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0054] The PTAT reference current source comprises a current mirror 01 , an amplifier 02 , a first NMOS transistor MN1 , a first transistor Q1 , a second transistor Q2 and a first resistor R1 .

[0055] A current mirror 01 is configured to access the PTAT current and mirror the PTAT current to output a mirror current and a first output current;

[0056] Amplifier 02, connected to current mirror 01, having a first input terminal and a second input terminal, configured to transmit PTAT current and mirror current, and to virtually short the first input terminal and the second input terminal;

[0057] The collector of the first transistor Q1 is connected to the first input terminal of the amplifier 02, the collector of the second transistor Q2 is connected to the second input terminal of the amplifier 02, the source of the first NMOS transistor MN1 is connected to the base of the first transistor Q1 and the base of the second transistor Q2, the gate of the first NMOS transistor MN1 is connected to the current mirror 01 and the amplifier 02, the drain of the first NMOS transistor MN1 is connected to the power supply VDD, the emitter of the second transistor Q2 is connected to the first end of the first resistor R1, and the emitter of the first transistor Q1 and the second end of the first resistor R1 are connected to the power ground.

[0058] It can be understood that the mirror multiple between the PTAT current and the mirror current is 1. The emitter junction area of ​​the second transistor Q2 is N times the emitter junction area of ​​the first transistor Q1, because the collector current Ic of the transistor satisfies the following formula:

[0059] I c =I s *e^(V be / V T )

[0060] Among them I s is the reverse saturation current, which is proportional to the emitter junction area, V be is the base-emitter voltage. V T is the thermal voltage, and VT = kT / q. Since the first transistor Q1 and the second transistor Q2 have the same base voltage, the voltage V across the first resistor R1 R1 That is, the base-emitter voltage V of the first transistor Q1 and the second transistor Q2 be The difference, that is:

[0061] V R1 =V be1 -V be2 =V T *ln((I c1 / I s1 ) / (I c2 / I s2 ))=V T *ln(N).

[0062] Among them, I c1 is the collector current of the first transistor Q1, I c2 are the collector currents of the second transistor Q2 respectively.

[0063] Without considering the temperature coefficient of the first resistor R1, the current I1 flowing through the first resistor R1 is:

[0064] I1=V R1 / R1=kT*ln(N) / q

[0065] This current I1 is proportional to the temperature, namely the PTAT current.

[0066] It is understandable that the diode connection method causes a portion of the mirror current to flow into the base of the first transistor Q1 and the base of the second transistor Q2, resulting in I c1 Slightly lower than I c2 By setting the first NMOS tube MN1, the base voltage of the first transistor Q1 and the base voltage of the second transistor Q2 are generated. Since the mirror current does not directly flow into the base of the first transistor Q1 and the base of the second transistor Q2, the I caused by the base current of the first transistor Q1 can be reduced. c1 and I c2 deviation.

[0067] Before using the first NMOS tube MN1, I c1 / I c2 =1+2 / β; after using the first NMOS tube MN1, I c1 / I c2 =1+2 / (β*(β+1)); where β is the current gain of the transistor.

[0068] In addition, although the output impedance of the current mirror 01 is low, so that there is a certain voltage difference between the PTAT current input terminal and the mirror current output terminal of the current mirror 01, by setting the amplifier 02, the deep negative feedback of the amplifier 02 realizes a virtual short for the first input terminal and the second input terminal, thereby reducing the I caused by the Early effect of the transistor. c1 and I c2 The difference between.

[0069] The Early effect refers to the phenomenon that when the collector-emitter voltage of a bipolar transistor changes, the base-collector depletion width (depletion region size) will also change. In a bipolar transistor, when the collector-emitter voltage increases, the reverse bias of the collector junction increases, causing the depletion region width to increase, thereby reducing the base region width. This causes more electrons to drift to the collector, resulting in an increase in the collector current. Overall, this phenomenon is similar to connecting a resistor in parallel between the collector and the emitter. That is:

[0070] I c =I s *(1+V ce / V A )*e^(V be / V T ), where V ce is the collector-emitter voltage, V A is the Early voltage. Ideally, V A Approaches infinity.

[0071] like Figure 2 As shown, the above PTAT reference current source further includes a second resistor R2;

[0072] A first end of the second resistor R2 is connected to the source of the first NMOS transistor MN1 , the base of the first transistor Q1 , and the base of the second transistor Q2 .

[0073] A current is generated through the second resistor R2 and the base voltages of the two transistors (the first transistor Q1 and the second transistor Q2) to increase the source current of the first NMOS transistor MN1, thereby reducing the possibility that the first NMOS transistor MN1 operates in the subthreshold region, so that the first NMOS transistor MN1 operates in the saturation region, thereby improving the stability of the PTAT reference current source.

[0074] like Figure 3 As shown, the PTAT reference current source further includes a third transistor Q3.

[0075] The base of the third transistor Q3 is connected to the source of the first NMOS transistor MN1, the base of the first transistor Q1 and the base of the second transistor Q2, and the emitter of the third transistor Q3 is connected to the power ground;

[0076] The collector of the third transistor Q3 serves as an auxiliary output terminal of the PTAT reference current source to output a second output current.

[0077] It can be understood that the third transistor Q3 serves as a replica of the first transistor Q1 and outputs a replicated second output current.

[0078] The second output current satisfies the following formula:

[0079] I3 / I1=A3 / A1

[0080] Wherein, A3 is the area of ​​the emitter junction of the third transistor Q3, A1 is the area of ​​the emitter junction of the first transistor Q1, I3 is the second output current, and I1 is the current flowing through the first transistor Q1.

[0081] It should be noted that by changing the area A3 of the emitter junction of the third transistor Q3 , different multiples of the mirror current can be obtained, thereby adjusting the second output current.

[0082] The PTAT current is replicated through the third transistor Q3, which can provide bias current for other modules.

[0083] like Figure 4 As shown, the PTAT reference current source further includes a tenth PMOS tube MP10; the source of the tenth PMOS tube MP10 is connected to the power supply VDD, and the drain of the tenth PMOS tube MP10 is connected to the current mirror 01, the amplifier 02 and the gate of the first NMOS tube MN1;

[0084] The gate of the tenth PMOS transistor MP10 serves as an inverting enable signal input terminal of the PTAT reference current source to receive the inverting enable signal.

[0085] It is understandable that the PTAT reference current source may have two operating points, one working state and the other corresponding to the zero current state. In order to avoid the circuit being in the zero current working state, it is necessary to introduce a related startup circuit, which is used to inject current into one side branch at startup, causing an imbalance in the zero current state. The tenth PMOS tube MP10 controlled by the startup signal serves as a startup circuit. At startup, the inverted enable signal is at a low level, and the tenth PMOS tube MP10 flows through a certain current and injects it into the first transistor Q1. After entering a stable working state, the inverted enable signal becomes a high level, thereby turning off the tenth PMOS tube MP10, so that the startup circuit no longer works. In a specific implementation, the startup circuit can be generated from a circuit that provides a bias for the PTAT reference current source.

[0086] The start-up of the PTAT reference current source is achieved through the tenth PMOS tube MP10, and the circuit is simple and reliable.

[0087] Figure 5FIG. 4 shows a partial exemplary circuit structure of a PTAT reference current source provided by an embodiment of the present invention. Figure 6 Another partial exemplary circuit structure of the PTAT reference current source provided by an embodiment of the present invention is shown. For the sake of convenience, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0088] like Figure 5 As shown, the amplifier 02 includes a second NMOS transistor MN2 and a third NMOS transistor MN3;

[0089] The drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2 and the gate of the third NMOS transistor MN3 serve together as the first output end of the amplifier 02, and are connected to the current mirror 01 and the gate of the first NMOS transistor MN1 to access the mirror current;

[0090] The source of the second NMOS transistor MN2 is used as the first input terminal of the amplifier 02 and is connected to the collector of the first transistor Q1 to transmit the mirror current;

[0091] The drain of the third NMOS transistor MN3 is used as the second output terminal of the amplifier 02 and is connected to the current mirror 01 to output the PTAT current;

[0092] The source of the third NMOS transistor MN3 serves as the second input terminal of the amplifier O2 and is connected to the collector of the second transistor Q2 to access the PTAT current.

[0093] The amplifier 02 includes two NMOS tubes, has a simple structure, and is suitable for chip products.

[0094] like Figure 5 As shown, the current mirror 01 includes a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9 and a third resistor R3;

[0095] The source of the fourth PMOS tube MP4, the source of the fifth PMOS tube MP5 and the source of the sixth PMOS tube MP6 are connected to the power supply VDD;

[0096] The drain of the fourth PMOS tube MP4 is connected to the source of the seventh PMOS tube MP7, the drain of the fifth PMOS tube MP5 is connected to the source of the eighth PMOS tube MP8, and the drain of the sixth PMOS tube MP6 is connected to the source of the ninth PMOS tube MP9;

[0097] The drain of the eighth PMOS tube MP8 is connected to the first end of the third resistor R3, the gate of the fourth PMOS tube MP4, the gate of the fifth PMOS tube MP5 and the gate of the sixth PMOS tube MP6;

[0098] The gate of the seventh PMOS transistor MP7, the gate of the eighth PMOS transistor MP8, the gate of the ninth PMOS transistor MP9 and the second end of the third resistor R3 are used together as the PTAT current input end of the current mirror 01, and are connected to the amplifier 02 to access the PTAT current;

[0099] The drain of the seventh PMOS transistor MP7 is used as a mirror current terminal of the current mirror 01, and is connected to the gate of the first NMOS transistor MN1 and the amplifier 02 to output the mirror current;

[0100] The drain of the ninth PMOS transistor MP9 serves as the output current output terminal of the current mirror O1 to output the first output current.

[0101] The third resistor R3 is used to provide a bias voltage for the current mirror O1.

[0102] The current mirror 01 has a high precision in mirroring the current.

[0103] like Figure 6 As shown, the amplifier 02 includes an operational amplifier U1 and a fourth NMOS transistor MN4;

[0104] The non-inverting input terminal of the operational amplifier U1 is used as the first output terminal of the amplifier 02 and the first input terminal of the amplifier 02, and is connected to the current mirror 01, the gate of the first NMOS transistor MN1 and the collector of the first transistor Q1;

[0105] The drain of the fourth NMOS transistor MN4 is used as the second output terminal of the amplifier 02 and is connected to the current mirror 01 to output the PTAT current;

[0106] The inverting input terminal of the operational amplifier U1 and the source of the fourth NMOS transistor MN4 serve together as the second input terminal of the amplifier O2, and are connected to the collector of the second transistor Q2;

[0107] The output terminal of the operational amplifier U1 is connected to the gate of the fourth NMOS transistor MN4.

[0108] It can be understood that the operational amplifier U1 is used as an operational amplifier, and its positive and negative input terminals are respectively connected to the collector of the first transistor Q1 and the collector of the second transistor Q2, and its output terminal is connected to the gate of the fourth NMOS transistor MN4, and the fourth NMOS transistor MN4 is used as a transmission tube for the PTAT current; in this way, the deep negative feedback characteristics of the operational amplifier U1 can be used to virtually short the collector of the first transistor Q1 and the collector of the second transistor Q2, thereby suppressing the influence of the Early effect on the PTAT current.

[0109] like Figure 6 As shown, the current mirror 01 includes a first PMOS tube MP1, a second PMOS tube MP2 and a third PMOS tube MP3;

[0110] The source of the first PMOS tube MP1, the source of the second PMOS tube MP2 and the source of the third PMOS tube MP3 are connected to the power supply VDD;

[0111] The drain of the second PMOS tube MP1, the gate of the first PMOS tube MP1, the gate of the second PMOS tube MP1 and the gate of the third PMOS tube MP3 are used together as the PTAT current input terminal of the current mirror 01, and are connected to the amplifier 02 to access the PTAT current;

[0112] The drain of the first PMOS transistor MP1 is used as the mirror current output terminal of the current mirror 01, and is connected to the gate of the first NMOS transistor MN1 and the amplifier 02 to output the mirror current;

[0113] The drain of the third PMOS transistor MP3 serves as an output current output terminal of the current mirror O1 to output a first output current.

[0114] The current mirror 01 has a simple and reliable structure.

[0115] Figure 5 and Figure 6 The other circuit parts shown are as follows Figures 1 to 4 As shown, no further description is given here.

[0116] The following is a combination of working principles Figure 5 to Figure 6 As shown for further explanation:

[0117] exist Figure 5 In the embodiment, the fourth field effect transistor MP4 and the fifth field effect transistor MP5 have the same size, and the seventh field effect transistor MP7 and the eighth field effect transistor MP8 have the same size, providing equal currents to the first transistor Q1 and the second transistor Q2 (i.e., the PTAT current and the mirror current have the same value). The second NMOS transistor MN2 transmits the mirror current, and the third NMOS transistor MN3 transmits the PTAT current. It can be deduced from the above formula that, without considering the temperature coefficient of the first resistor R1, the current I1 flowing through the first resistor R1 is:

[0118] I1=V R1 / R1=kT*ln(N) / q

[0119] This current I1 is proportional to the temperature, namely the PTAT current.

[0120] The sixth PMOS transistor MP6 and the ninth PMOS transistor MP9 mirror the PTAT current to obtain a first output current I0. It can be understood that the first output current I 01 Directly proportional to temperature.

[0121] exist Figure 6In the embodiment, the first field effect transistor MP1 and the second field effect transistor MP2 have the same size, and provide equal collector currents for the first transistor Q1 and the second transistor Q2 (i.e., the PTAT current and the mirror current have the same value). The first field effect transistor MP1 transmits the mirror current via the node where the non-inverting input terminal of the operational amplifier O2U1 is located, and the fourth NMOS transistor MN4 transmits the PTAT current.

[0122] and Figure 5 and Figure 6 The principle of the PTAT reference current source generating the PTAT current is the same as that in FIG. 1 , and will not be repeated here.

[0123] The sixth PMOS transistor MP6 and the ninth PMOS transistor MP9 mirror the PTAT current to obtain a first output current I0. It can be understood that the first output current I 01 Proportional to temperature.

[0124] Figure 5 and Figure 6 For the principle of the first NMOS tube MN1, please refer to Figure 1 The corresponding principle description; Figure 5 and Figure 6 The principle of the second resistor R2 can be found in Figure 2 The corresponding principle description; Figure 5 and Figure 6 Please refer to the principle of the third transistor Q3 in Figure 3 The corresponding principle description; Figure 5 and Figure 6 Please refer to the principle of the tenth PMOS tube MP10 in Figure 4 The corresponding principle description will not be repeated here.

[0125] An embodiment of the present invention further provides a chip, which includes the above-mentioned PTAT reference current source.

[0126] An embodiment of the present invention further provides an electronic device, which includes the above-mentioned PTAT reference current source.

[0127] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0128] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A PTAT reference current source, characterized in that: include: A current mirror configured to access the PTAT current and mirror the PTAT current to output a mirror current and a first output current; an amplifier connected to the current mirror, having a first input terminal and a second input terminal, configured to transmit the PTAT current and the mirror current, and to virtually short the first input terminal and the second input terminal; The PTAT reference current source also includes a first NMOS transistor, a first transistor, a second transistor and a first resistor; The collector of the first transistor is connected to the first input terminal of the amplifier, the collector of the second transistor is connected to the second input terminal of the amplifier, the source of the first NMOS transistor is connected to the base of the first transistor and the base of the second transistor, the gate of the first NMOS transistor is connected to the current mirror and the amplifier, the drain of the first NMOS transistor is connected to a power supply, the emitter of the second transistor is connected to the first end of the first resistor, and the emitter of the first transistor and the second end of the first resistor are connected to a power ground.

2. The PTAT reference current source according to claim 1, characterized in that: The amplifier includes a second NMOS tube and a third NMOS tube; The drain of the second NMOS tube, the gate of the second NMOS tube and the gate of the third NMOS tube serve together as the first output end of the amplifier, and are connected to the current mirror and the gate of the first NMOS tube to access the mirror current; The source of the second NMOS transistor is used as the first input terminal of the amplifier and is connected to the collector of the first transistor to transmit the mirror current; The drain of the third NMOS tube serves as the second output terminal of the amplifier and is connected to the current mirror to transmit the PTAT current; The source of the third NMOS transistor serves as the second input terminal of the amplifier and is connected to the collector of the second transistor to access the PTAT current.

3. The PTAT reference current source according to claim 1, characterized in that: The amplifier includes an operational amplifier and a fourth NMOS tube; The non-inverting input terminal of the operational amplifier serves as the first output terminal of the amplifier and the first input terminal of the amplifier, and is connected to the current mirror, the gate of the first NMOS tube and the collector of the first transistor; The drain of the fourth NMOS tube serves as the second output terminal of the amplifier and is connected to the current mirror to output the PTAT current; The inverting input terminal of the operational amplifier and the source of the fourth NMOS transistor serve together as the second input terminal of the amplifier, and are connected to the collector of the second transistor; The output end of the operational amplifier is connected to the gate of the fourth NMOS tube.

4. The PTAT reference current source according to claim 1, characterized in that: Also comprising a second resistor; The first end of the second resistor is connected to the source of the first NMOS transistor, the base of the first transistor and the base of the second transistor.

5. The PTAT reference current source according to claim 1, characterized in that: Also included is a third triode; The base of the third transistor is connected to the source of the first NMOS transistor, the base of the first transistor and the base of the second transistor, and the emitter of the third transistor is connected to the power ground; The collector of the third transistor serves as an auxiliary output terminal of the PTAT reference current source to output a second output current.

6. The PTAT reference current source according to claim 1, characterized in that: The current mirror comprises a first PMOS tube, a second PMOS tube and a third PMOS tube; The source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected to a power supply; The drain of the second PMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube and the gate of the third PMOS tube serve together as the PTAT current input terminal of the current mirror, and are connected to the amplifier to access the PTAT current; The drain of the first PMOS tube serves as a mirror current output terminal of the current mirror and is connected to the gate of the first NMOS tube and the amplifier; The drain of the third PMOS tube serves as an output current output terminal of the current mirror to output the first output current.

7. The PTAT reference current source according to claim 1, characterized in that: The current mirror includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube and a third resistor; The source of the fourth PMOS tube, the source of the fifth PMOS tube and the source of the sixth PMOS tube are connected to a power supply; The drain of the fourth PMOS tube is connected to the source of the seventh PMOS tube, the drain of the fifth PMOS tube is connected to the source of the eighth PMOS tube, and the drain of the sixth PMOS tube is connected to the source of the ninth PMOS tube; The drain of the eighth PMOS tube is connected to the first end of the third resistor, the gate of the fourth PMOS tube, the gate of the fifth PMOS tube and the gate of the sixth PMOS tube; The gate of the seventh PMOS tube, the gate of the eighth PMOS tube, the gate of the ninth PMOS tube and the second end of the third resistor serve together as the PTAT current input end of the current mirror, and are connected to the amplifier to access the PTAT current; The drain of the seventh PMOS tube serves as a mirror current output terminal of the current mirror, and is connected to the gate of the first NMOS tube and the amplifier to output the mirror current; The drain of the ninth PMOS tube serves as an output current output terminal of the current mirror to output the first output current.

8. The PTAT reference current source according to any one of claims 1 to 7, characterized in that: It also includes a tenth PMOS tube; the source of the tenth PMOS tube is connected to the power supply, and the drain of the tenth PMOS tube is connected to the current mirror, the amplifier and the gate of the first NMOS tube; The gate of the tenth PMOS tube serves as an inverting enable signal input terminal of the PTAT reference current source to receive an inverting enable signal.

9. A chip, characterized in that: The chip comprises the PTAT reference current source as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the PTAT reference current source as claimed in any one of claims 1 to 8.

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