Asynchronous bidirectional single-line communication method and circuit system

Abstract

The invention relates to the technical field of communication, and discloses an asynchronous bidirectional single-line communication method and a circuit system, and the circuit system comprises a receiving and transmitting switching module which is used for controlling data receiving and transmitting, and a data synchronization module which is used for carrying out the synchronization processing of a received single-line signal, and generating a synchronized single-line signal. The data analysis module is used for carrying out decoding processing on the synchronized single-line signals and generating decoded data, the data back-announcement module is used for carrying out encoding processing on data to be back-announced according to the decoded data, coded data is generated, hardware implementation is simplified, power consumption is reduced, and meanwhile, two-way communication between the host and the slave can be achieved.

Description

Technical Field

[0001] The invention relates to the technical field of communication, and discloses an asynchronous bidirectional single-line communication method and a circuit system. Background Art

[0002] With the development of science and technology, standard serial data communication protocols represented by SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), and UART (Universal Asynchronous Receiver Transmitter) have been widely used in various fields. Among them, standard SPI uses four wires to achieve two-way communication; standard I2C and standard UART use two wires to achieve two-way communication. As a type of serial asynchronous communication, the protocol of single-wire serial communication is defined between the host and the slave. The two can use a single wire to achieve two-way communication, which saves interface resources to the maximum extent.

[0003] In recent years, some customized single-line communication solutions have appeared at home and abroad. Although such solutions save pin resources, the protocols or designs are complex. Usually, data needs to be parsed after clock recovery, which involves relatively complex designs (including but not limited to various algorithms), increasing the complexity and power consumption of hardware implementation. Therefore, it is urgent to provide a better single-line communication solution to simplify hardware implementation and reduce power consumption.

[0004] For example, a Chinese patent with publication number CN110768778A discloses a single-line communication circuit, communication method and communication system, including a parsing clock generating unit and a data parsing unit, wherein the parsing clock generating unit outputs a single-line communication signal parsing clock to the data parsing unit, and the parsing clock generating unit includes a first delay module for receiving an external single-line communication signal, performing a first delay on the input single-line communication signal, and outputting a first delay signal; a control signal generating module for performing a first logical operation on the input single-line communication signal and the first delay signal to generate a new pulse signal as an oscillation source control signal; a clock generating module for receiving an oscillation source control signal, and under the control of the oscillation source control signal, the output signal is used as a single-line communication signal parsing clock. The above technical solution is a one-way communication and is difficult to meet application scenarios with lower area and power consumption requirements. Summary of the invention

[0005] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0006] In order to solve the above technical problems, the main purpose of the present invention is to provide an asynchronous bidirectional single-line communication method, comprising:

[0007] S1, the host initiates write control or read control on the slave, sends a single-line signal to the slave, and the slave receives the single-line signal as input;

[0008] S2, performing synchronization processing on the received single-line signal to generate a synchronized single-line signal;

[0009] S3, decoding the synchronized single-line signal to generate decoded data;

[0010] S4, the slave identifies the control type according to the decoded data, and if it is a read control, performs data reporting, encodes the data to be reported, and generates encoded data, otherwise, does not report data;

[0011] S5. The slave sends the encoded data as an output single-line signal, and the host receives the single-line signal as an input.

[0012] As a preferred solution of an asynchronous bidirectional single-line communication method of the present invention, wherein:

[0013] The host sends a write command, a write address and write data to the slave via a single line;

[0014] The transceiver switching module of the slave device switches to a receiving mode to receive a single-line signal;

[0015] The data synchronization module of the slave performs synchronization processing on the received single-line signal to generate a synchronized single-line signal;

[0016] The data analysis module of the slave decodes the synchronized single-line signal to generate decoded data, namely, the write command, write address and write data sent by the host.

[0017] As a preferred solution of an asynchronous bidirectional single-line communication method of the present invention, wherein:

[0018] The host sends a read command and a read address to the slave via a single line;

[0019] The transceiver switching module of the slave device switches to a receiving mode to receive a single-line signal;

[0020] The data synchronization module of the slave performs synchronization processing on the received single-line signal to generate a synchronized single-line signal;

[0021] The data parsing module of the slave decodes the synchronized single-line signal to generate decoded data, namely, the read command and read address sent by the host;

[0022] The data feedback module of the slave machine prepares corresponding data according to the decoded read command and read address, and performs encoding processing to generate encoded data, i.e., read data;

[0023] The transceiver switching module of the slave is switched to the sending mode, and the encoded data is sent to the host through a single line;

[0024] The transceiver switching module of the host switches to the receiving mode to receive the single-line signal sent back by the slave.

[0025] As a preferred solution of an asynchronous bidirectional single-line communication circuit system of the present invention, wherein:

[0026] An asynchronous bidirectional single-wire communication circuit system includes a master and a slave;

[0027] The host is used to initiate write control or read control on the slave;

[0028] The slave is used to respond to the write control or read control initiated by the host;

[0029] The slave comprises a peripheral circuit and an asynchronous bidirectional single-wire communication circuit;

[0030] The peripheral circuit is used to provide power, clock and reset for the asynchronous bidirectional single-wire communication circuit;

[0031] The asynchronous bidirectional single-line communication circuit includes a transceiver switching module, a data synchronization module, a data analysis module and a data feedback module, which are used to realize the communication control of the single-line signal.

[0032] As a preferred solution of an asynchronous bidirectional single-line communication circuit system of the present invention, wherein:

[0033] A transceiver switching module, used for controlling the transceiver of data, wherein the transceiver of data includes receiving a single-line signal and sending a single-line signal;

[0034] A data synchronization module, used for performing synchronization processing on the received single-line signal to generate a synchronized single-line signal;

[0035] A data analysis module is used to decode the synchronized single-line signal to generate decoded data, wherein the data analysis module includes decoding of write data frames and decoding of read data frames;

[0036] The data reporting module is used to encode the data to be reported according to the decoded data to generate encoded data.

[0037] As a preferred solution of an asynchronous bidirectional single-line communication circuit system of the present invention, wherein:

[0038] The transceiver switching module includes a tri-state gate circuit;

[0039] The three-state gate circuit states include high level, low level and high impedance state. If a three-state gate is in the high impedance state, it is equivalent to an open circuit;

[0040] When sending data, the output end of the tri-state gate circuit is set to a non-high impedance state and the input end is set to a high impedance state; when receiving data, the output end of the tri-state gate circuit is set to a high impedance state and the input end is set to a non-high impedance state.

[0041] As a preferred solution of an asynchronous bidirectional single-line communication circuit system of the present invention, wherein:

[0042] The data synchronization module includes a multi-level register, which performs synchronous processing on the data by beating the multi-level register, realizes the synchronization of the single-line signal, and reduces the metastable problem generated when the signal is transmitted between different clock domains;

[0043] The multi-level register beat locks the signal edge changes step by step through multiple registers, thereby eliminating data errors caused by clock deviation and signal instability;

[0044] The data synchronization module implements a single-line signal synchronization process, including:

[0045] S101, using a local clock to sample the input single-line signal, this process will check the state of the single-line signal in each clock cycle;

[0046] S102, using multiple levels of registers to perform phase-locked processing on the sampled data, and each level of registers will store a sampling result, and the next level of registers will be adjusted according to the result of the previous level;

[0047] S103, through the processing of multi-level registers, the signal is made more stable, the influence of burrs and noise is reduced, and finally a synchronized single-line signal is obtained;

[0048] S104. After being processed by the multi-stage registers, the data synchronization module outputs a single-line signal that has been synchronously processed. The signal has high reliability and accuracy and is suitable for further data processing or decoding.

[0049] As a preferred solution of an asynchronous bidirectional single-line communication circuit system of the present invention, wherein:

[0050] The decoding of the write data frame includes a data analysis module performing pulse width monitoring, falling edge monitoring, shift storage and other processing on the synchronized single-line signal, acquiring data of the command segment, address segment and data segment, and obtaining the decoded write command, write address and write data;

[0051] The decoding of the read data frame includes a data analysis module performing pulse width monitoring, falling edge monitoring and shift storage on the synchronized single-line signal, acquiring data of the command segment and address segment, and obtaining a decoded read command and read address.

[0052] As a preferred solution of an asynchronous bidirectional single-line communication circuit system of the present invention, wherein:

[0053] The data reporting module workflow includes:

[0054] S201, the data feedback module receives the decoded read data frame command and address data;

[0055] S202, based on the received read command and read address information, processing the reported data segment through the data reporting module;

[0056] S203, the data reporting module encodes the data segment to be reported according to the asynchronous bidirectional single-line communication protocol;

[0057] S204, during the encoding process, the data will be converted into a series of single-bit signals, and the pulse width T and tD of the single-bit signals will be set according to the asynchronous bidirectional single-wire communication protocol;

[0058] S205 , the data feedback module sends the encoded single-bit data to the host one by one via the data transceiver switching module.

[0059] Beneficial effects of the present invention:

[0060] The present invention provides an asynchronous bidirectional single-line communication method and circuit system, which simplifies hardware implementation and reduces power consumption. At the same time, bidirectional communication between a host and a slave can be realized.

[0061] The technology provided by the present invention can ensure that data exchange between the host and the slave can be carried out efficiently and reliably even without a complex synchronization mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0063] Figure 1 It is an overall flow chart of an asynchronous bidirectional single-line communication method of the present invention;

[0064] Figure 2 This is a composition diagram of an asynchronous bidirectional single-line communication circuit system of the present invention;

[0065] Figure 3 The present invention is a schematic diagram of an asynchronous bidirectional single-line communication circuit structure.

[0066] Figure 4 A schematic diagram of writing a data frame definition for an asynchronous bidirectional single-line communication protocol of the present invention;

[0067] Figure 5 A schematic diagram of a read data frame definition of an asynchronous bidirectional single-wire communication protocol of the present invention;

[0068] Figure 6 A schematic diagram of bit definition of an asynchronous bidirectional single-wire communication protocol according to the present invention;

[0069] Figure 7 A schematic diagram of data definition of an asynchronous bidirectional single-line communication protocol of the present invention; DETAILED DESCRIPTION

[0070] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0071] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0072] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0073] Embodiment 1:

[0074] like Figure 1 As shown, an asynchronous bidirectional single-line communication method includes:

[0075] S1, the host initiates write control or read control on the slave, sends a single-line signal to the slave, and the slave receives the single-line signal as input;

[0076] Among them, the host sends write control data or read control data to the slave through a single line;

[0077] Further, the transceiver switching module of the slave device switches to the receiving mode to receive the single-line signal;

[0078] S2, synchronously processing the received single-line signal to generate a synchronized single-line signal;

[0079] The data synchronization module of the slave performs synchronization processing on the received single-line signal to generate a synchronized single-line signal;

[0080] S3, decoding the synchronized single-line signal to generate decoded data;

[0081] The data analysis module of the slave decodes the synchronized single-line signal to generate decoded data, i.e., the write control data or read control data sent by the host;

[0082] S4, the slave identifies the control type according to the decoded data, and if it is a read control, performs data reporting, encodes the data to be reported, and generates encoded data, otherwise, does not report data;

[0083] The data feedback module of the slave device prepares corresponding read data according to the decoded read command and read address, and performs encoding processing to generate encoded data;

[0084] S5, the slave sends the encoded data as a single-line signal as output, and the host receives the single-line signal as input;

[0085] Among them, the transceiver switching module of the slave is switched to the sending mode, and the encoded data is sent to the host through a single line;

[0086] Furthermore, the host's transceiver switching module switches to a receiving mode to receive the single-line signal sent back by the slave.

[0087] Embodiment 2:

[0088] like Figure 2 As shown, an asynchronous bidirectional single-wire communication circuit system includes a master and a slave;

[0089] The host is used to initiate write control or read control on the slave;

[0090] The slave is used to respond to the write control or read control initiated by the host;

[0091] The slave includes a peripheral circuit and an asynchronous bidirectional single-wire communication circuit;

[0092] The peripheral circuit is used to provide power, clock and reset for the asynchronous bidirectional single-wire communication circuit;

[0093] The asynchronous bidirectional single-line communication circuit includes a transceiver switching module, a data synchronization module, a data analysis module and a data feedback module, which are used to realize the communication control of the single-line signal.

[0094] like Figure 3As shown, the asynchronous bidirectional single-line communication circuit includes:

[0095] The transceiver switching module 301 is used to control the transceiver of data, wherein the transceiver of the control data includes receiving a single-line signal and sending a single-line signal;

[0096] Furthermore, the transceiver switching module may be composed of a tri-state gate circuit to realize the alternating control of the single line by the host and the slave, and complete the reception or transmission of the single line signal;

[0097] Furthermore, a tri-state gate (also called a tri-state buffer) can be in one of three states: high level, low level, and high impedance state (usually referred to as "disabled" or "inactive" state). When a tri-state gate is in high impedance state, it is actually disconnected from the communication line, which allows other devices to use this line. Therefore, in the transceiver switching module, when the device needs to send data, its output is set to a non-high impedance state and its input is set to a high impedance state, which is equivalent to an open circuit; when it needs to receive data, the opposite is true;

[0098] If the host sends data to the slave, the host's three-state gate will enter the output mode and place the data signal on the line, while the slave's three-state gate will enter the input mode to read these signals; when the slave needs to send data to the host, the three-state gate states of the two will be exchanged, ensuring that only one party can control the signal on the single line at the same time, thereby preventing signal conflicts and allowing the host and slave to communicate alternately using this single line.

[0099] The data synchronization module 302 is used to perform synchronization processing on the received single-line signal to generate a synchronized single-line signal;

[0100] Furthermore, the data synchronization module includes a multi-level register, which performs synchronous processing on the data by beating the multi-level register, realizes the synchronization of the single-line signal, and reduces the metastable problem generated when the signal is transmitted between different clock domains;

[0101] Furthermore, multi-level register tapping locks signal edge changes step by step through multiple registers, thereby eliminating data errors caused by clock deviation and signal instability;

[0102] Furthermore, the data synchronization module implements the single-line signal synchronization process as follows:

[0103] S101, using a local clock to sample the input single-line signal, this process will check the state of the single-line signal in each clock cycle;

[0104] S102, using multiple levels of registers to perform phase-locked processing on the sampled data, and each level of registers will store a sampling result, and the next level of registers will be adjusted according to the result of the previous level;

[0105] S103, through the processing of multi-level registers, the signal is made more stable, the influence of burrs and noise is reduced, and finally a synchronized single-line signal is obtained;

[0106] S104, after being processed by the multi-level registers, the data synchronization module outputs a single-line signal that has been synchronously processed, and the signal has high reliability and accuracy and is suitable for further data processing or decoding;

[0107] The data analysis module 303 is used to decode the synchronized single-line signal to generate decoded data, wherein the data analysis module includes decoding of write data frames and decoding of read data frames;

[0108] Furthermore, for decoding of the write data frame, the data parsing module performs pulse width monitoring, falling edge monitoring, shift storage and other processing on the synchronized single-line signal, thereby acquiring the data of the command segment, address segment and data segment, and obtaining the decoded write data frame command, address and data;

[0109] like Figure 4 As shown, the write data frame is composed of a start bit 401, a command segment 402, an address segment 403, a data segment 404 and an end bit 405. The command segment 402, the address segment 403 and the data segment 404 are all composed of a plurality of 1-bit data. The write data frame is sent by the host.

[0110] Furthermore, the decoding of the read data frame, the data parsing module performs pulse width monitoring, falling edge monitoring and shift storage processing on the synchronized single-line signal, thereby obtaining the data of the command segment and the address segment, and obtaining the decoded read data frame command and address data;

[0111] like Figure 5 As shown, the read data frame consists of a start bit 501, a command segment 502, an address segment 503, an end bit 504, a data segment 505 and an end bit 506, wherein the start bit 501, the command segment 502, the address segment 503 and the end bit 504 are sent by the host; the data segment 505 and the end bit 506 are sent by the slave, and for the first bit of data in the data segment 505, the slave only sends the data bit, and the end bit 504 and the data bit of the first bit of data sent by the slave together constitute the first bit of data in the data segment 505, and the remaining bits of data sent by the slave all have data flag bits and data bits.

[0112] A data reporting module 304, configured to encode the data to be reported according to the decoded data to generate encoded data;

[0113] After receiving the decoded read data frame command and address data, the data reporting module needs to report the data segment and the end bit to the host. To this end, the data reporting module encodes the data to be reported according to the format of the asynchronous bidirectional single-line communication protocol to generate single-bit encoded data. During encoding, the pulse width T and tD are based on the pulse width corresponding to the single-line signal synchronized by the data synchronization module.

[0114] Furthermore, the workflow of the data feedback module includes:

[0115] S201, the data feedback module receives the decoded read data frame command and address data, which means that the module already knows which specific location the host requests to read data;

[0116] S202, based on the received read command and read address information, the data reporting module prepares the data segment to be reported;

[0117] S203, in order to send the data segment back to the host through the single line, the data reporting module needs to encode it according to the specified asynchronous bidirectional single-line communication protocol. This encoding usually involves converting binary data into a form that can be reliably transmitted on the single line;

[0118] S204. During the encoding process, the data will be converted into a series of single-bit signals, and the duration of each bit is determined by the pulse width T and tD defined by the protocol. Here, T and tD should refer to the pulse width of the single-line signal after synchronization by the data synchronization module as a standard to ensure that the data can be transmitted accurately;

[0119] S205, the data reporting module sends the encoded single-bit data to the host one by one through the data transceiver switching module;

[0120] Furthermore, in order to ensure the integrity and reliability of the data, some additional information needs to be added, such as start bit, stop bit, etc., depending on the communication protocol used;

[0121] Furthermore, the asynchronous bidirectional single-wire communication protocol includes bit definition, data definition and data frame definition; wherein the bit definition includes data flag bit definition, start bit definition, end bit definition and data bit definition; the data definition includes data "0" definition and data "1" definition; the data frame definition includes write data frame definition and read data frame definition. In the asynchronous bidirectional single-wire communication protocol, multi-bit data transmission can be big-endian transmission or little-endian transmission according to the specific protocol agreement;

[0122] like Figure 6As shown, the data flag bit, start bit and end bit are all composed of "high and low levels", and the time of high level and low level is T; the data bit is composed of "high level 1" or "low level 0", and the time tD of the data bit high level 1 or low level 0 must satisfy T*Nmin≤tD≤T*Nmax. Among them, T=N*Tclk (Tclk is the working clock cycle of the asynchronous bidirectional single-line communication circuit), N, Nmin and Nmax are agreed by the host and slave according to the specific protocol;

[0123] like Figure 7 As shown, 1 bit of data consists of 1 data flag bit and 1 data bit. The value of the data bit determines whether the transmitted data is "0" or "1", that is, when the data bit is high level 1, it represents 1 bit of data "1", and when the data bit is low level 0, it represents 1 bit of data "0";

[0124] After all data has been sent, the data feedback module will also send an end bit to inform the host that the data transmission is complete.

[0125] Importantly, it should be noted that the construction and arrangement of the present application shown in a plurality of different exemplary embodiments are only exemplary. Although only two embodiments are described in detail in this disclosure, it should be readily understood by those who refer to this disclosure that many modifications are possible, for example, the size, scale, structure, shape and proportion of various elements, and parameter values ​​(e.g., temperature, pressure, etc.), installation arrangement, use of materials, color, directional changes, etc., without substantially departing from the novel teachings and advantages of the subject matter described in the application. For example, the element shown as integrally formed can be composed of multiple parts or elements, the position of the element can be inverted or otherwise changed, and the nature or number or position of the discrete element can be changed or changed. Therefore, all such modifications are intended to be included in the scope of the present invention. The order or sequence of any process or method steps can be changed or reordered according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure of the execution function described herein, and is not only structurally equivalent but also equivalent structure. Without departing from the scope of the present invention, other replacements, modifications, changes and omissions can be made in the design, operating conditions and arrangement of the exemplary embodiments. Therefore, the invention is not limited to a specific embodiment, but extends to numerous modifications still falling within the scope of the appended claims.

[0126] Additionally, in order to provide a concise description of exemplary embodiments, all features of an actual embodiment (ie, those features that are not relevant to the best mode presently contemplated for carrying out the invention or those that are not relevant to implementing the invention) may not be described.

[0127] It should be understood that in the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort may be complex and time-consuming, but for those of ordinary skill having the benefit of this disclosure, the development effort will be a routine task of design, fabrication, and production without undue experimentation.

[0128] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. An asynchronous bidirectional single-line communication method, comprising: S1, the host initiates write control or read control on the slave, sends a single-line signal to the slave, and the slave receives the single-line signal as input; S2, performing synchronization processing on the received single-line signal to generate a synchronized single-line signal; S3, decoding the synchronized single-line signal to generate decoded data; S4, the slave identifies the control type according to the decoded data, and if it is a read control, performs data reporting, encodes the data to be reported, and generates encoded data, otherwise, does not report data; S5. The slave sends the encoded data as an output single-line signal, and the host receives the single-line signal as an input.

2. The asynchronous two-way single-line communication method according to claim 1, characterized in that: The host sends a write command, a write address and write data to the slave via a single line; The transceiver switching module of the slave device switches to a receiving mode to receive a single-line signal; The data synchronization module of the slave performs synchronization processing on the received single-line signal to generate a synchronized single-line signal; The data analysis module of the slave decodes the synchronized single-line signal to generate decoded data, namely, the write command, write address and write data sent by the host.

3. The asynchronous bidirectional single-line communication method according to claim 1, characterized in that: The host sends a read command and a read address to the slave via a single line; The transceiver switching module of the slave device switches to a receiving mode to receive a single-line signal; The data synchronization module of the slave performs synchronization processing on the received single-line signal to generate a synchronized single-line signal; The data parsing module of the slave decodes the synchronized single-line signal to generate decoded data, namely, the read command and read address sent by the host; The data feedback module of the slave machine prepares corresponding data according to the decoded read command and read address, and performs encoding processing to generate encoded data, where the encoded data is read data; The transceiver switching module of the slave is switched to the sending mode, and the encoded data is sent to the host through a single line; The transceiver switching module of the host switches to the receiving mode to receive the single-line signal sent back by the slave.

4. An asynchronous bidirectional single-wire communication circuit system, used to implement an asynchronous bidirectional single-wire communication method according to any one of claims 1 to 3, characterized in that: The asynchronous bidirectional single-wire communication circuit system comprises a master and a slave; The host is used to initiate write control or read control on the slave; The slave is used to respond to the write control or read control initiated by the host; The slave comprises a peripheral circuit and an asynchronous bidirectional single-wire communication circuit; The peripheral circuit is used to provide power, clock and reset for the asynchronous bidirectional single-wire communication circuit; The asynchronous bidirectional single-line communication circuit includes a transceiver switching module, a data synchronization module, a data analysis module and a data feedback module, which are used to realize the communication control of the single-line signal.

5. The asynchronous bidirectional single-line communication circuit system according to claim 4, characterized in that: A transceiver switching module, used for controlling the transceiver of data, wherein the transceiver of data includes receiving a single-line signal and sending a single-line signal; A data synchronization module, used for performing synchronization processing on the received single-line signal to generate a synchronized single-line signal; A data analysis module is used to decode the synchronized single-line signal to generate decoded data, wherein the data analysis module includes decoding of write data frames and decoding of read data frames; The data reporting module is used to encode the data to be reported according to the decoded data to generate encoded data.

6. The asynchronous bidirectional single-line communication circuit system according to claim 4, characterized in that: The transceiver switching module includes a tri-state gate circuit; The three-state gate circuit states include high level, low level and high impedance state. If a three-state gate is in the high impedance state, it is equivalent to an open circuit; When sending data, the output end of the tri-state gate circuit is set to a non-high impedance state and the input end is set to a high impedance state; when receiving data, the output end of the tri-state gate circuit is set to a high impedance state and the input end is set to a non-high impedance state.

7. The asynchronous bidirectional single-line communication circuit system according to claim 4, characterized in that: The data synchronization module includes a multi-level register, which performs synchronous processing on the data by beating the multi-level register, realizes the synchronization of the single-line signal, and reduces the metastable problem generated when the signal is transmitted between different clock domains; The multi-level register beat locks the signal edge change step by step through multiple registers, thereby eliminating data errors caused by clock deviation and signal instability.

8. The asynchronous bidirectional single-line communication circuit system according to claim 4, characterized in that: The data synchronization module implements a single-line signal synchronization process, including: S101, using a local clock to sample the input single-line signal, this process will check the state of the single-line signal in each clock cycle; S102, using multiple levels of registers to perform phase-locked processing on the sampled data, and each level of registers will store a sampling result, and the next level of registers will be adjusted according to the result of the previous level; S103, through the processing of multi-level registers, the signal is made more stable, the influence of burrs and noise is reduced, and finally a synchronized single-line signal is obtained; S104. After being processed by the multi-stage registers, the data synchronization module outputs a single-line signal that has been synchronously processed. The signal has high reliability and accuracy and is suitable for further data processing or decoding.

9. The asynchronous bidirectional single-line communication circuit system according to claim 4, characterized in that: The decoding of the write data frame includes a data analysis module performing pulse width monitoring, falling edge monitoring, shift storage and other processing on the synchronized single-line signal, acquiring data of the command segment, address segment and data segment, and obtaining the decoded write command, write address and write data; The decoding of the read data frame includes a data analysis module performing pulse width monitoring, falling edge monitoring and shift storage on the synchronized single-line signal, acquiring data of the command segment and address segment, and obtaining a decoded read command and read address.

10. The asynchronous bidirectional single-line communication circuit system according to claim 4, characterized in that: The data reporting module workflow includes: S201, the data feedback module receives the decoded read data frame command and address data; S202, based on the received read command and read address information, processing the reported data segment through the data reporting module; S203, the data reporting module encodes the data segment to be reported according to the asynchronous bidirectional single-line communication protocol; S204, during the encoding process, the data will be converted into a series of single-bit signals, and the pulse width T and tD of the single-bit signals will be set according to the asynchronous bidirectional single-wire communication protocol; S205 , the data feedback module sends the encoded single-bit data to the host one by one via the data transceiver switching module.

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