Multi-core system on chip and control method thereof

Abstract

The invention discloses a multi-core system on chip and a control method thereof. The method relates to the technical field of chip design, and comprises the following steps: determining a first CPU core for executing a current task from a plurality of CPU cores of a multi-core system on chip; and controlling the first CPU core to execute a current task, and controlling other CPU cores except the first CPU core in the plurality of CPU cores to be in a dormant state. The technical problem that the multi-core system on chip is poor in safety or large in power consumption due to the fact that the multi-core system on chip only supports all the CPU cores to execute the same task or all the CPU cores execute different tasks respectively in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a multi-core system on chip and a control method thereof. Background Art

[0002] At present, multi-core system on chip (SoC) is a very common architecture in the field of chip design, and the corresponding chips are widely used in daily production and life. Currently, common multi-core SoC systems are mainly divided into two categories. One is the single-core MCU system. Although this architecture is simple and low-cost, it is easy to be hacked due to the single-core characteristics, and the security is biased; the other is the heterogeneous redundant multi-core system. Specifically, the system contains multiple heterogeneous CPU cores, each CPU core processes the same task, and works in a heterogeneous redundant manner to provide the security of the SoC system. Although this method can significantly improve the security of the SoC system, it also greatly increases the power consumption and scheduling complexity of the system.

[0003] Currently, no effective solution has been proposed for the problem that the multi-core system on chip in the above-mentioned related technologies only supports all CPU cores to execute the same task, or all CPU cores to execute different tasks respectively, and the multi-core system on chip has poor security or high power consumption. Summary of the invention

[0004] An embodiment of the present invention provides a multi-core system on chip and a control method thereof, so as to at least solve the technical problems in the related art that the multi-core system on chip only supports all CPU cores to execute the same task, or all CPU cores execute different tasks respectively, and the multi-core system on chip has poor security or high power consumption.

[0005] According to one aspect of an embodiment of the present invention, a control method for a multi-core system-on-chip is provided, comprising: determining a first CPU core that executes a current task from multiple CPU cores of the multi-core system-on-chip; controlling the first CPU core to execute the current task, and controlling other CPU cores among the multiple CPU cores except the first CPU core to be in a sleep state.

[0006] According to another aspect of an embodiment of the present invention, a multi-core system on chip is provided, comprising: a plurality of CPU cores and a target CPU core, wherein the target CPU core is used to execute any one of the control methods for the multi-core system on chip.

[0007] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the steps of any one of the control methods for a multi-core system on chip are implemented.

[0008] In an embodiment of the present invention, by determining a first CPU core that executes a current task from multiple CPU cores of a multi-core system-on-chip; controlling the first CPU core to execute the current task, and controlling other CPU cores among the multiple CPU cores except the first CPU core to be in a sleep state, the purpose of dynamically selecting a CPU core to execute a task each time and simultaneously putting other CPU cores in a sleep state is achieved, thereby achieving the technical effect of improving the operating security of the multi-core system-on-chip while reducing the operating energy consumption, and further solving the technical problem in the related art that the multi-core system-on-chip only supports all CPU cores to execute the same task, or all CPU cores to execute different tasks respectively, and the multi-core system-on-chip has poor security or high power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0010] Figure 1 is a flow chart of a control method of a multi-core system on chip according to an embodiment of the present invention;

[0011] Figure 2 is a schematic diagram of an optional mimetic microcontroller system structure according to an embodiment of the present invention;

[0012] Figure 3 is an internal implementation architecture diagram of an optional system-on-chip scheduling subsystem according to an embodiment of the present invention;

[0013] Figure 4 is an internal implementation architecture diagram of an optional task management module according to an embodiment of the present invention;

[0014] Figure 5 is a schematic diagram of external connection relationships of an optional task management module according to an embodiment of the present invention;

[0015] Figure 6 is an internal implementation architecture diagram of another optional system-on-chip scheduling subsystem according to an embodiment of the present invention;

[0016] Figure 7 is a flow chart of an optional control method of a multi-core system on chip according to an embodiment of the present invention;

[0017] Figure 8 is a schematic diagram of a control device for a multi-core system on chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0019] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0020] First, to facilitate understanding of the embodiments of the present invention, some terms or nouns involved in the present invention are explained below:

[0021] Advanced High-performance Bus (AHB-BUS), a bus standard for connecting processors, memories, and peripherals, is often used in high-performance System on Chip (SoC) designs. AHB-BUS provides high-bandwidth, low-latency data transmission capabilities, supports parallel access to multiple master and slave devices, and helps improve the overall performance and efficiency of the system.

[0022] The quality of service level, or QoS level, is used to describe the performance, response speed, stability, etc. of the chip. Common indicators include data transmission speed, response time, bandwidth, latency, etc., through which the QoS level of the chip can be quantified.

[0023] According to an embodiment of the present invention, an embodiment of a method for controlling a multi-core system on chip is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0024] Figure 1is a flow chart of a control method of a multi-core system on chip according to an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0025] Step S102, determining a first CPU core that executes a current task from a plurality of CPU cores of the multi-core system on chip;

[0026] In step S102 of the present application, by selecting a core (the first CPU core) from multiple CPU cores in a multi-core system on chip (i.e., a multi-core SoC system) to execute the current task, dynamic scheduling of tasks can be achieved, so that the multi-core system on chip can flexibly allocate computing resources according to task characteristics and the current system status.

[0027] Optionally, in the case where the current task is the first task processed by the multi-core system-on-chip, the first CPU core can be manually selected by the user or can be a default. For example, in the case where the multiple CPU cores include three CPU cores, namely CPU0, CPU1, and CPU2, if the user does not manually set the CPU core to execute the first task, the task is executed by CPU0 by default, that is, CPU0 is used as the first CPU core. In the case where the current task is not the first task processed by the multi-core system-on-chip, the first CPU core for executing the current task can be determined from the multiple CPU cores based on the CPU selection policy corresponding to the current task.

[0028] Step S104, controlling the first CPU core to execute a current task, and controlling other CPU cores among the multiple CPU cores except the first CPU core to be in a dormant state.

[0029] In step S104 of the present application, after determining the core to execute the task, other unselected CPU cores will be put into a sleep state, which can significantly reduce the power consumption of the multi-core system-on-chip in a non-task execution state. This is achieved by reducing unnecessary power consumption.

[0030] Through the above steps S102 to S104, the purpose of dynamically selecting a CPU core to execute a task each time, while other CPU cores are in a dormant state, can be achieved, thereby achieving the technical effect of improving the operational security of the multi-core system-on-chip while reducing the operational energy consumption, thereby solving the technical problem that the multi-core system-on-chip in the related technology only supports all CPU cores to execute the same task, or all CPU cores execute different tasks respectively, and the multi-core system-on-chip has poor security or high power consumption. Specifically, by dynamically allocating tasks to specific CPU cores and putting other cores into a dormant state, not only can the task execution efficiency and response speed of the multi-core SoC system be optimized, but also the system power consumption can be significantly reduced, the system security and anti-attack capability can be enhanced, and a balance between security, performance and energy saving can be achieved. The above method is particularly suitable for occasions where a trade-off between high performance, low latency and low power consumption is required, such as mobile devices, Internet of Things terminals and embedded application systems, etc., which helps to extend the service life of the equipment and improve its adaptability and overall performance in complex environments.

[0031] In an optional embodiment, after controlling the first CPU core to execute a current task and controlling other CPU cores among multiple CPU cores except the first CPU core to be in a sleep state, the method further includes: when a current task is executed to completion, based on a target CPU selection strategy, determining a second CPU core from multiple CPU cores to execute a next task, wherein the next task is a task after a current task; controlling the second CPU core to execute the next task, and controlling the first CPU core to switch to a sleep state.

[0032] Optionally, after the current task (executed by the first CPU core) is completed, the multi-core system-on-chip can automatically determine the next CPU core (the second CPU core) to execute the subsequent task according to the preset target CPU selection strategy, while the CPU cores other than the first CPU core and the second CPU core are still in a dormant state. This achieves dynamic switching between task execution and CPU cores, ensuring the continuity and efficiency of task processing. By orderly waking up the second CPU core to execute the next task and putting the first CPU core that has completed the task into a dormant state, a balance can be established between task processing and power consumption control, which is helpful for load balancing and energy efficiency optimization. In the above method, since the active CPU core can be adjusted in real time, it can be ensured that only the core currently executing the task is active, and the remaining cores are in a low-power dormant state. This mechanism can significantly reduce the total power consumption of the multi-core system-on-chip, especially for battery-powered mobile devices, which can extend the battery life. Dynamically switching the CPU core that executes the task can increase the unpredictability of the multi-core system-on-chip, reduce the success rate of attackers' attacks on specific cores, and thus improve the overall security of the multi-core system-on-chip and its resistance to abnormal software and hardware attacks. By avoiding resource competition among multiple cores, it can be ensured that each task is executed on the CPU core that best suits its characteristics, thereby avoiding unnecessary waiting and scheduling time, thereby improving the speed and efficiency of multi-core chip systems in processing tasks. In summary, through dynamic core switching and sleep mechanisms, not only can efficient and continuous task processing be achieved, but also the power consumption management of multi-core chip systems can be further optimized, and the security, performance and stability of multi-core chip systems can be enhanced.

[0033] Optionally, in consideration of the dynamic switching between task execution and CPU core, the CPU core selected to execute the next task may be the same CPU core as the CPU core executing the current task. Therefore, it is possible to first detect whether the second CPU core and the first CPU core are the same CPU core. If they are different CPU cores, the CPU core is switched. Otherwise, there is no need to switch the CPU core.

[0034] In an optional embodiment, before determining the second CPU core to execute the next task from multiple CPU cores based on the target CPU selection strategy, the method further includes: obtaining task characteristics of the next task; and determining the target CPU selection strategy from multiple CPU selection strategies based on the task characteristics.

[0035] Optionally, before scheduling a task, the task characteristics of the next task are first obtained, and based on the task characteristics, a strategy that best matches the current task is selected from multiple preset CPU selection strategies. By matching the task characteristics with the optimal scheduling strategy, the task can be assigned to the CPU core that best suits its nature for execution, thereby improving the speed and efficiency of task processing. Selecting a scheduling strategy based on the actual needs of the task helps to minimize power consumption while ensuring performance and maximize energy efficiency. By dynamically adjusting the scheduling strategy, the multi-core system-on-chip can adapt to the needs of different types of tasks and improve adaptability and flexibility in a changing environment. In summary, by analyzing task characteristics to intelligently select a CPU scheduling strategy, it can be ensured that the multi-core SoC system can allocate and execute tasks efficiently, safely, and with low power consumption according to the specific needs of the task. Maximize task processing performance, minimize power consumption, and enhance system security and adaptability.

[0036] Optionally, the target CPU selection strategy for CPU core screening can be dynamically determined from a variety of selection strategies based on the task characteristics and the current system state of the multi-core system on chip. The task characteristics may include, but are not limited to, task type (compute-intensive or input / output I / O-intensive), task priority requirements, data size, quality of service (QoS) requirements (such as delay limits, throughput requirements), and expected execution time requirements. This information is used to determine which scheduling strategy is most suitable for the task. The current system state may include, but is not limited to, the load (usage rate), temperature, energy consumption, and available resources (such as memory, I / O bandwidth) of each CPU core. This state information is the key basis for selecting scheduling strategies and determining CPU core allocation.

[0037] Specifically, if the task characteristic is that the task has strict QoS requirements, such as high priority or low latency requirements, a selection strategy based on a QoS algorithm can be preferentially adopted to ensure that the task is assigned to a CPU core that can meet these requirements.

[0038] For tasks that do not have specific QoS requirements, you can select a strategy based on the current CPU load and junction temperature. If the load of all CPU cores is relatively balanced and the temperature is low, you can consider using a selection strategy based on a random algorithm to assign tasks to improve the uncertainty and anti-prediction capabilities of the system. If it is detected that some CPU cores are under high load or close to overheating, dynamically switch to a strategy based on CPU task load or chip junction temperature control to avoid system bottlenecks and overheating risks.

[0039] In some cases, multiple strategies may need to be considered simultaneously. For example, when the task has QoS requirements and the system has temperature or load issues, QoS-based, task load-based, and chip junction temperature-based strategies can be combined to achieve the best balance.

[0040] In an optional embodiment, multiple CPU selection strategies include at least: a selection strategy based on a random algorithm, a selection strategy based on a quality of service algorithm, a selection strategy based on CPU task load, and a selection strategy based on chip junction temperature control, wherein: the selection strategy based on the random algorithm is used to randomly select a CPU core; the selection strategy based on the quality of service algorithm is used to select a CPU core according to the quality of service requirements of the task; the selection strategy based on the CPU task load is used to select a CPU core according to the task loads corresponding to multiple CPU cores; the selection strategy based on chip junction temperature control is used to select a CPU core based on the temperatures of various parts in a multi-core system on chip.

[0041] Optionally, by providing four core selection strategies based on random algorithms, quality of service (QoS), CPU task load, and chip junction temperature control, the multi-core system-on-chip can select the most appropriate execution strategy based on different performance indicators, security requirements, and power consumption targets. By defining multiple strategies, the CPU core that executes the task can be dynamically adjusted according to the characteristics of the task, such as real-time, computing intensity, security requirements, and current hardware status (such as temperature and power consumption), to ensure the optimal effect of task processing. Users can select specific strategies, such as selecting a strategy based on chip junction temperature control when power consumption needs to be balanced, or using a strategy based on quality of service when QoS of data processing needs to be guaranteed. It also supports the system to automatically select the optimal strategy according to preset rules without human intervention. In the above methods, the strategy based on task load can ensure that computing resources are reasonably allocated to avoid overloading a single CPU core, and can improve the throughput and response speed of tasks. The introduction of random algorithm strategies can increase the unpredictability of the system, which is particularly effective in resisting certain types of attacks (such as side channel attacks) because it is difficult to determine the execution path of the task. QoS-based strategies can ensure that tasks with strict service quality requirements (such as audio and video stream processing, network communication, etc.) are given priority, thereby improving user experience and system reliability. Strategies based on chip junction temperature control can effectively avoid local overheating and reduce power consumption, which is crucial for devices running in limited heat dissipation environments and helps to extend device life and improve stability. The coexistence of multiple CPU selection strategies enables multi-core systems on chip to cope with different types of tasks and changing operating environments. Whether it is high-performance computing, real-time data processing or low-power operation mode, the most appropriate strategy can be found to execute.

[0042] Optionally, a random algorithm-based selection strategy is a scheduling method that determines which CPU core will process the next task by random selection. This method is usually used to ensure load balancing between CPU cores and reduce the ability of attackers to predict the task allocation pattern of CPU cores. The random algorithm-based selection strategy can be implemented as follows: a high-precision random number generator is integrated inside the multi-core system-on-chip, and the generator can be used to generate random numbers for CPU numbers. When the current task is completed and a new task (i.e., the next task) needs to be assigned, the random number generator generates a random number. According to the number of CPU cores in the current multi-core system-on-chip, the random number is mapped to a specific CPU core number. The current state of the CPU core (e.g., temperature, power consumption) is further checked. If it is within a safe range, the new task is assigned to the CPU core; if it is not within a safe range, a random number is regenerated until a CPU core that meets the conditions is found. Once the execution core of the new task (i.e., the next task) is determined, the CPU core will be awakened and prepared for task execution, while other CPU cores will be put into a dormant state.

[0043] Optionally, the selection strategy based on the QoS algorithm is a strategy that determines which CPU core processes the task based on the priority and characteristics of the task and the performance of the CPU core. The purpose is to optimize the service quality indicators such as response time, throughput and power consumption of task execution. The specific implementation process of the selection strategy based on the QoS algorithm is as follows: define QoS parameters for each task, such as priority, delay tolerance, data throughput requirements, etc. According to the performance of the CPU core (such as computing power, power consumption characteristics) and the current load, a QoS score is assigned to each CPU core. When a task needs to be scheduled, the multi-core system-on-chip selects the most suitable CPU core to execute the task based on the QoS parameters of the task and the QoS score of the CPU core, including assigning high-priority tasks to cores with better performance, or assigning tasks with low power requirements to cores with lower power consumption, etc.

[0044] Optionally, the selection strategy based on CPU task load is to decide which CPU core should handle the next task by monitoring the current load of the CPU core. The goal is to avoid overload and uneven load and improve system efficiency. The specific implementation process of the selection strategy based on CPU task load is as follows: Continuously monitor the load of each CPU core in the multi-core system-on-chip, which can be achieved by checking the core utilization, queue length and other indicators. When the load of a CPU core reaches a preset threshold, the multi-core system-on-chip will start looking for other cores with lower loads. Dynamically select a CPU core with the lowest current load based on the load information and assign the new task (i.e., the next task) to it.

[0045] Optionally, the selection strategy based on chip junction temperature control is to determine which CPU core should process the task or which core should temporarily enter a dormant state by monitoring the temperature of the chip. The purpose is to prevent the chip from overheating and maintain stable operation of the system. The specific implementation process of the selection strategy based on chip junction temperature control is as follows: Multiple temperature sensors are set inside the multi-core system-on-chip to monitor the temperature of different areas or CPU cores. A temperature threshold is set for each CPU core. If the core temperature is higher than the threshold, it should not be selected as the core to execute a new task. When a task needs to be scheduled, the temperature of each CPU core is checked, and the core with a lower temperature is preferentially selected to execute the new task (i.e., the next task). If the temperature of all CPU cores is close to or higher than the threshold, measures need to be taken to reduce the temperature, such as reducing the task execution frequency, enabling the cooling system, or temporarily hibernating the high-temperature core.

[0046] In an optional embodiment, before determining the second CPU core to execute the next task from multiple CPU cores based on the target CPU selection policy, the method also includes: receiving a selection operation for any CPU selection policy among the multiple CPU selection policies; and determining any CPU selection policy as the target CPU selection policy.

[0047] Optionally, the user or system administrator is allowed to directly intervene in the CPU scheduling policy, that is, the user can select an arbitrary policy from multiple preset CPU selection policies as the target CPU selection policy based on specific needs or preferences, thereby providing a more flexible scheduling mechanism. The user can select the most suitable scheduling policy according to his or her application scenario (such as the need for higher performance, lower power consumption or stricter security), thereby more directly affecting the behavior of the multi-core system-on-chip and achieving the expected performance goals. By dynamically selecting and updating the scheduling policy, the multi-core system-on-chip can better adapt to the ever-changing environment and task requirements, and achieve efficient resource utilization, whether it is to cope with sudden high loads or switch between different application scenarios. The user or management system can select the optimal scheduling policy based on real-time conditions, such as the temperature, power consumption and load status of the CPU core, which helps to balance the use of each CPU core, avoid overheating or excessive power consumption, and ensure system performance and stability. Through the policy selection of the user or system, it is possible to switch between multiple scheduling policies, such as a selection policy based on a random algorithm, a policy based on QoS, a policy based on CPU task load or a policy based on temperature, etc., which can provide the system with rich scheduling logic and enhance the processing capability of complex tasks.

[0048] In summary, by introducing a policy selection mechanism at the user or system level, the multi-core SoC system can flexibly switch between multiple scheduling strategies to meet the performance, power consumption and security requirements in different scenarios. In effect, the user-friendliness, adaptability and refinement of resource allocation of the multi-core system-on-chip can be improved. Through this policy selection mechanism, it can respond more intelligently to the direct needs of users and changes in the real-time environment, and provide a solid technical foundation for realizing high-performance, low-power and high-security heterogeneous multi-core SoC applications.

[0049] In an optional embodiment, when there are multiple target CPU selection strategies, a second CPU core that executes the next task is determined from multiple CPU cores based on the target CPU selection strategy, including: obtaining operating indicators of the multi-core system on chip; based on the operating indicators, using multiple target CPU selection strategies to determine the second CPU core from multiple CPU cores.

[0050] Optionally, the multi-core system-on-chip can not only rely on a single strategy, but also use multiple strategies to select the CPU core for the next task execution according to the operating indicators of the multi-core system-on-chip, such as temperature, power consumption, task load and QoS requirements. By comprehensively considering multiple operating indicators, it is possible to make more intelligent decisions between different target CPU selection strategies, ensuring that task allocation not only meets performance requirements, but also takes into account power consumption and temperature control, and avoids uneven resource allocation or performance bottlenecks that may be caused by a single strategy. The combined use of multiple strategies improves the adaptability of the multi-core system-on-chip to complex tasks and changing environments, so that it can be flexibly adjusted according to actual operating indicators to achieve the best operating state. The real-time acquisition of operating indicators and the dynamic adjustment of strategies enable the multi-core system-on-chip to continuously optimize during operation, and even when the task characteristics or environmental conditions change, it can quickly respond and adjust the selection of CPU cores to achieve the best execution effect. The use of comprehensive strategies can not only ensure the efficient operation of the multi-core system-on-chip, but also meet the user's needs for low power consumption, high performance, security and stability, and improve user experience and satisfaction.

[0051] Optionally, the multiple target CPU selection strategies can be any two or more CPU selection strategies selected from multiple CPUs. For example, a selection strategy based on a random algorithm + a selection strategy based on chip junction temperature control can be adopted. Specifically, the CPU core number to which the task is to be assigned is generated by a built-in random number generator, and the current chip junction temperature sensor is checked. If the CPU core junction temperature is within a safe range, the following task unit can be assigned to the CPU core (i.e., the second CPU core), and the CPU core is controlled to wake up and execute tasks, and other CPU cores are controlled to sleep. The minimum unit of the task is an Advanced High-Performance Bus-Lite Mode Transfer (AHB-Lite transfer) command. It can also be based on software task allocation, and the task unit will be executed and then re-enter the next task unit switching process, and repeat the process over and over again.

[0052] For another example, a switching strategy combining a selection strategy based on a QoS algorithm and a selection strategy based on CPU task load can also be adopted. Specifically, a QoS task level is assigned to each task according to the QoS algorithm, and high-level tasks are assigned to specific CPU cores for execution. For example, for a multi-core system-on-chip with two CPU cores, low-level tasks can be assigned to one of the CPU cores for execution, and the task load of each CPU core is monitored interspersed. If the task load of the CPU core exceeds the threshold in a certain time period, the next task will be assigned to another CPU core, and vice versa. For example, if the task level of the current task is low, the current task will be assigned to one of the CPU cores for execution. If the task load of the CPU core exceeds the threshold in a certain time period, the next task will be assigned to another CPU core.

[0053] It should be noted that when the target CPU selection strategies are different, the corresponding operating indicator combinations adopted will also be different. For example, when the selected multiple target CPU selection strategies are a selection strategy based on a random algorithm + a selection strategy based on chip junction temperature control, the corresponding operating indicator combination can be the task level of the task to be executed and the temperature of the multi-core system on chip. When the selected multiple target CPU selection strategies are a switching strategy combining a selection strategy based on a QoS algorithm + a selection strategy based on CPU task load, the corresponding operating indicator combination can be the task level of the task to be executed and the task loads corresponding to the multiple CPU cores. When the selected multiple target CPU selection strategies include a selection strategy based on a random algorithm, a selection strategy based on a quality of service algorithm, a selection strategy based on CPU task load, and a selection strategy based on chip junction temperature control, the corresponding operating indicator combination can include the task level of the task to be executed, the temperature of the multi-core system on chip, the task safety level, the quality of service level, the task loads corresponding to the multiple CPU cores, etc.

[0054] In an optional embodiment, based on operating indicators, multiple target CPU selection strategies are adopted to determine the second CPU core from multiple CPU cores, including: determining weight values ​​corresponding to the multiple target CPU selection strategies respectively; based on the operating indicators, using multiple target CPU selection strategies to select CPU cores, and obtaining CPU selection results corresponding to the multiple target CPU selection strategies respectively; determining the second CPU core from multiple CPU cores based on the CPU selection results corresponding to the multiple target CPU selection strategies respectively, and the weight values ​​corresponding to the multiple target CPU selection strategies respectively.

[0055] Optionally, by determining the weight value of each target CPU selection strategy, the importance of different strategies in the decision-making can be reflected, so that the strategy with higher weight can be given priority when the strategies conflict or are executed in parallel. The multi-core system-on-chip not only executes each strategy independently, but also combines the results of multiple strategies to obtain the final CPU core selection result based on operating indicators (such as power consumption, temperature, task load and QoS requirements) and strategy weights. As the operating indicators change, the strategy weights can be dynamically adjusted to adapt to new operating conditions to ensure the flexibility and timeliness of decision-making. In the above manner, by setting the strategy weights, the relationship between different operating indicators can be weighed more accurately, and the refined allocation of resources can be achieved, avoiding the waste of resources or uneven allocation that may be caused by a single indicator. Making decisions based on the results of multiple strategies can increase the robustness of the decision, reduce the risk of inaccurate decision-making due to the abnormality of a single indicator, and ensure that reasonable choices can be made in various situations. By considering the weight and operating indicators of each strategy, the stable operation of the hardware can be maintained while ensuring the efficiency of task execution, avoiding overheating or overload, and extending the service life of the equipment. Users or system administrators can optimize the selection of CPU cores according to specific needs or preferences by adjusting policy weights, which means that policies can be customized to suit different application scenarios, thereby enhancing the user-friendliness and adaptability of the system.

[0056] In summary, by setting policy weights and integrating the results of multiple policies, the refinement of multi-core system-on-chip resource allocation and dynamic optimization of decision-making can be achieved. In effect, the efficiency, stability and security of multi-core system-on-chip can be improved, while the flexibility of policy configuration and the system's adaptability to complex application scenarios can also be enhanced.

[0057] Optionally, the operation index can be divided into a task characteristic index and a current system status index of the multi-core system on chip. In the case of multiple CPU selection strategies including a selection strategy based on a random algorithm, a selection strategy based on a quality of service algorithm, a selection strategy based on CPU task load, and a selection strategy based on chip junction temperature control, the CPU core can be selected in the following manner:

[0058] When the multi-core system-on-chip is started, the weights of various policies are preset through the policy configuration interface, including the relative importance of random algorithms, QoS, task load, and junction temperature control strategies. A state record is initialized for each CPU core, including information such as task load, current temperature, and performance level. When a task (such as the next task of the current task) needs to be assigned, the task characteristics are first parsed, such as QoS requirements (priority, delay sensitivity, etc.). The current temperature distribution of the multi-core system-on-chip and the load of each CPU core are measured or queried.

[0059] Entering the CPU core selection process, first, a selection strategy based on the QoS algorithm is performed. According to the QoS requirements of the task, a set of CPU cores that can meet these requirements are preliminarily screened out. For tasks with clear performance requirements or delay constraints, CPU cores that cannot meet the QoS requirements are excluded. Then, load and junction temperature evaluation is performed. Among the CPU cores preliminarily screened out, the task load and junction temperature status of each CPU core are further evaluated, and CPU cores with too high temperature (exceeding the preset safety threshold) or too heavy load are preferentially excluded. Then, random selection and load balancing are performed. If there are still multiple qualified CPU cores after QoS and junction temperature evaluation, a random algorithm can be used to further narrow the selection range. On the basis of random selection, load balancing can be additionally considered to avoid always selecting the same core, thereby achieving a more balanced work distribution. The random algorithm can be configured to select from CPU cores with relatively low load or moderate temperature to ensure the overall stability and efficiency of the multi-core system-on-chip. Based on the above steps, a CPU core (i.e., the second CPU core) is selected from all qualified and load-balanced cores for task allocation. If all CPU cores are not meeting requirements (e.g., too hot, too heavily loaded), additional measures can be taken, such as delaying task assignments, attempting to wake up dormant cores, or adjusting the system operating mode to reduce overall load and temperature.

[0060] In an optional embodiment, the operating indicators include the task level of the task to be executed, and / or at least one of the following: the temperature of the multi-core system on chip, the task congestion, the task safety level, the service quality level, and the task load corresponding to multiple CPU cores.

[0061] Optionally, by considering the task level and the temperature, congestion, security level, QoS and CPU core load of the multi-core system, the priority of the task and the state of the execution environment can be more comprehensively evaluated, so as to make smarter and more refined scheduling decisions. The introduction of task security level and QoS level enables the multi-core system-on-chip to prioritize security and service quality when allocating resources, which is particularly important for application scenarios that perform sensitive tasks or are sensitive to latency. Real-time monitoring and analysis of operating indicators such as temperature and CPU core load allows the multi-core system-on-chip to dynamically adjust scheduling strategies to adapt to changing operating conditions, avoid overheating and overload, and improve resource utilization. The above methods comprehensively consider the task load and task congestion of each CPU core, so that the system can allocate tasks more reasonably, avoid uneven load between CPU cores, and improve the overall processing capacity of the multi-core system-on-chip. Temperature, as one of the operating indicators, helps the multi-core system-on-chip to dynamically adjust the activation and sleep of the CPU core according to the current thermal conditions, and achieve optimal control of power consumption, which is particularly important in application scenarios that require long-term operation or battery power. Consideration of task security levels makes the system more cautious when selecting CPU cores to execute tasks, and can assign tasks with high security levels to cores with higher security features, thereby improving the overall security of multi-core SoCs. The addition of service quality levels can ensure that tasks with strict QoS requirements are given priority, which is essential to ensuring the user experience of real-time applications such as audio and video transmission and online games. By monitoring and controlling temperature and avoiding core overload, the system can maintain a stable operating state, extend hardware life, reduce failure rates, and provide users with more reliable services. It can also allow users or system administrators to adjust the monitoring strategy of task levels and operating indicators according to specific needs, thereby achieving more personalized and scenario-based scheduling strategies and improving the degree of user customization of multi-core SoCs.

[0062] In summary, by introducing and comprehensively analyzing a wider range of operating indicators and optimizing the task scheduling and resource allocation mechanism of multi-core SoCs, the efficiency, power management capability, security, service quality, and user customization of multi-core SoCs can be improved. By fully considering task characteristics and system status, it is possible to respond to various operating scenarios more intelligently and efficiently, providing more comprehensive technical support for the realization of high-performance, low-power, and highly secure heterogeneous multi-core SoC applications.

[0063] Based on the above embodiments and optional embodiments, the present invention proposes an optional implementation of a multi-core system-on-chip control method, which can be applied to a Mimic MCU system architecture scenario. Figure 2 is a schematic diagram of an optional mimetic microcontroller system structure according to an embodiment of the present invention, such as Figure 2As shown in FIG. 1 , the mimetic microcontroller system is composed of a heterogeneous CPU subsystem, a system-level chip scheduling subsystem (SoC Schedule Subsystem) and a SoC subsystem, wherein the heterogeneous CPU subsystem has multiple CPU cores (such as CPU0, CPU1, CPU2, etc.) built in, and each CPU core is connected to the system-level chip scheduling subsystem through a corresponding high-performance bus standard (Advanced High-performance Bus, AHB-BUS). The method can be Figure 2 The SoC subsystem is executed by the system-level chip scheduling subsystem in the multi-core system-on-chip, and its role is to dynamically configure the working modes of multiple CPU cores in the multi-core system-on-chip. The SoC subsystem integrates multiple functional modules or components, which can include but are not limited to AHB bus subsystem, peripheral model interface, phase-locked loop, power-on reset, clock and reset management and other functional modules, which are used to provide corresponding connections and functional services for the system-level chip scheduling subsystem.

[0064] Specifically, Figure 3 1 is an internal implementation architecture diagram of an optional system-level chip scheduling subsystem according to an embodiment of the present invention (taking triple-redundant, lightweight advanced high-performance bus AHB-lite transmission as an example), such as Figure 3 As shown, the SCSchedule Subsystem system includes multiple modules such as CPU Transfer Queue module, Task Mode (TaskManagement) module, Platform-Level Interrupt Controller (PLIC) module, Heterogeneous CPU Core Power Management (CPU Power Management) module, Task Distribution and Judgment (Distribution & Judgment) module, among which:

[0065] For the CPU Transfer Queue module, each CPU processing channel corresponds to a CPU Transfer Queue module. The CPU Transfer Queue module is instantiated as many times as there are Channel channels (characterized by redundancy) to cache the commands sent from the corresponding CPU channels and take out command requests from the cache according to the commands of the queue management module.

[0066] The Task Management module is used to dynamically manage the task scheduling strategy of heterogeneous multi-core CPUs. It is generally implemented by another CPU core and can dynamically manage escape strategies to improve system security.

[0067] The PLIC module is used to receive interrupt request signals sent by various peripherals, process interrupt sources according to interrupt management settings (including interrupt enable, interrupt priority setting, interrupt mask, etc.), and summarize and send them to each CPU core.

[0068] The CPU Power Management module is used to manage the sleep and wake-up of each CPU core to minimize system power consumption.

[0069] The Distribution&Judgment module is used to receive the task distribution commands given by the task management module, and send the bus transmission commands scheduled by each channel to the peripheral module (system bus). In addition, it receives the peripheral processing results returned on the bus, and sends the peripheral return results to the corresponding CPU (heterogeneous execution body) channel according to the task distribution settings.

[0070] It should be noted that the corresponding CPU type (homogeneous or heterogeneous), quantity, CPU transmission bus protocol (Advanced High Performance Bus - Lightweight Edition AMBA AHB-Lite, Advanced Extensible Interconnect AMBA AXI, Wishbone Bus, etc.) described in this embodiment is not particularly limited. For convenience, the examples are described by taking heterogeneous CPU, three-core CPU, and AHB-Lite as examples.

[0071] The key Task Management module and CPU Power Management module are described in detail as follows:

[0072] Figure 4 This is an internal implementation architecture diagram of an optional task management module according to an embodiment of the present invention. The TaskManagement module is used to manage task scheduling, including setting the number of heterogeneous execution bodies, overall task segmentation, task scheduling allocation, interrupt mode management, CPU sleep policy management, CPU core performance and temperature sensor head (as a basis for task switching), etc. Since it involves multiple flexible configuration operations, it is usually necessary to embed a small CPU core for configuration. The performance and area of ​​this CPU core are much smaller than those of the main CPU core, and it is not open to ordinary users.

[0073] Among them, the Management CPU module is the core of the entire multi-core system on chip, which is used to flexibly schedule the task allocation and sleep arrangement of each CPU core according to the system configuration strategy and system status monitoring. Considering the performance, cost, power consumption and other aspects, this module can be instantiated with a relatively low-end policy CPU core (such as but not limited to the microcontroller core ARMCortex-M0), with a flash processor Flash, etc., and provide external configuration interfaces such as Joint Test Action Group (JTAG) and Universal Asynchronous Receiver / Transmitter (UART). During the task execution process, keep one of the CPU cores turned on and the other CPU cores in a dormant state (for example, CPUx is turned on, CPU0 and CPU1 are in a dormant state). The policy basis for the Management CPU module to issue a working mode switch comes from many aspects, including user configuration, current working status monitoring, policy management, etc., which can realize user autonomous switching or SoC automatic switching. Among them, the current working status monitoring is implemented by the Work Status Monitor module. The Work Status Monitor module is used to autonomously monitor the performance, operation status, task congestion, chip junction temperature and other information of each task of the chip, and to provide feedback to the management CPU as a basis for task switching.

[0074] The CPU Power Management module is used to manage the sleep of each CPU core according to the CPU core task allocation instructions given by the Task Management module to reduce the power consumption of the entire system as much as possible, and is the key to achieving the power consumption bonus of this embodiment. Figure 5 FIG. 1 is a schematic diagram of an optional external connection relationship of a task management module according to an embodiment of the present invention, wherein the connection relationship between the CPU Power Management module and the Task Management, heterogeneous CPU core and interrupt management module PLIC and other modules is shown in FIG. Figure 5As shown in the figure, the CPU Power Management module mainly receives the sleep enable command of a CPU core sent by the Task Management module, and then converts it into the enable request of the corresponding CPU core, receives the handshake signal fed back by the CPU core, monitors the sleep state signal of the CPU core, summarizes it into an interrupt signal and sends it to the PLIC module, and the PLIC module sends the sleep interrupt signal to the Task Management module for decision-making according to the agreed interrupt format. The whole process realizes the complete closed-loop interaction between the CPU Power Management module and each heterogeneous CPU core, the interrupt management module, and the Task Management module, and realizes the free control of the sleep enable and wake-up of each heterogeneous CPU core, thereby achieving the important goal of saving power. It should be noted that since each heterogeneous CPU core has different requirements for the sleep enable control signal, the signal names listed here are only for example, and some adjustments need to be made according to the actual instantiation of the heterogeneous CPU core.

[0075] Still Figure 2 As shown, the multi-core SoC system can be set as a triple-redundant heterogeneous CPU core, and the three CPU cores (i.e., CPU0, CPU1, and CPU2) are respectively ARM Cortex-M3, a microprocessor MIPS uAptivUC without an interlocked pipeline stage, and a five-level implementation of a reduced instruction set computer RISC-V E906. It should be noted that this embodiment does not limit the number of docked CPU cores, but at least two CPU cores are required to meet the security bonus requirements; since homogeneous CPU cores are easily hacked, it is also necessary to limit the docked CPU cores to adopt heterogeneous instruction set architectures; in addition, in order to reduce the difficulty of task scheduling in the Task Management module in this embodiment, the performance of each heterogeneous CPU core is recommended to be as similar as possible, and there should not be too much performance difference. This embodiment respectively instantiates the Cortex-M3 of the ARM instruction set architecture, the uAptivUC of the MIPS instruction set architecture, and the E906 of the RISC-V instruction set architecture, and the docking bus uses the AHB-Lite interface common to these three cores.

[0076] Figure 6 FIG. 1 is another optional internal implementation architecture diagram of the system-level chip scheduling subsystem according to an embodiment of the present invention (taking the dual-redundancy, lightweight advanced high-performance bus AHB-lite transmission as an example), such as Figure 6As shown, the multi-core SoC system is connected to two redundant heterogeneous CPU cores, namely ARM Cortex-A53 and RISC-V C906 with equivalent performance, and the internal bus adopts the Advanced eXtensible Interface (AXI) bus with higher throughput. The overall structure of the SoC system in this embodiment is similar to the multi-core SoC system based on triple redundancy in the aforementioned embodiment, which will not be described in detail here.

[0077] Based on the above embodiments and optional embodiments, the present invention proposes an optional implementation mode: Figure 7 is a flowchart of an optional multi-core system on chip control method according to an embodiment of the present invention, which can be applied to Figures 2 to 6 In the system architecture, Figure 7 As shown, the method includes:

[0078] S1, the multi-core system-on-chip is started, and the CPU selection strategy is imported into the firmware;

[0079] S2, configure the number of external CPU cores to work;

[0080] S3, configure task switching rules, task slice size, etc.;

[0081] S4, turn on the CPU core (CPU0 is turned on by default), and the other CPU cores are in sleep mode;

[0082] S5, start task processing, and the task runs on the first CPU core that is turned on;

[0083] S6, waiting for the current task to be completed;

[0084] S7, switching the second CPU core that executes the next task according to a preset scheduling policy (i.e., CPU selection policy);

[0085] S8, setting CPU core switching, including enabling the second CPU core and sleep control of the remaining CPU cores;

[0086] S9, checking the completion of the switching, and executing a new task (i.e., the next task) on the new CPU core (i.e., the second CPU core) after the switching is completed;

[0087] S10, start a new task execution process, and repeat the operations from step S5 to step S9 until all tasks are completed.

[0088] This embodiment is based on a dynamic heterogeneous multi-core architecture, and uses an escape method to dynamically select a core in the heterogeneous multi-core to process a task, while other cores are in a dormant state, and dynamically switch to other working cores according to the task completion status. The significant differences in the instruction set architecture of heterogeneous CPU cores and the advantages of dynamic selection of task execution CPU cores are used to improve the overall system security. In addition, compared to heterogeneous redundant systems, only one CPU core will be turned on to execute tasks at the same time, and other CPU cores are in a dormant state. This significantly reduces the overall power consumption of the SoC system while enjoying the security benefits brought by heterogeneous CPU cores, and also avoids the complex mimetic scheduling links in dynamic heterogeneous redundant systems. The software and hardware designed by the present invention have a wide range of applications in the field of multi-core CPUs, and are simple, efficient, safe, and low in power consumption.

[0089] In this embodiment, a multi-core system on chip is also provided, including: multiple CPU cores and a target CPU core, wherein the target CPU core is used to execute any one of the above-mentioned control methods for the multi-core system on chip.

[0090] In this embodiment, a control device for a multi-core system on chip is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the terms "module" and "device" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0091] According to an embodiment of the present invention, there is also provided an embodiment of a device for implementing the control method of the multi-core system on chip. Figure 8 is a schematic diagram of the structure of a control device of a multi-core system on chip according to an embodiment of the present invention. Figure 8 As shown, the control device of the multi-core system on chip includes: a CPU core determination module 200 and a CPU core control module 202, wherein:

[0092] A CPU core determination module 200, for determining a first CPU core that executes a current task from among multiple CPU cores of the multi-core system-on-chip;

[0093] The CPU core control module 202 is connected to the CPU core determination module 200 and is used to control the first CPU core to execute a current task and control other CPU cores among the multiple CPU cores except the first CPU core to be in a dormant state.

[0094] In an embodiment of the present invention, a CPU core determination module 200 is set to determine a first CPU core that executes a current task from multiple CPU cores of a multi-core system-on-chip; a CPU core control module 202 is connected to the CPU core determination module 200, and is used to control the first CPU core to execute a current task, and control other CPU cores except the first CPU core among the multiple CPU cores to be in a dormant state, thereby achieving the purpose of dynamically selecting a CPU core to execute a task each time and keeping other CPU cores in a dormant state at the same time, thereby achieving the technical effect of improving the operating security of the multi-core system-on-chip while reducing the operating energy consumption, and further solving the technical problem in the related art that the multi-core system-on-chip only supports all CPU cores to execute the same task, or all CPU cores to execute different tasks respectively, and the multi-core system-on-chip has poor security or high power consumption.

[0095] It should be noted that the above modules can be implemented by software or hardware. For example, for the latter, it can be implemented in the following ways: the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0096] It should be noted that the CPU core determination module 200 and the CPU core control module 202 correspond to steps S102 to S104 in the embodiment, and the examples and application scenarios implemented by the modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above embodiments. It should be noted that the modules as part of the device can be run in a computer terminal.

[0097] It should be noted that the optional or preferred implementation of this embodiment can refer to the relevant description in the embodiment, which will not be repeated here.

[0098] The control device of the multi-core system on chip may also include a processor and a memory. The CPU core determination module 200, the CPU core control module 202, etc. are stored in the memory as program modules, and the processor executes the program modules stored in the memory to implement corresponding functions.

[0099] The processor includes a kernel, which retrieves the corresponding program module from the memory. The kernel may be one or more. The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. The memory includes at least one memory chip.

[0100] According to an embodiment of the present application, an embodiment of a non-volatile storage medium is also provided. Optionally, in this embodiment, the non-volatile storage medium includes a stored program, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute any of the control methods for the multi-core system on chip.

[0101] Optionally, in this embodiment, the non-volatile storage medium may be located in any computer terminal in a computer terminal group in a computer network, or in any mobile terminal in a mobile terminal group, and the non-volatile storage medium includes a stored program.

[0102] Optionally, when the program is running, the device where the non-volatile storage medium is located is controlled to perform the following functions: determine a first CPU core that executes a current task from multiple CPU cores of the multi-core system-on-chip; control the first CPU core to execute a current task, and control other CPU cores among the multiple CPU cores except the first CPU core to be in a sleep state.

[0103] According to an embodiment of the present application, an embodiment of a processor is also provided. Optionally, in this embodiment, the processor is used to run a program, wherein when the program is run, any of the control methods of the multi-core system on chip is executed.

[0104] According to an embodiment of the present application, an embodiment of a computer program product is also provided. When executed on a data processing device, the program is suitable for executing the control method steps of initializing any of the multi-core system on chip described above.

[0105] Optionally, the above-mentioned computer program product, when executed on a data processing device, is suitable for executing an initialization program having the following method steps: determining a first CPU core that executes a current task from multiple CPU cores of a multi-core system on chip; controlling the first CPU core to execute a current task, and controlling other CPU cores among the multiple CPU cores except the first CPU core to be in a sleep state.

[0106] An embodiment of the present invention provides an electronic device, which includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the following steps are implemented: determining a first CPU core that executes a current task from multiple CPU cores of a multi-core system-on-chip; controlling the first CPU core to execute a current task, and controlling other CPU cores among the multiple CPU cores except the first CPU core to be in a sleep state.

[0107] The above sequence of the embodiments of the present invention is for description only and does not represent the superiority or inferiority of the embodiments.

[0108] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the above modules can be a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, modules or indirect coupling or communication connection of modules, which can be electrical or other forms.

[0110] The modules described above as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0111] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0112] If the above-mentioned integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable non-volatile storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a non-volatile storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the various embodiments of the present invention. The aforementioned non-volatile storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0113] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A control method for a multi-core system on chip, characterized in that: include: Determine a first CPU core that executes a current task from among multiple CPU cores of the multi-core system-on-chip; The first CPU core is controlled to execute the one current task, and other CPU cores among the multiple CPU cores except the first CPU core are controlled to be in a sleep state.

2. The method according to claim 1, characterized in that After controlling the first CPU core to execute the current task and controlling other CPU cores among the multiple CPU cores except the first CPU core to be in a dormant state, the method further includes: When the current task is executed to completion, determining a second CPU core to execute a next task from the multiple CPU cores based on a target CPU selection strategy, wherein the next task is a task after the current task; The second CPU core is controlled to execute the next task, and the first CPU core is controlled to switch to a sleep state.

3. The method according to claim 2, characterized in that Before determining the second CPU core to execute the next task from the multiple CPU cores based on the target CPU selection strategy, the method further includes: Obtaining task characteristics of the next task; Based on the task characteristics, the target CPU selection strategy is determined from a plurality of CPU selection strategies.

4. The method according to claim 2, characterized in that: Before determining the second CPU core to execute the next task from the multiple CPU cores based on the target CPU selection strategy, the method further includes: Receiving a selection operation for any CPU selection strategy among a plurality of CPU selection strategies; The arbitrary CPU selection policy is determined as the target CPU selection policy.

5. The method according to claim 4, characterized in that The multiple CPU selection strategies include at least: a selection strategy based on a random algorithm, a selection strategy based on a quality of service algorithm, a selection strategy based on CPU task load, and a selection strategy based on chip junction temperature control, wherein: The random algorithm-based selection strategy is used to randomly select a CPU core; The selection strategy based on the quality of service algorithm is used to select the CPU core according to the quality of service requirements of the task; The selection strategy based on CPU task load is used to select a CPU core according to the task loads respectively corresponding to the multiple CPU cores; The selection strategy based on chip junction temperature control is used to select a CPU core based on the temperature of each part of the multi-core system on chip.

6. The method according to claim 2, characterized in that In the case where there are multiple target CPU selection strategies, determining a second CPU core to execute the next task from the multiple CPU cores based on the target CPU selection strategy includes: Obtaining operating indicators of the multi-core system on chip; Based on the operation index, multiple target CPU selection strategies are adopted to determine the second CPU core from the multiple CPU cores.

7. The method according to claim 6, characterized in that Based on the operation indicator, multiple target CPU selection strategies are adopted to determine the second CPU core from the multiple CPU cores, including: Determine the weight values ​​corresponding to the multiple target CPU selection strategies respectively; Based on the operation index, the multiple target CPU selection strategies are used to select a CPU core, and CPU selection results corresponding to the multiple target CPU selection strategies are obtained; The second CPU core is determined from the multiple CPU cores based on the CPU selection results respectively corresponding to the multiple target CPU selection strategies and the weight values ​​respectively corresponding to the multiple target CPU selection strategies.

8. The method according to claim 6 or 7, characterized in that: The operation index includes the task level of the task to be executed, and / or at least one of the following: the temperature of the multi-core system on chip, the task congestion, the task safety level, the service quality level, and the task load corresponding to the multiple CPU cores.

9. A multi-core system on chip, characterized in that: include: A plurality of CPU cores and a target CPU core, wherein the target CPU core is used to execute the control method of the multi-core system on chip as claimed in any one of claims 1 to 8.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the control method of the multi-core system on chip described in any one of claims 1 to 8 are implemented.

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